ASIX AX88190P 10/100base pcmcia fast ethernet mac controller Datasheet

AX88190P
PCMCIA Fast Ethernet MAC Controller
10/100BASE PCMCIA Fast Ethernet MAC Controller
Document No.: AX190-16 / V1.6 / May. 12 ’00
Features
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•
•
•
•
•
•
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IEEE 802.3u 100BASE-T, TX, and T4 Compatible
Single chip PCMCIA bus 10/100Mbps Fast
Ethernet MAC Controller
NE2000 register level compatible instruction
Compliant with 16 bit PC Card Standard February 1995
Support both 10Mbps and 100Mbps data rate
Support both full-duplex or half-duplex operation
Provides a MII port for both 10/100Mbps operation
Support 256/512 bytes EEPROM (used for saving
CIS)
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•
•
•
Support automatic loading of Ethernet ID, CIS and
Adapter Configuration from EEPROM on poweron initialization
External and internal loop-back capability
128-pin LQFP low profile package
25MHz Operation, Dual 5V and 3.3V CMOS
process with 5V I/O tolerance. Or pure 3.3V
operation
*IEEE is a registered trademark of the Institute of Electrical and Electronic
Engineers, Inc.
*All other trademarks and registered trademark are the property of their
respective holders.
Product description
The AX88190 Fast Ethernet Controller is a high performance PCMCIA bus Ethernet Controller. The AX88190
contains a 16 bit PCMCIA interfaces to host CPU and compliant with PC Card Standard – February 1995. The
AX88190 implements both 10Mbps and 100Mbps Ethernet function based on IEEE802.3 / IEEE802.3u LAN
standard. The AX88190 supports 10Mbps/100Mbps media-independent interface (MII) to simplify the design. The
AX88190 is built in interface to connect FAX/MODEM chipset with parallel bus interface.
System Block Diagram
RJ11
RJ45
DAA
MAGNETIC
MODEM
PHY/TxRx
EEPROM
AX88190
SRAM
PCMCIA I/F
Always contact ASIX for possible updates before starting a design.
This data sheet contains new products information. ASIX ELECTRONICS reserves the rights to modify product specification without notice. No liability
is assumed as a result of the use of this product. No rights under any patent accompany the sale of the product.
ASIX ELECTRONICS CORPORATION
Frist Released Date : Oct/02/1998
2F, NO.13, Industry East Rd. II, Science-based Industrial Park, Hsin-Chu City, Taiwan, R.O.C.
TEL: 886-3-579-9500
FAX: 886-3-579-9558
http://www.asix.com.tw
AX88190
PCMCIA Fast Ethernet MAC Controller
CONTENTS
1.0 INTRODUCTION ...............................................................................................................................................5
1.1 GENERAL DESCRIPTION: .....................................................................................................................................5
1.2 AX88190 BLOCK DIAGRAM:...............................................................................................................................5
1.3 AX88190 PIN CONNECTION DIAGRAM ................................................................................................................6
2.0 SIGNAL DESCRIPTION....................................................................................................................................7
2.1 PCMCIA BUS INTERFACE SIGNALS GROUP .........................................................................................................7
2.2 EEPROM SIGNALS GROUP .................................................................................................................................8
2.3 MII INTERFACE SIGNALS GROUP ..........................................................................................................................8
2.4 MODEM INTERFACE PINS GROUP ..........................................................................................................................9
2.5 SRAM INTERFACE PINS GROUP ...........................................................................................................................9
2.6 MISCELLANEOUS PINS GROUP ............................................................................................................................10
2.7 POWER ON CONFIGURATION SETUP SIGNALS CROSS REFERENCE TABLE .................................................................10
3.0 MEMORY AND I/O MAPPING .....................................................................................................................11
3.1 EEPROM MEMORY MAPPING ..........................................................................................................................11
3.2 ATTRIBUTE MEMORY MAPPING.........................................................................................................................11
3.3 I/O MAPPING....................................................................................................................................................12
3.4 SRAM MEMORY MAPPING ...............................................................................................................................12
4.0 REGISTERS OPERATION..............................................................................................................................13
4.1 PCMCIA FUNCTION CONFIGURATION REGISTER SET OF LAN............................................................................13
4.1.1 Configuration Option Register of LAN (LCOR) Offset 3C0H (Read/Write)...............................................14
4.1.2 Configuration and Status Register of LAN (LCSR) Offset 3C2H (Read/Write) ..........................................15
4.1.3 I/O Base Register 0/1 of LAN (LIOBASE0/1) Offset 3CAH/3CCH (Read/Write) .......................................15
4.2 PCMCIA FUNCTION CONFIGURATION REGISTER SET OF MODEM.....................................................................16
4.2.1 Configuration Option Register of MODEM (MCOR) Offset 3E0H (Read/Write).......................................16
4.2.2 Configuration and Status Register of MODEM (MCSR) Offset 3E2H (Read/Write) ..................................17
4.2.3 I/O Base Register 0/1 of MODEM (MIOBASE0/1) Offset 3EAH/3ECH (Read/Write) ...............................17
4.3 REGISTERS OPERATION .....................................................................................................................................18
4.3.1 Command Register (CR) Offset 00H (Read/Write)....................................................................................20
4.3.2 Interrupt Status Register (ISR) Offset 07H (Read/Write)...........................................................................20
4.3.3 Interrupt mask register (IMR) Offset 0FH (Write) ....................................................................................21
4.3.4 Data Configuration Register (DCR) Offset 0EH (Write)...........................................................................21
4.3.5 Transmit Configuration Register (TCR) Offset 0DH (Write) .....................................................................21
4.3.6 Transmit Status Register (TSR) Offset 04H (Read) ...................................................................................22
4.3.7 Receive Configuration (RCR) Offset 0CH (Write) ....................................................................................22
4.3.8 Receive Status Register (RSR) Offset 0CH (Read) ....................................................................................22
4.3.9 Inter-frame gap (IFG) Offset 16H (Read/Write)........................................................................................22
4.3.10 Inter-frame gap Segment 1(IFGS1) Offset 12H (Read/Write)..................................................................23
4.3.11 Inter-frame gap Segment 2(IFGS2) Offset 13H (Read/Write)..................................................................23
4.3.12 MII/EEPROM Management Register (MEMR) Offset 14H (Read/Write) .................................................23
4.3.13 Test Register (TR) Offset 15H (Write).....................................................................................................23
5.0 PCMCIA DEVICE ACCESS FUNCTIONS ....................................................................................................24
5.1 ATTRIBUTE MEMORY ACCESS FUNCTION FUNCTIONS. .........................................................................................24
5.2 I/O ACCESS FUNCTION FUNCTIONS. ....................................................................................................................24
6.0 ELECTRICAL SPECIFICATION AND TIMINGS .......................................................................................25
6.1 ABSOLUTE MAXIMUM RATINGS .........................................................................................................................25
6.2 GENERAL OPERATION CONDITIONS ...................................................................................................................25
6.3 DC CHARACTERISTICS......................................................................................................................................25
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ASIX ELECTRONICS CORPORATION
AX88190
PCMCIA Fast Ethernet MAC Controller
6.4 A.C. TIMING CHARACTERISTICS........................................................................................................................26
6.4.1 XTAL / CLOCK.........................................................................................................................................26
6.4.2 Reset Timing.............................................................................................................................................26
6.4.3 Attribute Memory Read Timing.................................................................................................................27
6.4.4 Attribute Memory Write Timing ................................................................................................................28
6.4.5 I/O Read Timing .......................................................................................................................................29
6.4.6 I/O Write Timing.......................................................................................................................................30
6.4.7 MII Timing................................................................................................................................................31
6.4.8 Asynchronous Memory I/F Access Timing.................................................................................................32
7.0 PACKAGE INFORMATION ...........................................................................................................................33
APPENDIX A: APPLICATION NOTE 1..............................................................................................................34
A.1 USING CRYSTAL ..............................................................................................................................................34
A.2 USING OSCILLATOR .........................................................................................................................................34
A.3 DUAL POWER (5V AND 3.3V) APPLICATION .......................................................................................................35
A.4 SINGLE POWER (3.3V) APPLICATION .................................................................................................................35
A.5 DUAL POWER (5V AND 3.3V) APPLICATION WITH 3.3V PHY .............................................................................36
APPENDIX B: APPLICATION NOTE 2..............................................................................................................37
B.1 ADVANCE APPLICATION FOR USING CRYSTAL ...................................................................................................37
ERRATA OF AX88190 V1 .....................................................................................................................................38
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ASIX ELECTRONICS CORPORATION
AX88190
PCMCIA Fast Ethernet MAC Controller
FIGURES
FIG - 1 AX88190 BLOCK DIAGRAM ..............................................................................................................................5
FIG - 2 AX88190 PIN CONNECTION DIAGRAM...............................................................................................................6
TABLES
TAB - 1 PCMCIA BUS INTERFACE SIGNALS GROUP ........................................................................................................7
TAB - 2 EEPROM BUS INTERFACE SIGNALS GROUP........................................................................................................8
TAB - 3 MII INTERFACE SIGNALS GROUP........................................................................................................................8
TAB - 4 MODEM INTERFACE SIGNALS GROUP..................................................................................................................9
TAB - 5 SRAM INTERFACE PINS GROUP.........................................................................................................................9
TAB - 6 MISCELLANEOUS PINS GROUP..........................................................................................................................10
TAB - 7 POWER ON CONFIGURATION SETUP TABLE ......................................................................................................10
TAB - 8 EEPROM MEMORY MAPPING........................................................................................................................11
TAB - 9 ATTRIBUTE MEMORY MAPPING ......................................................................................................................11
TAB - 10 I/O ADDRESS MAPPING ................................................................................................................................12
TAB - 11 LOCAL MEMORY MAPPING ...........................................................................................................................12
TAB - 12 PCMCIA FUNCTION CONFIGURATION REGISTER MAPPING OF LAN...............................................................13
TAB - 13 PCMCIA FUNCTION CONFIGURATION REGISTER MAPPING OF MODEM........................................................16
TAB - 14 PAGE 0 OF MAC CORE REGISTERS MAPPING.................................................................................................18
TAB - 15 PAGE 1 OF MAC CORE REGISTERS MAPPING.................................................................................................19
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ASIX ELECTRONICS CORPORATION
AX88190
PCMCIA Fast Ethernet MAC Controller
1.0 Introduction
1.1 General Description:
The AX88190 provides industrial standard NE2000 registers level compatable instruction set. Various
drivers are easy acquired, maintenance and usage with no pain and tears
The AX88190 Fast Ethernet Controller is a high performance PCMCIA bus Ethernet Controller. The
AX88190 contains a 16 bit PCMCIA interfaces to host CPU and compliant with PC Card Standard –
February 1995. The AX88190 implements both 10Mbps and 100Mbps Ethernet function based on
IEEE802.3 / IEEE802.3u LAN standard. The AX88190 supports 10Mbps/100Mbps media-independent
interface (MII) to simplify the design. The AX88190 is built in interface to connect FAX/MODEM chipset
with parallel bus interface.
AX88190A use 128-pin LQFP low profile package, 25MHz operation frequency, dual 5V and 3.3V CMOS
process with 5V I/O tolerance or pure 3.3V operation.
1.2 AX88190 Block Diagram:
MEMA[15:1]
MEMD[15:0]
SMDC
SMDIO
MODEM
I/F
EECS
EECK
EEDI
EEDO
SRAM
Arbiter
SEEPROM
LOADER I/F
STA
MII I/F
Remote
DMA
FIFOs
NE2000
Registers
MAC
Core
PCMCIA Interface
Ctl BUS
SA[9:0]
SD[15:0]
Fig - 1 AX88190 Block Diagram
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ASIX ELECTRONICS CORPORATION
AX88190
PCMCIA Fast Ethernet MAC Controller
1.3 AX88190 Pin Connection Diagram
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
TXD[0]
TX_EN
TX_CLK
VSS
MDC
MDIO
RXD[3]
RXD[2]
RXD[1]
RXD[0]
RX_CLK
CRS
COL
RX_DV
RX_ER
VSS
MEMD[0]
MEMD[1]
MEMD[2]
MEMD[3]
MEMD[4]
HVDD
MEMD[5]
MEMD[6]
MEMD[7]
MEMD[8]
MEMD[9]
VSS
MEMD[10]
MEMD[11]
MEMD[12]
MEMD[13]
The AX88190 is housed in the 128-pin plastic light quad flat packFig - 2 AX88190 Pin Connection
Diagram shows the AX88190 pin assignment.
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
AX88190
PCMCIA
10/100BASE MAC
CONTROLLER
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
HVDD
MEMD[14]
MEMD[15]
MEMA[1]
MEMA[2]
VSS
MEMA[3]
MEMA[4]
MEMA[5]
MEMA[6]
LVDD
MEMA[7]
MEMA[8]
MEMA[9]
MEMA[10]
VSS
MEMA[11]
MEMA[12]
MEMA[13]
MEMA[14]
LVDD
MEMA[15]
MEMRD#
MEMWR#
VSS
VSS
SD[0]
SD[1]
SD[2]
SD[3]
VSS
SD[4]
SA[0]
SA[1]
SA[2]
SA[3]
SA[4]
SA[5]
SA[6]
SA[7]
SA[8]
SA[9]
VSS
IREQ#
WE#
IOWR#
IORD#
OE#
CE2#
CE1#
HVDD
SD[15]
SD[14]
SD[13]
SD[12]
VSS
SD[11]
SD[10]
SD[9]
SD[8]
HVDD
SD[7]
SD[6]
SD[5]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
TXD[1]
TXD[2]
TXD[3]
LVDD
CLKO25M
VSS
LCLK/XTALIN
XTALOUT
VSS
EECS
EECK
EEDI
EEDO
LVDD
MDCS#
MINT
MAUDIO
PPWDN
MRIN#
MPWDN
MRESET#
MRDY
VSS
IOIS16#
STSCHG#
SPKR#
REG#
INPACK#
WAIT#
LVDD
RESET
LVDD
Fig - 2 AX88190 Pin Connection Diagram
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ASIX ELECTRONICS CORPORATION
AX88190
PCMCIA Fast Ethernet MAC Controller
2.0 Signal Description
The following terms describe the AX88190 pin-out:
All pin names with the “#” suffix are asserted low.
The following abbreviations are used in following Tables.
I
O
I/O
OD
Input
Output
Input/Output
Open Drain
PU
PD
P
Pull Up
Pull Down
Power Pin
2.1 PCMCIA Bus Interface Signals Group
SIGNAL
SA[9:0]
SD[15:0]
TYPE
I
PIN NO.
10 – 1
I/O
IREQ#
O
20 – 23,
25 – 38,
30 – 33,
35 – 38
12
WAIT#
O
125
REG#
I
123
IORD#
I
15
IOWR#
I
14
OE#
I
16
WE#
I
13
IOIS16#
O
120
INPACK#
O
124
CE1#-CE2#
I
18, 17
BVD1_STSCHG#
BVD2_SPKR#
O
O
121
122
DESCRIPTION
System Address : Signals SA[9:0] are address bus input lines which
enable direct address of up to 64K memory and I/O spaces on card.
System Data Bus : Signals SD[15:0] constitute the bi-directional data
bus.
Interrupt Request : IREQ# is asserted to indicate the host system that
the PC Card device requires host software service.
Wait : This signal is set low to insert wait states during Remote DMA
transfer.
Attribute Memory and I/O Space Select : When the REG# signal is
asserted, access is limited to Attribute Memory and to the I/O space.
I/O Read : The host asserts IORD# to read data from AX88190 I/O
space.
I/O Write : The host asserts IOWR# to write data into AX88190 I/O
space.
Output Enable : The OE# line is used to gate Memory Read data from
memory on PC Card
Write Enable : The WE# signal is used for strobing Memory Write
data into the memory on PC Card.
I/O is 16 Bit Port : The IOIS16# is asserted when the address at the
socket corresponds to an I/O address to which the card responds, and
the I/O port addressed is capable of 16-bit access.
Input Port Acknowledge : The signal is asserted when the AX88190 is
selected and can respond to and I/O read cycle at the address on the
address bus.
Card Enable : The CE1# enables even numbered address bytes and
CE2# enables odd numbered address bytes
Battery Voltage Detect 1 / Status Change
Battery Voltage Detect 2 / Audio speaker out
Tab - 1 PCMCIA bus interface signals group
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ASIX ELECTRONICS CORPORATION
AX88190
PCMCIA Fast Ethernet MAC Controller
2.2 EEPROM Signals Group
SIGNAL
EECS
EECK
EEDI
EEDO
TYPE
O
O
O
I/PU
PIN NO.
106
107
108
109
DESCRIPTION
EEPROM Chip Select : EEPROM chip select signal.
EEPROM Clock : Signal connected to EEPROM clock pin.
EEPROM Data In : Signal connected to EEPROM data input pin.
EEPROM Data Out : Signal connected to EEPROM data output pin.
Tab - 2 EEPROM bus interface signals group
2.3 MII interface signals group
SIGNAL
RXD[3:0]
TYPE
I
PIN NO.
90 – 87
CRS
I
85
RX_DV
I
83
RX_ER
I
82
RX_CLK
I
86
COL
TX_EN
I
O
84
95
TXD[3:0]
O
99 – 96
TX_CLK
I
94
MDC
O
92
MDIO
I/O/PU
91
DESCRIPTION
Receive Data : RXD[3:0] is driven by the PHY synchronously with
respect to RX_CLK.
Carrier Sense : Asynchronous signal CRS is asserted by the PHY
when either the transmit or receive medium is non-idle.
Receive Data Valid : RX_DV is driven by the PHY synchronously
with respect to RX_CLK. Asserted high when valid data is present on
RXD [3:0].
Receive Error : RX_ER ,is driven by PHY and synchronous to
RX_CLK, is asserted for one or more RX_CLK periods to indicate to
the port that an error has detected.
Receive Clock : RX_CLK is a continuous clock that provides the
timing reference for the transfer of the RX_DV,RXD[3:0] and
RX_ER signals from the PHY to the MII port of the repeater.
Collision : this signal is driven by PHY when collision is detected.
Transmit Enable : TX_EN is transition synchronously with respect to
the rising edge of TX_CLK. TX_EN indicates that the port is
presenting nibbles on TXD [3:0] for transmission.
Transmit Data : TXD[3:0] is transition synchronously with respect to
the rising edge of TX_CLK. For each TX_CLK period in which
TX_EN is asserted, TXD[3:0] are accepted for transmission by the
PHY.
Transmit Clock : TX_CLK is a continuous clock from PHY. It
provides the timing reference for the transfer of the TX_EN and
TXD[3:0] signals from the MII port to the PHY.
Station Management Data Clock : The timing reference for MDIO.
All data transfers on MDIO are synchronized to the rising edge of this
clock. MDC is a 2.5MHz frequency clock output.
Station Management Data Input / Output : Serial data input/output
transfers from/to the PHYs . The transfer protocol conforms to the
IEEE 802.3u MII specification.
Tab - 3 MII interface signals group
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ASIX ELECTRONICS CORPORATION
AX88190
PCMCIA Fast Ethernet MAC Controller
2.4 Modem interface pins group
Signal Name
Type
Pin No.
Description
I/PU
118
O
O
O
117
111
116
MINT
I/PD
112
MRIN#
I/PU
115
MAUDIO
I/PD
113
Modem Ready : MRDY low indicates that modem is initializing the
modem after reset signal asserted or the modem is at SLEEP/STOP
mode.
Modem Reset :This signal asserts low to reset the modem chipset.
Modem Chip Select : This signal connected to modem chip select pin.
Modem Power Down : Rockwell modem chipset, this signal asserts
low to let modem chipset into power down mode. AT&T modem
chipset, this signal asserts high to let modem chipset into power down
mode.
Modem Interrupt : This signal driven by modem chipset to active
interrupt.
Ring Input :This signal is driven by DAA’s ring detect circuit. When
a telephone ringing signal is being received.
Modem Audio : This signal is passed to PCMCIA interface via SPKR.
MRDY
MRESET#
MDCS#
MPWDN
Tab - 4 Modem interface signals group
2.5 SRAM Interface pins group
SIGNAL
MEMA[15:1]
TYPE
O
MEMD[15:0]
I/O/PU
MEMRD#
MEMWR#
O
O
PIN NO.
43, 45 – 48,
50 –53’
55 – 58,
60 – 61
62 – 63,
65 – 68,
70 – 74,
76 – 80
42
41
DESCRIPTION
SRAM Address :
SRAM Data :
SRAM Read
SRAM Write
Tab - 5 SRAM Interface pins group
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ASIX ELECTRONICS CORPORATION
AX88190
PCMCIA Fast Ethernet MAC Controller
2.6 Miscellaneous pins group
SIGNAL
LCLK/XTALIN
TYPE
I
PIN NO.
103
XTALOUT
O
104
CLKO25M
PPWDN
O
O
101
114
RESET
I/PD
127
LVDD
P
HVDD
P
VSS
P
DESCRIPTION
CMOS Local Clock : A 25Mhz clock, +/- 100 ppm, 40%-60% duty
cycle.
Crystal Oscillator Input : A 25Mhz crystal, +/- 25 ppm can be
connected across XTALIN and XTALOUT.
Crystal Oscillator Output : A 25Mhz crystal, +/- 25 ppm can be
connected across XTALIN and XTALOUT. If a single-ended external
clock (LCLK) is connected to XTALIN, the crystal output pin should
be left floating.
Clock Output 25MHz : This clock is source from LCLK/XTALIN.
Phy Power Down : This pin connects to PHY chip power down mode
control input.
Reset
Reset is active high then place AX88190 into reset mode immediately.
During Falling edge the AX88190 loads the EEPROM data.
Power Supply : +3.3V DC.
44, 54,
100, 110,
126, 128
19, 29, 64, Power Supply : +5V DC.
75
Note : for pure 3.3V single power solution, all the HVDD pin can
connect to +3.3V. Care should be taken that HVDD input power must
be greater or equal ( > = ) than LVDD.
11, 24, 34, Power Supply : +0V DC or Ground Power.
39, 40, 49,
59, 69, 81,
93, 102, 105,
119
Tab - 6 Miscellaneous pins group
2.7 Power on configuration setup signals cross reference table
Signal Name
Share with
EEPROM SIZE
MEMD[6]
MPD_SET
MEMD[5]
PPD_SET
MEMD[4]
TEST
MEMD[3]
Description
EEPROM SIZE = 0 : Test mode.
EEPROM SIZE = 1 : Normal operation. (Default)
MPD_SET = 0 : MPWDN pin active high.
MPD_SET = 1 : MPWDN pin active low.
PPD_SET = 0 : PPWDN pin active high.
PPD_SET = 1 : PPWDN pin active low.
TEST = 0 : Test mode.
TEST = 1 : Normal operation. (Default)
All of the above signals are pull-up for default values.
Tab - 7 Power on Configuration Setup Table
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ASIX ELECTRONICS CORPORATION
AX88190
PCMCIA Fast Ethernet MAC Controller
3.0 Memory and I/O Mapping
There are four memory or I/O mapping used in AX88190.
1.
2.
3.
4.
EEPROM Memory Mapping
Attribute Memory Mapping
I/O Mapping
Local Memory Mapping
3.1 EEPROM Memory Mapping
EEPROM OFFSET
00H
01H
02H
03H
04H
05H
06H – 10H
10H – FFH
HIGH BYTE
RESERVED
CFH
NODE-ID1
NODE ID 3
NODE ID 5
CHECKSUM
RESERVED
CIS
LOW BYTE
WORD COUNT
CFL
NODE ID 0
NODE ID 2
NODE ID 4
RESERVED
RESERVED
CIS
Tab - 8 EEPROM Memory Mapping
3.2 Attribute Memory Mapping
ATTRIBUTE MEMORY
OFFSET
0000H
03BFH
03C0H
03C2H
03C4H
03C6H
03CAH
03CCH
03CEH
03DFH
03E0H
03E2H
03E4H
03E6H
03EAH
03ECH
03EEH
03FFH
CONTENTS
CIS
LCOR
LCCSR
LIOBASE0
LIOBASE1
RESERVED
MCOR
MCCSR
MIOBASE0
MIOBASE1
RESERVED
Tab - 9 Attribute Memory Mapping
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ASIX ELECTRONICS CORPORATION
AX88190
PCMCIA Fast Ethernet MAC Controller
3.3 I/O Mapping
SYSTEM I/O OFFSET
0000H
001FH
FUNCTION
MAC CORE REGISTER
Tab - 10 I/O Address Mapping
3.4 SRAM Memory Mapping
OFFSET
0000H
03BFH
03C0H
03C2H
03C4H
03C6H
03CAH
03CCH
03CEH
03DFH
03E0H
03E2H
03E4H
03E6H
03EAH
03ECH
03EEH
03FFH
0400H
0401H
0402H
0403H
0404H
0405H
0406H
07FFH
0800H
FFFFH
FUNCTION
CIS *1
LCOR *1
LCCSR *1
LIOBASE0 *1
LIOBASE1 *1
RESERVED
MCOR *1
MCCSR *1
MIOBASE0 *1
MIOBASE1 *1
RESERVED
NODE ID 0
NODE ID 1
NODE ID 2
NODE ID 3
NODE ID 4
NODE ID 5
RESERVED
62K X 8
SRAM BUFFER
Tab - 11 Local Memory Mapping
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ASIX ELECTRONICS CORPORATION
AX88190
PCMCIA Fast Ethernet MAC Controller
4.0 Registers Operation
There are four register sets in AX88190 :
1.
2.
3.
4.
The PCMCIA function configuration registers of LAN.
The PCMCIA function configuration registers of MODEM.
The MAC core register.
The special registers.
4.1 PCMCIA Function Configuration Register Set of LAN
REGISTER
LCOR
LCSR
LIOBASE0
LIOBASE1
NAME
CONFIGURATION OPTION REGISTER
CONFIGURATION AND STATUS REGISTER
I/O BASED REGISTER 0
I/O BASED REGISTER 1
OFFSET
3C0H
3C2H
3CAH
3CCH
Tab - 12 PCMCIA Function Configuration Register Mapping of LAN
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ASIX ELECTRONICS CORPORATION
AX88190
PCMCIA Fast Ethernet MAC Controller
4.1.1 Configuration Option Register of LAN (LCOR) Offset 3C0H (Read/Write)
FIELD
7
6
5:0
R/W/C
DESCRIPTION
R/W Software Reset
Assert this bit will reset the LAN function of AX88190. Return a 0 to this bit will leave the
LAN function of AX88190 in a post-reset state as same as that following a hardware reset.
The value of this bit is 0 at power-on.
R/W
Level IRQ
This bit should be set to 1, the AX88190 always generates Level Mode Interrupt.
R/W
Function Configuration Index
These six bits are used to indicate entry of the card configuration table locate in the CIS.
The default value is 0
.
On multifunction PC Card,
Bit 5, Bit 4 : MODEM I/O base registers
Bit 5
Bit 4
MODEM I/O base
0
0
Decided by MIOBASE registers ( See section 4.2.3 )
0
1
2f8H
1
0
3e8H
1
1
2e8H
Bit 3 : Enable Power Down mode
If bit 0 of LCOR is set to 0, this bit is ignored.
If bit 0 of LCOR is set to 1 and this bit is set to 1, the LAN will go into power down
mode. At power down mode AX88190 will disable MAC transmitting and receiving
operation. But the host interface will not be affected.
Bit 2 : Enable IREQ# Routing
If bit 0 of LCOR is set to 0, this bit is ignored.
If bit 0 of LCOR is set to 1 and this bit is set to 1, the LAN will generate interrupt request
via IREQ# signal. If this bit is set to 0, the LAN will not generate interrupt request via
IREQ# line.
Bit 1 : Enable Base and Limit Registers
If bit 0 of LCOR is set to 0, this bit is ignored.
If bit 0 of LCOR is set to 1 and this bit is set to 1,only I/O addresses that are qualified by
the Base and Limit registers are passed to LAN function. If this bit is set to 0,all I/O
addresses are passed to LAN function.
Bit 0 : Enable Function
If this bit is set to 0, the LAN function is disabled.
If this bit is set to 1, the LAN function is enabled.
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ASIX ELECTRONICS CORPORATION
AX88190
PCMCIA Fast Ethernet MAC Controller
4.1.2 Configuration and Status Register of LAN (LCSR) Offset 3C2H (Read/Write)
FIELD
7:3
2
1
0
R/W/C
DESCRIPTION
Reserved
R/W PPwrDwn : PHY power down setting
While this bit set to 1, PPWDN pin (pin 114) will be active to force PHY chip into power
down mode. As for PPWDN is active high or active low. Please refer section 2.7 Power on
configuration setup signal cross reference table.
R
Intr : Interrupt Request
The LAN function will set this bit to 1 when it need interrupt service and set it to 0 when it
is not request interrupt service.
R
IntrAck : Interrupt Acknowledge
This bit will be 0. The Intr will reflect the status of interrupt requesting.
4.1.3 I/O Base Register 0/1 of LAN (LIOBASE0/1) Offset 3CAH/3CCH (Read/Write)
The I/O Base registers (LIOBASE0 and LIOBASE1) determine the base address of the I/O range used to
access the LAN specific registers (MAC Core Registers).
I/O Base Register 0
FIELD
7:0
R/W/C
R/W Base I/O address bit 7 – 0.
DESCRIPTION
I/O Base Register 1
FIELD
7:0
R/W/C
R/W Base I/O address bit 15 – 8.
DESCRIPTION
15
ASIX ELECTRONICS CORPORATION
AX88190
PCMCIA Fast Ethernet MAC Controller
4.2 PCMCIA Function Configuration Register Set of MODEM
REGISTER
MCOR
MCSR
MIOBASE0
MIOBASE1
NAME
CONFIGURATION OPTION REGISTER
CONFIGURATION AND STATUS REGISTER
I/O BASED REGISTER 0
I/O BASED REGISTER 1
OFFSET
3E0H
3E2H
3EAH
3ECH
Tab - 13 PCMCIA Function Configuration Register Mapping of MODEM
4.2.1 Configuration Option Register of MODEM (MCOR) Offset 3E0H (Read/Write)
FIELD
7
6
5:0
R/W/C
DESCRIPTION
R/W Software Reset
Assert this bit will reset the MODEM function of AX88190. Return a 0 to this bit will
leave the MODEM function of AX88190 in a post-reset state as same as that following a
hardware reset. The value of this bit is 0 at power-on.
R/W
Level IRQ
This bit should be set to 1, the AX88190 always generates Level Mode Interrupt.
R/W
Function Configuration Index
These six bits are used to indicate entry of the card configuration table locate in the CIS.
The default value is 0
.
On multifunction PC Card,
Bit 5, Bit4 : Reserved
Bit 3 : IREQ# route to STSCHG#
If bit 0 of MCOR is set to 0, this bit is ignored.
If both bit 0 and bit 2 of MCOR are set to 1 and this bit is set to 1, the MODEM will route
interrupt request to STSCHG# signal. If this bit is set to 0, the MODEM will generate
interrupt request via IREQ# line.
Bit 2 : Enable IREQ# Routing
If bit 0 of MCOR is set to 0, this bit is ignored.
If bit 0 of MCOR is set to 1 and this bit is set to 1, the MODEM will generate interrupt
request via IREQ# signal. If this bit is set to 0, the MODEM will not generate interrupt
request via IREQ# line.
Bit 1 : Enable Base and Limit Registers
If bit 0 of MCOR is set to 0, this bit is ignored.
If bit 0 of MCOR is set to 1 and this bit is set to 1,only I/O addresses that are qualified
by the Base and Limit registers are passed to MODEM function. If this bit is set to 0,all
I/O addresses are passed to LAN function.
Bit 0 : Enable Function
If this bit is set to 0, the MODEM function is disabled.
If this bit is set to 1, the MODEM function is enabled.
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ASIX ELECTRONICS CORPORATION
AX88190
PCMCIA Fast Ethernet MAC Controller
4.2.2 Configuration and Status Register of MODEM (MCSR) Offset 3E2H (Read/Write)
FIELD
7:3
2
1
0
R/W/C
DESCRIPTION
Reserved
R/W MPwrDwn : Modem power down setting
While this bit set to 1, MPWDN pin (pin 116) will be active to force modem chip into power
down mode. As for MPWDN is active high or active low. Please refer section 2.7 Power on
configuration setup signal cross reference table.
R
Intr : Interrupt Request
The LAN function will set this bit to 1 when it need interrupt service and set it to 0 when it
is not request interrupt service.
R
IntrAck : Interrupt Acknowledge
This bit will be 0. The Intr will reflect the status of interrupt requesting.
4.2.3 I/O Base Register 0/1 of MODEM (MIOBASE0/1) Offset 3EAH/3ECH
(Read/Write)
The I/O Base registers (MIOBASE0 and MIOBASE1) determine the base address of the I/O range used to
access the MODEM specific registers.
I/O Base Register 0
FIELD
7:0
R/W/C
R/W Base I/O address bit 7 – 0.
DESCRIPTION
I/O Base Register 1
FIELD
7:0
R/W/C
R/W Base I/O address bit 15 – 8.
DESCRIPTION
17
ASIX ELECTRONICS CORPORATION
AX88190
PCMCIA Fast Ethernet MAC Controller
4.3 Registers Operation
All registers of MAC Core are 8-bit wide and mapped into pages which are selected by PS in the
Command Register.
PAGE 0 (PS1=0,PS0=0)
OFFSET
00H
0AH
READ
Command Register
( CR )
Page Start Register
( PSTART )
Page Stop Register
( PSTOP )
Boundary Pointer
( BNRY )
Transmit Status Register
( TSR )
Number of Collisions Register
( NCR )
Current Page Register
( CPR )
Interrupt Status Register
( ISR )
Current Remote DMA Address 0
( CRDA0 )
Current Remote DMA Address 1
( CRDA1 )
Reserved
0BH
Reserved
0CH
Receive Status Register
( RSR )
Frame Alignment Errors
( CNTR0 )
CRC Errors
( CNTR1 )
Missed Packet Errors
( CNTR2 )
Data Port
01H
02H
03H
04H
05H
06H
07H
08H
09H
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
to
1EH
1FH
WRITE
Command Register
( CR )
Page Start Register
( PSTART )
Page Stop Register
( PSTOP )
Boundary Pointer
( BNRY )
Transmit Page Start Address
( TPSR )
Transmit Byte Count Register 0
( TBCR0 )
Transmit Byte Count Register 1
( TBCR1 )
Interrupt Status Register
( ISR )
Remote Start Address Register 0
( RSAR0 )
Remote Start Address Register 1
( RSAR1 )
Remote Byte Count 0
( RBCR0 )
Remote Byte Count 1
( RBCR1 0
Receive Configuration Register
( RCR )
Transmit Configuration Register ( TCR )
Data Configuration Register
( DCR )
Interrupt Mask Register
( IMR )
Data Port
IFGS1
IFGS2
MII/EEPROM Access
Inter-frame Gap (IFG)
Reserved
IFGS1
IFGS2
MII/EEPROM Access
Test Register
Inter-frame Gap (IFG)
Reserved
Reset
Reserved
Tab - 14 Page 0 of MAC Core Registers Mapping
18
ASIX ELECTRONICS CORPORATION
AX88190
PCMCIA Fast Ethernet MAC Controller
PAGE 1 (PS1=0,PS0=1)
OFFSET
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
to
1EH
1FH
READ
Command Register
( CR )
Physical Address Register 0
( PARA0 )
Physical Address Register 1
( PARA1 )
Physical Address Register 2
( PARA2 )
Physical Address Register 3
( PARA3 )
Physical Address Register 4
( PARA4 )
Physical Address Register 5
( PARA5 )
Current Page Register
( CPR )
Multicast Address Register 0
( MAR0 )
Multicast Address Register 1
( MAR1 )
Multicast Address Register 2
( MAR2 )
Multicast Address Register 3
( MAR3 )
Multicast Address Register 4
( MAR4 )
Multicast Address Register 5
( MAR5 )
Multicast Address Register 6
( MAR6 )
Multicast Address Register 7
( MAR7 )
Data Port
WRITE
Command Register
( CR )
Physical Address Register 0
( PAR0 )
Physical Address Register 1
( PAR1 )
Physical Address Register 2
( PAR2 )
Physical Address Register 3
( PAR3 )
Physical Address Register 4
( PAR4 )
Physical Address Register 5
( PAR5 )
Current Page Register
( CPR )
Multicast Address Register 0
( MAR0 )
Multicast Address Register 1
( MAR1 )
Multicast Address Register 2
( MAR2 )
Multicast Address Register 3
( MAR3 )
Multicast Address Register 4
( MAR4 )
Multicast Address Register 5
( MAR5 )
Multicast Address Register 6
( MAR6 )
Multicast Address Register 7
( MAR7 )
Data Port
Inter-frame Gap Segment 1
IFGS1
Inter-frame Gap Segment 2
IFGS2
MII/EEPROM Access
Inter-frame Gap (IFG)
Reserved
Inter-frame Gap Segment 1
IFGS1
Inter-frame Gap Segment 2
IFGS2
MII/EEPROM Access
Test Register
Inter-frame Gap (IFG)
Reserved
Reset
Reserved
Tab - 15 Page 1 of MAC Core Registers Mapping
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ASIX ELECTRONICS CORPORATION
AX88190
PCMCIA Fast Ethernet MAC Controller
4.3.1 Command Register (CR) Offset 00H (Read/Write)
FIELD
7:6
5:3
2
1
0
NAME
DESCRIPTION
PS1,PS0 PS1,PS0 : Page Select
The two bit selects which register page is to be accessed.
PS1
PS0
0 0
page 0
0 1
page 1
RD2,RD1 RD2,RD1,RD0 : Remote DMA Command
,RD0 These three encoded bits control operation of the Remote DMA channel. RD2 could be set
to abort any Remote DMA command in process. RD2 is reset by AX88190 when a Remote
DMA has been completed. The Remote Byte Count should be cleared when a Remote DMA
has been aborted. The Remote Start Address are not restored to the starting address if the
Remote DMA is aborted.
RD2 RD1 RD0
0
0
0
Not allowed
0
0
1
Remote Read
0
1
0
Remote Write
0
1
1
Not allowed
1
X
X
Abort / Complete Remote DMA
TXP TXP : Transmit Packet
This bit could be set to initiate transmission of a packet
START START :
This bit is used to active AX88190 operation.
STOP STOP : Stop AX88190
This bit is used to stop the AX88190 operation.
4.3.2 Interrupt Status Register (ISR) Offset 07H (Read/Write)
FIELD
7
6
5
4
3
2
1
0
NAME
DESCRIPTION
RST Reset Status :
Set when AX88190 enters reset state and cleared when a start command is issued to the
CR. Writing to this bit is no effect.
RDC Remote DMA Complete
Set when remote DMA operation has been completed
CNT Counter Overflow
Set when MSB of one or more of the Tally Counters has been set.
OVW OVERWRITE : Set when receive buffer ring storage resources have been exhausted.
TXE Transmit Error
Set when packet transmitted with one or more of the following errors
n Excessive collisions
n FIFO Under-run
RXE Receive Error
Indicates that a packet was received with one or more of the following errors
CRC error
Frame Alignment Error
FIFO Overrun
Missed Packet
PTX Packet Transmitted
Indicates packet transmitted with no error
PRX Packet Received
Indicates packet received with no error.
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ASIX ELECTRONICS CORPORATION
AX88190
PCMCIA Fast Ethernet MAC Controller
4.3.3 Interrupt mask register (IMR) Offset 0FH (Write)
FIELD
7
6
5
4
3
2
1
0
NAME
RDCE
CNTE
OVWE
TXEE
RXEE
PTXE
PRXE
DESCRIPTION
Reserved
DMA Complete Interrupt Enable. Default “low” disabled.
Counter Overflow Interrupt Enable. Default “low” disabled.
Overwrite Interrupt Enable. Default “low” disabled.
Transmit Error Interrupt Enable. Default “low” disabled.
Receive Error Interrupt Enable. Default “low” disabled.
Packet Transmitted Interrupt Enable. Default “low” disabled.
Packet Received Interrupt Enable. Default “low” disabled.
4.3.4 Data Configuration Register (DCR) Offset 0EH (Write)
FIELD
7
6:2
1
0
NAME
DESCRIPTION
RDCR Remote DMA always completed
Reserved
BOS Byte Order Select
0: MS byte placed on AD15:AD8 and LS byte on AD7-AD0 (80X86).
1: MS byte placed on AD7::AD0 and LS byte on AD15:AD0(68K)
WTS Word Transfer Select
0 : Selects byte-wide DMA transfers.
1 : Selects word-wide DMA transfers.
4.3.5 Transmit Configuration Register (TCR) Offset 0DH (Write)
FIELD
7
6
5
4:3
2:1
0
NAME
DESCRIPTION
FDU Full Duplex :
This bit indicates the current media mode is Full Duplex or not.
0 : Half duplex
1 : Full duplex
PD
Pad Disable
0 : Pad will be added when packet length less than 60.
1 : Pad will not be added when packet length less than 60.
RLO Retry of late collision
0 : Don’t retransmit packet when late collision happens.
1 : Retransmit packet when late collision happens.
Reserved
LB1,LB0 Encoded Loop-back Control
These encoded configuration bits set the type of loop-back that is to be performed.
LB1 LB0
Mode 0
0
0
Normal operation
Mode 1
0
1
Internal NIC loop-back
Mode 2
1
0
PHYcevisor loop-back
CRC Inhibit CRC
0 : CRC appended by transmitter.
1 : CRC inhibited by transmitter.
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ASIX ELECTRONICS CORPORATION
AX88190
PCMCIA Fast Ethernet MAC Controller
4.3.6 Transmit Status Register (TSR) Offset 04H (Read)
FIELD
7
6:4
3
2
1
0
NAME
DESCRIPTION
OWC Out of window collision
Reserved
ABT Transmit Aborted
Indicates the AX88190 aborted transmission because of excessive collision.
COL Transmit Collided
Indicates that the transmission collided at least once with another station on the network.
Reserved
PTX Packet Transmitted
Indicates transmission without error.
4.3.7 Receive Configuration (RCR) Offset 0CH (Write)
FIELD
7
6
5
4
3
2
1
0
NAME
DESCRIPTION
Reserved
INTT Interrupt Trigger Mode
Must be setting to “1”.
MON Monitor Mode
0 : Normal Operation
1 : Monitor Mode, the input packet will be checked on NODE ADDRESS and CRC but not
buffered into memory.
PRO PRO : Promiscuous Mode
Enable the receiver to accept all packets with a physical address.
AM
AM : Accept Multicast
Enable the receiver to accept packets with a multicast address. That multicast address must
pass the hashing array.
AB
AB : Accept Broadcast
Enable the receiver to accept broadcast packet.
AR
AR : Accept Runt
Enable the receiver to accept runt packet.
SEP
SEP : Save Error Packet
Enable the receiver to accept and save packets with error.
4.3.8 Receive Status Register (RSR) Offset 0CH (Read)
FIELD
7
6
5
4
3
2
1
0
NAME
DIS
PHY
MPA
FO
FAE
CR
PRX
DESCRIPTION
Reserved
Receiver Disabled
Multicast Address Received.
Missed Packet
FIFO Overrun
Frame alignment error.
CRC error.
Packet Received Intact
4.3.9 Inter-frame gap (IFG) Offset 16H (Read/Write)
FIELD
7
6:0
NAME
DESCRIPTION
Reserved
IFG
Inter-frame Gap. Default value 15H.
22
ASIX ELECTRONICS CORPORATION
AX88190
PCMCIA Fast Ethernet MAC Controller
4.3.10 Inter-frame gap Segment 1(IFGS1) Offset 12H (Read/Write)
FIELD
7
6:0
NAME
DESCRIPTION
Reserved
IFG
Inter-frame Gap Segment 1. Default value 0cH.
4.3.11 Inter-frame gap Segment 2(IFGS2) Offset 13H (Read/Write)
FIELD
7
6:0
NAME
DESCRIPTION
Reserved
IFG
Inter-frame Gap Segment 2. Default value 11H.
4.3.12 MII/EEPROM Management Register (MEMR) Offset 14H (Read/Write)
FIELD
7
6
5
4
3
2
1
0
NAME
DESCRIPTION
EECLK EECLK:
EEPROM Clock
EEO EEO : (Read only)
EEPROM Data Out value. That reflects Pin-109 EEDO value.
EEI
EEI
EEPROM Data In. That output to Pin-108 EEDI as EEPROM data input value.
EECS EECS
EEPROM Chip Select
MDO MDO
MII Data Out
MDI MDI: (Read only)
MII Data In. That reflects Pin-91 MDIO value.
MDIR MII STA MDIO signal Direction
MII Read Control Bit, assert this bit let MDIO signal as the input signal. Deassert this bit
let MDIO as output signal.
MDC MDC
MII Clock
4.3.13 Test Register (TR) Offset 15H (Write)
FIELD
7:5
4
3
2:0
NAME
TF16T
TPE
IFG
DESCRIPTION
Reserved
Test for Collision
Test pin Enable
Select Test Pins Output
23
ASIX ELECTRONICS CORPORATION
AX88190
PCMCIA Fast Ethernet MAC Controller
5.0 PCMCIA Device Access Functions
The AX88190 , as a PCMCIA I/O device , needs support both Attribute Memory access function
and I/O access function. The Access methods are described as the following sections.
5.1 Attribute Memory access function functions.
Attribute Memory Read function
Function Mode
REG#
Standby Mode
X
Byte Access (8 bits)
L
L
Word Access (16 bits)
L
Odd Byte Only Access
L
CE2#
H
H
H
L
L
CE1#
H
L
L
L
H
SA0
X
L
H
X
X
OE#
X
L
L
L
L
WE#
X
H
H
H
H
SD[15:8]
High-Z
High-Z
High-Z
Not Valid
Not Valid
SD[7:0]
High-Z
Even-Byte
Not Valid
Even-Byte
High-Z
Attribute Memory Write function
Function Mode
REG#
Standby Mode
X
Byte Access (8 bits)
L
L
Word Access (16 bits)
L
Odd Byte Only Access
L
CE2#
H
H
H
L
L
CE1#
H
L
L
L
H
SA0
X
L
H
X
X
OE#
X
H
H
H
H
WE#
X
L
L
L
L
SD[15:8]
X
X
X
X
X
SD[7:0]
X
Even-Byte
X
Even-Byte
X
OE#
X
L
L
L
L
L
WE#
X
H
H
H
H
H
SD[15:8]
High-Z
High-Z
High-Z
Odd-Byte
High-Z
Odd-Byte
SD[7:0]
High-Z
Even-Byte
Odd-Byte
Even-Byte
High-Z
High-Z
SD[15:8]
X
X
X
Odd-Byte
X
Odd-Byte
SD[7:0]
X
Even-Byte
Odd-Byte
Even-Byte
X
X
5.2 I/O access function functions.
I/O Read function
Function Mode
Standby Mode
Byte Access (8 bits)
Word Access (16 bits)
I/O Inhibit
Odd Byte Only Access
I/O Write function
Function Mode
Standby Mode
Byte Access (8 bits)
Word Access (16 bits)
I/O Inhibit
Odd Byte Only Access
REG#
X
L
L
L
H
L
CE2#
H
H
H
L
X
L
CE1#
H
L
L
L
X
H
SA0
X
L
H
L
X
X
REG#
X
L
L
L
H
L
CE2#
H
H
H
L
X
L
CE1#
H
L
L
L
X
H
SA0
X
L
H
L
X
X
24
IORD# IOWR#
X
X
H
L
H
L
H
L
H
L
H
L
ASIX ELECTRONICS CORPORATION
AX88190
PCMCIA Fast Ethernet MAC Controller
6.0 Electrical Specification and Timings
6.1 Absolute Maximum Ratings
Description
SYM
Min
Max
Units
Ta
0
+85
°C
Ts
-55
+150
°C
HVdd
-0.3
+6
V
LVdd
-0.3
+4.6
V
HVin
-0.3
HVdd+0.5
V
LVin
-0.3
LVdd+0.5
V
Output Voltage
HVout
-0.3
HVdd+0.5
V
LVin
-0.3
LVdd+0.5
V
Lead Temperature (soldering 10 seconds maximum)
Tl
-55
+220
°C
Note : Stress above those listed under Absolute Maximum Ratings may cause permanent damage to the device.
Exposure to Absolute Maximum Ratings conditions for extended period, adversely affect device life and reliability.
Note : The power supply voltages must always fulfill HVdd >= LVdd inequality.
Operating Temperature
Storage Temperature
Supply Voltage
Supply Voltage
Input Voltage
6.2 General Operation Conditions
Description
Operating Temperature
Supply Voltage
SYM
Min
Ta
0
HVdd +4.75V
LVdd +2.70
+3.00
Tpy
25
+5.00V
+3.00
+3.30
Max
+75
+5.25V
+3.30
+3.60
Units
°C
V
V
V
Max
Units
V
V
V
V
uA
uA
Max
Units
V
V
V
V
uA
uA
Max
Units
mA
mA
mA
Note : The power supply voltages must always fulfill HVdd >= LVdd inequality.
6.3 DC Characteristics
(Vdd=5.0V, Vss=0V, Ta=0°C to 75°C)
Description
Low Input Voltage
High Input Voltage
Low Output Voltage
High Output Voltage
Input Leakage Current
Output Leakage Current
SYM
Vil
Vih
Vol
Voh
Iil
Iol
Min
2
Vdd-0.4
-1
-1
Tpy
(Vdd=3.0V to 3.6V, Vss=0V, Ta=0°C to 75°C)
Description
Low Input Voltage
High Input Voltage
Low Output Voltage
High Output Voltage
Input Leakage Current
Output Leakage Current
SYM
Vil
Vih
Vol
Voh
Iil
Iol
Min
1.9
Vdd-0.4
-1
-1
Tpy
SYM
DPt5v
DPt3v
SPt3v
Min
Description
Power Consumption (Dual power)
Power Consumption (Single power 3.3V)
25
0.8
0.4
+1
+1
0.8
0.4
+1
+1
Tpy
22
40
48
ASIX ELECTRONICS CORPORATION
AX88190
PCMCIA Fast Ethernet MAC Controller
6.4 A.C. Timing Characteristics
6.4.1 XTAL / CLOCK
Thigh
LCLK/XTALIN
Tr
Tf
Tlow
Tcyc
CLK25M
Tod
Symbol
Tcyc
Thigh
Tlow
Tr/Tf
Tod
Description
Min
CYCLE TIME
CLK HIGH TIME
CLK LOW TIME
CLK SLEW RATE
LCLK/XTALIN TO CLK25M OUT DELAY
16
16
1
Typ.
40
20
20
10
Max
24
24
4
Units
ns
ns
ns
ns
Typ.
-
Max
-
Units
LClk
6.4.2 Reset Timing
LCLK
RESET
Symbol
Trst
Description
Min
100
Reset pulse width
26
ASIX ELECTRONICS CORPORATION
AX88190
PCMCIA Fast Ethernet MAC Controller
6.4.3 Attribute Memory Read Timing
TcR
Ta(A)
Th(A)
A[9:0], REG#
Ta(CE)
Tsu(CE)
Tv(A)
CE#
Tsu(A)
Ta(OE)
Th(CE)
OE#
Tv(WT-OE)
Tw(WT)
Tdis(CE)
WAIT#
Ten(OE)
Tv(WT)
Tdis(OE)
D[15:0]
Symbol
TcR
Ta(A)
Ta(CE)
Ta(OE)
Tdis(OE)
Ten(OE)
Tv(A)
Tsu(A)
Th(A)
Tsu(CE)
Th(CE)
Tv(WT-OE)
Tw(WT)
Tv(WT)
DATA Valid
Description
Min
300
0.5
0
30
20
0
20
100
READ CYCLE TIME
ADDRESS ACCESS TIME
CARD ENABLE ACCESS TIME
OUTPUT ENABLE ACCESS TIME
OUTPUT DISABLE TIME FROM OE#
OUTPUT ENABLE TIME FROM OE#
DATA VALID FROM ADDRESS CHANGE
ADDRESS SETUP TIME
ADDRESS HOLD TIME
CARD ENABLE SETUP TIME
CARD ENABLE HOLD TIME
WAIT# VALID FROM OE#
WAIT# PULSE WIDTH
DATA SETUP FOR WAIT# RELEASED
27
Typ.
-
Max
120
100
100
100
10
200
-
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ASIX ELECTRONICS CORPORATION
AX88190
PCMCIA Fast Ethernet MAC Controller
6.4.4 Attribute Memory Write Timing
TcW
A[9:0], REG#
Tsu(CE-WEH)
CE#
Tsu(CE)
Tsu(A-WEH)
Th(CE)
OE#
Tsu(A)
Tw(WE)
Trec(WE)
WE#
Tv(WT-WE)
Tw(WT)
Tv(WT)
Th(OE-WE)
WAIT#
Tsu(OE-WE)
Tsu(D-WEH)
D[15:0](Din)
Th(D)
DATA Input Establish
Tdis(WE)
Tdis(OE)
Ten(OE)
Ten(WE)
D[15:0](Dout)
Symbol
TcW
Tw(WE)
Tsu(A)
Tsu(A-WEH)
Tsu(CE-WEH)
Tsu(D-WEH)
Th(D)
Trec(WE)
Tdis(WE)
Tdis(OE)
Ten(WE)
Ten(OE)
Tsu(OE-WE)
Th(OE-WE)
Tsu(CE)
Th(CE)
Tv(WT-WE)
Tw(WT)
Tv(WT)
Description
WRITE CYCLE TIME
WRITE PULSE WIDTH
ADDRESS SETUP TIME
ADDRESS SETUP TIME FOR WE#
CARD ENABLE SETUP TIME FOR WE#
DATA SETUP TIME FOR WE#
DATA HOLD TIME
WRITE RECOVER TIME
OUTPUT DISABLE TIME FROM WE#
OUTPUT DISABLE TIME FROM OE#
OUTPUT ENABLE TIME FROM WE#
OUTPUT ENABLE TIME FROM OE#
OUTPUT ENABLE SETUP TIME FROM OE#
OUTPUT ENABLE HOLD TIME FROM OE#
CARD ENABLE SETUP TIME
CARD ENABLE HOLD TIME
WAIT# VALID FROM WE#
WAIT# PULSE WIDTH
WE# HIGH FROM WAIT# RELEASED
28
Min
250
150
30
180
180
80
30
30
5
5
10
10
0
20
0
Typ.
-
Max
5
5
15
200
-
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ASIX ELECTRONICS CORPORATION
AX88190
PCMCIA Fast Ethernet MAC Controller
6.4.5 I/O Read Timing
A[9:0]
TsuREG
ThA
ThREG
TsuCE
ThCE
REG#
CE#
Tw
IORD#
TsuA
TdrINPACK
INPACK#
TdfINPACK
TdrIOIS16
IOIS16#
TdfIOIS16
Td
Tdr(WT)
WAIT#
TdfWT
Tw(WT)
D[15:0]
Symbol
Td
Th
Tw
TsuA
ThA
TsuCE
ThCE
TsuREG
ThREG
TdfINPACK
TdrINPACK
TdfIOIS16
TdrIOIS16
TdfWT
Tdr(WT)
Tw(WT)
Th
DATA Valid
Description
DATA DELAY AFTER IORD#
DATA HOLD FOLLOWING IORD#
IORD# WIDTH TIME
ADDRESS SETUP BEFORE IORD#
ADDRESS HOLD BEFORE IORD#
CE# SETUP BEFORE IORD#
CE# HOLD BEFORE IORD#
REG# SETUP BEFORE IORD#
REG# HOLD BEFORE IORD#
INPACK# DELAY FALLING FROM IORD#
INPACK# DELAY RISING FROM IORD#
IOIS16# DELAY FALLING FROM ADDRESS*
IOIS16# DELAY RISING FROM ADDRESS*
WAIT# DELAY FALLING FROM IORD#
DATA DELAY FROM WAIT# RISING
WAIT# WIDTH TIME
Min
0.5
165
70
20
5
20
5
0
0
-
Typ.
-
Max
50
10
10
10
0
5
0
100
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
us
ns
* Note : The address includes REG# and CE1# signal
29
ASIX ELECTRONICS CORPORATION
AX88190
PCMCIA Fast Ethernet MAC Controller
6.4.6 I/O Write Timing
A[9:0]
TsuREG
ThA
ThREG
TsuCE
ThCE
REG#
CE#
Tw
IOWR#
TsuA
TdrIOIS16
IOIS16#
TdfIOIS16
TdrIOWR
WAIT#
TdfWT
Tw(WT)
Th
Tsu
D[15:0]
Symbol
Tsu
Th
Tw
TsuA
ThA
TsuCE
ThCE
TsuREG
ThREG
TdfIOIS16
TdrIOIS16
TdfWT
Tw(WT)
TdrIOWR
DATA
Description
DATA SETUP BEFORE IOWR#
DATA HOLD FOLLOWING IOWR#
IOWR# WIDTH TIME
ADDRESS SETUP BEFORE IOWR#
ADDRESS HOLD BEFORE IOWR#
CE# SETUP BEFORE IOWR#
CE# HOLD BEFORE IOWR#
REG# SETUP BEFORE IOWR#
REG# HOLD BEFORE IOWR#
IOIS16# DELAY FALLING FROM ADDRESS*
IOIS16# DELAY RISING FROM ADDRESS*
WAIT# DELAY FALLING FROM IOWR#
WAIT# WIDTH TIME
IOWR# HIGH FROM WAIT# HIGH
Min
60
30
165
70
20
5
20
5
0
0
Typ.
-
Max
10
0
**
**
-
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
us
*Note : The address includes REG# and CE1# signal
** Note : There is no wait state while I/O Write operation
30
ASIX ELECTRONICS CORPORATION
AX88190
PCMCIA Fast Ethernet MAC Controller
6.4.7 MII Timing
Ttclk
Ttch
Ttcl
TXCLK
Ttv
Tth
TXD<3:0>
TXEN
Trclk
Trch
Trcl
RXCLK
Trs
Trh
RXD<3:0>
RXDV
Trs1
RXER
Symbol
Ttclk
Ttclk
Ttch
Ttch
Trch
Trch
Ttv
Tth
Trclk
Trclk
Trch
Trch
Trcl
Trcl
Trs
Trh
Trs1
Description
Min
14
140
14
140
5
14
140
14
140
6
10
10
Cycle time(100Mbps)
Cycle time(10Mbps)
high time(100Mbps)
high time(10Mbps)
low time(100Mbps)
low time(10Mbps)
Clock to data valid
Data output hold time
Cycle time(100Mbps)
Cycle time(10Mbps)
high time(100Mbps)
high time(10Mbps)
low time(100Mbps)
low time(10Mbps)
data setup time
data hold time
RXER data setup time
31
Typ.
40
400
40
400
-
Max
26
260
26
260
20
26
260
26
260
-
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ASIX ELECTRONICS CORPORATION
AX88190
PCMCIA Fast Ethernet MAC Controller
6.4.8 Asynchronous Memory I/F Access Timing
MEMORY WRITE
Tsu(A)
Th(A)
MEMA[15:1]
Tw(WR)
/MEMWR
Td(WtoR)
Tw(RDdis)
/MEMRD
Tsu(D)
Write Data
SD[15:0](Dout)
DATA Valid
Symbol
Tsu(A)
Th(A)
Tw(WR)
Tw(RDdis)
Td(WtoR)
Tsu(D)
Th(D)
Th(D)
Description
Min
36
0.3
ADDRESS SETUP TIME
ADDRESS HOLD TIME
WRITE PULSE WIDTH
READ DISABLE PULSE WIDTH
WRITE TO READ DEALY
DATA SETUP TIME
DATA HOLD TIME
1
16
0.3
Typ.
*
*
-
Max
1
4.5
2
Units
ns
ns
ns
ns
ns
ns
ns
MEMORY READ
Tsu(A)
Th(A)
MEMA[15:1]
Referance
Internal
“/MEMRD”
Tw(RD)
( High Level )
/MEMWR
( Low Level )
/MEMRD
Tsu(RD)
Read Data
MEMD[15:1]
Symbol
Th(RD)
Valid DATA
Typ.
Max
Units
ns
1
ns
*
ns
3
ns
0
2
ns
* NOTE : The pulse width can be seen as LCLK/XTALIN high time. See also 6.4.1 “Thigh” parameter.
NOTE : All most any brand asynchronous SRAM access time under 20 ns can fit into the specification.
Tsu(A)
Th(A)
Tw(RD)
Tsu(D)
Th(D)
Description
Min
30
1.3
ADDRESS SETUP TIME
ADDRESS HOLD TIME
READ PULSE WIDTH
DATA SETUP TIME
DATA HOLD TIME
32
ASIX ELECTRONICS CORPORATION
AX88190
PCMCIA Fast Ethernet MAC Controller
7.0 Package Information
A
A2
A1
L
L1
D
Hd
He
E
pin 1
e
b
θ
SYMBOL
MILIMETER
MIN.
A1
A2
NOM
MAX
0.1
1.3
1.4
A
1.5
1.7
b
0.155
0.16
0.26
D
13.90
14.00
14.10
E
13.90
14.00
14.10
e
0.40
Hd
15.60
16.00
16.40
He
15.60
16.00
16.40
L
0.30
0.50
0.70
L1
θ
1.00
0
10
33
ASIX ELECTRONICS CORPORATION
AX88190
PCMCIA Fast Ethernet MAC Controller
Appendix A: Application Note 1
A.1 Using Crystal
AX88190
To PHY
CLKO25M
XTALIN
XTALOUT
25MHz
Crystal
8pf
2Mohm
8pf
Note : The capacitors (8pf) may be various depend on the specification of crystal. While designing,
please refer to the suggest circuit provided by crystal supplier.
A.2 Using Oscillator
AX88190
To PHY
CLKO25M
XTALIN
3.3V Power OSC
XTALOUT
NC
25MHz
34
ASIX ELECTRONICS CORPORATION
AX88190
PCMCIA Fast Ethernet MAC Controller
A.3 Dual power (5V and 3.3V) application
RJ11
+5V
+5V
RJ45
DAA
MAGNETIC
MODEM
PHY/TxRx
HVdd
+5V
+3.3V
(option for core logic)
EEPROM
AX88190
+3.3V LVdd
SRAM
+5V
+5V
+5V PCMCIA I/F
A.4 Single power (3.3V) application
RJ11
+3.3V
RJ45
DAA
MAGNETIC
MODEM
PHY/TxRx
+3.3V HVdd
+3.3V LVdd
+3.3V
EEPROM
AX88190
SRAM
+3.3V
+3.3V
+3.3V PCMCIA I/F
35
ASIX ELECTRONICS CORPORATION
AX88190
PCMCIA Fast Ethernet MAC Controller
A.5 Dual power (5V and 3.3V) application with 3.3V PHY
The 510 and 1K Ohm resisters are just for voltage adjustment
RXD[3:0]
CRS
RX_DV
RX_ER
RX_CLK
COL
TX_EN
TXD[3:0]
TX_CLK
MDC
MDIO
AX88190
RXD[3:0]
CRS
RX_DV
RX_ER
RX_CLK
COL
TX_EN
TXD[3:0]
TX_CLK
MDC
MDIO
510 ohm
36
1k ohm
PHY
ASIX ELECTRONICS CORPORATION
AX88190
PCMCIA Fast Ethernet MAC Controller
Appendix B: Application Note 2
B.1 Advance Application for Using Crystal
Date: May 21, 1999
Condition: In short cable, AX88190 +AH 101 Phyceiver can’t link to BCM 5308
Switch.
Conclusion: 1. After measuring and verifying, we found it’s relevant to clock
source.
2. We ascertain the problem is caused by matching issues between
crystal and capacitor.
Solution: Change the value of capacitors beside crystal as below:
Y1
XIN
XOUT
25MHZ
R4
2M
C22
18p
C23
18p
Note: The capacitors may be various depend on the specification of crystal.
While designing, please refer to the circuit provided by crystal supplier.
37
ASIX ELECTRONICS CORPORATION
AX88190
PCMCIA Fast Ethernet MAC Controller
Errata of AX88190 V1
1. OE# synchronous problem result in PC hang
Solution : Using hardware CKT to pre-sync OE# signal as below.
CLK25M
12
1
3
11
2
D
PR
U2A
Q
CL
10
From AX88190
Pin 101
Q
U1B
74F74
9
CLK
8
D
Q
Q
U1A
74F74
5
OE_M#
To AX88190
Pin 16
CLK
6
1
3
PR
2
OE_#
From PCMCIA
Connector
Pin 9
CL
4
13
74F86
Jumper for future use
2. Interrupt Status can’t always clean up
Solution : Using software to do clean and check iteration until clean up.
Ex : IOBASE=300 ; Clear Tx/Rx interrupt.
Mov dx,307h
ClrISR :
ClrISRDone:
Mov al,3
Out dx,al
In al,dx
Test al,3
Jz ClrISRDone
Mov al,0
Out dx,al
Jmp ClrISR
…
; clear Tx/Rx interrupt
; output to clear ISR
; read ISR
; Check ISR cleared or not
; Clear ok
; if not, clear again
; clear successful
3. CE1# Bus decoder problem
Solution : Dis-connect AX88190 CE1# (pin 18) from PCMCIA connector CE1#
(pin 7). And connect AX88190 CE1# (pin 18) to logic “0” always
enable this signal.
38
ASIX ELECTRONICS CORPORATION
ASIX
AX88190
PCMCIA Fast Ethernet MAC Controller
(AX88190 APPLICATION USED LUC6612)
U4
R4
0
RESET
WAIT#
INPACK#
REG#
SPKR#
STSCHG#
SD8
SD9
SD10
GND
GND
PCMCIA
U8
1
2
3
4
EECS
EESK
EEDI
EEDO
CS
SK
DI
DO
VCC
NC
NC
GND
8
7
6
5
VDD
GND
93C56R
Y1
XIN
XOUT
25MHZ
R6
2M
C22
8p
SD4
GND
SD3
SD2
SD1
SD0
GND
GND
MEMWR#
MEMRD#
MA15
LVDD
MA14
MA13
MA12
MA11
GND
MA10
MA9
MA8
MA7
LVDD
MA6
MA5
MA4
MA3
GND
MA2
MA1
MD15
MD14
VDD
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
C23
8p
SD[4]
VSS
SD[3]
SD[2]
SD[1]
SD[0]
VSS
VSS
MEMWR#
MEMRD#
MEMA[15]
LVDD
MEMA[14]
MEMA[13]
MEMA[12]
MEMA[11]
VSS
MEMA[10]
MEMA[9]
MEMA[8]
MEMA[7]
LVDD
MEMA[6]
MEMA[5]
MEMA[4]
MEMA[3]
VSS
MEMA[2]
MEMA[1]
MEMD[15]
MEMD[14]
HVDD
TXD[0]
TX_EN
TX_CLK
VSS
MDC
MDIO
RXD[3]
RXD[2]
RXD[1]
RXD[0]
RX_CLK
CRS
COL
RX_DV
RX_ER
VSS
MEMD[0]
MEMD[1]
MEMD[2]
MEMD[3]
MEMD[4]
HVDD
MEMD[5]
MEMD[6]
MEMD[7]
MEMD[8]
MEMD[9]
VSS
MEMD[11]
MEMD[11]
MEMD[12]
MEMD[13]
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
LVDD
RESET
LVDD
WAIT#
INPACK#
REG#
SPKR#
STSCHG#
IOIS16#
GND
MEMRD#
MA12
MA10
MA9
MA14
MEMWR#
VDD
MA15
MA13
MA8
MA7
MA6
MA5
MA4
22
23
24
25
26
27
28
1
2
3
4
5
6
7
21
20
19
18
17
16
15
14
13
12
11
10
9
8
MA11
GND
MD7
MD6
MD5
MD4
MD3
GND
MD2
MD1
MD0
MA1
MA2
MA3
IS61C256AH
RESET#
R1
U5
(OPTION FOR TEST)
10K
LVDD
EEDO
EEDI
EESK
EECS
GND
XOUT
XIN
GND
R2
LVDD
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
PCLK
20
TXD3
TXD2
TXD1
#OE
A11
A9
A8
A13
#WE
VCC
A14
A12
A7
A6
A5
A4
A3
A10
#CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
IS61C256AH
C21
8p
TXD0
TXEN
TXCLK
GND
MDC
MDIO
RXD3
RXD2
RXD1
RXD0
RXCLK
CRS
COL
RXDV
RXER
GND
MD0
MD1
MD2
MD3
MD4
VDD
MD5
MD6
MD7
MD8
MD9
GND
MD10
MD11
MD12
MD13
U7A
4
VDD
LVDD
RESET
LVDD
WAIT#
INPACK#
REG#
SPKR#
STSCHG#
IOIS16#
VSS
MRDY
MRESET#
MPWDN
MRIN#
PPWDN
MAUDIO
MINT
MDCS#
LVDD
EEDO
EEDI
EECK
EECS
VSS
XTALOUT
LCLK/XT ALIN
VSS
CLKO25M
LVDD
TXD[3]
TXD[2]
TXD[1]
2
U6A
1
PCLK
3
3
2
D
PR
GND
IORD#
IOWR#
SA[0]
SA[1]
SA[2]
SA[3]
SA[4]
SA[5]
SA[6]
SA[7]
SA[8]
SA[9]
VSS
IREQ#
WE#
IOWR#
IORD#
OE#
CE2#
CE1#
HVDD
SD[15]
SD[14]
SD[13]
SD[12]
VSS
SD[11]
SD[10]
SD[9]
SD[8]
HVDD
SD[7]
SD[6]
SD[5]
Q
CL
SA7
SA6
SA5
SA4
SA3
SA2
SA1
SA0
SD0
SD1
SD2
IOIS16#
GND
VDD
SD15
SD14
SD13
SD12
GND
SD11
SD10
SD9
SD8
VDD
SD7
SD6
SD5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
GND
IREQ#
WE#
IOWR#
IORD#
OE_M#
CE2#
MA11
GND
MD15
MD14
MD13
MD12
MD11
GND
MD10
MD9
MD8
MA1
MA2
MA3
Q
5
CLK
74F86
6
74F74
1
VDD
GND
GND
SD11
SD12
SD13
SD14
SD15
CE2#
21
20
19
18
17
16
15
14
13
12
11
10
9
8
10
WE#
IREQ#
VDD
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
A10
#CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
12
OE#
11
D
U7B
PR
SA9
SA8
GND
CD1#
D11
D12
D13
D14
D15
CE2#
VS1#
IORD#
IOWR#
A17
A18
A19
A20
A21
VCC
VPP2
A22
A23
A24
A25
VS2#
RESET
WAIT#
INPACK#
REG#
SPKR#
STSCHG#
D8
D9
D10
CD2#
GND
#OE
A11
A9
A8
A13
#WE
VCC
A14
A12
A7
A6
A5
A4
A3
Q
Q
9
OE_M#
CLK
8
74F74
13
OE#
U2
GND
D3
D4
D5
D6
D7
CE1#
A10
OE#
A11
A9
A8
A13
A14
WE#
IREQ#
VCC
VPP1
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
IOIS16#
GND
22
23
24
25
26
27
28
1
2
3
4
5
6
7
CL
U1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
GND
SD3
SD4
SD5
SD6
SD7
MEMRD#
MA12
MA10
MA9
MA14
MEMWR#
VDD
MA15
MA13
MA8
MA7
MA6
MA5
MA4
AX88190
VDD
U9
VDD
GND
4.7u/16V
+
C29
+
C4
C28
0.01u
C1
0.01u
4
2
1
TAB
VIN
VSS
+
VOUT
3
LVDD
C5
0.01u
C6
C7
C8
C9
C10
C11
C24
C25
C26
C27
0.1u
0.1u
0.1u
0.1u
0.1u
0.1u
0.1u
0.1u
0.1u
0.1u
C14
C15
C16
C17
C18
C19
0.1u
0.1u
0.1u
0.1u
0.1u
0.1u
|LINK
|190LU1A1.SCH
GND
+
XC62FP
4.7u/16V
C12
C2
C3
0.01u
4.7u/16V
ASIX ELECTRONICS CORPORATION
LVDD
4.7u/16V
+
C20
C13
0.01u
Title
PCMCIA BUS & AX88190 & MEMORY
GND
4.7u/16V
ASIX ELECTRONICS CORPORATION
2F, NO.13, Industry East Rd. II, Science-based Industrial Park, Hsin-Chu City, Taiwan, R.O.C.
TEL: 886-3-579-9500
FAX: 886-3-579-9558
http://www.asix.com.tw
Size
B
Document Number
190LU1A. SCH
Date:
Tuesday, December 15, 1998
Rev
1.0
Sheet
1
of
3
AX88190
PCMCIA Fast Ethernet MAC Controller
U10
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
VDDA
R7
GND
GND
LLED
ALED
VDD
GND
TDP
TDN
GND
VDDA
24.9K
GND
VDDA
GND
GND
C30
1000p
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
PAD4
GND
VDDPLL
R10
4.7K
PCLK
GND
R8
GND
22.1K
MDIO
MDC
RESET#
VDD
GND
TXEN
TXD3
TXD2
VCCBG
ISET_100
GNDBG
LED_LINK/PHAD0
LED_ACT/PHAD1
VCCIOA
GNDIOA
TD+
TDGNDT
VCCT
CLKREF
GNDBT
VCCBT
TEST0
TEST1
GNDEQAP
RD+
RDVCCEQAP
VCCREC
GNDREC
BGREF0
BGREF1
LED_SPD/PHAD2
LED_FDX/PHAD3
VCCIOB
GNDIOB
MODE2
MODE1
MODE0
VCCDIGB
PHAD4
PCSEN#
TEST2
VCCPLL
LSCLK1
LSCLK2
GNDPLL
ISET_10
MDIO
MDC
RESET#
RX_EN
TX_ER/T XD4
TX_EN
TXD3
TXD2
GNDDIGB
TX_CLK
RX_ER/RXD4
RX_DV
RX_CLK
COL
CRS
GNDIOC
RXD0
RXD1
RXD2
RXD3
GNDDIGA
VCCDIGA
TXD0
TXD1
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
GND
RDP
RDN
VDDA
Set PHY ADDRESS TO 10000
GND
R11
SLED
FLED
VDD
GND
R12
PAD4
PHYAD4
FLED
PHYAD3
SLED
PHYAD2
ALED
PHYAD1
LLED
PHYAD0
24.9k
24.9K
R28
10K
R29
10K
R27
10K
R26
10K
R25
10K
VDD
GND
VDD
GND
R23
C32
8p
To PCMJ15 Connect
TXCLK
RXER
RXDV
33
R24
COL
CRS
33
RXCLK
GND
GND
VDD
C33
8p
RXD0
RXD1
RXD2
RXD3
FLED
R30
510
FDLED
SLED
R31
510
SPLED
ALED
R32
510
ACLED
LLED
R33
510
LILED
TXD0
TXD1
LUC6612
BY PASS CAP WITH DIGITAL POWER SUPPLY
VDD
VDD
C38
GND
R18
220
C41
C42
C43
C44
0.1u
0.1u
0.1u
0.1u
0.1u
C51
C46
C47
C48
C49
C50
0.01u
0.1u
0.1u
0.1u
0.1u
0.1u
4.7u/16V
C52
0.1u
L1
R14
49.9
VDD
VDDA
FB
J1
1
2
3
TDP
TDN
5
6
7
RDP
RDN
R16
49.9
14
13
12
CT
TD+
TD-
CT
TX+
TX-
RD+
RDCT
10
RX+ 9
RX- 8
CT
14ST9012P
R19
75
R20
75
C36
C31
0.01u
C40
0.01u
GND
U11
R15
49.9
C39
BY PASS CAP WITH ANALOG POWER SUPPLY
R17
220
R13
49.9
+
C35
0.01u
0.01u
C37
C53
0.01u/2KV
R21
75
R22
75
SPLED
LILED
GND
ACLED
FDLED
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
C45
+
GND
4.7u/16V
L2
VDD
VDDPLL
FB
C34
0.1u
ASIX ELECTRONICS CO.
Title
LUCENT LUC6612 PHY
PCMJ15
CHASSIS
0.01u
40
Size
B
Document Number
190LU1A1.SCH
Date:
Tuesday, December 15, 1998
Rev
1.0
Sheet
2
of
3
ASIX ELECTRONICS CORPORATION
AX88190
PCMCIA Fast Ethernet MAC Controller
J3
J2
1
2
3
4
5
6
7
8
9
10
11
12
1
2
3
6
4
5
7
8
RJ45N
CON12
D1
LED
SPLED
C54
D2
LED
LILED
0.01
D3
LED
ACLED
D4
LED
FDLED
CHASSIS
ASIX ELECTRONICS CORPORATION
Title
RJ45 & LED
Size
A
Document Number
190LED.SCH
Date:
Tuesday , December 15, 1998
41
Rev
1.0
Sheet
3
of
3
ASIX ELECTRONICS CORPORATION