GS816018/32/36DGT-400/375/333/250/200/150 400 MHz–150 MHz 2.5 V or 3.3 V VDD 2.5 V or 3.3 V I/O 1M x 18, 512K x 32, 512K x 36 18Mb Sync Burst SRAMs 100-Pin TQFP Commercial Temp Industrial Temp Features • FT pin for user-configurable flow through or pipeline operation • Single Cycle Deselect (SCD) operation • 2.5 V or 3.3 V +10%/–10% core power supply • 2.5 V or 3.3 V I/O supply • LBO pin for Linear or Interleaved Burst mode • Internal input resistors on mode pins allow floating mode pins • Default to Interleaved Pipeline mode • Byte Write (BW) and/or Global Write (GW) operation • Internal self-timed write cycle • Automatic power-down for portable applications • RoHS-compliant 100-lead TQFP package available Functional Description cycles can be initiated with either ADSP or ADSC inputs. In Burst mode, subsequent burst addresses are generated internally and are controlled by ADV. The burst address counter may be configured to count in either linear or interleave order with the Linear Burst Order (LBO) input. The Burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance. Flow Through/Pipeline Reads The function of the Data Output register can be controlled by the user via the FT mode pin (Pin 14). Holding the FT mode pin low places the RAM in Flow Through mode, causing output data to bypass the Data Output Register. Holding FT high places the RAM in Pipeline mode, activating the risingedge-triggered Data Output Register. Byte Write and Global Write Byte write operation is performed by using Byte Write enable (BW) input combined with one or more individual byte write signals (Bx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the Byte Write control inputs. Applications The GS816018/32/36DGT is an 18,874,368-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support. Sleep Mode Low power (Sleep mode) is attained through the assertion (High) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode. Controls Addresses, data I/Os, chip enables (E1, E2, E3), address burst control inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW, GW) are synchronous and are controlled by a positive-edge-triggered clock input (CK). Output enable (G) and power down control (ZZ) are asynchronous inputs. Burst Core and Interface Voltages The GS816018/32/36DGT operates on a 3.3 V or 2.5 V power supply. All input are 3.3 V and 2.5 V compatible. Separate output power (VDDQ) pins are used to decouple output noise from the internal circuits and are 3.3 V and 2.5 V compatible. Parameter Synopsis Pipeline 3-1-1-1 Flow Through 2-1-1-1 Rev: 1.03a 9/2013 tKQ tCycle Curr (x18) Curr (x32/x36) tKQ tCycle Curr (x18) Curr (x32/x36) -400 2.5 2.5 -375 2.5 2.66 -333 2.5 3.3 -250 2.5 4.0 -200 3.0 5.0 -150 3.8 6.7 Unit ns ns 370 430 350 410 310 365 250 290 210 240 185 200 mA mA 4.0 4.0 275 315 4.2 4.2 265 300 4.5 4.5 255 285 5.5 5.5 220 250 6.5 6.5 205 225 7.5 7.5 190 205 ns ns mA mA 1/24 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2011, GSI Technology GS816018/32/36DGT-400/375/333/250/200/150 A A E1 E2 NC NC BB BA E3 VDD VSS CK GW BW G ADSC ADSP ADV A A GS816018D 100-Pin TQFP Pinout NC NC NC VDDQ A NC NC VDDQ VSS NC DQPA DQA DQA VSS VDDQ DQA DQA VSS NC VDD ZZ DQA DQA VDDQ VSS DQA DQA NC NC VSS VDDQ NC NC NC LBO A A A A A1 A0 NC NC VSS VDD A A A A A A A A A VSS NC NC DQB DQB VSS VDDQ DQB DQB FT VDD NC VSS DQB DQB VDDQ VSS DQB DQB DQPB NC VSS VDDQ NC NC NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 1M x 18 10 71 Top View 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Rev: 1.03a 9/2013 2/24 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2011, GSI Technology GS816018/32/36DGT-400/375/333/250/200/150 A A E1 E2 BD BC BB BA E3 VDD VSS CK GW BW G ADSC ADSP ADV A A GS816032D 100-Pin TQFP Pinout NC DQC DQC VDDQ VSS DQC DQC DQC DQC VSS VDDQ DQC DQC NC DQB DQB VDDQ VSS DQB DQB DQB DQB VSS VDDQ DQB DQB VSS NC VDD ZZ DQA DQA VDDQ VSS DQA DQA DQA DQA VSS VDDQ DQA DQA NC LBO A A A A A1 A0 NC NC VSS VDD A A A A A A A A A FT VDD NC VSS DQD DQD VDDQ VSS DQD3 DQD DQD DQD VSS VDDQ DQD DQD NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 512K x 32 10 71 Top View 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Rev: 1.03a 9/2013 3/24 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2011, GSI Technology GS816018/32/36DGT-400/375/333/250/200/150 A A E1 E2 BD BC BB BA E3 VDD VSS CK GW BW G ADSC ADSP ADV A A GS816036D 100-Pin TQFP Pinout DQPC DQC DQC VDDQ VSS DQC DQC DQC DQC VSS VDDQ DQC DQC DQPB DQB DQB VDDQ VSS DQB DQB DQB DQB VSS VDDQ DQB DQB VSS NC VDD ZZ DQA DQA VDDQ VSS DQA DQA DQA DQA VSS VDDQ DQA DQA DQPA LBO A A A A A1 A0 NC NC VSS VDD A A A A A A A A A FT VDD NC VSS DQD DQD VDDQ VSS DQD3 DQD DQD DQD VSS VDDQ DQD DQD DQPD 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 512K x 36 10 71 Top View 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Rev: 1.03a 9/2013 4/24 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2011, GSI Technology GS816018/32/36DGT-400/375/333/250/200/150 TQFP Pin Description Symbol Type Description A 0, A 1 I Address field LSBs and Address Counter preset Inputs A I Address Inputs DQA DQB DQC DQD I/O Data Input and Output pins BW I Byte Write—Writes all enabled bytes; active low BA , BB I Byte Write Enable for DQA, DQB Data I/Os; active low BC , BD I Byte Write Enable for DQC, DQD Data I/Os; active low CK I Clock Input Signal; active high GW I Global Write Enable—Writes all bytes; active low E 1, E 3 I Chip Enable; active low E2 I Chip Enable; active high G I Output Enable; active low ADV I Burst address counter advance enable; active low ADSP, ADSC I Address Strobe (Processor, Cache Controller); active low ZZ I Sleep Mode control; active high FT I Flow Through or Pipeline mode; active low LBO I Linear Burst Order mode; active low VDD I Core power supply VSS I I/O and Core Ground VDDQ I Output driver power supply NC Rev: 1.03a 9/2013 No Connect 5/24 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2011, GSI Technology GS816018/32/36DGT-400/375/333/250/200/150 GS816018/32/36D Block Diagram Register A0–An D Q A0 A0 D0 Q0 A1 A1 D1 Q1 Counter Load A LBO ADV Memory Array CK ADSC ADSP Q D Register GW BW BA D Q Register D 36 Q BB 36 4 Register D Q D Q D Q Register Register D Q Register BC BD Register D Q Register E1 E2 E3 D Q Register D Q FT G ZZ 1 Power Down DQx1–DQx9 Control Note: Only x36 version shown for simplicity. Rev: 1.03a 9/2013 6/24 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2011, GSI Technology GS816018/32/36DGT-400/375/333/250/200/150 Mode Pin Functions Mode Name Pin Name Burst Order Control LBO Output Register Control FT Power Down Control ZZ State Function L Linear Burst H Interleaved Burst L Flow Through H or NC Pipeline L or NC Active H Standby, IDD = ISB Note: There is a pull-up device on the FT pin and a pull-down device on the ZZ pin , so this input pin can be unconnected and the chip will operate in the default states as specified in the above tables. Burst Counter Sequences Linear Burst Sequence Interleaved Burst Sequence A[1:0] A[1:0] A[1:0] A[1:0] A[1:0] A[1:0] A[1:0] A[1:0] 1st address 00 01 10 11 1st address 00 01 10 11 2nd address 01 10 11 00 2nd address 01 00 11 10 3rd address 10 11 00 01 3rd address 10 11 00 01 4th address 11 00 01 10 4th address 11 10 01 00 Note: The burst counter wraps to initial state on the 5th clock. Rev: 1.03a 9/2013 Note: The burst counter wraps to initial state on the 5th clock. 7/24 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2011, GSI Technology GS816018/32/36DGT-400/375/333/250/200/150 Byte Write Truth Table Function GW BW BA BB BC BD Notes Read H H X X X X 1 Write No Bytes H L H H H H 1 Write byte a H L L H H H 2, 3 Write byte b H L H L H H 2, 3 Write byte c H L H H L H 2, 3, 4 Write byte d H L H H H L 2, 3, 4 Write all bytes H L L L L L 2, 3, 4 Write all bytes L X X X X X Notes: 1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs, BA, BB, BC and/or BD. 2. Byte Write Enable inputs BA, BB, BC and/or BD may be used in any combination with BW to write single or multiple bytes. 3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs. 4. Bytes “C” and “D” are only available on the x32 and x36 versions. Rev: 1.03a 9/2013 8/24 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2011, GSI Technology GS816018/32/36DGT-400/375/333/250/200/150 Synchronous Truth Table Operation Address Used State Diagram Key E1 E2 E3 ADSP ADSC ADV W DQ3 Deselect Cycle, Power Down None X L X H X L X X High-Z Deselect Cycle, Power Down None X L L X X L X X High-Z Deselect Cycle, Power Down None X L X H L X X X High-Z Deselect Cycle, Power Down None X L L X L X X X High-Z Deselect Cycle, Power Down None X H X X X L X X High-Z Read Cycle, Begin Burst External R L H L L X X X Q Read Cycle, Begin Burst External R L H L H L X F Q Write Cycle, Begin Burst External W L H L H L X T D Read Cycle, Continue Burst Next CR X X X H H L F Q Read Cycle, Continue Burst Next CR H X X X H L F Q Write Cycle, Continue Burst Next CW X X X H H L T D Write Cycle, Continue Burst Next CW H X X X H L T D Read Cycle, Suspend Burst Current X X X H H H F Q Read Cycle, Suspend Burst Current H X X X H H F Q Write Cycle, Suspend Burst Current X X X H H H T D Write Cycle, Suspend Burst Current H X X X H H T D Notes: 1. X = Don’t Care, H = High, L = Low 2. E = T (True) if E2 = 1 and E1 = E3 = 0; E = F (False) if E2 = 0 or E1 = 1 or E3 = 1 3. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding. 4. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown as “Q” in the Truth Table above). 5. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish basic synchronous or synchronous burst operations and may be avoided for simplicity. 6. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above. 7. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above. Rev: 1.03a 9/2013 9/24 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2011, GSI Technology GS816018/32/36DGT-400/375/333/250/200/150 Simplified State Diagram X Deselect W R Simple Burst Synchronous Operation Simple Synchronous Operation W X R R First Write First Read CR CW W X CR R R X Burst Write Burst Read X CR CW CR Notes: 1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low. 2. The upper portion of the diagram assumes active use of only the Enable (E1, E2, and E3) and Write (BA, BB, BC, BD, BW, and GW) control inputs, and that ADSP is tied high and ADSC is tied low. 3. The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs, and assumes ADSP is tied high and ADV is tied low. Rev: 1.03a 9/2013 10/24 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2011, GSI Technology GS816018/32/36DGT-400/375/333/250/200/150 Simplified State Diagram with G X Deselect W R W X R R First Write CR CW W CW W X First Read X CR R Burst Write R CR CW W Burst Read X CW CR Notes: 1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G. 2. Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from Read cycles to Write cycles without passing through a Deselect cycle. Dummy Read cycles increment the address counter just like normal read cycles. 3. Transitions shown in gray tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet Data Input Set Up Time. Rev: 1.03a 9/2013 11/24 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2011, GSI Technology GS816018/32/36DGT-400/375/333/250/200/150 Absolute Maximum Ratings (All voltages reference to VSS) Symbol Description Value Unit VDD Voltage on VDD Pins –0.5 to 4.6 V VDDQ Voltage in VDDQ Pins –0.5 to VDD V VI/O Voltage on I/O Pins –0.5 to VDD +0.5 ( 4.6 V max.) V VIN Voltage on Other Input Pins –0.5 to VDD +0.5 ( 4.6 V max.) V IIN Input Current on Any Pin +/–20 mA IOUT Output Current on Any I/O Pin +/–20 mA PD Package Power Dissipation 1.5 W TSTG Storage Temperature –55 to 125 oC TBIAS Temperature Under Bias –55 to 125 oC Note: Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of this component. Power Supply Voltage Ranges Parameter Symbol Min. Typ. Max. Unit 3.3 V Supply Voltage VDD3 3.0 3.3 3.6 V 2.5 V Supply Voltage VDD2 2.3 2.5 2.7 V 3.3 V VDDQ I/O Supply Voltage VDDQ3 3.0 3.3 3.6 V 2.5 V VDDQ I/O Supply Voltage VDDQ2 2.3 2.5 2.7 V Parameter Symbol Min. Typ. Max. Unit Input High Voltage VIH 2.0 — VDD + 0.3 V Input Low Voltage VIL –0.3 — 0.8 V VDD3 Range Logic Levels Notes: 1. VIH (max) must be met for any instantaneous value of VDD. 2. VDD needs to power-up before or at the same time as VDDQ to make sure VIH (max) is not exceeded. Rev: 1.03a 9/2013 12/24 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2011, GSI Technology GS816018/32/36DGT-400/375/333/250/200/150 VDD2 Range Logic Levels Parameter Symbol Min. Typ. Max. Unit Input High Voltage VIH 0.6*VDD — VDD + 0.3 V Input Low Voltage VIL –0.3 — 0.3*VDD V Notes: 1. VIH (max) must be met for any instantaneous value of VDD. 2. VDD needs to power-up before or at the same time as VDDQ to make sure VIH (max) is not exceeded. Operating Temperature Parameter Symbol Min. Typ. Max. Unit Junction Temperature (Commercial Range Versions) TJ 0 25 85 C Junction Temperature (Industrial Range Versions)* TJ –40 25 100 C Note: * The part numbers of Industrial Temperature Range versions end with the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. Thermal Impedance Package Test PCB Substrate JA (C°/W) Airflow = 0 m/s JA (C°/W) Airflow = 1 m/s JA (C°/W) Airflow = 2 m/s JB (C°/W) JC (C°/W) 100 TQFP 4-layer 35.7 31.0 29.4 27.0 8.4 Notes: 1. Thermal Impedance data is based on a number of samples from mulitple lots and should be viewed as a typical number. 2. The characteristics of the test fixture PCB influence reported thermal characteristics of the device. Be advised that a good thermal path to the PCB can result in cooling or heating of the RAM depending on PCB temperature. Undershoot Measurement and Timing Overshoot Measurement and Timing VIH 20% tKC VDD + 2.0 V VSS 50% 50% VDD VSS – 2.0 V 20% tKC VIL Note: Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. Rev: 1.03a 9/2013 13/24 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2011, GSI Technology GS816018/32/36DGT-400/375/333/250/200/150 Capacitance (TA = 25oC, f = 1 MHZ, VDD = 2.5 V) Parameter Symbol Test conditions Typ. Max. Unit Input Capacitance CIN VIN = 0 V 4 5 pF Input/Output Capacitance CI/O VOUT = 0 V 6 7 pF Note: These parameters are sample tested. AC Test Conditions Parameter Conditions Input high level VDD – 0.2 V Input low level 0.2 V Input slew rate 1 V/ns Input reference level VDD/2 Output reference level VDDQ/2 Output load Fig. 1 Notes: 1. Include scope and jig capacitance. 2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted. 3. Device is deselected as defined by the Truth Table. Output Load 1 DQ 50 30pF* VDDQ/2 * Distributed Test Jig Capacitance Rev: 1.03a 9/2013 14/24 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2011, GSI Technology GS816018/32/36DGT-400/375/333/250/200/150 DC Electrical Characteristics Parameter Symbol Test Conditions Min Max Input Leakage Current (except mode pins) IIL VIN = 0 to VDD –1 uA 1 uA ZZ Input Current IIN1 VDD VIN VIH 0 V VIN VIH –1 uA –1 uA 1 uA 100 uA FT Input Current IIN2 VDD VIN VIL 0 V VIN VIL –100 uA –1 uA 1 uA 1 uA Output Leakage Current IOL Output Disable, VOUT = 0 to VDD –1 uA 1 uA Output High Voltage VOH2 IOH = –8 mA, VDDQ = 2.375 V 1.7 V — Output High Voltage VOH3 IOH = –8 mA, VDDQ = 3.135 V 2.4 V — Output Low Voltage VOL IOL = 8 mA — 0.4 V Rev: 1.03a 9/2013 15/24 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2011, GSI Technology Rev: 1.03a 9/2013 IDD 90 90 IDD Pipeline Flow Through 50 ISB 50 ISB Pipeline Flow Through 255 20 335 35 280 35 365 65 0 to 70°C IDDQ IDD IDDQ IDD IDDQ IDD IDDQ IDD Symbol Flow Through Pipeline Flow Through Pipeline Mode 110 110 70 70 275 20 355 35 300 35 385 65 –40 to 85°C -400 90 90 50 50 250 15 320 30 270 30 350 60 110 110 70 70 270 15 340 30 290 30 370 60 –40 to 85°C -375 0 to 70°C Notes: 1. IDD and IDDQ apply to any combination of VDD3, VDD2, VDDQ3, and VDDQ2 operation. 2. All parameters listed are worst case scenario. — Device Deselected; All other inputs VIH or VIL Deselect Current (x18) — Operating Current ZZ VDD – 0.2 V Device Selected; All other inputs VIH or VIL Output open (x32/ x36) Standby Current Test Conditions Parameter Operating Currents 90 90 50 50 240 15 285 25 260 25 315 50 0 to 70°C 110 110 70 70 260 15 305 25 280 25 335 50 –40 to 85°C -333 90 90 50 50 210 10 230 20 230 20 250 40 0 to 70°C 110 110 70 70 230 10 250 20 250 20 270 40 –40 to 85°C -250 85 90 50 50 195 10 195 15 210 15 210 30 0 to 70°C 105 110 70 70 215 10 215 15 230 15 230 30 –40 to 85°C -200 85 90 50 50 180 10 170 15 190 15 180 20 0 to 70°C 105 110 70 70 200 10 190 15 210 15 200 20 –40 to 85°C -150 mA mA mA mA mA mA mA mA Unit GS816018/32/36DGT-400/375/333/250/200/150 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. 16/24 © 2011, GSI Technology GS816018/32/36DGT-400/375/333/250/200/150 Pipeline Flow Through Parameter Symbol Clock Cycle Time -400 -375 -333 -250 -200 -150 Max Min Max Unit AC Electrical Characteristics Min Max Min Max Min Max Min Max Min tKC 2.5 — 2.66 — 3.3 — 4.0 — 5.0 — 6.7 — ns Clock to Output Valid tKQ — 2.5 — 2.5 — 2.5 — 2.5 — 3.0 — 3.8 ns Clock to Output Invalid tKQX 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — ns Clock to Output in Low-Z tLZ1 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — ns Setup time tS 0.9 — 0.9 — 1.0 — 1.2 — 1.4 — 1.5 — ns Hold time tH 0.1 — 0.1 — 0.1 — 0.2 — 0.4 — 0.5 — ns Clock Cycle Time tKC 4.0 — 4.2 — 4.5 — 5.5 — 6.5 — 7.5 — ns Clock to Output Valid tKQ — 4.0 — 4.2 — 4.5 — 5.5 — 6.5 — 7.5 ns Clock to Output Invalid tKQX 2.0 — 2.0 — 2.0 — 2.0 — 2.0 — 2.0 — ns Clock to Output in Low-Z tLZ1 2.0 — 2.0 — 2.0 — 2.0 — 2.0 — 2.0 — ns Setup time tS 1.2 — 1.2 — 1.3 — 1.5 — 1.5 — 1.5 — ns Hold time tH 0.2 — 0.2 — 0.3 — 0.5 — 0.5 — 0.5 — ns Clock HIGH Time tKH 0.9 — 0.9 — 1.0 — 1.3 — 1.3 — 1.5 — ns Clock LOW Time tKL 1.1 — 1.1 — 1.2 — 1.5 — 1.5 — 1.7 — ns Clock to Output in High-Z tHZ1 1.5 2.5 1.5 2.5 1.5 2.5 1.5 2.5 1.5 3.0 1.5 3.8 ns G to Output Valid tOE — 2.5 — 2.5 — 2.5 — 2.5 — 3.0 — 3.8 ns G to output in Low-Z tOLZ1 0 — 0 — 0 — 0 — 0 — 0 — ns G to output in High-Z tOHZ1 — 2.5 — 2.5 — 2.5 — 2.5 — 3.0 — 3.8 ns ZZ setup time tZZS2 5 — 5 — 5 — 5 — 5 — 5 — ns ZZ hold time tZZH2 1 — 1 — 1 — 1 — 1 — 1 — ns ZZ recovery tZZR 20 — 20 — 20 — 20 — 20 — 20 — ns Notes: 1. These parameters are sampled and are not 100% tested. 2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold times as specified above. Rev: 1.03a 9/2013 17/24 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2011, GSI Technology GS816018/32/36DGT-400/375/333/250/200/150 Pipeline Mode Timing Begin Read A Cont Cont Single Read Deselect Write B Read C Read C+1 Read C+2 Read C+3 Cont Single Write tKL tKH tKC Deselect Burst Read CK ADSP tS tH ADSC initiated read ADSC tS tH ADV tS tH A0–An A B C tS GW tS tH BW tH tS Ba–Bd tS Deselected with E1 tH E1 masks ADSP E1 tS tH E2 and E3 only sampled with ADSP and ADSC E2 tS tH E3 G tS tOE DQa–DQd Rev: 1.03a 9/2013 tOHZ Q(A) tKQ tH D(B) tKQX tLZ tHZ Q(C) 18/24 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Q(C+1) Q(C+2) Q(C+3) © 2011, GSI Technology GS816018/32/36DGT-400/375/333/250/200/150 Flow Through Mode Timing Begin Read A Cont Cont Write B Read C Read C+1 Read C+2 Read C+3 Read C Cont Deselect tKL tKC tKH CK ADSP Fixed High tS tH tS tH initiated read ADSC ADSC tS tH ADV tS tH A0–An A B C tS tH GW tS tH BW tS tH Ba–Bd tS Deselected with E1 tH E1 tS tH E2 and E3 only sampled with ADSC E2 tS tH E3 G tH tS tOE DQa–DQd Rev: 1.03a 9/2013 tOHZ Q(A) D(B) tKQ tLZ tHZ tKQX Q(C) Q(C+1) Q(C+2) 19/24 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Q(C+3) Q(C) © 2011, GSI Technology GS816018/32/36DGT-400/375/333/250/200/150 Sleep Mode During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high, the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM operates normally after 2 cycles of wake up time. Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of Sleep mode is dictated by the length of time the ZZ is in a High state. After entering Sleep mode, all inputs except ZZ become disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode. When the ZZ pin is driven high, ISB2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands may be applied while the SRAM is recovering from Sleep mode. Sleep Mode Timing Diagram tKH tKC tKL CK Setup Hold ADSP ADSC tZZR tZZS tZZH ZZ Rev: 1.03a 9/2013 20/24 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2011, GSI Technology GS816018/32/36DGT-400/375/333/250/200/150 Description A1 Standoff 0.05 0.10 0.15 A2 Body Thickness 1.35 1.40 1.45 b Lead Width 0.20 0.30 0.40 c Lead Thickness 0.09 — 0.20 D Terminal Dimension 21.9 22.0 22.1 D1 Package Body 19.9 20.0 20.1 E Terminal Dimension 15.9 16.0 16.1 E1 Package Body 13.9 14.0 14.1 e Lead Pitch — 0.65 — L Foot Length 0.45 0.60 0.75 L1 Lead Length — 1.00 — Y Coplanarity Lead Angle D D1 Symbol Pin 1 TQFP Package Drawing (Package GT) L c L1 Min. Nom. Max e b A1 A2 0.10 Y 0 — 7 E1 E Notes: 1. All dimensions are in millimeters (mm). 2. Package width and length do not include mold protrusion. Rev: 1.03a 9/2013 21/24 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2011, GSI Technology GS816018/32/36DGT-400/375/333/250/200/150 Ordering Information for GSI Synchronous Burst RAMs Org Part Number1 Type Package Speed2 (MHz/ns) TJ3 1M x 18 GS816018DGT-400 Pipeline/Flow Through RoHS-compliant TQFP 400/4.0 C 1M x 18 GS816018DGT-375 Pipeline/Flow Through RoHS-compliant TQFP 375/4.2 C 1M x 18 GS816018DGT-333 Pipeline/Flow Through RoHS-compliant TQFP 333/4.5 C 1M x 18 GS816018DGT-250 Pipeline/Flow Through RoHS-compliant TQFP 250/5.5 C 1M x 18 GS816018DGT-200 Pipeline/Flow Through RoHS-compliant TQFP 200/6.5 C 1M x 18 GS816018DGT-150 Pipeline/Flow Through RoHS-compliant TQFP 150/7.5 C 512K x 32 GS816032DGT-400 Pipeline/Flow Through RoHS-compliant TQFP 400/4.0 C 512K x 32 GS816032DGT-375 Pipeline/Flow Through RoHS-compliant TQFP 375/4.2 C 512K x 32 GS816032DGT-333 Pipeline/Flow Through RoHS-compliant TQFP 333/4.5 C 512K x 32 GS816032DGT-250 Pipeline/Flow Through RoHS-compliant TQFP 250/5.5 C 512K x 32 GS816032DGT-200 Pipeline/Flow Through RoHS-compliant TQFP 200/6.5 C 512K x 32 GS816032DGT-150 Pipeline/Flow Through RoHS-compliant TQFP 150/7.5 C 512K x 36 GS816036DGT-400 Pipeline/Flow Through RoHS-compliant TQFP 400/4.0 C 512K x 36 GS816036DGT-375 Pipeline/Flow Through RoHS-compliant TQFP 375/4.2 C 512K x 36 GS816036DGT-333 Pipeline/Flow Through RoHS-compliant TQFP 333/4.5 C 512K x 36 GS816036DGT-250 Pipeline/Flow Through RoHS-compliant TQFP 250/5.5 C 512K x 36 GS816036DGT-200 Pipeline/Flow Through RoHS-compliant TQFP 200/6.5 C 512K x 36 GS816036DGT-150 Pipeline/Flow Through RoHS-compliant TQFP 150/7.5 C 1M x 18 GS816018DGT-400I Pipeline/Flow Through RoHS-compliant TQFP 400/4.0 I 1M x 18 GS816018DGT-375I Pipeline/Flow Through RoHS-compliant TQFP 375/4.2 I 1M x 18 GS816018DGT-333I Pipeline/Flow Through RoHS-compliant TQFP 333/4.5 I 1M x 18 GS816018DGT-250I Pipeline/Flow Through RoHS-compliant TQFP 250/5.5 I 1M x 18 GS816018DGT-200I Pipeline/Flow Through RoHS-compliant TQFP 200/6.5 I 1M x 18 GS816018DGT-150I Pipeline/Flow Through RoHS-compliant TQFP 150/7.5 I 512K x 32 GS816032DGT-400I Pipeline/Flow Through RoHS-compliant TQFP 400/4.0 I 512K x 32 GS816032DGT-375I Pipeline/Flow Through RoHS-compliant TQFP 375/4.2 I 512K x 32 GS816032DGT-333I Pipeline/Flow Through RoHS-compliant TQFP 333/4.5 I 512K x 32 GS816032DGT-250I Pipeline/Flow Through RoHS-compliant TQFP 250/5.5 I 512K x 32 GS816032DGT-200I Pipeline/Flow Through RoHS-compliant TQFP 200/6.5 I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS816018DGT-150IT. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user. 3. C = Commercial Temperature Range. I = Industrial Temperature Range. 4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings. Rev: 1.03a 9/2013 22/24 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2011, GSI Technology GS816018/32/36DGT-400/375/333/250/200/150 Ordering Information for GSI Synchronous Burst RAMs Org Part Number1 Type Package Speed2 (MHz/ns) TJ3 512K x 32 GS816032DGT-150I Pipeline/Flow Through RoHS-compliant TQFP 150/7.5 I 512K x 36 GS816036DGT-400I Pipeline/Flow Through RoHS-compliant TQFP 400/4.0 I 512K x 36 GS816036DGT-375I Pipeline/Flow Through RoHS-compliant TQFP 375/4.2 I 512K x 36 GS816036DGT-333I Pipeline/Flow Through RoHS-compliant TQFP 333/4.5 I 512K x 36 GS816036DGT-250I Pipeline/Flow Through RoHS-compliant TQFP 250/5.5 I 512K x 36 GS816036DGT-200I Pipeline/Flow Through RoHS-compliant TQFP 200/6.5 I 512K x 36 GS816036DGT-150I Pipeline/Flow Through RoHS-compliant TQFP 150/7.5 I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS816018DGT-150IT. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user. 3. C = Commercial Temperature Range. I = Industrial Temperature Range. 4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings. Rev: 1.03a 9/2013 23/24 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2011, GSI Technology GS816018/32/36DGT-400/375/333/250/200/150 18Mb Sync SRAM Datasheet Revision History File Name Types of Changes Format or Content Description of changes • Creation of new datasheet 8160xxD_r1 8160xxD_r1_01 Content • Addition of IDD numbers 8160xxD_r1_02 Content • Updated Absolute Maximum Ratings 8160xxD_r1_03 Content • Updated to reflect MP status • (Rev1.03a: Corrected thermal impedance numbers) Rev: 1.03a 9/2013 24/24 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2011, GSI Technology Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: GSI Technology: GS816036DGT-250I GS816018DGT-375 GS816018DGT-400I GS816018DGT-333I GS816032DGT-400I GS816036DGT-375 GS816032DGT-333 GS816032DGT-400 GS816036DGT-375I GS816036DGT-150 GS816036DGT-333I GS816032DGT-250I GS816018DGT-400 GS816032DGT-375 GS816018DGT-333 GS816036DGT-400I GS816032DGT-200 GS816032DGT-333I GS816018DGT-150 GS816036DGT-333 GS816032DGT-375I GS816018DGT-150I GS816036DGT-400 GS816018DGT-375I GS816032DGT-150I GS816036DGT-250 GS816032DGT-200I GS816018DGT-250 GS816032DGT-250 GS816018DGT-200I GS816018DGT-200 GS816032DGT-150 GS816036DGT-150I GS816018DGT-250I GS816036DGT-200 GS816036DGT-200I