AMD AM27X2048-150JI 2 megabit (128 k x 16-bit) cmos expressrom device Datasheet

FINAL
Am27X2048
2 Megabit (128 K x 16-Bit) CMOS ExpressROM Device
DISTINCTIVE CHARACTERISTICS
■ ±10% power supply tolerance
■ As an OTP EPROM alternative:
— Factory optimized programming
■ High noise immunity
— Fully tested and guaranteed
■ Low power dissipation
— 100 µA maximum CMOS standby current
■ As a Mask ROM alternative:
■ Available in Plastic Dual-In-line Package (PDIP)
and Plastic Leaded Chip Carrier (PLCC)
— Shorter leadtime
— Lower volume per code
■ Latch-up protected to 100 mA from –1 V to
VCC + 1 V
■ Fast access time
— 70 ns
■ Versatile features for simple interfacing
■ Single +5 V power supply
— Both CMOS and TTL input/output compatibility
■ Compatible with JEDEC-approved EPROM
pinout
— Two line control functions
GENERAL DESCRIPTION
The Am27X2048 is a factory programmed and tested
OTP EPROM. It is programmed after packaging prior to
final test. Every device is rigorously tested under AC
and DC operating conditions to your stable code. It is
organized as 128 Kwords by 16 bits per word and is
available in plastic dual in-line packages (PDIP), as
well as plastic leaded chip carrier (PLCC) packages.
ExpressROM devices provide a board-ready memory
solution for medium to high volume codes with short
leadtimes. This offers manufacturers a cost-effective
and flexible alternative to OTP EPROMs and mask programmed ROMs.
Data can be accessed as fast as 70 ns, allowing
high-performance microprocessors to operate with reduced WAIT states. The device offers separate Output
Enable (OE#) and Chip Enable (CE#) controls, thus
eliminating bus contention in a multiple bus microprocessor system.
AMD’s CMOS process technology provides high
speed, low power, and high noise immunity. Typical
power consumption is only 125 mW in active mode,
and 100 µW in standby mode.
BLOCK DIAGRAM
VCC
Data Outputs DQ0–DQ15
VSS
OE#
CE#
A0–A16
Address
Inputs
Output Enable
Chip Enable
and
Prog Logic
Output
Buffers
Y
Decoder
Y
Gating
X
Decoder
2,097,152
Bit Cell
Matrix
15653D-1
Publication# 15653 Rev: D Amendment/0
Issue Date: May 1998
PRODUCT SELECTOR GUIDE
Family Part Number
Am27X2048
VCC = 5.0 V ± 5%
Speed Options
VCC = 5.0 V ± 10%
-255
-70
-90
-120
-150
-200
Max Access Time (ns)
70
90
120
150
200
250
CE# (E#) Access (ns)
70
90
120
150
200
250
OE# (G#) Access (ns)
40
40
50
65
75
75
CONNECTION DIAGRAMS
DQ15
3
38
A16
DQ15
CE (E)
VPP
DU (Note 2)
DQ14
4
37
A15
6
5
4
3
2
1 44 43 42 41 40
DQ13
5
36
A14
DQ12
7
39
A13
DQ12
6
35
A13
DQ11
8
38
A12
DQ11
7
34
A12
DQ10
9
37
A11
DQ10
8
33
A11
DQ9
10
36
A10
DQ9
9
32
A10
DQ8
11
35
A9
A9
VSS
12
34
VSS
NC
13
33
NC
DQ8
10
31
A14
PGM# (P#)
A15
VCC
39
A16
40
2
PGM# (P#)
1
VCC
VPP
CE# (E#)
DQ14
PLCC
DQ13
DIP
A7
DQ5
16
30
A6
DQ4
29
17
18 19 20 21 22 23 24 25 26 27 28
A5
14
28
27
A6
DQ4
15
26
A5
DQ3
16
25
A4
DQ2
17
24
A3
DQ1
18
23
A2
DQ0
19
22
A1
OE# (G#)
20
21
A0
DQ3
DQ5
13
A4
A7
DQ6
A3
A8
31
A2
32
15
A1
14
DQ6
A0
DQ7
DU (Note 2)
A8
OE# (G#)
VSS
29
DQ0
30
12
DQ1
11
DQ2
VSS
DQ7
15653D-3
15653D-2
Notes:
1. JEDEC nomenclature is in parenthesis.
2. Don’t use (DU) for PLCC.
PIN DESIGNATIONS
A0–A16
= Address Inputs
CE# (E#)
= Chip Enable Input
LOGIC SYMBOL
17
OE# (G#)
= Output Enable Input
PGM# (P#)
= Program Enable Input
VCC
= VCC Supply Voltage
VPP
= Program Voltage Input
VSS
= Ground
NC
= No Internal Connection
2
16
A0–A16
DQ0–DQ15 = Data Input/Outputs
DQ0–DQ15
CE# (E#)
OE# (G#)
15653D-4
Am27X2048
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed
by a combination of the following:
AM27X2048
-70
J
C
XXXXX
CODE DESIGNATION
Assigned by AMD
TEMPERATURE RANGE
C = Commercial (0°C to +70°C)
I = Industrial (–40°C to +85°C)
PACKAGE TYPE
P = 40-Pin Plastic Dual In-Line Package (PD 040)
J = 44-Pin Plastic Leaded Chip Carrier (PL 044)
SPEED OPTION
See Product Selector Guide and Valid Combinations
DEVICE NUMBER/DESCRIPTION
Am27X2048
2 Megabit (128 K x 16-Bit) CMOS ExpressROM Device
Valid Combinations
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.
AM27X2048-70
AM27X2048-90
AM27X2048-120
AM27X2048-150
PC, JC, PI, JI
AM27X2048-200
AM27X2048-255
VCC = 5.0 V ± 5%
Am27X2048
3
FUNCTIONAL DESCRIPTION
Read Mode
CE# should be decoded and used as the primary device-selecting function, while OE# be made a common
connection to all devices in the array and connected to
the READ line from the system control bus. This assures that all deselected memory devices are in their
low-power standby mode and that the output pins are
only active when data is desired from a particular memory device.
To obtain data at the device outputs, Chip Enable (CE#)
and Output Enable (OE#) must be driven low. CE# controls the power to the device and is typically used to select the device. OE# enables the device to output data,
independent of device selection. Addresses must be
stable for at least t ACC –t OE. Refer to the Switching
Waveforms section for the timing diagram.
System Applications
Standby Mode
During the switch between active and standby conditions, transient current peaks are produced on the rising and falling edges of Chip Enable. The magnitude of
these transient current peaks is dependent on the output capacitance loading of the device. At a minimum, a
0.1 µF ceramic capacitor (high frequency, low inherent
inductance) should be used on each device between
VCC and VSS to minimize transient effects. In addition,
to overcome the voltage drop caused by the inductive
effects of the printed circuit board traces on ExpressROM device arrays, a 4.7 µF bulk electrolytic capacitor
should be used between VCC and VSS for each eight
devices. The location of the capacitor should be close
to where the power supply is connected to the array.
The device enters the CMOS standby mode when CE#
is at VCC ± 0.3 V. Maximum VCC current is reduced to
100 µA. The device enters the TTL-standby mode
when CE# is at VIH. Maximum VCC current is reduced
to 1.0 mA. When in either standby mode, the device
places its outputs in a high-impedance state, independent of the OE# input.
Output OR-Tieing
To accommodate multiple memory connections, a
two-line control function provides:
■ Low memory power dissipation, and
■ Assurance that output bus contention will not occur.
MODE SELECT TABLE
Mode
CE#
OE#
PGM#
VPP
Outputs
Read
VIL
VIL
X
X
DOUT
Output Disable
X
VIH
X
X
High Z
Standby (TTL)
VIH
X
X
X
High Z
VCC ± 0.3 V
X
X
X
High Z
Standby (CMOS)
Note:
X = Either VIH or VIL.
4
Am27X2048
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature
OTP Products. . . . . . . . . . . . . . . . . . –65°C to +125°C
Ambient Temperature
with Power Applied. . . . . . . . . . . . . . –55°C to +125°C
Commercial (C) Devices
Ambient Temperature (TA) . . . . . . . . . . .0°C to +70°C
Industrial (I) Devices
Voltage with Respect to VSS
All pins except VCC . . . . . . . . . –0.6 V to VCC + 0.6 V
Ambient Temperature (TA) . . . . . . . . .–40°C to +85°C
VCC (Note 1). . . . . . . . . . . . . . . . . . . . . –0.6 V to 7.0 V
VCC for ± 5% devices . . . . . . . . . . +4.75 V to +5.25 V
VCC for ± 10% devices . . . . . . . . . +4.50 V to +5.50 V
Note:
1. Minimum DC voltage on input or I/O pins –0.5 V. During
voltage transitions, the input may overshoot VSS to –2.0 V
for periods of up to 20 ns. Maximum DC voltage on input
and I/O pins is VCC + 5 V. During voltage transitions, input
and I/O pins may overshoot to VCC + 2.0 V for periods up
to 20 ns.
Supply Read Voltages
Operating ranges define those limits between which the functionality of the device is guaranteed.
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only; functional operation of the device at these
or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure of
the device to absolute maximum ratings for extended periods
may affect device reliability.
Am27X2048
5
DC CHARACTERISTICS over operating range (unless otherwise specified)
Parameter
Symbol
Parameter Description
Test Conditions
VOH
Output HIGH Voltage
IOH = –400 µA
VOL
Output LOW Voltage
IOL = 2.1 mA
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
ILI
Input Load Current
ILO
Min
Max
Unit
2.4
V
0.45
V
2.0
VCC + 0.5
V
–0.5
+0.8
V
VIN = 0 V to VCC
1.0
µA
Output Leakage Current
VOUT = 0 V to VCC
5.0
µA
ICC1
VCC Active Current (Note 2)
CE# = VIL, f = 10 MHz,
IOUT = 0 mA
50
mA
ICC2
VCC TTL Standby Current
CE# = VIH
1.0
mA
ICC3
VCC CMOS Standby Current
CE# = VCC ± 0.3 V
100
µA
Caution: The device must not be removed from (or inserted into) a socket when VCC or VPP is applied.
Notes:
1. VCC must be applied simultaneously or before VPP, and removed simultaneously or after VPP..
30
30
25
25
Supply Current
in mA
Supply Current
in mA
2. ICC1 is tested with OE# = VIH to simulate open outputs.
3. Minimum DC Input Voltage is –0.5 V. During transitions, the inputs may overshoot to –2.0 V for periods less than 20 ns.
Maximum DC Voltage on output pins is VCC + 0.5 V, which may overshoot to VCC + 2.0 V for periods less than 20 ns.
20
15
Figure 1.
6
2
3
4
5
6
7
Frequency in MHz
8
9
15
10
–75 –50 –55 0 25 50 75 100 125 150
Temperature in °C
10
1
20
10
15653D-5
15653D-6
Typical Supply Current vs. Frequency
VCC = 5.5 V, T = 25°C
Figure 2. Typical Supply Current vs. Temperature
VCC = 5.5 V, f = 10 MHz
Am27X2048
TEST CONDITIONS
Table 1.
5.0 V
Test Specifications
Test Condition
2.7 kΩ
Device
Under
Test
CL
Output Load
Unit
1 TTL gate
Output Load Capacitance, CL
(including jig capacitance)
100
pF
Input Rise and Fall Times
≤ 20
ns
Input Pulse Levels
0.45–2.4
V
Input timing measurement reference
levels
0.8, 2.0
V
Output timing measurement
reference levels
0.8, 2.0
V
6.2 kΩ
Note:
Diodes are IN3064 or equivalents.
All
15653D-7
Figure 3.
Test Setup
SWITCHING TEST WAVEFORM
2.4 V
2.0 V
2.0 V
Test Points
0.8 V
0.8 V
0.45 V
Input
Output
Note: For CL = 100 pF.
15653D-8
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted
Changing, State Unknown
Does Not Apply
Center Line is High Impedance State (High Z)
KS000010-PAL
Am27X2048
7
AC CHARACTERISTICS
Parameter Symbols
JEDEC
Standard
tAVQV
tACC
tELQV
Am27X2048
Description
Test Setup
-70
-90
-120
-150
-200
-255
Unit
Address to Output Delay
CE#,
Max
OE# = VIL
70
90
120
150
200
250
ns
tCE
Chip Enable to Output Delay
OE# = VIL Max
70
90
120
150
200
250
ns
tGLQV
tOE
Output Enable to Output
Delay
CE# = VIL Max
40
40
50
65
75
75
ns
tEHQZ
tGHQZ
tDF
(Note 2)
Chip Enable High or Output
Enable High to Output High Z,
Whichever Occurs First
Max
25
25
30
30
40
60
ns
tAXQX
tOH
Output Hold Time from
Addresses, CE# or OE#,
Whichever Occurs First
Min
0
0
0
0
0
0
ns
Caution: Do not remove the device from (or insert it into) a socket or board that has VPP or VCC applied.
Notes:
1. VCC must be applied simultaneously or before VPP, and removed simultaneously or after VPP.
2. This parameter is sampled and not 100% tested.
3. Switching characteristics are over operating range, unless otherwise specified.
4. See Figure 3 and Table 1 for test specifications.
SWITCHING WAVEFORMS
2.4
Addresses
0.45
2.0
0.8
2.0
0.8
Addresses Valid
CE#
tCE
OE#
tDF (Note 2)
tOE
High Z
Output
tACC
(Note 1)
tOH
High Z
Valid Output
15653D-9
Notes:
1. OE# may be delayed up to tACC – tOE after the falling edge of the addresses without impact on tACC.
2. tDF is specified from OE# or CE#, whichever occurs first.
PACKAGE CAPACITANCE
Parameter
Symbol
CIN
COUT
PD 040
Parameter Description
Test Conditions
Typ
Max
Typ
Max
Unit
Input Capacitance
VIN = 0
10
12
7
10
pF
Output Capacitance
VOUT = 0
12
15
12
14
pF
Notes:
1. This parameter is only sampled and not 100% tested.
2. TA = +25°C, f = 1 MHz.
8
PL 044
Am27X2048
PHYSICAL DIMENSIONS
PD 040—40-Pin Plastic Dual In-Line Package (measured in inches)
2.040
2.080
.600
.625
21
40
.008
.015
.530
.580
Pin 1 I.D.
.630
.700
20
.045
.065
0°
10°
.005 MIN
.140
.225
16-038-SC_AF
PD 040
DG76
2-28-95 ae
SEATING PLANE
.090
.110
.120
.160
.014
.022
.015
.060
PL 044—44-Pin Plastic Leaded Chip Carrier (measured in inches)
.685
.695
.650
.656
.042
.056
.062
.083
Pin 1 I.D.
.685
.695
.650
.656
.500 .590
REF .630
.013
.021
.026
.032
.050 REF
.009
.015
TOP VIEW
.090
.120
.165
.180
SEATING PLANE
SIDE VIEW
Am27X2048
16-038-SQ
PL 044
EC80
11.3.97 lv
9
REVISION SUMMARY FOR AM27X2048
Revision F
Global
Changed formatting to match current data sheets.
Product Selector Guide
OE# (G#) Access (ns): Corrected -90 speed option to
40 from 4.
Absolute Maximum Ratings
Storage Temperature: Removed “All Other Products ...
–65°C to +150°C”.
Trademarks
Copyright © 1998 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc.
Flashrite is a trademark of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
10
Am27X2048
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