LINER LTC3874-1 Polyphase step-down synchronous slave controller with sub-milliohm dcr sensing Datasheet

LTC3874-1
PolyPhase Step-Down
Synchronous Slave Controller with
Sub-Milliohm DCR Sensing
Features
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Description
Phase Extender for High Phase Count Voltage Rails
Operates with Power Blocks, DrMOS or External
Gate Drivers and MOSFETs
Accurate Phase-to-Phase Current Sharing
Sub-Milliohm DCR Current Sensing
Phase-Lockable Fixed Frequency 250kHz to 1MHz
Immediate Response to Master IC's Fault
Up to 12-Phase Operation
Wide VIN Range: 4.5 to 38V
VOUT Range : Up to 3.5V (LOWDCR Pin High)
Up to 5.5V (LOWDCR Pin Low)
Proprietary Current Mode Control Loop
Programmable CCM/DCM Operation
Programmable Phase Shift Control
24-Lead (4mm × 4mm) QFN Package
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Effectively working with a master controller, the LTC3874-1
supports all the programmable features as well as fault
protection.
L, LT, LTC, LTM, Linear Technology, the Linear logo, PolyPhase and µModule are registered
trademarks of Analog Devices, Inc. All other trademarks are the property of their respective
owners. Protected by U.S. Patents, including 5481178, 5705919, 5929620, 6144194, 6177787,
6580258, 5408150.
Applications
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The LTC®3874-1 is a dual PolyPhase® current mode synchronous step-down slave controller. It enables high current, multiphase applications when paired with a companion
master controller by extending the phase count. Compatible master controllers include the LTC3884-1, LTC3774,
LTC3875, LTC3877 and LTC3866. The LTC3874-1 employs
a unique architecture that enhances the signal-to-noise
ratio of the current sense signal, allowing the use of submilliohm DC resistance power inductors to maximize
efficiency while reducing switching jitter. Its peak current
mode architecture allows for accurate phase-to-phase
current sharing even for dynamic loads.
High Current Distributed Power Systems
Telecom, Datacom and Storage Systems
Intelligent Energy Efficient Power Regulation
Typical Application
High Efficiency, 4-Phase 1.8V/120A Step-Down Supply
VIN
7V TO 14V
DrMOS
LTC3874-1
PWM0
PWM1
DrMOS
649Ω
649Ω
+
470µF
×2
100µF
×3
0.22µF
0.22µF
1.8V
VSENSE0+
VSENSE1+
RUN0
RUN1
FAULT0
FAULT1
PGOOD0
PGOOD1
ITH0
ITH1
SYNC
ISENSE0+
ISENSE0–
ISENSE1+
ISENSE1–
RUN0
RUN1
FAULT0
FAULT1
MODE0
MODE1
ITH0
ITH1
SYNC
INTVCC
VCC0
VCC1
PHASMD
LDWDCR
ILIM
FREQ
GND
4-Phase Efficiency and Power
Loss vs Output Current, SubMilliohm DCR vs Traditional
DCR
VOUT
1.8V
120A
100µF
×3
+
470µF
×2
4.7µF
100k
VIN = 12V
VOUT = 1.8V
95 fSW = 425kHz
CCM
90
80
70
0
38741 TA01a
17
14
EFFICIENCY
11
85
75
REFER TO LTC3884-1 DATA SHEET
FOR MASTER SETUP
20
100
POWER LOSS
8
POWER LOSS (W)
LTC3884-1
(0.29mΩ DCR)
0.215µH
EFFICIENCY (%)
VIN
(0.29mΩ DCR)
0.215µH
0.29mΩ
1.5mΩ 5
0.29mΩ
1.5mΩ
2
10 20 30 40 50 60 70 80 90 100 110 120
LOAD CURRENT (A)
38741 TA01b
PIN NOT USED IN THIS CIRCUIT: EXTVCC
38741f
For more information www.linear/LTC3874-1
1
LTC3874-1
Absolute Maximum Ratings
Pin Configuration
(Note 1)
PWM0
FAULT1
FAULT0
LOWDCR
ITH0
MODE0
TOP VIEW
24 23 22 21 20 19
+
ISENSE0
1
18 VCC0
ISENSE0– 2
17 VIN
RUN0 3
16 INTVCC
25
GND
RUN1 4
15 EXTVCC
ISENSE1– 5
14 VCC1
ISENSE1+ 6
PHASMD
SYNC
9 10 11 12
ILIM
8
FREQ
7
ITH1
13 PWM1
MODE1
VIN.............................................................. −0.3V to 40V
VCC0, VCC1..................................................... −0.3V to 6V
ISENSE0+, ISENSE0 –, ISENSE1+, ISENSE1–..... −0.3V to INTVCC
EXTVCC, INTVCC, RUN0, RUN1..................... −0.3V to 6V
MODE0, MODE1, ILIM, LOWDCR,
PHASMD, FREQ..................................... −0.3V to INTVcc
SYNC, FAULT0, FAULT1, ITH0, ITH1.......... −0.3V to INTVcc
INTVCC Peak Output Current.................................100mA
Operating Junction Temperature Range
(Note 2)................................................... −40°C to 125°C
Storage Temperature Range................... −65°C to 150°C
UF PACKAGE
24-LEAD (4mm × 4mm) PLASTIC QFN
TJMAX = 125°C, θJA = 46.9°C/W, θJC_BOT = 4.5°C/W
EXPOSED PAD (PIN 25) IS GND, MUST BE SOLDERED TO PCB
Order Information
http://www.linear.com/product/LTC3874-1#orderinfo
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC3874EUF-1#PBF
LTC3874EUF-1#TRPBF
38741
24-Lead (4mm × 4mm) Plastic QFN
–40°C to 125°C
LTC3874IUF-1#PBF
LTC3874IUF-1#TRPBF
38741
24-Lead (4mm × 4mm) Plastic QFN
–40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
2
38741f
For more information www.linear.com/LTC3874-1
LTC3874-1
Electrical Characteristics
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = 12V, VRUN0,1 = 3.3V unless otherwise specified.
SYMBOL
PARAMETER
VIN
Input Voltage Range
VOUT
Output Voltage Range
IQ
Input DC Supply Current
Normal Operation
Shutdown
VUVLO
CONDITIONS
MIN
TYP
4.5
LOWDCR = INTVCC (Note 3)
LOWDCR = 0V
MAX
UNITS
38
V
3.5
5.5
V
V
VRUN0,1 = 3.3V
VRUN0,1 = 0V
4.6
1.8
mA
mA
Undervoltage Lockout Threshold
VINTVCC Falling
VINTVCC Rising
3.5
3.8
V
V
ISENSE Pins Bias Current
VISENSE0,1 < (VINTVCC – 3.3V)
VISENSE0,1 > (VINTVCC – 3.3V)
Control Loop
IISENSE0,1
VISENSE(MAX) Maximum Current Sense Threshold
(Table 3)
ILIM = INTVCC, LOWDCR = INTVCC,
VISENSE0,1 = 1.2V, VITH = 2.18V
l
±0.15
±1
±0.4
±3
µA
µA
l
26.8
28.8
30.8
mV
ILIM = 0V, LOWDCR = INTVCC,
VISENSE0,1 = 1.2V, VITH = 2.18V
l
14.5
16
17.5
mV
ILIM = INTVCC, LOWDCR = 0V,
VISENSE0,1 = 1.2V, VITH = 2.18V
l
65
72
79
mV
ILIM = 0V, LOWDCR = 0V,
VISENSE0,1 = 1.2V, VITH = 2.18V
l
33
40
47
mV
l
l
VCC – 0.2
0.2
5
V
V
µA
PWM Outputs
PWM
PWM Output High Voltage
PWM Output Low Voltage
PWM Output Current in Hi-Z State
ILOAD = 500µA
ILOAD = –500µA
tON(MIN)
Minimum On-Time
(Note 4)
–5
60
ns
INTVCC Regulator
VINTVCC
Internal VCC Voltage No Load
6V < VIN < 38V
VLDO INT
INTVCC Load Regulation
ICC = 0mA to 20mA
VEXTVCC
EXTVCC Switchover Voltage
VEXTVCC Ramping Positive (Note 5)
VLDO EXT
EXTVCC Voltage Drop
ICC = 20mA, VEXTVCC = 5V
VLDOHYS
EXTVCC Hysteresis
5.25
l
4.5
5.5
5.75
V
0.5
2
%
100
mV
4.7
50
V
300
mV
Oscillator and Phase-Locked Loop
fRANGE
PLL SYNC Range
l
250
VFREQ = 0.9V
1000
500
kHz
fNOM
Nominal Frequency
IFREQ
Frequency Setting Current
θ SYNC- θ0
SYNC to Ch0 Phase Relationship Based on
the Falling Edge of SYNC and Rising Edge of
PWM0
PHASMD = 0
PHASMD = 1/3 • INTVCC
PHASMD = 2/3 • INTVCC
PHASMD = INTVCC
180
60
120
90
Deg
Deg
Deg
Deg
θ SYNC- θ1
SYNC to Ch1 Phase Relationship Based on
the Falling Edge of SYNC and Rising Edge of
PWM1
PHASMD = 0
PHASMD = 1/3 • INTVCC
PHASMD = 2/3 • INTVCC
PHASMD = INTVCC
0
300
240
270
Deg
Deg
Deg
Deg
9
10
kHz
11
µA
Digital Inputs RUN0, RUN1, MODE0, MODE1, FAULT0, FAULT1, LOWDCR
VIH
Input High Threshold Voltage
l
VIL
Input Low Threshold Voltage
l
2.0
1.4
V
V
38741f
For more information www.linear/LTC3874-1
3
LTC3874-1
Electrical Characteristics
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3874-1 is tested under pulsed load conditions such
that TJ ≈ TA. The LTC3874E-1 is guaranteed to meet specifications
from 0°C to 85°C junction temperature. Specifications over the –40°Ç
to 125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LTC3874I-1 is guaranteed over the –40°C to 125°C operating junction
temperature range. Note that the maximum ambient temperature
consistent with these specifications is determined by specific operating
conditions in conjunction with board layout, the related package thermal
impedance and other environmental factors. The junction temperature TJ
is calculated from the ambient temperature TA and power dissipation PD
according to the following formula: TJ = TA + (PD • 46.9°C/W)
Note 3: Output voltage is set and controlled by master controller in
multiphase operations.
Note 4: The minimum on-time condition corresponds to an inductor
peak-to-peak ripple current ≥40% of IMAX (see Minimum On-Time
Considerations in the Applications Information section).
Note 5: EXTVCC is enabled only if VIN is higher than 6.5V.
Typical Performance Characteristics
90
90
80
80
70
70
60
VIN = 12V
VOUT = 1.8V
fSW = 425kHz
40
30
20
10
0
VIN = 12V
VOUT = 1.8V
95 fSW = 425kHz
CCM
60
VIN = 12V
VOUT = 1.2V
fSW = 425kHz
50
40
30
20
CCM
DCM
CCM
DCM
10
0 10 20 30 40 50 60 70 80 90 100 110 120
LOAD CURRENT (A)
0
4
14
EFFICIENCY
11
85
80
POWER LOSS
8
0.29mΩ
1.5mΩ 5
0.29mΩ
1.5mΩ
2
70
0 10 20 30 40 50 60 70 80 90 100 110 120
LOAD CURRENT (A)
38741 G2
Load Step (Forced Continuous
Mode) 4-Phase with Master
Controller LTC3884-1
38741 G3
Load Step (Discontinuous
Conduction Mode) 4-Phase with
Master Controller LTC3884-1
ILOAD
50A/DIV
ILOAD
50A/DIV
IL(MASTER0)
10A/DIV
I(MASTER0)
10A/DIV
IL(SLAVE0)
10A/DIV
I(SLAVE0)
10A/DIV
VOUT
AC-COUPLED
50mV/DIV
VOUT
AC-COUPLED
50mV/DIV
50µs/DIV
90
17
75
0 10 20 30 40 50 60 70 80 90 100 110 120
LOAD CURRENT (A)
38741 G1
V IN = 12V
V OUT = 1.2V
ILOAD 0A TO 20A
20
100
EFFICIENCY (%)
100
EFFICIENCY (%)
100
50
Efficiency and Power Loss vs
Output Current (4-Phase with
Master Controller LTC3884-1)
Efficiency vs Output Current
and Mode (4-Phase with Master
Controller LTC3884-1)
POWER LOSS (W)
EFFICIENCY (%)
Efficiency vs Output Current
and Mode (4-Phase with Master
Controller LTC3884-1)
(TA = 25°C unless otherwise specified)
38741 G04
VIN = 12V
VOUT = 1.2V
ILOAD 0A TO 20A
50µs/DIV
38741 G05
38741f
For more information www.linear.com/LTC3874-1
LTC3874-1
Typical Performance Characteristics
(TA = 25°C unless otherwise specified)
Start-Up Into a Prebiased Load
2-Phase Operation LTC3884-1
and LTC3874-1
Inductor Current at Light Load
RUN
ALL RUN PINS
TIED TOGETHER
2V/DIV
FORCED
CONTINUOUS
MODE
5A/DIV
VOUT
IN CCM
500mV/DIV
DISCONTINUOUS
CONDUCTION
MODE
5A/DIV
1µs/DIV
2ms/DIV
38741 G06
VIN = 12V
VOUT = 1.2V
Quiescent Current vs Temperature
without EXTVCC
Current Sense Threshold vs
ITH Voltage
INTVCC Line Regulation
6
100
6
4
60
4
VISENSE (mV)
INTVCC VOLTAGE (V)
SUPPLY CURRENT (mA)
5
3
2
0
150
4.1
ILIM = INTVCC
0
10
ILIM = GND
10
5
0
20
30
INPUT VOLTAGE (V)
40
–40
Undervoltage Lockout Threshold
(INTVCC vs Threshold)
LOWDCR = H,
RANGE = H
0
0.5
1
6
1.5
VITH (V)
2
2.5
3
38741 G10
Quiescent Current vs Input
Voltage without EXTVCC
RISING
3.9
UVLO THRESHOLD (V)
CURRENT SENSE THRESHOLD (mV)
30
15
LOWDCR = H,
RANGE = L
38741 G9
Maximum Current Sense Threshold
vs Common Mode Voltage
(LOWDCR = INTVCC, VITH = 2.18V)
20
20
–20
38741 G8
25
40
3.7
3.5
SUPPLY CURRENT (mA)
50
100
TEMPERATURE (°C)
LOWDCR = L,
RANGE = L
0
1
0
LOWDCR = L, RANGE = H
80
5
3
–50
38741 G07
VIN 12V
VOUT = 1.2V
FALLING
3.3
3.1
2.9
5
4
2.7
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
VISENSE COMMON MODE VOLTAGE (V)
38741 G11
2.5
–50
–5
45
125
95
TEMPERATURE (°C)
38741 G12
3
0
10
20
30
INPUT VOLTAGE (V)
40
38741 G13
38741f
For more information www.linear/LTC3874-1
5
LTC3874-1
Pin Functions
+
+
−
−
ISENSE0 /ISENSE1 (Pin 1/Pin 6): Current Sense Comparator Inputs. The (+) inputs to the current comparators are
normally connected to DCR sensing networks.
ISENSE0 /ISENSE1 (Pin 2/Pin 5): Current Sense Comparator Inputs. The (−) inputs to the current comparators are
connected to the outputs.
RUN0/RUN1 (Pin 3/Pin 4): Enable Run Inputs. Logic high
on the RUN pin enables the corresponding channel.
MODE0/MODE1(Pin 24/Pin 7): DCM/CCM Mode Control
Pins. Each channel runs in forced continuous mode if the
mode pin is logic high. There is an internal 500k pull-down
resistor on the mode pin. To select discontinuous conduction mode, float or pull down the mode pin.
ITH0/ITH1(Pin 23/Pin 8): Current Control Threshold. Each
associated channel’s current comparator tripping threshold
increases with its ITH voltage. These pins must be connected to the master controller’s ITH pins.
FREQ(Pin 9): Frequency Set Pin. There is a precision
10µA current flowing out of this pin. A resistor to ground
sets a voltage which in turn programs the frequency. This
pin sets the default switching frequency when there is no
external clock on the SYNC pin. See the application section
for detailed information.
ILIM(Pin 10): Current Comparators Sense Voltage Limit.
Program a DC voltage at this pin to set the maximum current sense threshold for the current comparators.
SYNC (Pin 11): External Clock Synchronization Input. If an
external clock is present at this pin, the switching frequency
will be synchronized to the falling edge of external clock.
Tie this pin to GND if not used.
PHASMD (Pin 12): Phase Set Pin. This pin determines the
relative phases between the external clock on pin SYNC
and the internal controllers. See Table 1 in the Operation
section for details.
PWM0/PWM1(Pin 19/Pin 13): (Top) Gate Signal Outputs.
This signal goes to the PWM or top gate input of the external driver, integrated driver MOSFET or power block. This
6
is a three-state compatible output. To support three-state
mode, an external resistor divider is typically used from
VCC0/VCC1 to ground.
VCC0/VCC1(Pin 18/Pin 14): PWM Pin Driver Supplies.
Decouple this pin to GND with a capacitor (0.1μF) to an
external supply or tie this pin to the INTVCC pin. PWM0/
PWM1 signal swing is from ground to VCC0/VCC1.
EXTVCC(Pin 15): External Power Input to an Internal Switch
Connected to INTVCC. The switch closes and supplies the
IC power, bypassing the internal low dropout regulator,
whenever EXTVCC is higher than 4.7V and VIN is greater
than 7V. Do not exceed 6V on this pin.
INTVCC(Pin 16): Internal 5.5V Regulator Output. The control
circuits are powered from this voltage. Decouple this pin
to GND with a minimum of 4.7μF low ESR tantalum or
ceramic capacitor.
VIN (Pin 17): Main Input Supply. Decouple this pin to GND
with a capacitor (0.1μF to 1μF).
FAULT0/FAULT1 (Pin 21/Pin 20): Master Controller Fault
Inputs. Connect these pins to the master chip fault indicator pins to respond to the fault signals from the master
controller. When a FAULT pin is floating or low, the PWM
pin of the corresponding channel is in three-state. There
is an internal 500k pull-down resistor on each FAULT pin.
LOWDCR(Pin 22): Sub-milliohm DCR Current Sensing
Enable Pin. There is an internal 500k pull-up resistor
between the LOWDCR pin and INTVCC. Floating or pulling this pin logic high will enable the sub-milliohm DCR
current sensing. Pulling this pin logic low will disable the
sub-milliohm DCR current sensing.
GND(Exposed Pad Pin 25): Ground. Connect this pad,
through vias, to a solid ground plane under the circuit.
The sources of the bottom N-channel MOSFETs, the (–)
terminal of CINTVCC, and the (–) terminal of CIN should
connect to this ground plane as closely as possible to
the IC. All small-signal components and compensation
components should also connect to this ground plane.
38741f
For more information www.linear.com/LTC3874-1
LTC3874-1
Functional Block Diagram
10µA
SYNC
PHASMD
One of Two Channels (CH0) Shown
EXTVCC
4.7V
FREQ
PLL-SYNC
–
+
ICMP
VIN
–
+
SYNC/PHASE
DETECT
+
5.5V
REG
OSC
S
R
IREV
5K
–
+
VCC0
ON
UVLO
ILIM RANGE SELECT
HI: 1:1
LO: 1:1.8
FAULTB
1
5k
FCNT
DC
AMP
RUN
SWITCH
LOGIC
AND
ANTISHOOTTHROUGH
PWM0
DrMOS
SLOPE
COMPENSATION
INTVCC
CIN
INTVCC
Q
REV
+
COUT0
ISENSE0+
ISENSE0–
UVLO
38741 BD
+
–
+
–
INTVCC
+
–
1
60k
+
–
ILIM
VIN
1.7V
REF
ITH0
LOWDCR
MODE0
RUN0
FAULT0
SGND
38741f
For more information www.linear/LTC3874-1
7
LTC3874-1
Operation
Main Control Loop
The LTC3874-1 is a constant frequency, LTC proprietary
current mode step-down slave controller for parallel operation with master controllers. During normal operation, each
top MOSFET is turned on when the clock for that channel
sets the RS latch, and turned off when the main current
comparator, ICMP, resets the RS latch. The peak inductor
current at which ICMP resets the RS latch is controlled by
the voltage on the ITH pin, which is the output of the master
controller. When the load current increases, the master
controller increases the ITH voltage, which in turn causes
the peak current in the corresponding slave channels to
increase, until the average inductor current matches the
new load current. After the top MOSFET has turned off,
the bottom MOSFET is turned on until the beginning of
the next cycle in Continuous Conduction Mode (CCM) or
until the inductor current starts to reverse, as indicated
by the reverse current comparator IREV, in Discontinuous
Conduction Mode (DCM). The LTC3874-1 slave controllers
DO NOT regulate the output voltage but regulate the current in each channel for current sharing with the master
controllers. Output voltage regulation is achieved through
the voltage feedback control loop in the master controllers.
Sub-Milliohm DCR Current Sensing
The LTC3874-1 employs a unique architecture to enhance
the signal-to-noise ratio that enables it to operate with
a small sense signal of a sub-milliohm value inductor
DCR to improve power efficiency and reduce jitter due to
switching noise.
Floating or pulling the LOWDCR pin high will enable submilliohm DCR current sensing. The LTC3874-1 can sense
a DCR value as low as 0.2mΩ with careful PCB layout.
The proprietary signal processing circuit provides a 14dB
signal-to-noise ratio improvement. As with conventional
8
current mode architectures, the current limit threshold is
still a function of the inductor peak current and the DCR
value, and can be accurately set with the ILIM and ITH pins.
INTVCC/EXTVCC Power
Power for most internal circuitry is derived from the INTVCC
pin. When the EXTVCC pin is left open or tied to a voltage
less than 4.7V, an internal 5.5V linear regulator supplies
INTVCC power from VIN. If EXTVCC is taken above 4.7V
and VIN is higher than 7V, the 5.5V regulator is turned off
and an internal switch is turned on connecting EXTVCC.
EXTVCC can be applied before VIN. Using the EXTVCC allows
the INTVCC power to be drawn from an external source.
Start-Up and Shutdown (RUN0, RUN1)
The two channels of the LTC3874-1 can be independently
shut down using the RUN0 and RUN1 pins. Pulling either
of these pins below 1.4V shuts down the main control
circuits for that channel. During shutdown, the PWM pin is
in three-state mode. Pulling either of these pins above 2V
enables the controller. The RUN0/1 pins are actively pulled
down until the INTVCC voltage passes the undervoltage
lockout threshold of 3.8V. For multiphase operation, the
RUN0/1 pins must be connected together and driven by
the RUN pins on the master controller. Because a large
RC filter in the LTC3874-1 needs to settle during initialization, the RUN pins can only be pulled up 4ms after VIN
is ready. Do not exceed the Absolute Maximum Rating of
6V on these pins.
The start-up of each channel’s output voltage VOUT is
controlled by the master controller. After the RUN pins are
released, the master controller drives the output based on
the programmed delay time and rise time. The slave controller LTC3874-1 follows the ITH voltage set by the master
to supply the same current to the output during startup.
38741f
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LTC3874-1
Operation
Light Load Current Operation (Discontinuous
Conduction Mode, Continuous Conduction Mode)
The LTC3874-1 can operate either in discontinuous conduction mode or forced continuous conduction mode.
To select forced continuous mode, tie the MODE pin to a
DC voltage above 2V (e.g., INTVCC). To select discontinuous conduction mode, tie the MODE pin to a DC voltage
below 1.4V (e.g., GND).In forced continuous mode,
the inductor current is allowed to reverse at light loads
or under large transient conditions. The peak inductor
current is determined by the voltage on the ITH pin. In
this mode, the efficiency at light loads is lower than in
discontinuous mode. However, continuous mode has the
advantages of lower output ripple and less interference
with audio circuitry. When the MODE pin is connected to
GND, the LTC3874-1 operates in discontinuous mode at
light loads. At very light loads, the current comparator
ICMP may remain tripped for several cycles and force the
external top MOSFET to stay off for the same number of
cycles (i.e., skipping pulses). This mode provides higher
light load efficiency than forced continuous mode and the
inductor current is not allowed to reverse. There is a 500k
pull-down resistor internally connected to the MODE pin.
If the MODE0/1 pins are left floating, both channels are in
discontinuous conduction mode by default.
Multichip Operations (PHASMD and SYNC Pins)
The PHASMD pin determines the relative phases between
the internal channels as well as the external clock signal on
SYNC pin as shown in Table 1. The phases tabulated are
relative to zero degree phase being defined as the falling
edge of the clock on SYNC pin.
Table 1
PHASMD
CHANNEL 0 PHASE
CHANNEL 1 PHASE
GND
180°
0°
1/3 INTVCC
60°
300°
2/3 INTVCC or Float
120°
240°
INTVCC
90°
270°
The SYNC pin is used to synchronize switching frequency
between the master and slave controllers. Input capacitance
ESR requirements and efficiency losses are substantially
reduced because the peak current drawn from the input
capacitor is effectively divided by the number of phases
used and power loss is proportional to the RMS current
squared. A two stage, single output voltage implementation can reduce input path power loss by 75% and radically reduce the required RMS current rating of the input
capacitor(s).
Single Output Multiphase Operation
The LTC3874-1 is configured for single output multiphase
converters with a master controller by making these connections
• Tie all the ITH pins of paralleled channels together for
current sharing between masters and slaves;
• Tie all SYNC or PLLIN pins of paralleled channels together or tie the master chip’s CLKOUT pin to the slave
chip’s SYNC pin for switching frequency synchronization
among channels.
• Tie all the RUN pins of paralleled channels together for
startup and shutdown at the same time.
• Tie the fault indictor pin of the master controller if available to the FAULT pin of the slave controller for fault
protection.
• The LTC3874-1 MODE pin can be tied to the master chip
PGOOD pin for start-up control. During soft-start, the
LTC3874-1 operates in DCM mode. When the soft-start
interval is done, the LTC3874-1 operates in CCM mode.
Examples of single output multiphase converters are
shown in Figure 1.
The Typical Application on the first page of this data sheet
is a basic LTC3874-1 application circuit configured as a
slave controller. In paralleled operation, the current sensing
scheme and circuit parameters in the LTC3874-1 have to
be the same as the master controller to achieve balanced
current sharing between masters and slaves. Input and
output capacitors are selected based on RMS current
rating, ripple and transient specs.
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9
LTC3874-1
Operation
3 PHASE OPERATION
3 PHASE + 1 PHASE OPERATION
CH0
0°
CH1
240°
CH1
CH2
0°
120°
CH1
60°
300°
LTC3866
LTC3874-1
LTC3884-1
LTC3874-1
CLKOUT
SYNC
SYNC
SYNC
PHASMD = 1/3 INTVCC
PHASMD = 1/3 INTVCC
4 PHASE OPERATION
CH1
CH2
0°
4 PHASE OPERATION
CH0
180°
CH1
90°
CH1
270°
CH2
0°
CH0
180°
CH1
90°
270°
LTC3774
LTC3874-1
LTC3884-1
LTC3874-1
CLKOUT
SYNC
SYNC
SYNC
PHASMD = FLOAT
PHASMD = GND
PHASMD = INTVCC
6 PHASE OPERATION
6 PHASE OPERATION
CH1
CH2
0°
CH0
180°
120°
CH0
CH1
240°
60°
CH0
CH1
180°
300°
CH1
CH2
0°
180°
CH0
CH1
60°
300°
CH0
CH1
120°
240°
LTC3774
LTC3874-1
LTC3874-1
LTC3884-1
LTC3874-1
LTC3874-1
CLKOUT
SYNC
SYNC
SYNC
SYNC
SYNC
PHASMD = INTVCC
PHASMD = GND
PHASMD = 2/3 INTVCC
PHASMD = 1/3 INTVCC
PHASMD = 2/3 INTVCC
38741 F01
Figure 1. Multiphase Operation
Frequency Selection and Phase-Locked Loop
(FREQ and SYNC Pins)
The selection of switching frequency is a trade-off between efficiency and component size. Low frequency
operation increases efficiency by reducing MOSFET
switching losses, but requires larger inductance and/or
capacitance to maintain low output ripple voltage. The
switching frequency of the LTC3874-1 controllers can be
selected using the FREQ pin. If the SYNC pin is not being driven by an external clock source, the FREQ pin can
be used to program the controller’s operating frequency
from 250kHz to 1MHz. There is a precision 10µA current
10
flowing out of the FREQ pin, so the user can program the
controller’s switching frequency with a single resistor to
GND. A curve is provided later in the application section
showing the relationship between the voltage on the FREQ
pin and switching frequency (Figure 5). A phase-locked
loop (PLL) is integrated in the LTC3874-1 to synchronize
the internal oscillator to an external clock source on the
SYNC pin. The PLL loop filter network is integrated inside
the LTC3874-1. The phase-locked loop is capable of locking to any frequency within the range of 250kHz to 1MHz.
The frequency setting resistor should always be present
to set the controller’s initial switching frequency before
locking to the external clock.
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Applications Information
Current Limit Programming
Table 3. Current Sense Threshold vs ITH Voltage (continued)
To match the master controller current limit, each channel
of the LTC3874-1 can be programmed separately with
the ILIM and LOWDCR pins. The 4-level logic input pin
ILIM setup summary is shown in Table 2. When ILIM is
grounded, both channels are set to be low current range.
When ILIM is tied to INTVCC, both channels are set to be
high current range.
Which setting should be used? For balanced load current
sharing, use the same current range setting as in the
master controller. Note, the LTC3874-1 does not have
active clamping circuit on ITH pin for peak current limit
and over current protection. Over current protection relies
on the master controller to drive the ITH pin not to exceed
the clamped voltage. The relationship between the current
sense threshold and ITH voltage can be found in Table 3.
Table 2. ILIM vs Range
ILIM
CHANNEL 0
CURRENT LIMIT
CHANNEL 1
CURRENT LIMIT
GND
Range Low
Range Low
1/3 INTVCC
Range High
Range Low
2/3 INTVCC or Float
Range Low
Range High
INTVcc
Range High
Range High
Table 3. Current Sense Threshold vs ITH Voltage
CURRENT SENSE THRESHOLD (mV)
LOWDCR = H
LOWDCR = L
CURRENT SENSE THRESHOLD (mV)
LOWDCR = H
LOWDCR = L
ITH (V)
RANGE = H
RANGE = L
RANGE = H
RANGE = L
1.58
18.9
10.5
47.2
26.2
1.51
17.7
9.9
44.3
24.6
1.45
16.6
9.2
41.5
23.0
1.38
15.5
8.6
38.6
21.4
ISENSE+ and ISENSE− Pins
ISENSE+ and ISENSE– are the inputs to the current comparators. When the LOWDCR pin is high, their common
mode input voltage range is 0V to 3.5V. ISENSE– should
be connected directly to VOUT of the master controller.
ISENSE+ is connected to an R • C filter with time constant
one-fifth of L/DCR of the output inductor. Care must be
taken not to float these pins during normal operation. Filter
components, especially capacitors, must be placed close
to the LTC3874-1, and the sense lines should run close
together to a Kelvin connection underneath the current
sense element. The LTC3874-1 is designed to be used with
a sub-milliohm DCR value; without proper care, parasitic
resistance, capacitance and inductance will degrade the
current sense signal integrity, making the programmed
current limit unpredictable. In Figure 2, resistor R must be
placed close to the output inductor and capacitor C close to
the IC pins to prevent noise coupling to the sense signal.
ITH (V)
RANGE = H
RANGE = L
RANGE = H
RANGE = L
2.40
32.5
18.1
81.3
45.1
2.33
31.4
17.4
78.4
43.6
2.26
30.2
16.8
75.6
42.0
2.20
29.1
16.2
72.7
40.4
2.18
28.8
16.0
72.0
40.0
2.13
28.0
15.5
69.9
38.8
2.06
26.8
14.9
67.1
37.3
1.99
25.7
14.3
64.2
35.7
The LTC3874-1 can also be used like any conventional
current mode controller by disabling the LOWDCR pin,
connecting it to ground. An RC filter can be used to sense
the output inductor signal and connects to the ISENSE+
pin. Its time constant, R • C, should equal to L/DCR of
the output inductor. By pulling down the LOWDCR pin,
the current limit increases by 2.5 times. See Table 3 for
details. In these applications, the common mode operating voltage range of ISENSE+, ISENSE– is from 0V to 5.5V.
1.92
24.6
13.6
61.4
34.1
Table 4. Output Voltage Range vs LOWDCR Pin
1.85
23.4
13.0
58.5
32.5
LOWDCR
1.79
22.3
12.4
55.7
30.9
Low
0V to 5.5V
1.72
21.1
11.7
52.8
29.4
High
0V to 3.5V
1.68
20.4
11.3
51.0
28.4
OUTPUT VOLTAGE
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11
LTC3874-1
Applications Information
VIN
VIN
INDUCTANCE
LTC3874-1
DrMOS
PWM
ISENSE+
ISENSE–
L
DCR
VOUT
Typically, C is selected in the range of 0.047µF to 0.47µF.
This forces R to around 2kΩ, reducing error that might
have been caused by the ISENSE pins’ ±1uA current.
R
C
38741 F02
Figure 2 Inductor DCR Current Sensing
Inductor DCR Current Sensing
The LTC3874-1 is specifically designed for high load current
applications requiring the highest possible efficiency; it is
capable of sensing the signal of an inductor DCR in the
sub-milliohm range (Figure 2). The DCR is the DC winding
resistance of the inductor’s copper, which is often less
than 1mΩ for high current inductors. In high current and
low output voltage applications, conduction loss of a high
DCR or a sense resistor will cause a significant reduction
in power efficiency. For a specific output requirement,
choose the inductor with the DCR that satisfies the maximum desirable sense voltage, and use the relationship of
the sense pin filters to output inductor characteristics as
depicted below.
DCR =
VISENSE(MAX)
ΔI
IMAX + L
2
RC = L/DCR when the LOWDCR pin is low
where:
VISENSE(MAX): Maximum sense voltage for a given ITH
voltage
IMAX: Maximum load current
ΔIL: Inductor ripple current
L, DCR: Output inductor characteristics
12
There will be some power loss in R that relates to the duty
cycle. It will be highest in continuous mode at maximum
input voltage:
PLOSS (R) =
( VIN(MAX) − VOUT ) • VOUT
R
Ensure that R has a power rating higher than this value.
However, DCR sensing eliminates the conduction loss
of a sense resistor; it will provide a better efficiency at
heavy loads. To maintain a good signal-to-noise ratio for
the current sense signal, using a minimum ∆VISENSE of
2mV for duty cycles less than 40% is desirable when the
LOWDCR pin is high; use a minimum ∆VISENSE of 10mV
for duty cycles less than 40% when the LOWDCR pin is
low. The actual ripple voltage will be determined by the
following equation:
ΔVISENSE =
VOUT ⎛ VIN − VOUT ⎞
VIN ⎜⎝ R C • fOSC ⎟⎠
Inductor Value Calculation
RC = L/(5 • DCR) when the LOWDCR pin is high
R, C: Filter time constant
To ensure that the load current will be delivered over the full
operating temperature range, the temperature coefficient
of the DCR resistance, approximately 0.4%/°C, should be
taken into consideration.
Given the desired input and output voltages, the inductor
value and operating frequency, fOSC, directly determine
the inductor’s peak-to-peak ripple current:
IRIPPLE =
VOUT ⎛ VIN – VOUT ⎞
VIN ⎜⎝ fOSC • L ⎟⎠
Lower ripple current reduces core losses in the inductor,
ESR losses in the output capacitors, and output voltage
ripple. Thus, highest efficiency operation is obtained at
low frequency with a small ripple current. Achieving this,
however, requires a large inductor.
A reasonable starting point is to choose a ripple current
that is about 40% of IOUT(MAX). Note that the largest ripple
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Applications Information
current occurs at the highest input voltage. To guarantee
that ripple current does not exceed a specified maximum,
the inductor should be chosen according to:
L≥
VIN – VOUT VOUT
•
fOSC •IRIPPLE VIN
Inductor Core Selection
Once the inductance value is determined, the type of inductor must be selected. Core loss is independent of core
size for a fixed inductor value, but it is very dependent on
inductance selected. As inductance increases, core losses
go down. Unfortunately, increased inductance requires
more turns of wire and therefore copper losses will increase.
Ferrite designs have very low core loss and are preferred
at high switching frequencies, so design goals can
concentrate on copper loss and preventing saturation.
Ferrite core material saturates “hard,” which means that
inductance collapses abruptly when the peak design current
is exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
Power MOSFET and Schottky Diode
(Optional) Selection
When we use discrete gate driver and MOSFETs, at least
two external power MOSFETs need to be selected: One
N-channel MOSFET for the top (main) switch and one or
more N‑channel MOSFET(s) for the bottom (synchronous)
switch. The number, type and on-resistance of all MOSFETs
selected take into account the voltage step-down ratio
as well as the actual position (main or synchronous) in
which the MOSFET will be used. A much smaller and much
lower input capacitance MOSFET should be used for the
top MOSFET in applications that have an output voltage
that is less than one-third of the input voltage. In applications where VIN >> VOUT , the top MOSFETs’ on-resistance
is normally less important for overall efficiency than its
input capacitance at operating frequencies above 300kHz.
MOSFET manufacturers have designed special purpose
devices that provide reasonably low on-resistance with
significantly reduced input capacitance for the main switch
application in switching regulators.
The peak-to-peak MOSFET gate drive levels are set by the
internal regulator voltage, VINTVCC, requiring the use of
logic-level threshold MOSFETs in most applications. Pay
close attention to the BVDSS specification for the MOSFETs
as well; many of the logic-level MOSFETs are limited to
30V or less. Selection criteria for the power MOSFETs
include the on-resistance, RDS(ON), input capacitance,
input voltage and maximum output current. MOSFET input
capacitance is a combination of several components but
can be taken from the typical gate charge curve included
on most data sheets (Figure 3). The curve is generated by
forcing a constant input current into the gate of a common
source, current source loaded stage and then plotting the
gate voltage versus time.
VIN
VGS
MILLER EFFECT
a
V
b
QIN
CMILLER = (QB – QA)/VDS
+
VGS
–
+V
DS
–
38741 F03
Figure 3. Gate Charge Characteristic
The initial slope is the effect of the gate-to-source and
the gate-to-drain capacitance. The flat portion of the
curve is the result of the Miller multiplication effect of the
drain-to-gate capacitance as the drain drops the voltage
across the current source load. The upper sloping line is
due to the drain-to-gate accumulation capacitance and
the gate-to-source capacitance. The Miller charge (the
increase in coulombs on the horizontal axis from a to b
while the curve is flat) is specified for a given VDS drain
voltage, but can be adjusted for different VDS voltages by
multiplying the ratio of the application VDS to the curve
specified VDS values. A way to estimate the CMILLER term
is to take the change in gate charge from points a and b
on a manufacturer’s data sheet and divide by the stated
VDS voltage specified. CMILLER is the most important selection criteria for determining the transition loss term in
the top MOSFET but is not directly specified on MOSFET
data sheets. CRSS and COS are specified sometimes but
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13
LTC3874-1
Applications Information
definitions of these parameters are not included. When the
controller is operating in continuous mode the duty cycles
for the top and bottom MOSFETs are given by:
Main Switch Duty Cycle =
VOUT
VIN
⎛V –V ⎞
Synchronous Switch Duty Cycle = ⎜ IN OUT ⎟
VIN
⎝
⎠
The power dissipation for the main and synchronous
MOSFETs at maximum output current are given by:
PMAIN =
( ) (1+ δ )RDS(ON) +
VOUT
IMAX
VIN
2
⎛ IMAX ⎞
(RDR )(CMILLER ) •
⎝ 2 ⎟⎠
( VIN )2 ⎜
The term (1 + δ ) is generally given for a MOSFET in the
form of a normalized RDS(ON) vs temperature curve, but
δ = 0.005/°C can be used as an approximation for low
voltage MOSFETs.
An optional Schottky diode across the synchronous
MOSFET conducts during the dead time between the conduction of the two large power MOSFETs. This prevents the
body diode of the bottom MOSFET from turning on, storing
charge during the dead time and requiring a reverse-recovery period which could cost as much as several percent in
efficiency. A 2A to 8A Schottky is generally a good compromise for both regions of operation due to the relatively
small average current. Larger diodes result in additional
transition loss due to their larger junction capacitance.
INTVCC Regulators and EXTVCC
where δ is the temperature dependency of RDS(ON), RDR
is the effective top driver resistance (approximately 2Ω at
VGS = VMILLER), VIN is the drain potential and the change
in drain potential in the particular application. VTH(MIN)
is the data sheet specified typical gate threshold voltage
specified in the power MOSFET data sheet at the specified
drain current. CMILLER is the calculated capacitance using
the gate charge curve from the MOSFET data sheet and
the technique described above.
The LTC3874-1 features a PMOS LDO that supplies power
to INTVCC from the VIN supply. INTVCC powers most of
the LTC3874-1’s internal circuitry. The linear regulator
regulates the voltage at the INTVCC pin to 5.5V when VIN
is greater than 6V. EXTVCC connects to INTVCC through
another P-channel MOSFET and can supply the needed
power when its voltage is higher than 4.7V and VIN is
higher than 7V. Each of these can supply a peak current of
100mA and must be bypassed to ground with a minimum
value of 4.7µF ceramic capacitor or low ESR electrolytic
capacitor. No matter what type of bulk capacitor is used,
an additional 0.1µF ceramic capacitor placed directly adjacent to the INTVCC and GND pins is highly recommended.
Good bypassing is needed to prevent interaction between
the channels.
Both MOSFETs have I2R losses while the topside N-channel
equation includes an additional term for transition losses,
which peak at the highest input voltage. For VIN < 20V,
the high current efficiency generally improves with larger
MOSFETs, while for VIN > 20V, the transition losses rapidly
increase to the point that the use of a higher RDS(ON) device
with lower CMILLER actually provides higher efficiency. The
synchronous MOSFET losses are greatest at high input
voltage when the top switch duty factor is low or during
a short-circuit when the synchronous switch is on close
to 100% of the period.
For applications where the main input power is 5V, tie
the VIN and INTVCC pins together and tie the combined
pins to the 5V input with a 1Ω or 2.2Ω resistor as shown
in Figure 4 to minimize the voltage drop caused by the
gate charge current. This will override the INTVCC linear
⎡
1 ⎤
1
+
⎢
⎥•f
⎢⎣ VINTVCC – VTH(MIN) VTH(MIN) ⎥⎦
2
V –V
PSYNC = IN OUT IMAX (1+ δ )RDS(ON)
VIN
( )
14
When the voltage applied to EXTVCC rises above 4.7V and
VIN above 7V, the INTVCC linear regulator is turned off and
the EXTVCC is connected to INTVCC. Using the EXTVCC allows the MOSFET driver and control power to be derived
from other high efficiency sources such as +5V rails in
the system. Do not apply more than 6V to the EXTVCC pin.
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Applications Information
regulator and will prevent INTVCC from dropping too low
due to the dropout voltage. Make sure the INTVCC voltage
is at or exceeds the RDS(ON) test voltage for the MOSFET,
which is typically 4.5V for logic-level devices.
LTC3874-1
VIN
INTVCC
RVIN
1Ω
CINTVCC
4.7µF
+
5V
CIN
38741 F04
Figure 4. Setup for a 5V Input
The relationship between the voltage on the FREQ pin and
the operating frequency is shown in Figure 5 and specified
in the Electrical Characteristic table. If an external clock is
detected on the SYNC pin, the internal switch mentioned
above will turn off and isolate the influence of the FREQ
pin. Note that the LTC3874-1 can only be synchronized
to an external clock whose frequency is within the range
of the LTC3874-1’s internal VCO. This is guaranteed to be
between 250kHz and 1MHz. A simplified block diagram
is shown in Figure 6.
1600
Undervoltage Lockout
1400
The LTC3874-1 has a precision UVLO comparator constantly monitoring the INTVCC voltage. It locks out the
switching action and pulls down RUN pins when INTVCC is
below 3.5V. In multiphase operation, when the LTC3874-1
is in undervoltage lockout, the RUN pin is pulled down to
disable the master’s switching action. To prevent oscillation when there is a disturbance on the INTVCC, the UVLO
comparator has 300mV of precision hysteresis.
Phase-Locked Loop and Frequency Synchronization
The LTC3874-1 has a phase-locked loop (PLL) comprised
of an internal voltage-controlled oscillator (VCO) and a
phase detector. This allows the internal clock to be locked
to the falling edge of an external clock signal applied to the
SYNC pin. The turn-on of the top MOSFET is synchronized
or out-of-phase with the falling edge of external clock.
The phase detector is an edge sensitive digital type that
provides zero degrees phase shift between the external
and internal oscillators. This type of phase detector does
not exhibit false lock to harmonics of the external clock.
The output of the phase detector is a pair of complementary current sources that charge or discharge the internal
filter network. There is a precision 10µA of current flowing
out of the FREQ pin. This allows the user to use a single
resistor to GND to set the switching frequency when no
external clock is applied to the SYNC pin. The internal
switch between the FREQ pin and the integrated PLL
filter network is ON, allowing the filter network to be precharged to the same voltage potential as the FREQ pin.
FREQUENCY (kHz)
1200
1000
800
600
400
200
0
0
0.5
1
1.5
2
FREQ PIN VOLTAGE (V)
2.5
38741 F05
Figure 5. Relationship Between Oscillator Frequency
and Voltage at the FREQ Pin
2.4V 5.5V
RSET
10µA
FREQ
EXTERNAL
OSCILLATOR
SYNC
DIGITAL
SYNC
PHASE/
FREQUENCY
DETECTOR
VCO
38741 F06
Figure 6. Phase-Locked Loop Block Diagram
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15
LTC3874-1
Applications Information
If the external clock frequency is greater than the internal oscillator’s frequency, fOSC, then current is sourced
continuously from the phase detector output, pulling up
the filter network. When the external clock frequency is
less than fOSC, current is sunk continuously, pulling down
the filter network. If the external and internal frequencies
are the same but exhibit a phase difference, the current
sources turn on for an amount of time corresponding to
the phase difference. The voltage on the filter network is
adjusted until the phase and frequency of the internal and
external oscillators are identical. At the stable operating
point, the phase detector output is high impedance and
the filter capacitor holds the voltage.
Typically, the external clock (on the SYNC pin) input high
threshold is 2V, while the input low threshold is 1.4V.
Fault Protection and Response
Master controllers monitor system voltage, current, temperature and provide many protection features during all
kinds of fault conditions. The LTC3874-1 slave controllers do not provide as many fault protections as master
controllers but respond to the fault signal from the master
controller. FAULT0 and FAULT1 pins are designed to share
the fault signal between masters and slaves. In a typical
parallel application, connect the fault pins on LTC3874-1
to the master fault indictor pins, so that the slave controller can respond to all fault signals from the master. When
the FAULT pin is pulled below 1.4V, the PWM pin in the
corresponding channel is in three-state. When the FAULT
pin voltage is above 2V, the corresponding channel is back
to normal operation. During fault conditions, all internal
circuits in the LTC3874-1 are still running so the slave
controllers can immediately return to normal operation
when the FAULT pin is released.
The LTC3874-1 has internal thermal shutdown protection
which forces the PWM pin three-state when the junction
temperature is higher than 160°C. The thermal shutdown
has 10°C of hysteresis. In thermal shutdown, the FAULT0
and FAULT1 pins are also pulled low. The RUN pins are not
internally pulled low. There is a 500k pull-down resistor
on each FAULT pin which sets the default voltage on the
FAULT pins low if the FAULT pins are floating.
16
Transient Response and Loop Stability
In a typical parallel operation, the LTC3874-1 cooperates
with master controllers to supply more current. To achieve
balanced current sharing between master and slave, it is
recommended that each slave channel copies the power
stage design from the master channel. Select the same
inductors, same MOSFET driver, same power MOSFETs,
and same output capacitors between the master and slave
channels. Control loop and compensation design on the
ITH pin should start with the single phase operation of the
master controller. The multiphase transient response and
loop stability is almost the same as the single phase operation of the master by tying the ITH pins together between
master and slaves. For example, design the compensation
for a single phase 1.8V/20A output using LTC3884-1 with
a 0.33μH inductor and 530μF output capacitors. To extend
the output to 1.8V/40A, simply parallel one channel of
LTC3874-1 with the same inductor and output capacitors
(total output capacitors are 1060μF) and tie the ITH pin of
LTC3874-1 to the master ITH. The loop stability and transient
responses of the two phase converter are very similar to
the single phase design without any extra compensator
on the ITH pin of the slave controller. Furthermore, LTpowerCAD is provided on the LTC website as a free download
for transient and stability analysis.
To minimize the high frequency noise on the ITH trace
between master and slave ITH pins, a small filter capacitor
in the range of tens of pF can be placed closely at each ITH
pin of the slave controller. This small capacitor normally
does not significantly affect the closed-loop bandwidth
but increases the gain margin at high frequency.
Mode Selection and Pre-Biased Startup
There may be situations that require the power supply to
start up with a pre-bias on the output capacitors. In this
case, it is desirable to start up without discharging the
output capacitors. The LTC3874-1 can be configured to
operate in DCM mode for pre-biased start-up. The master
chip’s PGOOD pin can be connected to the MODE pins of
the LTC3874-1 to ensure the DCM operation at startup
and CCM operation in steady state.
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Minimum On-Time Considerations
MOSFET Driver Selection
Minimum on-time tON(MIN) is the smallest time duration that
the LTC3874-1 is capable of turning on the top MOSFET.
It is determined by internal timing delays and the gate
charge required to turn on the top MOSFET. Low duty
cycle applications may approach this minimum on-time
limit and care should be taken to ensure that:
Gate driver ICs, DrMOSs and power blocks with an interface compatible with the LTC3874-1’s three-state PWM
outputs should be used.
tON(MIN) <
VOUT
VIN • f
If the duty cycle falls below what can be accommodated
by the minimum on-time, the controller will begin to skip
cycles. The output voltage will continue to be regulated, but
the ripple voltage and current will increase. The minimum
on-time for the LTC3874-1 is approximately 60ns, with
reasonably good PCB layout, minimum 30% inductor current ripple and at least 2mV – 3mV (10mV – 15mV when
the LOWDCR pin is low) ripple on the current sense signal.
The minimum on-time can be affected by PCB switching noise in the current loop. As the peak sense voltage
decreases the minimum on-time gradually increases to
100ns. This is of particular concern in forced continuous
applications with low ripple current at light loads. If the
duty cycle drops below the minimum on-time limit in this
situation, a significant amount of cycle skipping can occur
with correspondingly larger current and voltage ripple.
PWM Pins
The PWM output pins are three-state compatible outputs,
designed to drive MOSFET drivers, DrMOSs, etc. which do
not represent a heavy capacitive load. An external resistor
divider may be used on the PWM pins to set the voltage
to mid-rail while in the high impedance state.
The VCC pin is the corresponding PWM pin driver supply.
Decouple this pin to GND with a capacitor (0.1μF) or tie
this pin to the INTVCC pin. If the VCC pin is connected to
an external supply, make sure it comes first before the
RUN pin goes high.
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the IC. Figure 7 illustrates the current waveforms present in the various branches of the 2-phase synchronous
regulators operating in the continuous mode. Check the
following in the PC layout:
1. Are the signal and power grounds kept separate? The
combined IC signal ground pin and the ground return
of CINTVCC must return to the combined COUT (–) terminals. The ITH traces should be as short as possible.
The CIN capacitor should have short leads and PC trace
lengths. The output capacitor (–) terminals should be
connected as close as possible to the (–) terminals of
the input capacitor by placing the capacitors next to
each other.
2. Are the ISENSE+ and ISENSE– leads routed together with
minimum PC trace spacing? The filter capacitor between
ISENSE+ and ISENSE– should be as close as possible to
the IC. Ensure accurate current sensing with Kelvin
connections at the sense resistor or inductor, whichever
is used for current sensing.
3. Is the INTVCC decoupling capacitor connected close to
the IC, between the INTVCC and the ground pins? This
capacitor carries the MOSFET drivers current peaks. An
additional 1μF ceramic capacitor placed immediately
next to the INTVCC and GND pins can help improve
noise performance substantially.
4. Keep the switching nodes (SW1, SW0), away from
sensitive small-signal nodes, especially from the opposite channel’s current sensing feedback pins. All of
these nodes have very large and fast moving signals
and therefore should be kept on the output side of the
LTC3874-1 and occupy minimum PC trace area. If DCR
sensing is used, place the resistor (Figure 2, “R”) close
to the switching node.
38741f
For more information www.linear/LTC3874-1
17
LTC3874-1
Applications Information
SW1
L1
D1
VOUT1
COUT1
RL1
VIN
RIN
CIN
SW0
BOLD LINES INDICATE
HIGH SWITCHING
CURRENT. KEEP LINES
TO A MINIMUM LENGTH.
D0
L0
VOUT0
COUT0
RL0
38741 F07
Figure 7. Recommended Printed Circuit Layout Diagram
5. Use a modified star ground technique: a low impedance,
large copper area central grounding point on the same
side of the PC board as the input and output capacitors
with tie-ins for the bottom of the INTVCC decoupling
capacitor, the bottom of the voltage feedback resistive
divider and the GND pin of the IC.
PC Board Layout Debugging
Start with one controller at a time. It is helpful to use a
DC-50MHz current probe to monitor the current in the
inductor while testing the circuit. Monitor the output
switching node (SW pin) to synchronize the oscilloscope
to the internal oscillator and probe the actual output voltage
18
as well. Check for proper performance over the operating
voltage and current range expected in the application. The
frequency of operation should be maintained over the input
voltage range down to dropout and until the output load
drops below the low current operation threshold.
The duty cycle percentage should be maintained from cycle
to cycle in a well-designed, low noise PCB implementation.
Variation in the duty cycle at a subharmonic rate can suggest noise pickup at the current or voltage sensing inputs
or inadequate loop compensation. Overcompensation of
the loop can be used to tame a poor PC layout if regulator
bandwidth optimization is not required. Only after each
controller is checked for its individual performance should
38741f
For more information www.linear.com/LTC3874-1
LTC3874-1
Applications Information
both controllers be turned on at the same time. A particularly
difficult region of operation is when one controller channel
is nearing its current comparator trip point when the other
channel is turning on its top MOSFET. This occurs around
50% duty cycle on either channel due to the phasing of
the internal clocks and may cause minor duty cycle jitter.
Reduce VIN from its nominal level to verify operation of
the regulator in dropout. Check the operation of the undervoltage lockout circuit by further lowering VIN while
monitoring the outputs to verify operation.
Investigate whether any problems exist only at higher output currents or only at higher input voltages. If problems
coincide with high input voltages and low output currents,
look for capacitive coupling between the BOOST, SW, TG,
and possibly BG connections and the sensitive voltage
and current pins. The capacitor placed across the current
sensing pins needs to be placed immediately adjacent to
the pins of the IC. This capacitor helps to minimize the
effects of differential noise injection due to high frequency
capacitive coupling. If problems are encountered with
high current output loading at lower input voltages, look
for inductive coupling between CIN, Schottky and the top
MOSFET components to the sensitive current and voltage
sensing traces. In addition, investigate common ground
path voltage pickup between these components and the
GND pin of the IC.
The master chip LTC3884-1 design can be found in the
LTC3884-1 data sheet (Design Example section).
The LTC3884-1 SYNC pin is connected to the LTC3874-1
SYNC pin for switching frequency synchronization. The
LTC3874-1 PHASMD pin is tied to INTVCC to form a
PolyPhase configuration.
The slave chip LTC3874-1 should use the same inductor,
DrMOS, CIN, and COUT as the master chip. DCR sensing
is also used for the slave chip. The LTC3884-1 ITH pins
and the LTC3874-1 ITH pins are connected together. The
LTC3874-1 LOWDCR pin is pulled high and the ILIM pin
is forced to INTVCC to obtain the same current limit as
LTC3884-1.
The LTC3884-1 RUN pins and the LTC3874-1 RUN pins
are connected together. The LTC3884-1 FAULT pins are
connected to LTC3874-1 FAULT pins so the LTC3874-1
will be disabled if the LTC3884-1 is under any fault event.
The LTC3874-1 MODE pins are tied to the LTC3884-1
PGOOD pins for start-up control. During soft-start, the
LTC3874-1 operates in DCM mode. When the soft-start
interval is done, the LTC3874-1 operates in CCM mode.
Design Example
Using master controller LTC3884-1 and slave controller
LTC3874-1 for a single-output, 4-phase high current
regulator, assume VIN = 12V (nominal), and VIN = 15V
(maximum), VOUT = 1.05V, IMAX = 120A, and f = 500kHz
(see Figure 8).
38741f
For more information www.linear/LTC3874-1
19
LTC3874-1
Applications Information
0.47µF
1mΩ
649Ω
1Ω
VIN
7V TO 14V
4.7µF
2.2µF
VIN
VOUT
10nF
5k
5k
5k
5k
VDD33
4.7µF
+
–
IIN
IIN
PWM0
VSENSE1+
ISENSE0+
VSENSE0–
ISENSE0–
VSENSE1–
ISENSE1–
WP
ISENSE1+
TSNS1
BOOT
PHASE
VIN
TDA21470
SW
EN
22µF
×4
VDR
5V
TOUT/FLT
VDRV
PGND
4.7µF
LGND
+
330pF
4.7µF
220nF
VOUT
1.05 V
120A
COUT2
470µF
×2
2.5V
PWM1
ITH0
SDA
ITH
ITH1
SCL
ITHR0
SHARE_CLK
ITHR1
ALERT
VDD25
VDD33
VOUT 0_CFG
VCC0
VOUT 1_CFG
330pF
6.8nF
0.47µF
VIN1
24.9k
20k
24.9k
BOOT
PHASE
VIN
TDA21470
SW
EN
22µF
×4
1µF
17.8k
5.76k
VDR
5V
PGOOD0
EXTVCC
PGOOD1
PHAS_CFG
PWM
TOUT/FLT
VDRV
PGND
VCC
4.7µF
FREQ_CFG
SYNC
0.215µH, L2
COUT3
100µF
×3
6.3V
VOS
ASEL0
RUN1
0Ω
649Ω
7.32k
RUN0
5k
PWM
VCC
FAULT1
5k
COUT1
100µF
×3
6.3V
VOS
FAULT0
5k
0.215µH, L1
LTC3884-1
VCC1
5k
VIN1
220nF
INTVCC
VSENSE0+
TSNS0
10nF
0Ω
VIN1
LGND
330pF
4.7µF
GND
0.47µF
COUT4
470µF
×2
2.5V
+
0Ω
2Ω
VIN
7V TO 14V
VIN
INTVCC
RUN0
PHASM0
LTC3874-1
RUN1
ILIM
0.1µF
SYNC
VIN1
4.7µF
PWM0
PWM
TOUT/FLT
MODE1
ISENSE0+
VDRV
PGND
VDR
5V
220nF
FAULT0
VCC0
VCC1
47pF
ITH1
VCC
4.7µF
LGND
4.7µF
PWM1
COUT5
100µF
×3
6.3V
+
COUT6
470µF
×2
2.5V
330pF
+
ISENSE1
649Ω
ISENSE1–
ITH0
ITH
0.215µH, L3
VOS
MODE0
FAULT1
1µF
22µF
×4
LOWDCR
ISENSE0–
VDD33
BOOT
PHASE
VIN
TDA21470
SW
EN
FREQ
100k
0.47µF
GND
VIN1
PIN NOT USED IN CIRCUIT LTC3884-1: ASEL1
PIN NOT USED IN CIRCUIT LTC3874-1: EXTVCC
BOOT
PHASE
VIN
TDA21470
SW
EN
22µF
×4
0.215µH, L4
COUT7
100µF
×3
6.3V
VOS
PINS NOT USED IN CIRCUITS TDA21470: REFIN , GATEL, IOUT, OCSET
COUT1, 3, 5, 7: MURATA GRM32ER60J107ME20L (100µF, 6.3V, X5R, 1210)
COUT2, 4, 6, 8: PANASONIC ETPF470M5H (470µF, 2.5V)
L1, L2, L3, L4: EATON FP1007R3-R22-R (0.215µH, DCR = 0.29mΩ)
VDR IS FROM EXTERNAL 5V POWER SUPPLY
0Ω
220nF
VDR
5V
PWM
TOUT/FLT
VDRV
PGND
VCC
4.7µF
LGND
4.7µF
+
COUT8
470µF
×2
2.5V
3874 F08
330pF
649Ω
Figure 8. High Efficiency 500kHz 4-Phase 1.05V Step-Down Converter
20
38741f
For more information www.linear.com/LTC3874-1
LTC3874-1
Package Description
Please refer to http://www.linear.com/product/LTC3874-1#packaging for the most recent package drawings.
UF Package
24-Lead Plastic QFN (4mm × 4mm)
(Reference LTC DWG # 05-08-1697 Rev B)
0.70 ±0.05
4.50 ±0.05
2.45 ±0.05
3.10 ±0.05 (4 SIDES)
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
4.00 ±0.10
(4 SIDES)
BOTTOM VIEW—EXPOSED PAD
R = 0.115
TYP
0.75 ±0.05
PIN 1 NOTCH
R = 0.20 TYP OR
0.35 × 45° CHAMFER
23 24
PIN 1
TOP MARK
(NOTE 6)
0.40 ±0.10
1
2
2.45 ±0.10
(4-SIDES)
(UF24) QFN 0105 REV B
0.200 REF
0.00 – 0.05
0.25 ±0.05
0.50 BSC
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-X)—TO BE APPROVED
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
38741f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representaFor of
more
information
www.linear/LTC3874-1
tion that the interconnection
its circuits
as described
herein will not infringe on existing patent rights.
21
LTC3874-1
Typical Application
High Efficiency Dual 1.0V/1.5V Step-Down Converter
VIN
7V TO 14V
VIN
(0.29mΩ DCR)
0.215µH
VOUT0
1V
60A
+
470µF
×2
100µF
×3
DrMOS
(0.29mΩ DCR)
0.215µH
649Ω
0.22µF
LTC3884-1
1V
VOUT1
DrMOS
649Ω
0.22µF
REFER TO LTC3884-1 DATA SHEET
FOR MASTER SETUP
LTC3874-1
PWM0
PWM1
1.5V
VSENSE0+
VSENSE1+
RUN0
RUN1
FAULT0
FAULT1
PGOOD0
PGOOD1
ITH0
ITH1
SYNC
ISENSE0+
ISENSE0–
ISENSE1+
ISENSE1–
RUN0
RUN1
FAULT0
FAULT1
MODE0
MODE1
ITH0
ITH1
SYNC
INTVCC
VCC0
VCC1
PHASMD
LDWDCR
ILIM
PIN NOT USED IN THIS CIRCUIT: EXTVCC
FREQ
GND
VOUT1
1.5V
60A
100µF
×3
+
470µF
×2
4.7µF
100k
3874 TA02
Related Parts
PART NUMBER DESCRIPTION
COMMENTS
LTM4676A
Dual 13A or Single 26A Step-Down DC/DC µModule Regulator 4.5V ≤ VIN ≤17V; 0.5V ≤ VOUT (±0.5%) ≤ 5.5V, I2C/PMBus Interface,
with Digital Power System Management
16mm × 16mm × 5mm, BGA Package
LTM4675
Dual 9A or Single 18A μModule Regulator with Digital Power
System Management
4.5V ≤ VIN ≤17V; 0.5V ≤ VOUT (±0.5%) ≤ 5.5V, I2C/PMBus Interface,
11.9mm × 16mm × 5mm, BGA Package
LTM4677
Dual 18A or Single 36A μModule Regulator with Digital Power
System Management
4.5V ≤ VIN ≤16V; 0.5V ≤ VOUT (±0.5%) ≤ 1.8V, I2C/PMBus Interface,
16mm × 16mm × 5.01mm, BGA Package
LTC3884/
LTC3884-1
Dual Output Multiphase Step-Down Controller with Sub mΩ
DCR Sensing Current Mode Control and Digital Power System
Management
4.5V ≤ VIN ≤ 38V, 0.5V ≤ VOUT (±0.5%) ≤ 5.5V, 70ms Start-Up, I2C/
PMBus Interface, Programmable Analog Loop Compensation, Input
Current Sense
LTC3887/
LTC3887-1
Dual Output Multiphase Step-Down DC/DC Controller with
Digital Power System Management, 70ms Start-Up
4.5V ≤ VIN ≤ 24V, 0.5V ≤ VOUT0,1 (±0.5%) ≤ 5.5V, 70ms Start-Up, I2C/
PMBus Interface, -1 Version Uses DrMOS or Power Blocks
LTC3882/
LTC3882-1
Dual Output Multiphase Step-Down DC/DC Voltage Mode
Controller with Digital Power System Management
3V ≤ VIN ≤ 38V, 0.5V ≤ VOUT1,2 ≤ 5.25V, ±0.5% VOUT Accuracy I2C/
PMBus Interface, Uses DrMOS or Power Blocks
LTC3866
Single Output Current Mode Synchronous Step-Down
Controller with Sub-Milliohm DCR Sensing
4.5V ≤ VIN ≤ 38V, 0.6V ≤ VOUT ≤ 3.5V, with Remote VOUT Sense, 4mm
× 4mm, QFN-24, TSSOP-24 Packages
LTC3883/
LTC3883-1
Single Phase Step-Down DC/DC Controller with Digital Power
System Management
VIN Up to 24V, 0.5V ≤ VOUT ≤ 5.5V, Input Current Sense Amplifier, I2C/
PMBus Interface with EEPROM and 16-Bit ADC, ±0.5% VOUT Accuracy
LTC3875
Dual, Multiphase Current Mode Synchronous Step-Down
Controller with Sub-Milliohm DCR Sensing, Up to 12 Phases
4.5V ≤ VIN ≤ 38V, 0.6V ≤ VOUT ≤ 3.5V, with Remote Sense
LTC3774
Dual, Multiphase Current Mode Synchronous Step-Down
Controller with Sub-Milliohm DCR Sensing, Up to 12 Phases
VIN Up to 40V, 0.6V ≤ VOUT ≤ 3.5V, Very High Output Current
Applications with Accurate Current Share Between Phases
Supporting LTC3880/-1, LTC3883/-1, LTC3886, LTC3887/-1
LTC3877
Dual Phase Step-Down Synchronous Controller with 6-Bit VID
Output Voltage Programming and Low Value DCR Sensing
4.5V ≤ VIN ≤ 38V, 0.6V ≤ VOUT ≤ 1.23V with VID in 10mV Steps, 0.6V ≤
VOUT ≤ 5V without VID, Up to 12-Phase Operation
22
®
38741f
LT 0917 • PRINTED IN USA
For more information www.linear.com/LTC3874-1
www.linear.com/LTC3874-1
 LINEAR TECHNOLOGY CORPORATION 2017