CY7C1361C/CY7C1363C 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM Features Functional Description ■ Supports 100, 133 MHz Bus Operations ■ Supports 100 MHz Bus Operations (Automotive) ■ 256K × 36/512K × 18 Common I/O ■ 3.3V –5% and +10% Core Power Supply (VDD) ■ 2.5V or 3.3V I/O Power Supply (VDDQ) ■ Fast Clock-to-Output Times ❐ 6.5 ns (133-MHz version) ■ Provide High Performance 2-1-1-1 Access Rate ■ User-selectable Burst Counter supporting Intel® Pentium® Interleaved or Linear Burst Sequences ■ Separate Processor and Controller Address Strobes ■ Synchronous Self-timed Write ■ Asynchronous Output Enable ■ Available in Pb-free 100-Pin TQFP Package, Pb-free and non Pb-free 119-Ball BGA Package, and 165-Ball FBGA Package ■ TQFP Available with 3-Chip Enable and 2-Chip Enable ■ IEEE 1149.1 JTAG-Compatible Boundary Scan ■ “ZZ” Sleep Mode option The CY7C1361C/CY7C1363C[1] is a 3.3V, 256K x 36/512K x 18 synchronous flow-through SRAMs, respectively designed to interface with high speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133 MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE1), depth-expansion Chip Enables (CE2 and CE3[2]), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (BWx, and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and the ZZ pin. The CY7C1361C/CY7C1363C enables either interleaved or linear burst sequences, selected by the MODE input pin. A HIGH selects an interleaved burst sequence, while a LOW selects a linear burst sequence. Burst accesses can be initiated with the Processor Address Strobe (ADSP) or the cache Controller Address Strobe (ADSC) inputs. Address advancement is controlled by the Address Advancement (ADV) input. Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor (ADSP) or Address Strobe Controller (ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin (ADV). The CY7C1361C/CY7C1363C operates from a +3.3V core power supply while all outputs may operate with either a +2.5 or +3.3V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible. Selection Guide Description Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current Commercial/ Industrial 133 MHz 100 MHz Unit 6.5 8.5 ns 250 180 mA 40 40 mA 60 mA Automotive Notes 1. For best-practices recommendations, refer to the Cypress application note System Design Guidelines on www.cypress.com. 2. CE3 is for A version of TQFP (3 Chip Enable Option) and 165 FBGA package only. 119 BGA is offered only in 2 Chip Enable. Cypress Semiconductor Corporation Document #: 38-05541 Rev. *G • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised August 26, 2009 [+] Feedback CY7C1361C/CY7C1363C Logic Block Diagram – CY7C1361C (256K x 36) ADDRESS REGISTER A 0, A1, A A [1:0] MODE BURST Q1 COUNTER AND LOGIC Q0 CLR ADV CLK ADSC ADSP DQ D , DQP D DQ D , DQP D BW D BYTE BYTE WRITE REGISTER WRITE REGISTER DQ C, DQP C DQ C, DQP C BW C BYTE BYTE WRITE REGISTER WRITE REGISTER DQ B , DQP B BW B DQ B , DQP B BYTE BYTE WRITE REGISTER MEMORY ARRAY SENSE AMPS OUTPUT BUFFERS DQ s DQP A DQP B DQP C DQP D WRITE REGISTER DQ A , DQP A BW A BWE DQ A , DQPA BYTE BYTE WRITE REGISTER WRITE REGISTER INPUT REGISTERS GW ENABLE REGISTER CE1 CE2 CE3 OE SLEEP CONTROL ZZ Logic Block Diagram – CY7C1363C (512K x 18) A0,A1,A ADDRESS REGISTER A[1:0] MODE BURST Q1 COUNTER AND LOGIC CLR Q0 ADV CLK ADSC ADSP BW B DQ B ,DQP B WRITE REGISTER BW A DQ A ,DQP A WRITE REGISTER DQ B ,DQP B WRITE DRIVER MEMORY ARRAY SENSE AMPS OUTPUT BUFFERS DQs DQP A DQP B DQ A ,DQP A WRITE DRIVER BWE GW CE 1 CE 2 CE 3 ENABLE REGISTER INPUT REGISTERS OE ZZ Document #: 38-05541 Rev. *G SLEEP CONTROL Page 2 of 32 [+] Feedback CY7C1361C/CY7C1363C Pin Configurations NC NC NC CY7C1363C (512K x 18) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 VDDQ VSSQ NC NC DQB DQB VSSQ VDDQ DQB DQB VSS/DNU VDD NC VSS DQB DQB VDDQ VSSQ DQB DQB DQPB NC VSSQ VDDQ NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 MODE A A A A A1 A0 NC NC VSS VDD NC A A A A A A A A DQPB DQB DQB VDDQ VSSQ DQB DQB DQB DQB VSSQ VDDQ DQB DQB VSS NC VDD ZZ DQA DQA VDDQ VSSQ DQA DQA DQA DQA VSSQ VDDQ DQA DQA DQPA 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 CY7C1361C (A) (256K x 36) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 MODE A A A A A1 A0 NC NC VSS VDD NC A A A A A A A A DQPC DQC DQC VDDQ VSSQ DQC DQC DQC DQC VSSQ VDDQ DQC DQC VSS/DNU VDD NC VSS DQD DQD VDDQ VSSQ DQD DQD DQD DQD VSSQ VDDQ DQD DQD DQPD A A CE1 CE2 NC NC BWB BWA CE3 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A A A CE1 CE2 BWD BWC BWB BWA CE3 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A Figure 1. 100-Pin TQFP (3 Chip Enables - A version) Document #: 38-05541 Rev. *G A NC NC VDDQ VSSQ NC DQPA DQA DQA VSSQ VDDQ DQA DQA VSS NC VDD ZZ DQA DQA VDDQ VSSQ DQA DQA NC NC VSSQ VDDQ NC NC NC Page 3 of 32 [+] Feedback CY7C1361C/CY7C1363C NC NC VSS VDD NC NC A A A A A A A MODE A A A A A1 A0 Document #: 38-05541 Rev. *G NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 VDDQ VSSQ NC NC DQB DQB VSSQ VDDQ DQB DQB VSS/DNU VDD NC VSS DQB DQB VDDQ VSSQ DQB DQB DQPB NC VSSQ VDDQ NC NC NC CY7C1363C (512K x 18) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 A NC NC VDDQ VSSQ NC DQPA DQA DQA VSSQ VDDQ DQA DQA VSS NC VDD ZZ DQA DQA VDDQ VSSQ DQA DQA NC NC VSSQ VDDQ NC NC NC 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 DQPB DQB DQB VDDQ VSSQ DQB DQB DQB DQB VSSQ VDDQ DQB DQB VSS NC VDD ZZ DQA DQA VDDQ VSSQ DQA DQA DQA DQA VSSQ VDDQ DQA DQA DQPA A A A A A1 A0 NC NC VSS VDD NC NC A A A A A A A CY7C1361C (256K x 36) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 MODE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 DQPC DQC DQC VDDQ VSSQ DQC DQC DQC DQC VSSQ VDDQ DQC DQC VSS/DNU VDD NC VSS DQD DQD VDDQ VSSQ DQD DQD DQD DQD VSSQ VDDQ DQD DQD DQPD 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 A A CE1 CE2 NC NC BWB BWA A VDD VSS CLK GW BWE OE ADSC ADSP ADV A A A A CE1 CE2 BWD BWC BWB BWA A VDD VSS CLK GW BWE OE ADSC ADSP ADV A A Figure 2. 100-Pin TQFP (2 Chip Enables - AJ Version) Page 4 of 32 [+] Feedback CY7C1361C/CY7C1363C Figure 3. 100- Ball BGA (2 Chip Enables with JTAG) CY7C1361C (256K x 36) 1 A VDDQ 2 A 3 A B C NC/288M NC/144M CE2 A A A D E DQC DQC DQPC DQC VSS VSS F VDDQ DQC VSS G H J K DQC DQC VDDQ DQD DQC DQC VDD DQD L DQD DQD M VDDQ N DQD 4 ADSP 5 A 6 A 7 VDDQ ADSC VDD A A A A NC/512M NC/1G NC CE1 VSS VSS DQPB DQB DQB DQB OE VSS DQB VDDQ BWC VSS NC VSS ADV BWB VSS NC VSS DQB DQB VDD DQA DQB DQB VDDQ DQA NC BWA VSS DQA DQA DQD BWD VSS DQA VDDQ DQD VSS VSS DQA DQA GW VDD CLK BWE A1 P DQD DQPD VSS A0 VSS DQPA DQA R NC A MODE VDD NC A NC T U NC VDDQ NC/72M TMS A TDI A TCK A TDO NC/36M NC ZZ VDDQ 5 6 7 A VDDQ CY7C1363C (512K x 18) 1 2 3 4 ADSP A A VDDQ A A B NC/288M CE2 A NC/144M A A A A A NC/512M C ADSC VDD A D DQB NC VSS NC VSS DQPA NC E NC DQB VSS CE1 VSS NC DQA F VDDQ NC VSS DQA VDDQ G H J NC DQB VDDQ DQB NC VDD BWB VSS NC OE ADV VSS VSS VSS NC DQA VDD DQA NC VDDQ K NC DQB VSS CLK L M DQB VDDQ NC DQB VSS VSS NC N DQB NC VSS BWE A1 P NC DQPB VSS R T U NC NC/72M VDDQ A A TMS MODE A TDI Document #: 38-05541 Rev. *G GW VDD NC VSS NC/1G NC DQA BWA VSS DQA NC NC VDDQ VSS DQA NC A0 VSS NC DQA VDD NC/36M TCK NC A TDO A A NC NC ZZ VDDQ Page 5 of 32 [+] Feedback CY7C1361C/CY7C1363C Figure 4. 165-Ball FBGA (3 Chip Enable) CY7C1361C (256K x 36) 1 2 3 4 5 6 7 8 9 10 11 A B C D E F G H J K L M N P NC/288M A CE1 BWC BWB CE3 BWE ADSC ADV A NC R NC/144M A CE2 BWD BWA CLK GW OE ADSP A NC/576M DQPC DQC NC DQC VDDQ VSS VSS VSS VSS VSS VSS VSS VDD VDDQ VDDQ VSS VDD NC/1G DQB DQPB DQB DQC DQC VDDQ VDD VSS VSS VSS VDD VDDQ DQB DQB DQC DQC VDDQ VDD VSS VSS VSS VDD VDDQ DQB DQB DQC NC DQD DQC VSS DQD VDDQ NC VDDQ VDD VDD VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD VDD VDD VDDQ NC VDDQ DQB NC DQA DQB ZZ DQA DQD DQD VDDQ VDD VSS VSS VSS VDD VDDQ DQA DQA DQD DQD VDDQ VDD VSS VSS VSS VDD VDDQ DQA DQA DQD DQPD DQD NC VDDQ VDDQ VDD VSS VSS NC VSS VSS NC VDD VSS VDDQ VDDQ DQA NC DQA DQPA NC NC/72M A A TDI TDO A A A A MODE NC/36M A A TMS TCK A A A A NC/18M A1 A0 VDDQ CY7C1363C (512K x 18) 1 2 3 4 5 6 7 8 9 10 11 A B C D E F G H J K L M N P NC/288M A CE1 BWB NC CE3 BWE ADSC ADV A A NC/144M A CE2 NC BWA CLK GW OE ADSP A NC NC NC DQB VDDQ VDDQ VSS VDD VSS VSS VSS VSS VSS VSS VSS VDD VDDQ VDDQ NC/1G NC NC DQB VDDQ VDD VSS VSS VSS VDD VDDQ NC DQA NC NC VSS DQB DQB VDD VDD VDD VDD VDDQ VDDQ NC VDDQ NC VSS VSS VSS VSS VSS VSS VSS VDD VDD VDD VDD VSS VSS VSS VSS VSS DQB VSS NC VDDQ VDDQ NC VDDQ NC NC DQA DQA DQA ZZ NC DQB NC VDDQ VDD VSS VSS VSS VDD VDDQ DQA NC DQB NC VDDQ VDD VSS VSS VSS VDD VDDQ DQA NC DQB DQPB NC NC VDDQ VDDQ VDD VSS VSS NC VSS NC/18M VSS NC VDD VSS VDDQ VDDQ DQA NC NC NC NC NC/72M A A TDI A1 TDO A A A A R MODE NC/36M A A TMS A0 TCK A A A A Document #: 38-05541 Rev. *G NC/576M DQPA DQA Page 6 of 32 [+] Feedback CY7C1361C/CY7C1363C Pin Definitions Name I/O Description A0, A1, A InputSynchronous Address Inputs used to select one of the address locations. Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3[2] are sampled active. A[1:0] feed the 2-bit counter. BWA,BWB BWC,BWD InputSynchronous Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM. Sampled on the rising edge of CLK. GW InputSynchronous Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a global write is conducted (ALL bytes are written, regardless of the values on BWX and BWE). CLK InputClock Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst counter when ADV is asserted LOW, during a burst operation. CE1 InputSynchronous Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2 and CE3[2] to select/deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only when a new external address is loaded. CE2 InputSynchronous Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE3[2] to select/deselect the device. CE2 is sampled only when a new external address is loaded. CE3[2] InputSynchronous Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE2 to select/deselect the device.CE3 is sampled only when a new external address is loaded. OE InputAsynchronous Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tristated, and act as input data pins. OE is masked during the first clock of a read cycle when emerging from a deselected state. ADV InputSynchronous Advance Input signal, sampled on the rising edge of CLK. When asserted, it automatically increments the address in a burst cycle. ADSP InputSynchronous Address Strobe from Processor, sampled on the rising edge of CLK, active LOW. When asserted LOW, addresses presented to the device are captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH. ADSC InputSynchronous Address Strobe from Controller, sampled on the rising edge of CLK, active LOW. When asserted LOW, addresses presented to the device are captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. BWE InputSynchronous Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be asserted LOW to conduct a byte write. ZZ InputAsynchronous ZZ “sleep” Input, active HIGH. When asserted HIGH places the device in a non-time-critical “sleep” condition with data integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ pin has an internal pull down. DQs I/OSynchronous Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the addresses presented during the previous clock rise of the read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQPX are placed in a tristate condition.The outputs are automatically tristated during the data portion of a write sequence, during the first clock when emerging from a deselected state, and when the device is deselected, regardless of the state of OE. DQPX I/OSynchronous Bidirectional Data Parity I/O Lines. Functionally, these signals are identical to DQs. During write sequences, DQPX is controlled by BWX correspondingly. MODE InputStatic VDD Power Supply Document #: 38-05541 Rev. *G Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDD or left floating selects interleaved burst sequence. This is a strap pin and should remain static during device operation. Mode Pin has an internal pull up. Power supply inputs to the core of the device. Page 7 of 32 [+] Feedback CY7C1361C/CY7C1363C Pin Definitions (continued) Name VDDQ VSS VSSQ I/O Description I/O Power Supply Power supply for the I/O circuitry. Ground I/O Ground Ground for the core of the device. Ground for the I/O circuitry. TDO JTAG serial output Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the Synchronous JTAG feature is not being used, this pin should be left unconnected. This pin is not available on TQFP packages. TDI JTAG serial input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG Synchronous feature is not being used, this pin can be left floating or connected to VDD through a pull up resistor. This pin is not available on TQFP packages. TMS JTAG serial input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG Synchronous feature is not being used, this pin can be disconnected or connected to VDD. This pin is not available on TQFP packages. TCK JTAGClock Clock input to the JTAG circuitry. If the JTAG feature is not being used, this pin must be connected to VSS. This pin is not available on TQFP packages. NC – No Connects. Not internally connected to the die. 18M, 36M, 72M, 144M, 288M, 576M, and 1G are address expansion pins and are not internally connected to the die. VSS/DNU Ground/DNU Document #: 38-05541 Rev. *G This pin can be connected to Ground or should be left floating. Page 8 of 32 [+] Feedback CY7C1361C/CY7C1363C Functional Overview Single Write Accesses Initiated by ADSC All synchronous inputs pass through input registers controlled by the rising edge of the clock. Maximum access delay from the clock rise (t CDV) is 6.5 ns (133 MHz device). This write access is initiated when the following conditions are satisfied at clock rise: (1) CE1, CE2, and CE3[2] are all asserted active, (2) ADSC is asserted LOW, (3) ADSP is deasserted HIGH, and (4) the write input signals (GW, BWE, and BWX) indicate a write access. ADSC is ignored if ADSP is active LOW. The CY7C1361C/CY7C1363C supports secondary cache in systems using either a linear or interleaved burst sequence. The interleaved burst order supports Pentium and i486™ processors. The linear burst sequence is suited for processors that use a linear burst sequence. The burst order is user-selectable, and is determined by sampling the MODE input. Accesses can be initiated with either the Processor Address Strobe (ADSP) or the Controller Address Strobe (ADSC). Address advancement through the burst sequence is controlled by the ADV input. A two-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access. Byte write operations are qualified with the Byte Write Enable (BWE) and Byte Write Select (BWX) inputs. A Global Write Enable (GW) overrides all byte write inputs and writes data to all four bytes. All writes are simplified with on-chip synchronous self-timed write circuitry. Three synchronous Chip Selects (CE1, CE2, CE3[2]) and an asynchronous Output Enable (OE) provide for easy bank selection and output tristate control. ADSP is ignored if CE1 is HIGH. Single Read Accesses A single read access is initiated when the following conditions are satisfied at clock rise: (1) CE1, CE2, and CE3[2] are all asserted active and (2) ADSP or ADSC is asserted LOW (if the access is initiated by ADSC, the write inputs must be deasserted during this first cycle). The address presented to the address inputs is latched into the address register and the burst counter/control logic and presented to the memory core. If the OE input is asserted LOW, the requested data will be available at the data outputs a maximum to tCDV after clock rise. ADSP is ignored if CE1 is HIGH. Single Write Accesses Initiated by ADSP This access is initiated when the following conditions are satisfied at clock rise: (1) CE1, CE2, CE3[2] are all asserted active and (2) ADSP is asserted LOW. The addresses presented are loaded into the address register and the burst inputs (GW, BWE, and BWX) are ignored during this first clock cycle. If the write inputs are asserted active (see Partial Truth Table for Read/Write on page 11 for appropriate states that indicate a write) on the next clock rise, the appropriate data will be latched and written into the device.Byte writes are allowed. All I/Os are tristated during a byte write. Since this is a common I/O device, the asynchronous OE input signal must be deasserted and the I/Os must be tristated prior to the presentation of data to DQs. As a safety precaution, the data lines are tristated once a write cycle is detected, regardless of the state of OE. Document #: 38-05541 Rev. *G The addresses presented are loaded into the address register and the burst counter/control logic and delivered to the memory core. The information presented to DQ[A:D] is written into the specified address location. Byte writes are allowed. All I/Os are tristated when a write is detected, even a byte write. Since this is a common I/O device, the asynchronous OE input signal must be deasserted and the I/Os must be tristated prior to the presentation of data to DQs. As a safety precaution, the data lines are tristated once a write cycle is detected, regardless of the state of OE. Burst Sequences The CY7C1361C/CY7C1363C provides an on-chip two-bit wraparound burst counter inside the SRAM. The burst counter is fed by A[1:0], and can follow either a linear or interleaved burst order. The burst order is determined by the state of the MODE input. A LOW on MODE will select a linear burst sequence. A HIGH on MODE selects an interleaved burst order. Leaving MODE unconnected causes the device to default to a interleaved burst sequence. Table 1. Interleaved Burst Address Table (MODE = Floating or VDD) First Address A1: A0 Second Address A1: A0 Third Address A1: A0 Fourth Address A1: A0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 Table 2. Linear Burst Address Table (MODE = GND) First Address A1: A0 Second Address A1: A0 Third Address A1: A0 Fourth Address A1: A0 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 Sleep Mode The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation ‘sleep’ mode. Two clock cycles are required to enter into or exit from this ‘sleep’ mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the ‘sleep’ mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the ‘sleep’ mode. CE1, CE2, CE3[2], ADSP, and ADSC must remain inactive for the duration of tZZREC after the ZZ input returns LOW. Page 9 of 32 [+] Feedback CY7C1361C/CY7C1363C ZZ Mode Electrical Characteristics Parameter Description Test Conditions IDDZZ Sleep mode standby current ZZ > VDD – 0.2V tZZS tZZREC tZZI tRZZI Device operation to ZZ ZZ recovery time ZZ active to sleep current ZZ Inactive to exit sleep current ZZ > VDD – 0.2V ZZ < 0.2V This parameter is sampled This parameter is sampled Min Comm/ind’l Automotive Max Unit 50 60 2tCYC mA mA ns ns ns ns 2tCYC 2tCYC 0 Truth Table The Truth Table for CY7C1361C and CY7C1363C follows. [3, 4, 5, 6, 7] Cycle Description Address CE CE CE ZZ 1 2 3 Used ADSP ADSC ADV WRITE OE CLK DQ Deselected Cycle, Power Down None H X X L X L X X X L-H Tristate Deselected Cycle, Power Down None L L X L L X X X X L-H Tristate Deselected Cycle, Power Down None L X H L L X X X X L-H Tristate Deselected Cycle, Power Down None L L X L H L X X X L-H Tristate Deselected Cycle, Power Down None X X X L H L X X X L-H Tristate Sleep Mode, Power-down None X X X H X X X X X X Tristate Read Cycle, Begin Burst External L H L L L X X X L L-H Q Read Cycle, Begin Burst External L H L L L X X X H L-H Write Cycle, Begin Burst External L H L L H L X L X L-H Tristate D Read Cycle, Begin Burst External L H L L H L X H L L-H Q Read Cycle, Begin Burst External L H L L H L X H H L-H Read Cycle, Continue Burst Next X X X L H H L H L L-H Tristate Q Read Cycle, Continue Burst Next X X X L H H L H H L-H Tristate Read Cycle, Continue Burst Next H X X L X H L H L L-H Q Read Cycle, Continue Burst Next H X X L X H L H H L-H Tristate Write Cycle, Continue Burst Next X X X L H H L L X L-H D Write Cycle, Continue Burst Next H X X L X H L L X L-H D Read Cycle, Suspend Burst Current X X X L H H H H L L-H Q Read Cycle, Suspend Burst Current X X X L H H H H H L-H Tristate Read Cycle, Suspend Burst Current H X X L X H H H L L-H Q Read Cycle, Suspend Burst Current H X X L X H H H H L-H Tristate Write Cycle, Suspend Burst Current X X X L H H H L X L-H D Write Cycle, Suspend Burst Current H X X L X H H L X L-H D Notes 3. X=”Don't Care.” H = Logic HIGH, L = Logic LOW. 4. WRITE = L when any one or more Byte Write enable signals and BWE = L or GW = L. WRITE = H when all Byte write enable signals, BWE, GW = H. 5. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock. 6. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a don't care for the remainder of the write cycle. 7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW). Document #: 38-05541 Rev. *G Page 10 of 32 [+] Feedback CY7C1361C/CY7C1363C Partial Truth Table for Read/Write The Partial Truth Table for Read/Write follows.[3, 8] Function (CY7C1361C) GW BWE BWD BWC BWB BWA Read H H X X X X Read H L H H H H Write Byte (A, DQPA) H L H H H L Write Byte (B, DQPB) H L H H L H Write Bytes (B, A, DQPA, DQPB) H L H H L L Write Byte (C, DQPC) H L H L H H Write Bytes (C, A, DQPC, DQPA) H L H L H L Write Bytes (C, B, DQPC, DQPB) H L H L L H Write Bytes (C, B, A, DQPC, DQPB, DQPA) H L H L L L Write Byte (D, DQPD) H L L H H H Write Bytes (D, A, DQPD, DQPA) H L L H H L Write Bytes (D, B, DQPD, DQPA) H L L H L H Write Bytes (D, B, A, DQPD, DQPB, DQPA) H L L H L L Write Bytes (D, B, DQPD, DQPB) H L L L H H Write Bytes (D, B, A, DQPD, DQPC, DQPA) H L L L H L Write Bytes (D, C, A, DQPD, DQPB, DQPA) H L L L L H Write All Bytes H L L L L L Write All Bytes L X X X X X Truth Table for Read/Write The Truth Table for Read/Write follows.[3, 8] GW BWE Read H H X X Read H L H H Write Byte A – (DQA and DQPA) H L H L Write Byte B – (DQB and DQPB) H L L H Write All Bytes H L L L Write All Bytes L X X X Function (CY7C1363C) BWB BWA Note 8. Table only lists a partial listing of the byte write combinations. Any Combination of BWX is valid Appropriate write will be done based on which byte write is active. Document #: 38-05541 Rev. *G Page 11 of 32 [+] Feedback CY7C1361C/CY7C1363C IEEE 1149.1 Serial Boundary Scan (JTAG) Test Access Port (TAP) The CY7C1361C/CY7C1363C incorporates a serial boundary scan test access port (TAP) in the BGA package only. The TQFP package does not offer this functionality. This part operates in accordance with IEEE Standard 1149.1-1900, but does not have the set of functions required for full 1149.1 compliance. These functions from the IEEE specification are excluded because their inclusion places an added delay in the critical speed path of the SRAM. Note that the TAP controller functions in a manner that does not conflict with the operation of other devices using 1149.1 fully compliant TAPs. The TAP operates using JEDEC-standard 3.3V or 2.5V I/O logic levels. Test Clock (TCK) The CY7C1361C/CY7C1363C contains a TAP controller, instruction register, boundary scan register, bypass register, and ID register. Test Data-In (TDI) Disabling the JTAG Feature It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately be connected to VDD through a pull up resistor. TDO should be left unconnected. Upon power up, the device comes up in a reset state which does not interfere with the operation of the device. TAP Controller State Diagram 1 TEST-LOGIC RESET 0 RUN-TEST/ IDLE The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK. Test MODE SELECT (TMS) The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. It is allowable to leave this ball unconnected if the TAP is not used. The ball is pulled up internally, resulting in a logic HIGH level. The TDI ball is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) of any register. (See TAP Controller Block Diagram.) Test Data-Out (TDO) The TDO output ball is used to serially clock data-out from the registers. The output is active depending upon the current state of the TAP state machine. The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register. (See TAP Controller State Diagram.) TAP Controller Block Diagram 0 1 SELECT DR-SCA N 1 SELECT IR-SCAN 0 1 1 0 0 1 CAPTURE-DR Bypass Register CAPTURE-IR 2 1 0 0 0 SHIFT-DR 0 SHIFT-IR 0 TDI Selection Circuitry Instruction Register Selection Circuitry TDO 31 30 29 . . . 2 1 0 1 1 EXIT1-DR 1 EXIT1-IR 0 0 PAUSE-IR 1 Boundary Scan Register 0 1 EXIT2-DR 0 EXIT2-IR 1 TCK 1 UPDATE-DR 1 x . . . . . 2 1 0 0 PAUSE-DR 0 Identification Register 1 0 UPDATE-IR 1 TM S TAP CONTROLLER 0 The 0/1 next to each state represents the value of TMS at the rising edge of TCK. Document #: 38-05541 Rev. *G Page 12 of 32 [+] Feedback CY7C1361C/CY7C1363C Performing a TAP Reset TAP Instruction Set A RESET is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating. Overview At power up, the TAP is reset internally to ensure that TDO comes up in a High-Z state. TAP Registers Registers are connected between the TDI and TDO balls and allow data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction register. Data is serially loaded into the TDI ball on the rising edge of TCK. Data is output on the TDO ball on the falling edge of TCK. Instruction Register Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO balls as shown in the TAP Controller Block Diagram on page 12. Upon power up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section. When the TAP controller is in the Capture-IR state, the two least significant bits are loaded with a binary ‘01’ pattern to enable fault isolation of the board-level serial test data path. Bypass Register To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single-bit register that can be placed between the TDI and TDO balls. This enables data to be shifted through the SRAM with minimal delay. The bypass register is set LOW (VSS) when the BYPASS instruction is executed. Boundary Scan Register The boundary scan register is connected to all the input and bidirectional balls on the SRAM. The boundary scan register is loaded with the contents of the RAM I/O ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO balls when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD, and SAMPLE Z instructions can be used to capture the contents of the I/O ring. The 119-Ball BGA Boundary Scan Order on page 18 and 165-Ball FBGA Boundary Scan Order on page 19 show the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI and the LSB is connected to TDO. Identification (ID) Register The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other information described in Identification Register Definitions on page 16. Document #: 38-05541 Rev. *G Eight different instructions are possible with the three-bit instruction register. All combinations are listed in the Instruction Codes table. Three of these instructions are listed as RESERVED and should not be used. The other five instructions are described in detail in this section. The TAP controller used in this SRAM is not fully compliant to the 1149.1 convention because some of the mandatory 1149.1 instructions are not fully implemented. The TAP controller cannot be used to load address data or control signals into the SRAM and cannot preload the I/O buffers. The SRAM does not implement the 1149.1 commands EXTEST or INTEST or the PRELOAD portion of SAMPLE/PRELOAD; rather, it performs a capture of the I/O ring when these instructions are executed. Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO balls. To execute the instruction once it is shifted in, the TAP controller needs to be moved into the Update-IR state. EXTEST EXTEST is a mandatory 1149.1 instruction which is to be executed whenever the instruction register is loaded with all 0s. EXTEST is not implemented in this SRAM TAP controller, and therefore this device is not compliant to 1149.1. The TAP controller does recognize an all-0 instruction. When an EXTEST instruction is loaded into the instruction register, the SRAM responds as if a SAMPLE/PRELOAD instruction has been loaded. There is one difference between the two instructions. Unlike the SAMPLE/PRELOAD instruction, EXTEST places the SRAM outputs in a High-Z state. IDCODE The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO balls and enables the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register upon power up or whenever the TAP controller is given a test logic reset state. SAMPLE Z The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO balls when the TAP controller is in a Shift-DR state. It also places all SRAM outputs into a High-Z state. SAMPLE/PRELOAD SAMPLE/PRELOAD is a 1149.1-mandatory instruction. When the SAMPLE/PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. Page 13 of 32 [+] Feedback CY7C1361C/CY7C1363C PRELOAD enables an initial data pattern to be placed at the latched parallel outputs of the boundary scan register cells prior to the selection of another boundary scan test operation. The user must be aware that the TAP controller clock can only operate at a frequency up to 20 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output undergoes a transition. The TAP may then try to capture a signal while in transition (metastable state). This does not harm the device, but there is no guarantee as to the value that will be captured. Repeatable results may not be possible. The shifting of data for the SAMPLE and PRELOAD phases can occur concurrently when required - that is, while data captured is shifted out, the preloaded data can be shifted in. BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO balls. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. To guarantee that the boundary scan register captures the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller's capture setup plus hold times (tCS and tCH). The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the CK and CK# captured in the boundary scan register. Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions. After the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. TAP Timing 1 2 Test Clock (TCK ) 3 t TH t TM SS t TM SH t TDIS t TDIH t TL 4 5 6 t CY C Test M ode Select (TM S) Test Data-In (TDI) t TDOV t TDOX Test Data-Out (TDO) DON’T CA RE Document #: 38-05541 Rev. *G UNDEFINED Page 14 of 32 [+] Feedback CY7C1361C/CY7C1363C TAP AC Switching Characteristics Over the Operating Range[9, 10] Parameter Parameter Min Max Unit Clock tTCYC TCK Clock Cycle Time tTF TCK Clock Frequency tTH TCK Clock HIGH Time 20 ns tTL TCK Clock LOW Time 20 ns 50 ns 20 MHz Output Times tTDOV TCK Clock LOW to TDO Valid tTDOX TCK Clock LOW to TDO Invalid 10 ns 0 ns 5 ns Set-up Times tTMSS TMS Setup to TCK Clock Rise tTDIS TDI Setup to TCK Clock Rise 5 ns tCS Capture Setup to TCK Rise 5 ns tTMSH TMS Hold after TCK Clock Rise 5 ns tTDIH TDI Hold after Clock Rise 5 ns tCH Capture Hold after Clock Rise 5 ns Hold Times Notes 9. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register. 10. Test conditions are specified using the load in TAP AC test conditions. tR/tF = 1 ns. Document #: 38-05541 Rev. *G Page 15 of 32 [+] Feedback CY7C1361C/CY7C1363C 3.3V TAP AC Test Conditions 2.5V TAP AC Test Conditions Input pulse levels.................................................VSS to 3.3V Input pulse levels................................................. VSS to 2.5V Input rise and fall times....................................................1 ns Input rise and fall time .....................................................1 ns Input timing reference levels........................................... 1.5V Input timing reference levels......................................... 1.25V Output reference levels .................................................. 1.5V Output reference levels ................................................ 1.25V Test load termination supply voltage .............................. 1.5V Test load termination supply voltage ............................ 1.25V 3.3V TAP AC Output Load Equivalent 2.5V TAP AC Output Load Equivalent 1.25V 1.5V 50Ω 50Ω TDO TDO Z O= 50Ω Z O= 50Ω 20pF 20pF TAP DC Electrical Characteristics And Operating Conditions (0°C < TA < +70°C; VDD = 3.3V ±0.165V unless otherwise noted)[11] Parameter Description Description Conditions VOH1 Output HIGH Voltage IOH = –4.0 mA VOH2 Output HIGH Voltage VOL1 Output LOW Voltage IOL = 8.0 mA VOL2 Output LOW Voltage VIH Input HIGH Voltage VDDQ = 3.3V VIL Input LOW Voltage VDDQ = 2.5V IX Input Load Current Min Max Unit VDDQ = 3.3V 2.4 V IOH = –1.0 mA VDDQ = 2.5V 2.0 V IOH = –100 µA VDDQ = 3.3V 2.9 V VDDQ = 2.5V 2.1 V VDDQ = 3.3V 0.4 V IOL = 8.0 mA VDDQ = 2.5V 0.4 V IOL = 100 µA VDDQ = 3.3V 0.2 V VDDQ = 2.5V 0.2 V 2.0 VDD + 0.3 V VDDQ = 2.5V 1.7 VDD + 0.3 V VDDQ = 3.3V –0.5 0.7 V –0.3 0.7 V –5 5 µA GND < VIN < VDDQ Identification Register Definitions Instruction Field CY7C1361C (256K x36) CY7C1363C (512K x18) Description Revision Number (31:29) 000 000 Device Depth (28:24)[12] 01011 01011 Device Width (23:18) 119-BGA 101001 101001 Defines memory type and architecture Device Width (23:18) 165-FBGA 000001 000001 Defines memory type and architecture Defines width and density Cypress Device ID (17:12) Cypress JEDEC ID Code (11:1) ID Register Presence Indicator (0) 100110 010110 00000110100 00000110100 1 1 Describes the version number. Reserved for Internal Use Allows unique identification of SRAM vendor. Indicates the presence of an ID register. Notes 11. All voltages referenced to VSS (GND). 12. Bit #24 is “1” in the Register Definitions for both 2.5V and 3.3V versions of this device. Document #: 38-05541 Rev. *G Page 16 of 32 [+] Feedback CY7C1361C/CY7C1363C Scan Register Sizes Register Name Bit Size (x 36) Bit Size (x 18) Instruction 3 3 Bypass 1 1 ID 32 32 Boundary Scan Order (119-ball BGA package) 71 71 Boundary Scan Order (165-ball FBGA package) 71 71 Identification Codes Instruction Code Description EXTEST 000 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM outputs to High-Z state. IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operations. SAMPLE Z 010 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a High-Z state. RESERVED 011 Do Not Use: This instruction is reserved for future use. SAMPLE/PRELOAD 100 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Does not affect SRAM operation. RESERVED 101 Do Not Use: This instruction is reserved for future use. RESERVED 110 Do Not Use: This instruction is reserved for future use. BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM operations. Document #: 38-05541 Rev. *G Page 17 of 32 [+] Feedback CY7C1361C/CY7C1363C 119-Ball BGA Boundary Scan Order CY7C1361C (256K x 36) Bit # ball ID CY7C1363C (512K x 18) Signal Name Bit # ball ID Signal Name Bit # ball ID Signal Name Bit # ball ID Signal Name 1 K4 CLK 37 P4 A0 1 K4 CLK 37 P4 A0 2 H4 GW 38 N4 A1 2 H4 GW 38 N4 A1 3 M4 BWE 39 R6 A 3 M4 BWE 39 R6 A 4 F4 OE 40 T5 A 4 F4 OE 40 T5 A 5 B4 ADSC 41 T3 A 5 B4 ADSC 41 T3 A 6 A4 ADSP 42 R2 A 6 A4 ADSP 42 R2 A 7 G4 ADV 43 R3 MODE 7 G4 ADV 43 R3 MODE 8 C3 A 44 P2 DQPD 8 C3 A 44 Internal Internal 9 B3 A 45 P1 DQD 9 B3 A 45 Internal Internal 10 D6 DQPB 46 L2 DQD 10 T2 A 46 Internal Internal 11 H7 DQB 47 K1 DQD 11 Internal Internal 47 Internal Internal 12 G6 DQB 48 N2 DQD 12 Internal Internal 48 P2 DQPB 13 E6 DQB 49 N1 DQD 13 Internal Internal 49 N1 DQB 14 D7 DQB 50 M2 DQD 14 D6 DQPA 50 M2 DQB 15 E7 DQB 51 L1 DQD 15 E7 DQA 51 L1 DQB 16 F6 DQB 52 K2 DQD 16 F6 DQA 52 K2 DQB 17 G7 DQB 53 Internal Internal 17 G7 DQA 53 Internal Internal 18 H6 DQB 54 H1 DQC 18 H6 DQA 54 H1 DQB 19 T7 ZZ 55 G2 DQC 19 T7 ZZ 55 G2 DQB 20 K7 DQA 56 E2 DQC 20 K7 DQA 56 E2 DQB 21 L6 DQA 57 D1 DQC 21 L6 DQA 57 D1 DQB 22 N6 DQA 58 H2 DQC 22 N6 DQA 58 Internal Internal 23 P7 DQA 59 G1 DQC 23 P7 DQA 59 Internal Internal 24 N7 DQA 60 F2 DQC 24 Internal Internal 60 Internal Internal 25 M6 DQA 61 E1 DQC 25 Internal Internal 61 Internal Internal 26 L7 DQA 62 D2 DQPC 26 Internal Internal 62 Internal Internal 27 K6 DQA 63 C2 A 27 Internal Internal 63 C2 A 28 P6 DQPA 64 A2 A 28 Internal Internal 64 A2 A 29 T4 A 65 E4 CE1 29 T6 A 65 E4 CE1 30 A3 A 66 B2 CE2 30 A3 A 66 B2 CE2 31 C5 A 67 L3 BWD 31 C5 A 67 Internal Internal 32 B5 A 68 G3 BWC 32 B5 A 68 Internal Internal 33 A5 A 69 G5 BWB 33 A5 A 69 G3 BWB 34 C6 A 70 L5 BWA 34 C6 A 70 L5 BWA 35 A6 A 71 Internal Internal 35 A6 A 71 Internal Internal 36 B6 A 36 B6 A Document #: 38-05541 Rev. *G Page 18 of 32 [+] Feedback CY7C1361C/CY7C1363C 165-Ball FBGA Boundary Scan Order CY7C1361C (256K x 36) CY7C1363C (512K x 18) Bit # ball ID Signal Name Bit # ball ID Signal Name Bit # ball ID Signal Name Bit # ball ID Signal Name 1 B6 CLK 37 R6 A0 1 B6 CLK 37 R6 A0 2 B7 GW 38 P6 A1 2 B7 GW 38 P6 A1 3 A7 BWE 39 R4 A 3 A7 BWE 39 R4 A 4 B8 OE 40 P4 A 4 B8 OE 40 P4 A 5 A8 ADSC 41 R3 A 5 A8 ADSC 41 R3 A 6 B9 ADSP 42 P3 A 6 B9 ADSP 42 P3 A 7 A9 ADV 43 R1 MODE 7 A9 ADV 43 R1 MODE 8 B10 A 44 N1 DQPD 8 B10 A 44 Internal Internal 9 A10 A 45 L2 DQD 9 A10 A 45 Internal Internal 10 C11 DQPB 46 K2 DQD 10 A11 A 46 Internal Internal 11 E10 DQB 47 J2 DQD 11 Internal Internal 47 Internal Internal 12 F10 DQB 48 M2 DQD 12 Internal Internal 48 N1 DQPB 13 G10 DQB 49 M1 DQD 13 Internal Internal 49 M1 DQB 14 D10 DQB 50 L1 DQD 14 C11 DQPA 50 L1 DQB 15 D11 DQB 51 K1 DQD 15 D11 DQA 51 K1 DQB 16 E11 DQB 52 J1 DQD 16 E11 DQA 52 J1 DQB 17 F11 DQB 53 Internal Internal 17 F11 DQA 53 Internal Internal 18 G11 DQB 54 G2 DQC 18 G11 DQA 54 G2 DQB 19 H11 ZZ 55 F2 DQC 19 H11 ZZ 55 F2 DQB 20 J10 DQA 56 E2 DQC 20 J10 DQA 56 E2 DQB 21 K10 DQA 57 D2 DQC 21 K10 DQA 57 D2 DQB 22 L10 DQA 58 G1 DQC 22 L10 DQA 58 Internal Internal 23 M10 DQA 59 F1 DQC 23 M10 DQA 59 Internal Internal 24 J11 DQA 60 E1 DQC 24 Internal Internal 60 Internal Internal 25 K11 DQA 61 D1 DQC 25 Internal Internal 61 Internal Internal 26 L11 DQA 62 C1 DQPC 26 Internal Internal 62 Internal Internal 27 M11 DQA 63 B2 A 27 Internal Internal 63 B2 A 28 N11 DQPA 64 A2 A 28 Internal Internal 64 A2 A 29 R11 A 65 A3 CE1 29 R11 A 65 A3 CE1 30 R10 A 66 B3 CE2 30 R10 A 66 B3 CE2 31 P10 A 67 B4 BWD 31 P10 A 67 Internal Internal 32 R9 A 68 A4 BWC 32 R9 A 68 Internal Internal 33 P9 A 69 A5 BWB 33 P9 A 69 A4 BWB 34 R8 A 70 B5 BWA 34 R8 A 70 B5 BWA 71 A6 CE3 71 A6 CE3 35 P8 A 36 P11 A Document #: 38-05541 Rev. *G 35 P8 A 36 P11 A Page 19 of 32 [+] Feedback CY7C1361C/CY7C1363C Maximum Ratings Neutron Soft Error Immunity Description Test Conditions Typ Max* Unit LSBU Logical Single-Bit Upsets 25°C 361 394 FIT/ Mb LMBU Logical Multi-Bit Upsets 25°C 0 0.01 FIT/ Mb Single Event Latch up 85°C 0 0.1 FIT/ Dev Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Parameter Storage Temperature ................................ –65°C to + 150°C Ambient Temperature with Power Applied ........................................... –55°C to + 125°C Supply Voltage on VDD Relative to GND .......–0.5V to + 4.6V Supply Voltage on VDDQ Relative to GND ..... –0.5V to + VDD DC Voltage Applied to Outputs in tri-state.............................................–0.5V to VDDQ + 0.5V SEL DC Input Voltage ................................... –0.5V to VDD + 0.5V * No LMBU or SEL events occurred during testing; this column represents a statistical χ2, 95% confidence limit calculation. For more details refer to Application Note AN 54908 “Accelerated Neutron SER Testing and Calculation of Terrestrial Failure Rates” Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage........................................... >2001V (per MIL-STD-883, Method 3015) Latch up Current..................................................... >200 mA Operating Range Ambient VDD VDDQ Temperature Commercial 0°C to +70°C 3.3V – 5%/+10% 2.5V – 5% to VDD Industrial –40°C to +85°C Automotive –40°C to +125°C Range Electrical Characteristics Over the Operating Range Parameter Description VDD Power Supply Voltage VDDQ I/O Supply Voltage VOH Output HIGH Voltage VOL Output LOW Voltage VIH Input HIGH Voltage[13] VIL Input LOW Voltage[13] IX Input Leakage Current except ZZ and MODE [13, 14] Test Conditions for 3.3V I/O for 2.5V I/O for 3.3V I/O, IOH = −4.0 mA for 2.5V I/O, IOH = −1.0 mA for 3.3V I/O, IOL= 8.0 mA for 2.5V I/O, IOL= 1.0 mA for 3.3V I/O for 2.5V I/O for 3.3V I/O for 2.5V I/O GND ≤ VI ≤ VDDQ Input Current of MODE IOZ Input = VSS Input = VDD Input Current of ZZ Input = VSS Input = VDD Output Leakage Current GND < VI < VDDQ, Output Disabled Min 3.135 3.135 2.375 2.4 2.0 2.0 1.7 –0.3 –0.3 –5 Max 3.6 VDD 2.625 Unit V V V V V 0.4 V 0.4 V VDD + 0.3V V VDD + 0.3V V 0.8 V 0.7 V 5 μA –30 5 –5 –5 30 5 μA μA μA μA μA Notes 13. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC) > –2V (Pulse width less than tCYC/2). 14. TPower-up: Assumes a linear ramp from 0V to VDD(min.) within 200ms. During this time VIH < VDD and VDDQ < VDD. Document #: 38-05541 Rev. *G Page 20 of 32 [+] Feedback CY7C1361C/CY7C1363C Electrical Characteristics Over the Operating Range (continued)[13, 14] Parameter Description IDD VDD Operating Supply Current Test Conditions VDD = Max., IOUT = 0 mA, 7.5 ns cycle,133 MHz f = fMAX = 1/tCYC 10 ns cycle,100 MHz ISB1 Automatic CE Power-down Current—TTL Inputs Max. VDD, Device Deselected, VIN> VIH or VIN < VIL, f = fMAX, inputs switching ISB2 Automatic CE Power-down Current—CMOS Inputs Max. VDD, Device Deselected, VIN > VDD – 0.3V or VIN < 0.3V, f = 0, inputs static ISB3 Automatic CE Power-down Current—CMOS Inputs ISB4 Automatic CE Power-down Current—TTL Inputs Max. VDD, Device Deselected, All speeds (Comm/Ind’l) VIN > VDDQ – 0.3V or VIN < 0.3V, 10 ns cycle,100 MHz f = fMAX, inputs switching (Automotive) Max. VDD, Device Deselected, All speeds (Comm/Ind’l) VIN > VIH or VIN < VIL 10 ns cycle,100 MHz f = 0, inputs static (Automotive) Min Max 250 Unit mA 180 110 150 mA mA 40 mA 100 120 mA mA 40 mA 60 mA All speeds (Comm/Ind’l) 10 ns cycle,100 MHz (Automotive) All speeds Capacitance[15] Parameter CIN CCLK CI/O Description Test Conditions Input Capacitance Clock Input Capacitance Input/Output Capacitance TA = 25°C, f = 1 MHz, VDD = 3.3V VDDQ = 2.5V 100 TQFP Max. 5 5 5 119 BGA 165 FBGA Max. Max. 5 5 5 5 7 7 Unit 100 TQFP Package 29.41 119 BGA 165 FBGA Package Package 34.1 16.8 Unit pF pF pF Thermal Resistance[15] Parameter ΘJA Description Test Conditions Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) ΘJC Test conditions follow standard test methods and procedures for measuring thermal impedance, according to EIA/JESD51 6.31 14.0 3.0 °C/W °C/W Figure 5. AC Test Loads and Waveforms 3.3V I/O Test Load R = 317Ω 3.3V OUTPUT OUTPUT RL = 50Ω Z0 = 50Ω VT = 1.5V (a) ALL INPUT PULSES VDDQ GND 5 pF INCLUDING JIG AND SCOPE R = 351Ω 10% 90% 10% 90% ≤ 1 ns ≤ 1 ns (b) (c) 2.5V I/O Test Load R = 1667Ω 2.5V OUTPUT OUTPUT RL = 50Ω Z0 = 50Ω VT = 1.25V (a) ALL INPUT PULSES VDDQ GND 5 pF INCLUDING JIG AND SCOPE R = 1538Ω (b) 10% 90% 10% 90% ≤ 1 ns ≤ 1 ns (c) Note 15. Tested initially and after any design or process change that may affect these parameters. Document #: 38-05541 Rev. *G Page 21 of 32 [+] Feedback CY7C1361C/CY7C1363C Switching Characteristics Over the Operating Range[20, 21] Description Parameter tPOWER VDD(Typical) to the first Access[16] –133 Min –100 Max Min Max Unit 1 1 ms Clock tCYC Clock Cycle Time 7.5 10 ns tCH Clock HIGH 3.0 4.0 ns tCL Clock LOW 3.0 4.0 ns Output Times tCDV Data Output Valid After CLK Rise tDOH Data Output Hold After CLK Rise 2.0 2.0 ns tCLZ Clock to Low-Z[17, 18, 19] 0 0 ns tCHZ Clock to High-Z[17, 18, 19] 3.5 3.5 ns tOEV OE LOW to Output Valid 3.5 3.5 ns tOELZ tOEHZ OE LOW to Output Low-Z[17, 18, 19] OE HIGH to Output High-Z[17, 18, 19] 6.5 0 8.5 0 3.5 ns ns 3.5 ns Set-up Times tAS Address Setup Before CLK Rise 1.5 1.5 ns tADS ADSP, ADSC Setup Before CLK Rise 1.5 1.5 ns tADVS ADV Setup Before CLK Rise 1.5 1.5 ns tWES GW, BWE, BW[A:D] Setup Before CLK Rise 1.5 1.5 ns tDS Data Input Setup Before CLK Rise 1.5 1.5 ns tCES Chip Enable Setup 1.5 1.5 ns tAH Address Hold After CLK Rise 0.5 0.5 ns tADH ADSP, ADSC Hold After CLK Rise 0.5 0.5 ns tWEH GW, BWE, BW[A:D] Hold After CLK Rise 0.5 0.5 ns tADVH ADV Hold After CLK Rise 0.5 0.5 ns tDH Data Input Hold After CLK Rise 0.5 0.5 ns tCEH Chip Enable Hold After CLK Rise 0.5 0.5 ns Hold Times Notes 16. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially, before a read or write operation can be initiated. 17. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage. 18. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High-Z prior to Low-Z under the same system conditions. 19. This parameter is sampled and not 100% tested. 20. Timing reference level is 1.5V when VDDQ = 3.3V and is 1.25V when VDDQ = 2.5V. 21. Test conditions shown in (a) of AC Test Loads unless otherwise noted. Document #: 38-05541 Rev. *G Page 22 of 32 [+] Feedback CY7C1361C/CY7C1363C Timing Diagrams Figure 6. Read Cycle Timing[22] tCYC CLK t t ADS t CL CH tADH ADSP t ADS tADH ADSC t AS tAH A1 ADDRESS A2 t GW, BWE,BW WES t WEH X t CES Deselect Cycle t CEH CE t ADVS t ADVH ADV ADV suspends burst OE t OEV t OEHZ t CLZ Data Out (Q) High-Z Q(A1) t CDV t OELZ t CHZ t DOH Q(A2) Q(A2 + 1) Q(A2 + 2) t CDV Q(A2 + 3) Q(A2) Q(A2 + 1) Q(A2 + 2) Burst wraps around to its initial state Single READ BURST READ DON’T CARE UNDEFINED Note 22. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH. Document #: 38-05541 Rev. *G Page 23 of 32 [+] Feedback CY7C1361C/CY7C1363C Timing Diagrams (continued) Figure 7. Write Cycle Timing[22, 23] t CYC CLK t t ADS CH t CL tADH ADSP t ADS ADSC extends burst tADH t ADS tADH ADSC t AS tAH A1 ADDRESS A2 A3 Byte write signals are ignored for first cycle when ADSP initiates burst t WES tWEH BWE, BW X t WES t WEH GW t CES tCEH CE t ADVS tADVH ADV ADV suspends burst OE t Data in (D) High-Z t DS t DH D(A1) D(A2) D(A2 + 1) D(A2 + 1) D(A2 + 2) D(A2 + 3) D(A3) D(A3 + 1) D(A3 + 2) OEHZ Data Out (Q) BURST READ Single WRITE BURST WRITE DON’T CARE Extended BURST WRITE UNDEFINED Note 23. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BWX LOW. Document #: 38-05541 Rev. *G Page 24 of 32 [+] Feedback CY7C1361C/CY7C1363C Timing Diagrams (continued) Figure 8. Read/Write Cycle Timing[22, 24, 25] tCYC CLK t t ADS CH t CL tADH ADSP ADSC t AS ADDRESS A1 tAH A2 A3 A4 t WES t A5 A6 WEH BWE, BW X t CES tCEH CE ADV OE t DS Data In (D) Data Out (Q) High-Z t OEHZ Q(A1) tDH t OELZ D(A3) D(A5) Q(A4) Q(A2) Back-to-Back READs D(A6) t CDV Single WRITE Q(A4+1) Q(A4+2) BURST READ DON’T CARE Q(A4+3) Back-to-Back WRITEs UNDEFINED Notes 24. The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC. 25. GW is HIGH. Document #: 38-05541 Rev. *G Page 25 of 32 [+] Feedback CY7C1361C/CY7C1363C Timing Diagrams (continued) Figure 9. ZZ Mode Timing[26, 27] CLK t ZZ ZZ I t ZZREC t ZZI SUPPLY I DDZZ t RZZI ALL INPUTS (except ZZ) Outputs (Q) DESELECT or READ Only High-Z DON’T CARE Notes 26. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device. 27. DQs are in high-Z when exiting ZZ sleep mode. Document #: 38-05541 Rev. *G Page 26 of 32 [+] Feedback CY7C1361C/CY7C1363C Ordering Information The table below contains only the parts that are currently available. If you don’t see what you are looking for, please contact your local sales representative. For more information, visit the Cypress website at www.cypress.com and refer to the product summary page at http://www.cypress.com/products Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office closest to you, visit us at http://www.cypress.com/go/datasheet/offices Table 3. Ordering Information Speed (MHz) 133 Ordering Code CY7C1361C-133AXC CY7C1363C-133AXC CY7C1361C-133AJXC CY7C1363C-133AJXC Package Diagram Part and Package Type 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free (3 Chip Enable) Commercial 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free (2 Chip Enable) CY7C1361C-133AXI 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free (3 Chip Enable) CY7C1363C-133AJXI 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free (2 Chip Enable) 100 CY7C1361C-100AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free (3 Chip Enable) CY7C1361C-100BGC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) 100 CY7C1361C-100AXE 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Document #: 38-05541 Rev. *G Operating Range lndustrial Commercial Automotive Page 27 of 32 [+] Feedback CY7C1361C/CY7C1363C Package Diagrams (continued) Figure 10. 100-Pin TQFP (14X20X1.4 mm) 16.00±0.20 1.40±0.05 14.00±0.10 100 81 80 1 20.00±0.10 22.00±0.20 0.30±0.08 0.65 TYP. 30 12°±1° (8X) SEE DETAIL A 51 31 50 0.20 MAX. R 0.08 MIN. 0.20 MAX. 0.10 1.60 MAX. 0° MIN. SEATING PLANE STAND-OFF 0.05 MIN. 0.15 MAX. 0.25 NOTE: 1. JEDEC STD REF MS-026 GAUGE PLANE 0°-7° R 0.08 MIN. 0.20 MAX. 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 3. DIMENSIONS IN MILLIMETERS 0.60±0.15 0.20 MIN. 51-85050-*B 1.00 REF. DETAIL Document #: 38-05541 Rev. *G A Page 28 of 32 [+] Feedback CY7C1361C/CY7C1363C Figure 11. 119-Ball BGA (14X22X2.4 mm) Ø0.05 M C Ø0.25 M C A B A1 CORNER Ø0.75±0.15(119X) Ø1.00(3X) REF. 1 2 3 4 5 6 7 7 6 5 4 3 2 1 A A B B C D 1.27 C D E E F F H 19.50 J K L 20.32 G H 22.00±0.20 G J K L M 10.16 M N P N P R R T T U U 1.27 0.70 REF. A 3.81 7.62 30° TYP. 14.00±0.20 0.15(4X) 0.15 C 2.40 MAX. B 0.90±0.05 0.25 C 12.00 51-85115-*B C Document #: 38-05541 Rev. *G 0.60±0.10 0.56 SEATING PLANE Page 29 of 32 [+] Feedback CY7C1361C/CY7C1363C Figure 12. 165-Ball FBGA (13X15X1.4 mm) TOP VIEW BOTTOM VIEW PIN 1 CORNER PIN 1 CORNER Ø0.08 M C 1 2 3 4 5 6 7 8 9 10 11 Ø0.25 M C A B A Ø0.50 -0.06 (165X) +0.14 B 11 10 9 8 7 6 5 4 3 2 1 C A D B E C 1.00 F D G 15.00±0.10 E H F J L M 14.00 15.00±0.10 G K H J K N L 7.00 P M R N P A R A 1.00 5.00 B 13.00±0.10 1.40 MAX. 0.35±0.06 0.36 SEATING PLANE C 0.15 C 0.53±0.05 0.25 C 10.00 B 13.00±0.10 0.15(4X) NOTES : SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD) PACKAGE WEIGHT : 0.475g JEDEC REFERENCE : MO-216 / ISSUE E PACKAGE CODE : BB0AC 51-85180-*B Document #: 38-05541 Rev. *G Page 30 of 32 [+] Feedback CY7C1361C/CY7C1363C Document History Page Document Title: CY7C1361C/CY7C1363C 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM Document Number: 38-05541 REV. ECN NO. Submission Date Orig. of Change Description of Change ** 241690 See ECN RKF New data sheet *A 278969 See ECN RKF Changed Boundary Scan order to match the B rev of these devices. *B 332059 See ECN PCI Removed 117-MHz Speed Bin Address expansion pins/balls in the pinouts for all packages are modified as per JEDEC standard Added Address Expansion pins in the Pin Definitions Table Changed Device Width (23:18) for 119-BGA from 000001 to 101001 Added separate row for 165 -FBGA Device Width (23:18) Changed IDDZZ from 35 mA to 50 mA Changed ISB1 and ISB3 from 40 mA to 110 and 100 mA, respectively Modified VOL, VOH test conditions Corrected ISB4 Test Condition from (VIN ≥ VDD – 0.3V or VIN ≤ 0.3V) to (VIN ≥ VIH or VIN ≤ VIL) in the Electrical Characteristics table Changed ΘJA and ΘJc for TQFP Package from 25 and 9 °C/W to 29.41 and 6.13 °C/W respectively Changed ΘJA and ΘJc for BGA Package from 25 and 6°C/W to 34.1 and 14.0 °C/W respectively Changed ΘJA and ΘJc for FBGA Package from 27 and 6 °C/W to 16.8 and 3.0 °C/W respectively Added lead-free information for 100-pin TQFP, 119 BGA and 165 FBGA packages Updated Ordering Information Table *C 377095 See ECN PCI Changed ISB2 from 30 to 40 mA Modified test condition in note# 14 from VIH < VDD to VIH < VDD *D 408298 See ECN RXU Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901 North First Street” to “198 Champion Court” Changed tri state to tri-state. Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the Electrical Characteristics Table. Replaced Package Name column with Package Diagram in the Ordering Information table. Updated the ordering information. *E 433033 See ECN NXR Included Automotive range. *F 501793 See ECN VKN Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND Changed tTH, tTL from 25 ns to 20 ns and tTDOV from 5 ns to 10 ns in TAP AC Switching Characteristics table. Updated the Ordering Information table. *G 2756340 08/26/2009 Document #: 38-05541 Rev. *G VKN/AESA Updated template Included Soft Error Immunity Data Modified Ordering Information table by including parts that are available and modified the disclaimer for the Ordering information. Page 31 of 32 [+] Feedback CY7C1361C/CY7C1363C Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products PSoC Clocks & Buffers psoc.cypress.com clocks.cypress.com Wireless wireless.cypress.com Memories memory.cypress.com Image Sensors image.cypress.com © Cypress Semiconductor Corporation, 2004-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 38-05541 Rev. *G Revised August 26, 2009 Page 32 of 32 All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback