NTR4003N Small Signal MOSFET 30 V, 0.56 A, Single N−Channel, SOT−23 Features • Low Gate Voltage Threshold (VGS(TH)) to Facilitate Drive Circuit • • • • • Design Low Gate Charge for Fast Switching ESD Protected Gate SOT−23 Package Provides Excellent Thermal Performance Minimum Breakdown Voltage Rating of 30 V These are Pb−Free Devices http://onsemi.com V(BR)DSS RDS(on) TYP ID MAX 1.0 W @ 4.0 V 30 V 0.56 A 1.5 W @ 2.5 V Applications • Notebooks: N−Channel ♦ • Level Shifters ♦ Logic Switches ♦ Low Side Load Switches Portable Applications 3 1 MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Symbol Value Unit Drain−to−Source Voltage VDSS 30 V Gate−to−Source Voltage VGS ±20 V ID 0.5 A Parameter Continuous Drain Current (Note 1) Steady State Power Dissipation (Note 1) TA = 25°C TA = 85°C Steady State Continuous Drain Current (Note 1) t < 10 s TA = 25°C MARKING DIAGRAM/ PIN ASSIGNMENT 0.37 PD 0.69 ID 0.56 TA = 85°C Power Dissipation (Note 1) 3 Drain A 0.83 W tp = 10 ms IDM 1.7 A TJ, Tstg −55 to 150 °C Source Current (Body Diode) IS 1.0 A Lead Temperature for Soldering Purposes (1/8” from case for 10 s) TL 260 °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Symbol Max Unit Junction−to−Ambient − Steady State (Note 1) RqJA 180 °C/W Junction−to−Ambient − t < 10 s (Note 1) RqJA 150 Junction−to−Ambient − Steady State (Note 2) RqJA 300 1. Surface−mounted on FR4 board using 1 in sq pad size (Cu area = 1.127 in sq [1 oz] including traces). 2. Surface−mounted on FR4 board using the minimum recommended pad size. © Semiconductor Components Industries, LLC, 2006 May, 2006 − Rev. 0 SOT−23 CASE 318 STYLE 21 1 TR8 M G G 1 Gate 2 Source TR8 = Specific Device Code M = Date Code G = Pb−Free Package (Note: Microdot may be in either location) *Date Code orientation and overbar may vary depending upon manufacturing location. ORDERING INFORMATION Device THERMAL RESISTANCE RATINGS Parameter 1 2 0.40 PD Operating Junction and Storage Temperature 3 W t<5s Pulsed Drain Current 2 Package Shipping† NTR4003NT1G SOT−23 (Pb−Free) 3000/Tape & Reel NTR4003NT3G SOT−23 (Pb−Free) 10,000/Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. Publication Order Number: NTR4003N/D NTR4003N ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified) Parameter Symbol Test Condition Min Drain−to−Source Breakdown Voltage V(BR)DSS VGS = 0 V, ID = 100 mA 30 Drain−to−Source Breakdown Voltage Temperature Coefficient V(BR)DSS/TJ Typ Max Units OFF CHARACTERISTICS V 40 Zero Gate Voltage Drain Current IDSS VGS = 0 V, VDS = 30 V TJ = 25°C Gate−to−Source Leakage Current IGSS VDS = 0 V, VGS = ±10 V VGS(TH) VGS = VDS, ID = 250 mA mV/°C 1.0 mA ±1.0 mA 1.4 V ON CHARACTERISTICS (Note 3) Gate Threshold Voltage Negative Threshold Temperature Coefficient VGS(TH)/TJ Drain−to−Source On Resistance RDS(on) Forward Transconductance gFS 0.8 3.4 mV/°C VGS = 4.0 V, ID = 10 mA 1.0 1.5 VGS = 2.5 V, ID = 10 mA 1.5 2.0 VDS = 3.0 V, ID = 10 mA 0.33 VGS = 0 V, f = 1.0 MHz, VDS = 5.0 V 19.7 W S CHARGES AND CAPACITANCES Input Capacitance Ciss Output Capacitance Coss 21 Reverse Transfer Capacitance Crss 8.1 Total Gate Charge QG(TOT) 1.15 Threshold Gate Charge QG(TH) VGS = 5.0 V, VDS = 24 V, ID = 0.1 A pF 0.15 Gate−to−Source Gate Charge QGS Gate−to−Drain Charge QGD 0.23 td(on) 16.7 nC 0.32 SWITCHING CHARACTERISTICS (Note 4) Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time tr td(off) VGS = 4.5 V, VDD = 5.0 V, ID = 0.1 A, RG = 50 W tf 47.9 ns 65.1 64.2 SOURCE−DRAIN DIODE CHARACTERISTICS Forward Diode Voltage Reverse Recovery Time VSD tRR VGS = 0 V, IS = 10 mA TJ = 25°C 0.65 TJ = 125°C 0.45 VGS = 0 V, dIS/dt = 8A/ms, IS = 10 mA 3. Pulse Test: pulse width v 300 ms, duty cycle v 2%. 4. Switching characteristics are independent of operating junction temperatures. http://onsemi.com 2 14 0.7 V ns NTR4003N TYPICAL PERFORMANCE CURVES (TJ = 25°C unless otherwise noted) 1.6 1.6 VDS ≥ 10 V VGS = 10 V to 5 V 0.8 4V 0.4 3.5 V TJ = 25°C 0.8 TJ = 125°C 0.4 0 1 0 2 VDS, DRAIN−TO−SOURCE VOLTAGE (V) 3 1 2 4 VGS, GATE−TO−SOURCE VOLTAGE (V) Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) 0 10 ID = 0.2 A 8 6 4 2 0 2.4 2.8 3.2 3.6 VGS, GATE−TO−SOURCE VOLTAGE (V) 4 VGS = 10 V TJ = 125°C 0.8 0.6 TJ = 25°C 0.4 TJ = −55°C 0.2 0 0 0.1 0.2 0.3 0.4 0.5 0.6 ID, DRAIN CURRENT (AMPS) Figure 4. On−Resistance vs. Drain Current and Temperature 1000 1.80 VGS = 0 V ID = 0.3 A VGS = 4.5 V IDSS, LEAKAGE (nA) 1.60 5 1 Figure 3. On−Resistance vs. Gate−to−Source Voltage RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) (NORMALIZED) TJ = −55°C 1.2 2.5 V 0 RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) ID, DRAIN CURRENT (A) ID, DRAIN CURRENT (A) 4.5 V 1.2 1.40 1.20 1.00 TJ = 150°C 100 TJ = 125°C 0.80 0.60 −25 10 −50 0 25 50 75 100 125 150 0 5 10 15 20 25 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) TJ, JUNCTION TEMPERATURE (°C) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−to−Source Leakage Current vs. Voltage http://onsemi.com 3 30 NTR4003N TYPICAL PERFORMANCE CURVES (TJ = 25°C unless otherwise noted) VGS, GATE−TO−SOURCE VOLTAGE (V) 50 40 30 Ciss 20 Coss 10 0 Crss 0 4 8 12 16 5 TJ = 25°C ID = 0.1 A 4 3 2 1 0 0.4 0 20 DRAIN−TO−SOURCE VOLTAGE (V) Figure 8. Gate−to−Source & Drain−to−Source Voltage vs. Total Charge 1 VGS = 0 V 0.1 0.01 0.8 QG, TOTAL GATE CHARGE (nC) Figure 7. Capacitance Variation IS, SOURCE CURRENT (A) C, CAPACITANCE (pF) TJ = 25°C VGS = 0 V TJ = 150°C TJ = 25°C 0.001 0.4 0.6 VSD, SOURCE−TO−DRAIN VOLTAGE (V) Figure 9. Diode Forward Voltage vs. Current http://onsemi.com 4 0.8 1.2 NTR4003N PACKAGE DIMENSIONS SOT−23 (TO−236) CASE 318−08 ISSUE AN NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. 4. 318−01 THRU −07 AND −09 OBSOLETE, NEW STANDARD 318−08. D SEE VIEW C 3 HE E c 1 DIM A A1 b c D E e L L1 HE 2 b 0.25 e q A L A1 L1 MIN 0.89 0.01 0.37 0.09 2.80 1.20 1.78 0.10 0.35 2.10 MILLIMETERS NOM MAX 1.00 1.11 0.06 0.10 0.44 0.50 0.13 0.18 2.90 3.04 1.30 1.40 1.90 2.04 0.20 0.30 0.54 0.69 2.40 2.64 MIN 0.035 0.001 0.015 0.003 0.110 0.047 0.070 0.004 0.014 0.083 INCHES NOM 0.040 0.002 0.018 0.005 0.114 0.051 0.075 0.008 0.021 0.094 MAX 0.044 0.004 0.020 0.007 0.120 0.055 0.081 0.012 0.029 0.104 STYLE 21: PIN 1. GATE 2. SOURCE 3. DRAIN VIEW C SOLDERING FOOTPRINT* 0.95 0.037 0.95 0.037 2.0 0.079 0.9 0.035 0.8 0.031 SCALE 10:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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