Sony CXA3201N Rx gain control amplifier Datasheet

CXA3201N
RX Gain Control Amplifier
For the availability of this product, please contact the sales office.
Description
CXA3201N is an RX gain control amplifier suitable
for CDMA cellular/PCS phone.
16 pin SSOP (Plastic)
Features
• Wide gain control range
• Linear gain slope
• Wideband operation (50MHz to 300MHz)
• Very small package (16 Pin SSOP)
• Low voltage operation
• Two input ports
• Power save function included
Absolute Maximum Ratings
• Supply voltage
VCC
6
V
• Operating temperature
Topr –55 to +125 °C
• Storage temperature
Tstg –65 to +150 °C
• Allowable Power dissipation PD
330
mW
• Supply voltage range
–0.3 to 6
V
• Logic input voltage
–0.3 to VCC + 0.3 V
• Signal input voltage
–0.3 to VCC + 0.3 V
• Differental signal input voltage
0 to 2.5
V
Operating Condition
Supply voltage
VCC
2.7 to 3.8
V
Applications
CDMA cellular/PCS phone
Structure
Bipolar silicon monolithic IC
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E97807-PS
CXA3201N
Block Diagram
IF Input for CDMA
CDMA IN
CDMA INX
OUT
SWITCH
IF Input for FM
FM IN
FM INX
Input Select
MODE
Gain control
GCTL
Supply Voltage
OUTX
VCC1, 2
Bias
Driver
Ground
GND
Power Save
PSV
Pin Configuration
CDMA IN
1
16
GCTL
CDMA INX
2
15
VCC1
GND
3
14
VCC1
FM IN
4
13
VCC2
FM INX
5
12
GND
GND
6
11
GND
MODE
7
10
OUTX
PSV
8
9
–2–
OUT
IF Output
CXA3201N
Pin Description
Pin
No.
1
Symbol
CDMA IN
Pin voltage
TYP (V)
Equivalent circuit
Description
1.15
2k
2k
Differential input pins for received
CDMA IF signal.
2
CDMA INX
GND
1.15
3
6
11
12
GND
0
4
FM IN
1.15
1
2
Ground.
2k
2k
Differential input pins for received
FM IF signal.
5
FM INX
GND
1.15
4
5
VCC1
7
7
MODE
Input select pin.
CDMA IN for High FM IN for Low.
30k
—
GND
VCC1
8
PSV
—
Power save function pin.
High: Active
Low: Power save
8
135k
GND
–3–
CXA3201N
Pin
No.
Symbol
Pin voltage
TYP (V)
Equivalent circuit
Description
10
9
VCC2
9
OUT
—
460
460
12.3k
12.3k
Differential output pins for received
CDMA IF signal.
Open collector output.
10
OUTX
—
GND
13
VCC2
3.0
Positive power supply for output
stage.
14
15
VCC1
3.0
Positive power supply.
VCC1
8k
16
GCTL
—
8k
Gain control pin.
16
6k
6k
GND
–4–
CXA3201N
Electrical Characteristics
(VCC = 3.0V, Ta = 27°C)
DC Characteristics
Parameter
Symbol
Conditions
Min. Typ. Max. Unit
Current consumption 1
ICC1
Vpsv = 3.0V, Vgctl = 1.5V, Pin 13, 14
7
10.2
15
Current consumption 2
ICC2
Vpsv = 0 V, Vgctl = 1.5V, Pin 13, 14
10
27
50
Input current pin 7H
ImodeH
Vmode = 3.0V
Input current pin 7L
ImodeL
Vmode = 0.5V
Input current pin 8H
IpsvH
Vpsv = 3.0V
Input current pin 8L
IpsvL
Vpsv = 0 V
Input current pin 16H
IgctlH
Vgctl = 3.0V
Input current pin 16L
IgctlL
Vgctl = 0.5V
–1
MODE high voltage
VmH
Pin 7
2.5
MODE low voltage
VmL
Pin 7
PSV high voltage
VpsH
Pin 8
PSV low voltage
VpsL
Pin 8
1
–1
1
µA
–15
1
0.5
2.5
V
0.5
AC Characteristics
Parameter
mA
(VCC = 3.0V, Ta = 27°C)
Symbol
Conditions
Min. Typ. Max. Unit
Operating frequency
range
Fr
Gain CDMA2.4
GCDMA2.4
Vmode = "H", f = 210.38MHz, Vgctl = 2.4V
42
46
50
Gain CDMA1.5
GCDMA1.5
Vmode = "H", Vgctl = 1.5V
–7
–3
1
Gain CDMA0.6
GCDMA0.6
Vmode = "H", Vgctl = 0.6V
–59
–55
–51
CDMA Gain slope
GCLIN
Vmode = "H", Gain CDMA at Vgctl = 2.0V
– Gain CDMA at Vgctl = 1.0V
58
61
64
Gain FM2.4
GFM2.4
Vmode = "L", f = 85.38MHz, Vgctl = 2.4V
42
46
50
Gain FM1.5
GFM1.5
Vmode = "L", Vgctl = 1.5V
–7
–3
1
Gain FM0.6
GFM0.6
Vmode = "L", Vgctl = 0.6V
–59
–55
–51
FM Gain slope
GFMLIN
58
61
64
Input level 3rd order
intercept point
IIP3
–42
–38
Noise Figure
NF
300 MHz
50
Vmode = "L", Gain FM at Vgctl = 2.0V
– Gain FM at Vgctl = 1.0V
Vmode = "H", GCDMA = 40dB∗1
f1 = 209.38MHz, f2 = 211.38MHz
Measure of 210.38MHz
Vmode = "H", GCDMA = 40dB∗1
Measure of 210.38MHz
∗1 Adjust GCTL voltage, and set the overall gain to 40dB.
–5–
5
dB
dB/V
dB
dB/V
dBm
8
dB
CXA3201N
Measurement Circuit
∗1
V16
1k
180n
1 CDMA IN
GCTL 16
A16
1000p
CDMA
INPUT
1000p
∗2
2 CDMA INX
VCC1 15
3 GND
VCC1 14
4 FM IN
VCC2 13
5 FM INX
GND 12
0.01µ
V14
∗1
A14
1.5µ
0.01µ
1000p
FM
INPUT
1000p
∗4
150n∗3
6 GND
GND 11
V7
A7
150n∗3
7 MODE
OUTX 10
1.6k
∗1
OUTPUT
V8
A8
8 PSV
OUT 9
∗1 TOKO, Inc. B5FL 616DS-1135
∗2 Coilcraft, Inc. 0805HS-181TKBC
∗3 Coilcraft, Inc. 0805HS-151TKBC
∗4 Coilcraft, Inc. 1008CS-152XKBC
–6–
CXA3201N
Application Circuit
VCC
1000p
1k
GCTL 16
1 CDMA IN
CDMA
RX IF
INPUT
∗
Gain Control
Voltage
∗
2 CDMA INX
VCC1 15
0.01µ
100p
1000p
VCC1 14
3 GND
0.01µ
1000p
FM
RX IF
INPUT
∗
4 FM IN
VCC2 13
5 FM INX
GND 12
6 GND
GND 11
∗
1000p
∗
1000p
CDMA
FM
7 MODE
OUTX 10
RX IF
OUTPUT
Active
Sleep
8 PSV
OUT
9
1000p
∗
∗ Must be adjusting values to result a best impedance matching between BPF filter and this IC.
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
–7–
CXA3201N
Design Reference Values
Single ended measurement
Item
(VCC = 3.0V, Ta = 27°C)
Conditions
Symbol
Typ.
Unit
2.7
kΩ
1.4
pF
Input resistance
Rin
Input capacitance
Cin
Output resistance
Rout
5.9
kΩ
Output capacitance
Cout
0.85
pF
f = 210.38MHz, Vgctl = 1.5V
Notes on Operation
1) This IC is a wideband amplifier with wide gain control range. The decouping capacitors between GND Pin
and VCC Pin should be as close to the IC as possible.
2) The resistors connected to Pins 9 and 10 should be as close to the IC as possible.
3) This IC assumes the excellent characteristics when the differential input impedance between Pins 1 and 2,
Pins 4 and 5 is 500Ω. Refer to the Measurement Circuit for the external element settings, etc.
4) Pay attention to handling this IC because its electrostatic discharge strength is weak.
–8–
CXA3201N
IIP3
Sensitivity
0
60
VCC = 3.0V
VCC = 3.0V
40
–10
–20
IIP3 [dBm]
Power gain [dB]
20
0
–20
–30
–40
–40
T = –40°C
T = 27°C
T = 85°C
–60
–50
–60
–80
–80
0
0.5
1
1.5
2
2.5
T = –40°C
T = 27°C
T = 85°C
3
–60
–40
–20
0
60
6
VCC = 3.0V
VCC = 3.0V
4
Gain error [dB]
20
Noise figure [dB]
40
Gain Error from Room Temp
Noise Figure
25
15
10
T = –40°C
T = 27°C
T = 85°C
5
0
–10
20
Power gain [dB]
Vgctl [V]
0
10
20
2
0
–2
T = –40°C
T = 85°C
–4
30
40
50
–6
–80
60
–60
–40
–20
0
Power gain [dB]
Power gain [dB]
–9–
20
40
60
CXA3201N
Package Outline
Unit: mm
16PIN SSOP (PLASTIC)
+ 0.2
1.25 – 0.1
∗5.0 ± 0.1
0.1
16
9
1
6.4 ± 0.2
∗4.4 ± 0.1
A
8
+ 0.05
0.15 – 0.02
0.65
+ 0.1
0.22 – 0.05
0.13 M
0.5 ± 0.2
0.1 ± 0.1
0° to 10°
DETAIL A
NOTE: Dimension “∗” does not include mold protrusion.
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SONY CODE
SSOP-16P-L01
LEAD TREATMENT
SOLDER / PALLADIUM
PLATING
EIAJ CODE
SSOP016-P-0044
LEAD MATERIAL
42/COPPER ALLOY
PACKAGE MASS
0.1g
JEDEC CODE
NOTE : PALLADIUM PLATING
This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame).
– 10 –
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