Fujitsu MB95150M 8-bit microcontroller Datasheet

FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-12613-3E
8-bit Microcontroller
CMOS
F2MC-8FX MB95150M Series
MB95156M/F156M/F156N/F156J/FV100D-103
■ DESCRIPTION
The MB95150M series is general-purpose, single-chip microcontrollers. In addition to a compact instruction set,
the microcontrollers contain a variety of peripheral functions.
Note : F2MC is the abbreviation of FUJITSU Flexible Microcontroller.
■ FEATURE
• F2MC-8FX CPU core
Instruction set optimized for controllers
• Multiplication and division instructions
• 16-bit arithmetic operations
• Bit test branch instruction
• Bit manipulation instructions etc.
• Clock
• Main clock
• Main PLL clock
• Sub clock
• Sub PLL clock
(Continued)
Be sure to refer to the “Check Sheet” for the latest cautions on development.
“Check Sheet” is seen at the following support page
URL : http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html
“Check Sheet” lists the minimal requirement items to be checked to prevent problems beforehand in system
development.
Copyright©2006-2007 FUJITSU LIMITED All rights reserved
MB95150M Series
(Continued)
• Timer
• 8/16-bit compound timer × 2 channels
Can be used to interval timer, PWC timer, PWM timer and input capture.
• 8/16-bit PPG × 2 channels
• 16-bit PPG × 1 channel
• Time-base timer × 1 channel
• Watch prescaler × 1 channel
• LIN-UART × 1 channel
• LIN function, clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable
• Full duplex double buffer
• UART/SIO × 1 channel
• Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable
• Full duplex double buffer
• External interrupt × 8 channels
• Interrupt by edge detection (rising, falling, or both edges can be selected)
• Can be used to recover from low-power consumption (standby) modes.
• 8/10-bit A/D converter × 8 channels
8-bit or 10-bit resolution can be selected.
• LCD controller (LCDC)
• 16 SEG × 4 COM (Max 64 pixels)
• With blinking function
• Low-power consumption (standby) mode
• Stop mode
• Sleep mode
• Watch mode
• Time-base timer mode
• I/O port: Max 39
• General-purpose I/O ports (CMOS) : 39 ports
• Programmable input voltage levels of port
Automotive input level / CMOS input level / hysteresis input level
• Flash memory security function
Protects the content of Flash memory (Flash memory device only)
2
MB95150M Series
■ PRODUCT LINEUP
Part number
Parameter
Type
MB95156M
MB95F156M
MB95F156N
MASK ROM product
Flash memory product
ROM capacity
32 Kbytes
RAM capacity
1 Kbyte
Option*1
Reset output
Yes/No
Yes
Clock system
No
Dual clock
Low voltage
detection reset
Yes/No
Clock supervisor
Yes/No
CPU functions
MB95F156J
No
Yes
No
Yes
Number of basic instructions
: 136
Instruction bit length
: 8 bits
Instruction length
: 1 to 3 bytes
Data bit length
: 1, 8, and 16 bits
Minimum instruction execution time : 61.5 ns (at machine clock frequency 16.25 MHz)
Interrupt processing time
: 0.6 µs (at machine clock frequency 16.25 MHz)
Peripheral functions
General-purpose I/O port (CMOS) : 39 ports
Ports (Max 39 ports) Programmable input voltage levels of port :
Automotive input level / CMOS input level / hysteresis input level
Time-base timer
(1 channel)
Interrupt cycle : 0.5 ms, 2.1 ms, 8.2 ms, 32.8 ms (at main oscillation clock 4 MHz)
Watchdog timer
Reset generated cycle
At main oscillation clock 10 MHz : Min 105 ms
At sub oscillation clock 32.768 kHz : Min 250 ms
Wild register
Capable of replacing 3 bytes of ROM data
UART/SIO
(1 channel)
Data transfer capable in UART/SIO
Full duplex double buffer, variable data length (5/6/7/8-bit), built-in baud rate
generator
NRZ type transfer format, error detected function
LSB-first or MSB-first can be selected.
Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable
LIN-UART
(1 channel)
Dedicated reload timer allowing a wide range of communication speeds to be set.
Full duplex double buffer
Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable
LIN functions available as the LIN master or LIN slave.
8/10-bit A/D converter
8-bit or 10-bit resolution can be selected.
(8 channels)
LCD controller
(LCDC)
COM output
: 4 (Max)
SEG output
: 16 (Max)
LCD drive power supply (bias) pin
:4
16 SEG × 4 COM
: 64 pixels can be displayed.
Duty LCD mode
Operable in LCD standby mode
With blinking function
Built-in division resistance for LCD drive
(Continued)
3
MB95150M Series
(Continued)
Part number
Peripheral functions
Parameter
MB95156M
MB95F156M
MB95F156N
MB95F156J
8/16-bit compound
timer (2 channels)
Each channel of the timer can be used as “8-bit timer × 2 channels” or “16-bit timer
× 1 channel”.
Built-in timer function, PWC function, PWM function, capture function, and square
waveform output
Count clock : 7 internal clocks and external clock can be selected.
16-bit PPG
(1 channel)
PWM mode or one-shot mode can be selected.
Counter operating clock : Eight selectable clock sources
Support for external trigger start
8/16-bit PPG
(2 channels)
Each channel of the PPG can be used as “8-bit PPG × 2 channels” or “16-bit PPG ×
1 channel”.
Counter operating clock : Eight selectable clock sources
Watch counter
Count clock : Four selectable clock sources (125 ms, 250 ms, 500 ms, or 1 s)
Counter value can be set from 0 to 63. (Capable of counting for 1 minute when
selecting clock source 1 second and setting counter value to 60)
Watch prescaler
(1 channel)
4 selectable interval times (125 ms, 250 ms, 500 ms, or 1 s)
External interrupt
(8 channels)
Interrupt by edge detection (rising, falling, or both edges can be selected.)
Can be used to recover from standby modes.
Flash memory
Supports automatic programming, Embedded AlgorithmTM *2
Write/Erase/Erase-Suspend/Resume commands
A flag indicating completion of the algorithm
Number of write/erase cycles (Minimum) : 10000 times
Data retention time : 20 years
Boot block configuration
Erase can be performed on each block
Block protection with external programming voltage
Flash Security Feature for protecting the content of the Flash
Standby mode
Sleep, stop, watch, and time-base timer
*1 : For details of option, refer to “■ MASK OPTION”.
*2 : Embedded Algorithm is a trade mark of Advanced Micro Devices Inc.
Note : Part number of evaluation products in MB95150M series is MB95FV100D-103. When using it, the MCU
board (MB2146-303A) is required.
4
MB95150M Series
■ OSCILLATION STABILIZATION WAIT TIME
The initial value of the main clock oscillation stabilization wait time is fixed to the maximum value. The maximum
value is shown as follows.
Oscillation stabilization wait time
Remarks
(2 −2) /FCH
Approx. 4.10 ms (at main oscillation clock 4 MHz)
14
■ PACKAGES AND CORRESPONDING PRODUCTS
Part number
Package
MB95156M
MB95F156M/F156N/F156J
MB95FV100D-103
FPT-48P-M26
FPT-52P-M01
BGA-224P-M08
: Available
: Unavailable
5
MB95150M Series
■ DIFFERENCES AMONG PRODUCTS AND NOTES ON SELECTING PRODUCTS
• Notes on Using Evaluation Products
The Evaluation product has not only the functions of the MB95150M series but also those of other products to
support software development for multiple series and models of the F2MC-8FX family. The I/O addresses for
peripheral resources not used by the MB95150M series are therefore access-barred. Read/write access to these
access-barred addresses may cause peripheral resources supposed to be unused to operate, resulting in
unexpected malfunctions of hardware or software.
Particularly, do not use word access to odd numbered byte address in the prohibited areas (If these access are
used, the address may be read or written unexpectedly).
Also, as the read values of prohibited addresses on the evaluation product are different to the values on the
Flash memory and MASK ROM products, do not use these values in the program.
The functions corresponding to certain bits in single-byte registers may not be supported on some mask ROM
and Flash memory products. However, reading or writing to these bits will not cause malfunction of the hardware.
Also, as the evaluation, Flash memory, and mask ROM products are designed to have identical software operation, no particular precautions are required.
• Difference of Memory Spaces
If the amount of memory on the Evaluation product is different from that of the Flash memory product or MASK
ROM product, carefully check the difference in the amount of memory from the model to be actually used when
developing software.
For details of memory space, refer to “■ CPU CORE”.
• Current Consumption
• The current consumption of Flash memory product is typically greater than for MASK ROM product.
• For details of current consumption, refer to “■ ELECTRICAL CHARACTERISTICS”.
• Package
For details of information on each package, refer to “■ PACKAGES AND CORRESPONDING PRODUCTS” and
“■ PACKAGE DIMENSIONS”.
• Operating voltage
The operating voltage are different between the Evaluation, Flash memory products, and MASK ROM product.
For details of operating voltage, refer to “■ ELECTRICAL CHARACTERISTICS”.
6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
P61/SEG09/PPG11
P62/SEG10/TO10
P63/SEG11/TO11
P64/SEG12/EC1
P65/SEG13/SCK
P66/SEG14/SOT
P67/SEG15/SIN
P14/PPG0
P13/TRG0/ADTG
P12/UCK0
P11/UO0
P10/UI0
P07/INT07/AN07
P06/INT06/AN06
P05/INT05/AN05
P04/INT04/AN04
P03/INT03/AN03
P02/INT02/AN02
P01/INT01/AN01
P00/INT00/AN00
MOD
X0
X1
VSS
48
47
46
45
44
43
42
41
40
39
38
37
P60/SEG08/PPG10
PB7/SEG07/EC0
PB6/SEG06/TO01
PB5/SEG05/TO00
PB4/SEG04/PPG01
PB3/SEG03/PPG00
PB2/SEG02
PB1/SEG01
PB0/SEG00
PA3/COM3
PA2/COM2
PA1/COM1
MB95150M Series
■ PIN ASSIGNMENT
(TOP VIEW)
LQFP-48
36
35
34
33
32
31
30
29
28
27
26
25
PA0/COM0
P95
P94
P93/V0
P92/V1
P91/V2
P90/V3
RST
X0A
X1A
C
VCC
(FPT-48P-M26)
(Continued)
7
P07/INT07/AN07
P06/INT06/AN06
P05/INT05/AN05
P04/INT04/AN04
P03/INT03/AN03
P02/INT02/AN02
NC
P01/INT01/AN01
P00/INT00/AN00
MOD
X0
X1
VSS
14
15
16
17
18
19
20
21
22
23
24
25
26
52
51
50
49
48
47
46
45
44
43
42
41
40
P60/SEG08/PPG10
PB7/SEG07/EC0
PB6/SEG06/TO01
PB5/SEG05/TO00
PB4/SEG04/PPG01
PB3/SEG03/PPG00
NC
PB2/SEG02
PB1/SEG01
PB0/SEG00
PA3/COM3
PA2/COM2
PA1/COM1
MB95150M Series
(Continued)
(TOP VIEW)
P61/SEG09/PPG11
P62/SEG10/TO10
P63/SEG11/TO11
P64/SEG12/EC1
P65/SEG13/SCK
P66/SEG14/SOT
NC
P67/SEG15/SIN
P14/PPG0
P13/TRG0/ADTG
P12/UCK0
P11/UO0
P10/UI0
8
1
2
3
4
5
6
7
8
9
10
11
12
13
LQFP-52
(FPT-52P-M01)
39
38
37
36
35
34
33
32
31
30
29
28
27
PA0/COM0
P95
P94
P93/V0
P92/V1
P91/V2
NC
P90/V3
RST
X0A
X1A
C
VCC
MB95150M Series
■ PIN DESCRIPTION
Pin no.
LQFP*1 LQFP*2
Pin name
I/O
circuit
type*3
Function
General-purpose I/O port.
The pin is shared with LCDC SEG output (SEG09) and 8/16-bit
PPG ch.1 output (PPG11).
1
1
P61/SEG09/
PPG11
2
2
P62/SEG10/TO10
3
3
P63/SEG11/TO11
4
4
P64/SEG12/EC1
5
5
P65/SEG13/SCK
General-purpose I/O port.
The pin is shared with LCDC SEG output (SEG13) and LINUART clock I/O (SCK) .
6
6
P66/SEG14/SOT
General-purpose I/O port.
The pin is shared with LCDC SEG output (SEG14) and LINUART data output (SOT) .
7
8
P67/SEG15/SIN
8
9
P14/PPG0
9
10
P13/TRG0/ADTG
General-purpose I/O port.
The pins are shared with LCDC SEG output (SEG10, SEG11)
and 8/16-bit compound timer ch.1 output (TO10, TO11) .
M
N
General-purpose I/O port.
The pin is shared with LCDC SEG output (SEG12) and 8/16-bit
compound timer ch.1 clock input (EC1).
General-purpose I/O port.
The pin is shared with LCDC SEG output (SEG15) and LINUART data input (SIN) .
General-purpose I/O port.
The pin is shared with 16-bit PPG ch.0 output (PPG0) .
H
General-purpose I/O port.
The pin is shared with 16-bit PPG ch.0 trigger input (TRG0) and
A/D converter trigger input (ADTG) .
10
11
P12/UCK0
General-purpose I/O port.
The pin is shared with UART/SIO ch.0 clock I/O (UCK0) .
11
12
P11/UO0
General-purpose I/O port.
The pin is shared with UART/SIO ch.0 data output (UO0) .
12
13
P10/UI0
13
14
P07/INT07/AN07
14
15
P06/INT06/AN06
15
16
P05/INT05/AN05
16
17
P04/INT04/AN04
17
18
P03/INT03/AN03
18
19
P02/INT02/AN02
19
21
P01/INT01/AN01
20
22
P00/INT00/AN00
21
23
MOD
G
General-purpose I/O port.
The pin is shared with UART/SIO ch.0 data input (UI0) .
D
General-purpose I/O port.
The pins are shared with external interrupt input (INT00 to INT07)
and A/D converter analog input (AN00 to AN07).
B
The operating mode designation pin
(Continued)
9
MB95150M Series
(Continued)
Pin no.
LQFP*1 LQFP*2
Pin name
22
24
X0
23
25
X1
24
26
25
I/O
circuit
type*3
Function
A
Main clock oscillation pins
VSS
⎯
Power supply pin (GND)
27
VCC
⎯
Power supply pin
26
28
C
⎯
Capacitor connection pin
27
29
X1A
28
30
X0A
A
Sub clock oscillation pins (32 kHz)
29
31
RST
B’
Reset pin
30
32
P90/V3
31
34
P91/V2
32
35
P92/V1
R
General-purpose I/O port.
The pins are shared with power supply pin for LCDC drive (V0 to
V3) .
33
36
P93/V0
34
37
P94
35
38
P95
S
General-purpose I/O port
36
39
PA0/COM0
37
40
PA1/COM1
38
41
PA2/COM2
M
General-purpose I/O port.
The pins are shared with LCDC COM output (COM0 to COM3) .
39
42
PA3/COM3
40
43
PB0/SEG00
41
44
PB1/SEG01
42
45
PB2/SEG02
43
47
PB3/SEG03/
PPG00
44
48
PB4/SEG04/
PPG01
45
49
PB5/SEG05/TO00
46
50
PB6/SEG06/TO01
47
51
PB7/SEG07/EC0
48
52
P60/SEG08/
PPG10
M
General-purpose I/O port.
The pin is shared with LCDC SEG output (SEG08) and 8/16-bit
PPG ch.1 output (PPG10) .
⎯
7, 20,
33, 46
NC
⎯
Internal connect pins.
Be sure this pin is left open.
General-purpose I/O port.
The pins are shared with LCDC SEG output (SEG00 to SEG02) .
M
General-purpose I/O port.
The pins are shared with LCDC SEG output (SEG03, SEG04)
and 8/16-bit PPG ch.0 output (PPG00, PPG01).
General-purpose I/O port.
The pins are shared with LCDC SEG output (SEG05, SEG06)
and 8/16-bit compound timer ch.0 output (TO00, TO01).
General-purpose I/O port.
The pin is shared with LCDC SEG output (SEG07) and 8/16-bit
compound timer ch.0 clock input (EC0).
*1 : FPT-48P-M26
*2 : FPT-52P-M01
*3 : For the I/O circuit type, refer to “■ I/O CIRCUIT TYPE”.
10
MB95150M Series
■ I/O CIRCUIT TYPE
Type
Circuit
X1 (X1A)
A
Remarks
Clock input
N-ch
X0 (X0A)
• Oscillation circuit
• High-speed side
Feedback resistance : approx. 1 MΩ
• Low-speed side
Feedback resistance : approx. 10 MΩ
Standby control
B
• Only for input
• Hysteresis input
Mode input
• Hysteresis input
• Reset output
Reset input
B’
Reset output
N-ch
Pull-up control
R
P-ch
P-ch
Digital output
Digital output
•
•
•
•
•
CMOS output
Hysteresis input
Analog input
With pull-up control
Automotive input
N-ch
D
Analog input
Automotive input
A/D control
Hysteresis input
Standby control
External
interrupt control
Pull-up control
R
P-ch
P-ch
G
N-ch
Digital output
Digital output
•
•
•
•
•
CMOS output
CMOS input
Hysteresis input
With pull-up control
Automotive input
•
•
•
•
CMOS output
Hysteresis input
With pull-up control
Automotive input
CMOS input
Hysteresis input
Automotive input
Standby control
Pull-up control
R
P-ch
P-ch
H
Digital output
Digital output
N-ch
Hysteresis input
Standby control
Automotive input
(Continued)
11
MB95150M Series
(Continued)
Type
Circuit
Remarks
P-ch
Digital output
Digital output
N-ch
M
•
•
•
•
CMOS output
LCD output
Hysteresis input
Automotive input
•
•
•
•
•
CMOS output
LCD output
CMOS input
Hysteresis input
Automotive input
•
•
•
•
CMOS output
LCD power supply
Hysteresis input
Automotive input
LCD output
Hysteresis input
Automotive input
LCD control
Standby control
P-ch
Digital output
Digital output
N-ch
N
LCD output
CMOS input
Hysteresis input
Automotive input
LCD control
Standby control
P-ch
N-ch
Digital output
Digital output
LCD built-in division
resistance I/O
R
Hysteresis input
LCD control
Standby control
Automotive input
P-ch
N-ch
S
Digital output
Digital output
Hysteresis input
Standby control
12
Automotive input
• CMOS output
• Hysteresis input
• Automotive input
MB95150M Series
■ HANDLING DEVICES
• Preventing Latch-up
Care must be taken to ensure that maximum voltage ratings are not exceeded when they are used.
Latch-up may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins
other than medium- and high-withstand voltage pins or if higher than the rating voltage is applied between VCC
pin and VSS pin.
When latch-up occurs, power supply current increases rapidly and might thermally damage elements.
• Stable Supply Voltage
Supply voltage should be stabilized.
A sudden change in power-supply voltage may cause a malfunction even within the guaranteed operating range
of the Vcc power-supply voltage.
For stabilization, in principle, keep the variation in Vcc ripple (p-p value) in a commercial frequency range
(50/60 Hz) not to exceed 10% of the standard Vcc value and suppress the voltage variation so that the transient
variation rate does not exceed 0.1 V/ms during a momentary change such as when the power supply is switched.
• Precautions for Use of External Clock
Even when an external clock is used, oscillation stabilization wait time is required for power-on reset, wake-up
from sub clock mode or stop mode.
■ PIN CONNECTION
• Treatment of Unused Pin
Leaving unused input pins unconnected can cause abnormal operation or latch-up, leaving to permanent damage. Unused input pins should always be pulled up or down through resistance of at least 2 kΩ. Any unused
input/output pins may be set to output mode and left open, or set to input mode and treated the same as unused
input pins. If there is unused output pin, make it to open.
• Power Supply Pins
In products with multiple VCC or VSS pins, the pins of the same potential are internally connected in the device
to avoid abnormal operations including latch-up. However, you must connect the pins to external power supply
and a ground line to lower the electro-magnetic emission level, to prevent abnormal operation of strobe signals
caused by the rise in the ground level, and to conform to the total output current rating.
Moreover, connect the current supply source with the VCC and VSS pins of this device at the low impedance.
It is also advisable to connect a ceramic bypass capacitor of approximately 0.1 µF between VCC and VSS pins
near this device.
13
MB95150M Series
• Mode Pin (MOD)
Connect the MOD pin directly to VCC or VSS.
To prevent the device unintentionally entering test mode due to noise, lay out the printed circuit board so as to
minimize the distance from the MOD pin to VCC or VSS pins and to provide a low-impedance connection.
Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. A bypass capacitor of VCC pin
must have a capacitance value higher than CS. For connection of smoothing capacitor CS, refer to the diagram
below.
• C pin connection diagram
C
CS
• NC Pins
Any pins marked “NC” (not connected) must be left open.
14
MB95150M Series
■ PROGRAMMING FLASH MEMORY MICROCONTROLLERS USING PARALLEL
PROGRAMMER
• Supported Parallel Programmers and Adapters
The following table lists supported parallel programmers and adapters.
Package
Applicable adapter model
FPT-48P-M26
TEF110-95F156HPFV
FPT-52P-M01
TEF110-95F156HPMC
Parallel programmers
AF9708 (Ver 02.35G or more)
AF9709/B (Ver 02.35G or more)
AF9723+AF9834 (Ver 02.08E or more)
Note : For information on applicable adapter models and parallel programmers, contact the following:
Flash Support Group, Inc. TEL: +81-53-428-8380
• Sector Configuration
The individual sectors of Flash memory correspond to addresses used for CPU access and programming by
the parallel programmer as follows:
• MB95F156M/F156N/F156J
Flash memory
CPU address
8000H
Programmer address*
18000H
FFFFH
1FFFFH
32 Kbytes
*: Programmer addresses are corresponding to CPU addresses, used when the parallel programmer
programs data into Flash memory.
These programmer addresses are used for the parallel programmer to program or erase data in
Flash memory.
• Programming Method
1) Set the type code of the parallel programmer to 17222.
2) Load program data to programmer addresses 18000H to 1FFFFH.
3) Programmed by parallel programmer.
15
MB95150M Series
■ BLOCK DIAGRAM
F2MC-8FX CPU
RST
Reset control
X0/X1
X0A/X1A
Clock control
ROM
RAM
Interrupt control
Watch prescaler
Wild register
Watch counter
P00/INT00 to P07/INT07
External interrupt
8/16-bit PPG ch.1
P11/UO0
UART/SIO
P12/UCK0
P13/TRG0/ADTG
P14/PPG0
(P00/AN00 to P07/AN07)
16-bit PPG
8/10-bit
A/D converter
Internal bus
P10/UI0
P60/SEG08/PPG10
P61/SEG09/PPG11
P62/SEG10/TO10
8/16-bit compound
timer ch.1
P63/SEG11/TO11
P64/SEG12/EC1
P65/SEG13/SCK
LIN-UART
P66/SEG14/SOT
P67/SEG15/SIN
P90/V3 to P93/V0
P94,P95
LCDC
8/16-bit PPG ch.0
PA0/COM0 to PA3/COM3
PB0/SEG00 to PB2/SEG02
PB3/SEG03/PPG00
PB4/SEG04/PPG01
PB5/SEG05/TO00
8/16-bit compound
timer ch.0
Port
Other pins
MOD, VCC, VSS, C, NC
16
Port
PB6/SEG06/TO01
PB7/SEG07/EC0
MB95150M Series
■ CPU CORE
1. Memory space
Memory space of the MB95150M series is 64 Kbytes and consists of I/O area, data area, and program area.
The memory space includes special-purpose areas such as the general-purpose registers and vector table.
Memory map of the MB95150M series is shown below.
• Memory Map
MB95156M
MB95F156M/F156N/F156J
0000H
0000H
I/O
I/O
0080H
0100H
RAM 1 Kbyte
Register
0200H
0480H
Access
prohibited
0F80H
0080H
RAM 1 Kbyte
0100H Register
0200H
0480H
1000H
I/O
0080H
RAM 3.75 Kbytes
0100H Register
0200H
0F80H
Extended I/O
Extended I/O
1000H
1000H
Access
prohibited
Access
prohibited
8000H
8000H
Flash memory
60 Kbytes
Flash memory
32 Kbytes
MASK ROM
32 Kbytes
FFFFH
0000H
Access
prohibited
0F80H
Extended I/O
MB95FV100D-103
FFFFH
FFFFH
17
MB95150M Series
2. Register
The MB95150M series has two types of registers; dedicated registers in the CPU and general-purpose registers
in the memory. The dedicated registers are as follows:
Program counter (PC)
: A 16-bit register to indicate locations where instructions are stored.
Accumulator (A)
: A 16-bit register for temporary storage of arithmetic operations. In the case of
an 8-bit data processing instruction, the lower 1 byte is used.
Temporary accumulator (T) : A 16-bit register which performs arithmetic operations with the accumulator.
In the case of an 8-bit data processing instruction, the lower 1 byte is used.
Index register (IX)
: A 16-bit register for index modification.
Extra pointer (EP)
: A 16-bit pointer to point to a memory address.
Stack pointer (SP)
: A 16-bit register to indicate a stack area.
Program status (PS)
: A 16-bit register for storing a register bank pointer, a direct bank pointer, and
a condition code register.
Initial Value
16-bit
PC
: Program counter
FFFDH
AH
AL
: Accumulator
0000H
TH
TL
: Temporary accumulator
0000H
IX
: Index register
0000H
EP
: Extra pointer
0000H
SP
: Stack pointer
0000H
PS
: Program status
0030H
The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and a direct bank pointer
(DP) and the lower 8 bits for use as a condition code register (CCR) . (Refer to the diagram below.)
• Structure of the Program Status
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9
PS
R4
R3
R2
RP
18
R1
R0
DP2
DP1
DP
bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DP0
H
I
IL1
IL0
N
Z
V
C
CCR
MB95150M Series
The RP indicates the address of the register bank currently being used. The relationship between the content
of RP and the real address conforms to the conversion rule illustrated below:
• Rule for Conversion of Actual Addresses in the General-purpose Register Area
RP upper
"0"
"0"
"0"
"0"
"0"
"0"
OP code lower
"0"
"1"
R4
R3
R2
R1
R0
b2
b1
b0
Generated address A15 A14 A13 A12 A11 A10 A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
The DP specifies the area for mapping instructions (16 different instructions such as MOV A, dir) using direct
addresses to 0080H to 00FFH.
Direct bank pointer (DP2 to DP0)
Specified address area
Mapping area
XXXB (no effect to mapping)
0000H to 007FH
0000H to 007FH (without mapping)
000B (initial value)
0080H to 00FFH (without mapping)
001B
0100H to 017FH
010B
0180H to 01FFH
011B
0080H to 00FFH
100B
0200H to 027FH
0280H to 02FFH
101B
0300H to 037FH
110B
0380H to 03FFH
111B
0400H to 047FH
The CCR consists of the bits indicating arithmetic operation results or transfer data contents and the bits that
control CPU operations at interrupt.
H flag
: Set to “1” when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation.
Cleared to “0” otherwise. This flag is for decimal adjustment instructions.
I flag
: Interrupt is enabled when this flag is set to “1”. Interrupt is disabled when this flag is set to “0”.
The flag is set to “0” when reset.
IL1, IL0 : Indicates the level of the interrupt currently enabled. Processes an interrupt only if its request level
is higher than the value indicated by these bits.
IL1
IL0
Interrupt level
Priority
0
0
0
High
0
1
1
1
0
2
1
1
3
Low (no interruption)
N flag
: Set to “1” if the MSB is set to “1” as the result of an arithmetic operation. Cleared to “0” when the
Z flag
V flag
: Set to “1” when an arithmetic operation results in “0”. Cleared to “0” otherwise.
bit is set to “0”.
C flag
: Set to “1” if the complement on 2 overflows as a result of an arithmetic operation. Cleared to “0”
otherwise.
: Set to “1” when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared
to “0” otherwise. Set to the shift-out value in the case of a shift instruction.
19
MB95150M Series
The following general-purpose registers are provided:
General-purpose registers: 8-bit data storage registers
The general-purpose registers are 8 bits and located in the register banks on the memory. 1-bank contains
8-register. Up to a total of 32 banks can be used on the MB95150M series. The bank currently in use is specified
by the register bank pointer (RP), and the lower 3 bits of OP code indicates the general-purpose register 0 (R0)
to general-purpose register 7 (R7).
• Register Bank Configuration
8-bit
1F8H
This address = 0100H + 8 × (RP)
Address 100H
R0
R0
R0
R1
R2
R3
R4
R5
107H
R6
R1
R2
R3
R4
R5
R6
R1
R2
R3
R4
R5
R6
1FFH
R7
R7
R7
Bank 0
Memory area
20
Bank 31
32 banks
32 banks (RAM area)
The number of banks is
limited by the usable RAM
capacitance.
MB95150M Series
■ I/O MAP
Address
Register
abbreviation
Register name
R/W
Initial value
0000H
PDR0
Port 0 data register
R/W
00000000B
0001H
DDR0
Port 0 direction register
R/W
00000000B
0002H
PDR1
Port 1 data register
R/W
00000000B
0003H
DDR1
Port 1 direction register
R/W
00000000B
0004H
⎯
(Disabled)
⎯
⎯
0005H
WATR
Oscillation stabilization wait time setting register
R/W
11111111B
0006H
PLLC
PLL control register
R/W
00000000B
0007H
SYCC
System clock control register
R/W
1010X011B
0008H
STBC
Standby control register
R/W
00000000B
0009H
RSRR
Reset source register
R/W
XXXXXXXXB
000AH
TBTC
Time-base timer control register
R/W
00000000B
000BH
WPCR
Watch prescaler control register
R/W
00000000B
000CH
WDTC
Watchdog timer control register
R/W
00000000B
000DH
to
0015H
⎯
(Disabled)
⎯
⎯
0016H
PDR6
Port 6 data register
R/W
00000000B
0017H
DDR6
Port 6 direction register
R/W
00000000B
0018H
to
001BH
⎯
(Disabled)
⎯
⎯
001CH
PDR9
Port 9 data register
R/W
00000000B
001DH
DDR9
Port 9 direction register
R/W
00000000B
001EH
PDRA
Port A data register
R/W
00000000B
001FH
DDRA
Port A direction register
R/W
00000000B
0020H
PDRB
Port B data register
R/W
00000000B
0021H
DDRB
Port B direction register
R/W
00000000B
0022H
to
002BH
⎯
(Disabled)
⎯
⎯
002CH
PUL0
Port 0 pull-up register
R/W
00000000B
002DH
PUL1
Port 1 pull-up register
R/W
00000000B
002EH
to
0035H
⎯
(Disabled)
⎯
⎯
(Continued)
21
MB95150M Series
Address
Register
abbreviation
Register name
R/W
Initial value
0036H
T01CR1
8/16-bit compound timer 01 control status register 1 ch.0
R/W
00000000B
0037H
T00CR1
8/16-bit compound timer 00 control status register 1 ch.0
R/W
00000000B
0038H
T11CR1
8/16-bit compound timer 11 control status register 1 ch.1
R/W
00000000B
0039H
T10CR1
8/16-bit compound timer 10 control status register 1 ch.1
R/W
00000000B
003AH
PC01
8/16-bit PPG1 control register ch.0
R/W
00000000B
003BH
PC00
8/16-bit PPG0 control register ch.0
R/W
00000000B
003CH
PC11
8/16-bit PPG1 control register ch.1
R/W
00000000B
003DH
PC10
8/16-bit PPG0 control register ch.1
R/W
00000000B
003EH
to
0041H
⎯
(Disabled)
⎯
⎯
0042H
PCNTH0
16-bit PPG status control register (upper byte) ch.0
R/W
00000000B
0043H
PCNTL0
16-bit PPG status control register (lower byte) ch.0
R/W
00000000B
0044H
to
0047H
⎯
(Disabled)
⎯
⎯
0048H
EIC00
External interrupt circuit control register ch.0/ch.1
R/W
00000000B
0049H
EIC10
External interrupt circuit control register ch.2/ch.3
R/W
00000000B
004AH
EIC20
External interrupt circuit control register ch.4/ch.5
R/W
00000000B
004BH
EIC30
External interrupt circuit control register ch.6/ch.7
R/W
00000000B
004CH
to
004FH
⎯
(Disabled)
⎯
⎯
0050H
SCR
LIN-UART serial control register
R/W
00000000B
0051H
SMR
LIN-UART serial mode register
R/W
00000000B
0052H
SSR
LIN-UART serial status register
R/W
00001000B
0053H
RDR/TDR
LIN-UART reception/transmission data register
R/W
00000000B
0054H
ESCR
LIN-UART extended status control register
R/W
00000100B
0055H
ECCR
LIN-UART extended communication control register
R/W
000000XXB
0056H
SMC10
UART/SIO serial mode control register 1 ch.0
R/W
00000000B
0057H
SMC20
UART/SIO serial mode control register 2 ch.0
R/W
00100000B
0058H
SSR0
UART/SIO serial status register ch.0
R/W
00000001B
0059H
TDR0
UART/SIO serial output data register ch.0
R/W
00000000B
005AH
RDR0
UART/SIO serial input data register ch.0
R
00000000B
005BH
to
006BH
⎯
(Disabled)
⎯
⎯
(Continued)
22
MB95150M Series
Address
Register
abbreviation
Register name
R/W
Initial value
006CH
ADC1
8/10-bit A/D converter control register 1
R/W
00000000B
006DH
ADC2
8/10-bit A/D converter control register 2
R/W
00000000B
006EH
ADDH
8/10-bit A/D converter data register (Upper byte)
R/W
00000000B
006FH
ADDL
8/10-bit A/D converter data register (Lower byte)
R/W
00000000B
0070H
WCSR
Watch counter status register
R/W
00000000B
0071H
⎯
(Disabled)
⎯
⎯
0072H
FSR
Flash memory status register
R/W
000X0000B
0073H
SWRE0
Flash memory sector writing control register 0
R/W
00000000B
0074H
SWRE1
Flash memory sector writing control register 1
R/W
00000000B
0075H
⎯
(Disabled)
⎯
⎯
0076H
WREN
Wild register address compare enable register
R/W
00000000B
0077H
WROR
Wild register data test setting register
R/W
00000000B
0078H
⎯
Register bank pointer (RP) , Mirror of direct bank pointer (P)
⎯
⎯
0079H
ILR0
Interrupt level setting register 0
R/W
11111111B
007AH
ILR1
Interrupt level setting register 1
R/W
11111111B
007BH
ILR2
Interrupt level setting register 2
R/W
11111111B
007CH
ILR3
Interrupt level setting register 3
R/W
11111111B
007DH
ILR4
Interrupt level setting register 4
R/W
11111111B
007EH
ILR5
Interrupt level setting register 5
R/W
11111111B
007FH
⎯
(Disabled)
⎯
⎯
0F80H
WRARH0
Wild register address setting register (upper byte) ch.0
R/W
00000000B
0F81H
WRARL0
Wild register address setting register (lower byte) ch.0
R/W
00000000B
0F82H
WRDR0
Wild register data setting register ch.0
R/W
00000000B
0F83H
WRARH1
Wild register address setting register (upper byte) ch.1
R/W
00000000B
0F84H
WRARL1
Wild register address setting register (lower byte) ch.1
R/W
00000000B
0F85H
WRDR1
Wild register data setting register ch.1
R/W
00000000B
0F86H
WRARH2
Wild register address setting register (upper byte) ch.2
R/W
00000000B
0F87H
WRARL2
Wild register address setting register (lower byte) ch.2
R/W
00000000B
0F88H
WRDR2
Wild register data setting register ch.2
R/W
00000000B
0F89H
to
0F91H
⎯
(Disabled)
⎯
⎯
0F92H
T01CR0
8/16-bit compound timer 01 control status register 0 ch.0
R/W
00000000B
0F93H
T00CR0
8/16-bit compound timer 00 control status register 0 ch.0
R/W
00000000B
0F94H
T01DR
8/16-bit compound timer 01 data register ch.0
R/W
00000000B
(Continued)
23
MB95150M Series
Address
Register
abbreviation
Register name
R/W
Initial value
0F95H
T00DR
8/16-bit compound timer 00 data register ch.0
R/W
00000000B
0F96H
TMCR0
8/16-bit compound timer 00/01 timer mode control register ch.0
R/W
00000000B
0F97H
T11CR0
8/16-bit compound timer 11 control status register 0 ch.1
R/W
00000000B
0F98H
T10CR0
8/16-bit compound timer 10 control status register 0 ch.1
R/W
00000000B
0F99H
T11DR
8/16-bit compound timer 11 data register ch.1
R/W
00000000B
0F9AH
T10DR
8/16-bit compound timer 10 data register ch.1
R/W
00000000B
0F9BH
TMCR1
8/16-bit compound timer 10/11 timer mode control register ch.1
R/W
00000000B
0F9CH
PPS01
8/16-bit PPG1 cycle setting buffer register ch.0
R/W
11111111B
0F9DH
PPS00
8/16-bit PPG0 cycle setting buffer register ch.0
R/W
11111111B
0F9EH
PDS01
8/16-bit PPG1 duty setting buffer register ch.0
R/W
11111111B
0F9FH
PDS00
8/16-bit PPG0 duty setting buffer register ch.0
R/W
11111111B
0FA0H
PPS11
8/16-bit PPG1 cycle setting buffer register ch.1
R/W
11111111B
0FA1H
PPS10
8/16-bit PPG0 cycle setting buffer register ch.1
R/W
11111111B
0FA2H
PDS11
8/16-bit PPG1 duty setting buffer register ch.1
R/W
11111111B
0FA3H
PDS10
8/16-bit PPG0 duty setting buffer register ch.1
R/W
11111111B
0FA4H
PPGS
8/16-bit PPG start register
R/W
00000000B
0FA5H
REVC
8/16-bit PPG output inversion register
R/W
00000000B
0FA6H
to
0FA9H
⎯
(Disabled)
⎯
⎯
0FAAH
PDCRH0
16-bit PPG down counter register (upper byte) ch.0
R
00000000B
0FABH
PDCRL0
16-bit PPG down counter register (lower byte) ch.0
R
00000000B
0FACH
PCSRH0
16-bit PPG cycle setting buffer register (upper byte) ch.0
R/W
11111111B
0FADH
PCSRL0
16-bit PPG cycle setting buffer register (lower byte) ch.0
R/W
11111111B
0FAEH
PDUTH0
16-bit PPG duty setting buffer register (upper byte) ch.0
R/W
11111111B
0FAFH
PDUTL0
16-bit PPG duty setting buffer register (lower byte) ch.0
R/W
11111111B
0FB0H
to
0FBBH
⎯
(Disabled)
⎯
⎯
0FBCH
BGR1
LIN-UART baud rate generator register 1
R/W
00000000B
0FBDH
BGR0
LIN-UART baud rate generator register 0
R/W
00000000B
0FBEH
PSSR0
UART/SIO dedicated baud rate generator
prescaler selection register ch.0
R/W
00000000B
0FBFH
BRSR0
UART/SIO dedicated baud rate generator
baud rate setting register ch.0
R/W
00000000B
0FC0H
to
0FC2H
⎯
(Disabled)
⎯
⎯
(Continued)
24
MB95150M Series
(Continued)
Address
Register
abbreviation
Register name
R/W
Initial value
0FC3H
AIDRL
A/D input disable register (lower byte)
R/W
00000000B
0FC4H
LCDCC
LCDC control register
R/W
00010000B
0FC5H
LCDCE1
LCDC enable register 1
R/W
00110000B
0FC6H
LCDCE2
LCDC enable register 2
R/W
00000000B
0FC7H
LCDCE3
LCDC enable register 3
R/W
00000000B
0FC8H
to
0FCAH
⎯
(Disabled)
⎯
⎯
0FCBH
LCDCB1
LCDC blinking setting register 1
R/W
00000000B
0FCCH
LCDCB2
LCDC blinking setting register 2
R/W
00000000B
0FCDH
to
0FD4H
LCDRAM
LCDC display RAM
R/W
00000000B
0FD5H
to
0FE2H
⎯
(Disabled)
⎯
⎯
0FE3H
WCDR
Watch counter data register
R/W
00111111B
0FE4H
to
0FE6H
⎯
(Disabled)
⎯
⎯
0FE7H
ILSR2
Input level select register 2
R/W
00000000B
0FE8H,
0FE9H
⎯
(Disabled)
⎯
⎯
0FEAH
CSVCR
Clock supervisor control register
R/W
00011100B
0FEBH
to
0FEDH
⎯
(Disabled)
⎯
⎯
0FEEH
ILSR
Input level select register
R/W
00000000B
0FEFH
WICR
Interrupt pin control register
R/W
01000000B
0FF0H
to
0FFFH
⎯
(Disabled)
⎯
⎯
• R/W access symbols
R/W : Readable/Writable
R
: Read only
W
: Write only
• Initial value symbols
0 : The initial value of this bit is “0”.
1 : The initial value of this bit is “1”.
X : The initial value of this bit is undefined.
25
MB95150M Series
■ INTERRUPT SOURCE TABLE
Interrupt source
Vector table address
Same level
Bit name of
priority order
interrupt level
(at simultaneous
setting register
occurrence)
Upper
Lower
IRQ0
FFFAH
FFFBH
L00 [1 : 0]
IRQ1
FFF8H
FFF9H
L01 [1 : 0]
IRQ2
FFF6H
FFF7H
L02 [1 : 0]
IRQ3
FFF4H
FFF5H
L03 [1 : 0]
UART/SIO ch.0
IRQ4
FFF2H
FFF3H
L04 [1 : 0]
8/16-bit compound timer ch.0 (Lower)
IRQ5
FFF0H
FFF1H
L05 [1 : 0]
8/16-bit compound timer ch.0 (Upper)
IRQ6
FFEEH
FFEFH
L06 [1 : 0]
LIN-UART (reception)
IRQ7
FFECH
FFEDH
L07 [1 : 0]
LIN-UART (transmission)
IRQ8
FFEAH
FFEBH
L08 [1 : 0]
8/16-bit PPG ch.1 (Lower)
IRQ9
FFE8H
FFE9H
L09 [1 : 0]
8/16-bit PPG ch.1 (Upper)
IRQ10
FFE6H
FFE7H
L10 [1 : 0]
(Unused)
IRQ11
FFE4H
FFE5H
L11 [1 : 0]
8/16-bit PPG ch.0 (Upper)
IRQ12
FFE2H
FFE3H
L12 [1 : 0]
8/16-bit PPG ch.0 (Lower)
IRQ13
FFE0H
FFE1H
L13 [1 : 0]
8/16-bit compound timer ch.1 (Upper)
IRQ14
FFDEH
FFDFH
L14 [1 : 0]
16-bit PPG ch.0
IRQ15
FFDCH
FFDDH
L15 [1 : 0]
(Unused)
IRQ16
FFDAH
FFDBH
L16 [1 : 0]
(Unused)
IRQ17
FFD8H
FFD9H
L17 [1 : 0]
8/10-bit A/D converter
IRQ18
FFD6H
FFD7H
L18 [1 : 0]
Time-base timer
IRQ19
FFD4H
FFD5H
L19 [1 : 0]
Watch prescaler/Watch counter
IRQ20
FFD2H
FFD3H
L20 [1 : 0]
(Unused)
IRQ21
FFD0H
FFD1H
L21 [1 : 0]
8/16-bit compound timer ch.1 (Lower)
IRQ22
FFCEH
FFCFH
L22 [1 : 0]
Flash memory
IRQ23
FFCCH
FFCDH
L23 [1 : 0]
External interrupt ch.0
External interrupt ch.4
External interrupt ch.1
External interrupt ch.5
External interrupt ch.2
External interrupt ch.6
External interrupt ch.3
External interrupt ch.7
26
Interrupt
request
number
High
Low
MB95150M Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Parameter
Symbol
Power supply voltage*1
Power supply voltage
for LCD
Input voltage*1
Output voltage*
1
Maximum clamp current
Total maximum clamp
current
“L” level maximum
output current
Rating
Unit
Remarks
Min
Max
Vcc
Vss − 0.3
Vss + 6.0
V
V0 to V3
Vss − 0.3
Vss + 6.0
V
*2
VI
Vss − 0.3
Vss + 6.0
V
*3
VO
Vss − 0.3
Vss + 6.0
V
*3
ICLAMP
− 2.0
+ 2.0
mA
Applicable to pins*4
Σ|ICLAMP|
⎯
20
mA
Applicable to pins*4
IOL
⎯
15
mA
Applicable to pins*4
Applicable to pins*4
Average output current =
operating current × operating ratio
(1 pin)
“L” level average
current
IOLAV
⎯
4
mA
“L” level total maximum
output current
ΣIOL
⎯
100
mA
ΣIOLAV
⎯
50
mA
Total average output current =
operating current × operating ratio
(Total of pins)
IOH
⎯
− 15
mA
Applicable to pins*4
Applicable to pins*4
Average output current =
operating current × operating ratio
(1 pin)
“L” level total average
output current
“H” level maximum
output current
“H” level average
current
IOHAV
⎯
−4
mA
“H” level total maximum
output current
ΣIOH
⎯
− 100
mA
ΣIOHAV
⎯
− 50
mA
Power consumption
Pd
⎯
320
mW
Operating temperature
TA
− 40
+ 85
°C
Tstg
− 55
+ 150
°C
“H” level total average
output current
Storage temperature
Total average output current =
operating current × operating ratio
(Total of pins)
(Continued)
27
MB95150M Series
(Continued)
*1 : The parameter is based on VSS = 0.0 V.
*2 : V0 to V3 should not exceed VCC + 0.3 V.
*3 : VI and Vo should not exceed VCC + 0.3 V. VI must not exceed the rating voltage. However, if the maximum current
to/from an input is limited by some means with external components, the ICLAMP rating supersedes the VI rating.
*4 : Applicable to pins : P00 to P07, P10 to P14, P60 to P67, P90 to P95, PA0 to PA3, PB0 to PB7
• Use within recommended operating conditions.
• Use at DC voltage (current).
• +B signal is an input signal that exceeds VCC voltage. The + B signal should always be applied a limiting
resistance placed between the + B signal and the microcontroller.
• The value of the limiting resistance should be set so that when the + B signal is applied the input current
to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.
• Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input
potential may pass through the protective diode and increase the potential at the VCC pin, and this affects
other devices.
• Note that if the + B signal is inputted when the microcontroller power supply is off (not fixed at 0 V), the power
supply is provided from the pins, so that incomplete operation may result.
• Note that if the + B input is applied during power-on, the power supply is provided from the pins and the
resulting power supply voltage may not be sufficient to operate the power-on reset.
• Care must be taken not to leave the + B input pin open.
• Note that analog system input/output pins other than the A/D input pins (LCD drive pins, etc.) cannot accept
+ B signal input.
• Sample recommended circuits :
• Input/Output Equivalent circuits
Protective diode
+ B input (0 V to 16 V)
Vcc
Limiting
resistance
P-ch
N-ch
R
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
28
MB95150M Series
2. Recommended Operating Conditions
(Vss = 0.0 V)
Parameter
Symbol Conditions
Value
Unit
Remarks
Min
Max
2.4*1,*2
5.5*1
2.3
5.5
2.7
5.5
2.3
5.5
V0 to V3
VSS
VCC
V
The range of liquid crystal
power supply (The optimal value depends
on liquid crystal display elements used.)
Smoothing
capacitor
CS
0.1
1.0
µF
*3
Operating
temperature
TA
−40
+85
°C Other than MB95FV100D-103
+5
+35
°C MB95FV100D-103
Power supply
voltage
Power supply
voltage for LCD
VCC
In normal operating
V
Hold condition in
STOP mode
In normal operating
Hold condition in
STOP mode
⎯
Other than
MB95FV100D-103
MB95FV100D-103
*1 : The values vary with the operating frequency, machine clock or analog guarantee range.
*2 : The value is 2.88 V when the low voltage detection reset is used.
*3 : Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. A bypass capacitor of VCC
pin must have a capacitance value higher than CS. For connection of smoothing capacitor CS, refer to the
diagram below.
29
MB95150M Series
• C pin connection diagram
C
CS
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
30
MB95150M Series
3. DC Characteristics
(Vcc = 5.0 V ± 10%, Vss = 0.0 V, TA = − 40 °C to + 85 °C)
Parameter
Symbol
Pin name
Conditions
Value
Min
Typ
Max
Unit
Remarks
P10, P67
*1
0.7 VCC
⎯
VCC +
0.3
V
When selecting CMOS
input level
P00 to P07,
P10 to P14,
P60 to P67,
P90 to P95,
PA0 to PA3,
PB0 to PB7
⎯
0.8 Vcc
⎯
Vcc +
0.3
V
Pin input at selecting of
automotive input level
*1
0.8 VCC
⎯
VCC +
0.3
V
Hysteresis input
⎯
0.8 VCC
⎯
VCC +
0.3
V
Hysteresis input
P10, P67
*1
VSS −
0.3
⎯
0.3 VCC
V
When selecting CMOS
input level
(Hysteresis input)
P00 to P07,
P10 to P14,
P60 to P67,
P90 to P95,
PA0 to PA3,
PB0 to PB7
⎯
VSS −
0.3
⎯
0.5 Vcc
V
Pin input at selecting of
automotive input level
*1
VSS −
0.3
⎯
0.2 VCC
V
Hysteresis input
VILM
RST, MOD
⎯
VSS −
0.3
⎯
0.2 VCC
V
Hysteresis input
“H” level output
voltage
VOH
All output pins IOH = −4.0 mA
VCC−0.5
⎯
⎯
V
“L”level output
voltage
VOL
All output pins,
IOL = 4.0 mA
RST*2
⎯
⎯
0.4
V
ILI
Port other than
0.0 V < VI <
P00 to P07,
Vcc
P10 to P14
−5
⎯
+5
When specifying
µA without pull-up
resistance
P00 to P07,
P10 to P14
VI = 0.0 V
25
50
100
kΩ
When specifying with
pull-up resistance
V1 = VCC
50
100
200
kΩ
MASK ROM product
only
VIH1
VIHA
“H” level input
voltage
VIHS1
VIHM RST, MOD
VIL
VILA
“L” level input
voltage
VILS
Input leak
current
(Hi-Z output
leak current)
Pull-up
resistance
RPULL
Pull-down
resistance
RMOD MOD
(Continued)
31
MB95150M Series
(Vcc = 5.0 V ± 10%, Vss = 0.0 V, TA = − 40 °C to + 85 °C)
Parameter
Symbol
Pin name
Conditions
VCC = 5.5 V,
FCH = 20 MHz,
FMP = 10 MHz
Main clock mode
(divided by 2)
Value
Min
Typ
Max
ICCL
Flash memory product
(at other than Flash
mA
memory writing and
erasing)
9.5
12.5
⎯
30
35
mA
Flash memory product
(at Flash memory
writing and erasing)
⎯
11.9
17.2
mA
Flash memory product
(When A/D conversion)
⎯
7.2
9.5
mA MASK ROM product
⎯
9.6
14.2
mA
MASK ROM product
(When A/D conversion)
⎯
15.2
20.0
Flash memory product
(at other than Flash
mA
memory writing and
erasing)
⎯
35.7
42.5
mA
Flash memory product
(at Flash memory
writing and erasing)
⎯
19.0
27.5
mA
Flash memory product
(When A/D conversion)
⎯
11.6
15.2
mA MASK ROM product
⎯
15.4
22.7
mA
VCC = 5.5 V,
FCH = 20 MHz,
FMP = 10 MHz
Main sleep mode
(divided by 2)
⎯
4.5
7.5
mA
VCC = 5.5 V,
FCH = 32 MHz,
FMP = 16 MHz
Main sleep mode
(divided by 2)
⎯
7.2
12.0
mA
VCC = 5.5 V,
FCL = 32 kHz,
FMPL = 16 kHz
Sub clock mode
(divided by 2) ,
TA = + 25 °C
⎯
45
100
µA
VCC = 5.5 V,
FCH = 32 MHz,
FMP = 16 MHz,
Vcc
Main clock mode
(External clock
(divided by 2)
operation)
ICCS
Remarks
⎯
ICC
Power supply
current*3
Unit
MASK ROM product
(When A/D conversion)
(Continued)
32
MB95150M Series
(Vcc = 5.0 V ± 10%, Vss = 0.0 V, TA = − 40 °C to + 85 °C)
Parameter
Symbol
Conditions
Value
Unit Remarks
Min
Typ
Max
ICCLS
VCC = 5.5 V,
FCL = 32 kHz,
FMPL = 16 kHz
Sub sleep mode
(divided by 2) ,
TA = + 25 °C
⎯
10
81
µA
ICCT
VCC = 5.5 V,
FCL = 32 kHz
Watch mode,
Main stop mode
TA = + 25 °C
⎯
4.6
27.0
µA
VCC = 5.5 V,
FCH = 4 MHz,
FMP = 10 MHz
Main PLL mode
(multiplied by 2.5)
⎯
9.3
12.5
Flash
mA memory
product
⎯
7.0
9.5
MASK
mA ROM
product
VCC = 5.5 V,
FCH = 6.4 MHz,
FMP = 16 MHz
Main PLL mode
(multiplied by 2.5)
⎯
14.9
20.0
Flash
mA memory
product
⎯
11.2
15.2
MASK
mA ROM
product
ICCSPLL
VCC = 5.5 V,
FCL = 32 kHz,
FMPL = 128 kHz
Sub PLL mode
(multiplied by 4)
TA = + 25 °C
⎯
160
400
µA
ICTS
VCC = 5.5 V,
FCH = 10 MHz
Time-base timer
mode
TA = + 25 °C
⎯
0.40
1.10
mA
ICCH
VCC = 5.5 V,
Sub stop mode
TA = + 25 °C
⎯
3.5
20
µA
Between V3 and
VSS
⎯
300
⎯
kΩ
⎯
⎯
5
kΩ
⎯
⎯
7
kΩ
ICCMPLL
Power supply
current*3
LCD division
resistance
Pin name
RLCD
Vcc
(External clock
operation)
⎯
COM0 to COM3
RVCOM COM0 to COM3
output impedance
SEG00 to SEG15
RVSEG SEG00 to SEG15
output impedance
V1 to V3 = 5.0V
(Continued)
33
MB95150M Series
(Continued)
(Vcc = 5.0 V ± 10%, Vss = 0.0 V, TA = − 40 °C to + 85 °C)
Parameter
Symbol
Pin name
Conditions
LCD leak current
ILCDL
V0 to V3
COM0 to COM3
SEG00 to SEG15
Input capacitance
CIN
Other than Vcc,
Vss
Value
Unit Remarks
Min
Typ
Max
⎯
−1
⎯
+1
µA
f = 1 MHz
⎯
5
15
pF
*1 : P10 and P67 can switch the input level to either the “CMOS input level” or “hysteresis input level”.
The switching of the input level can be set by the input level selection register (ILSR) .
*2 : Product without clock supervisor only
*3 : • The power-supply current is determined by the external clock. When both low voltage detection option
and clock supervisor are selected, the power-supply current will be a value of adding current consumption
of the low voltage detection circuit (ILVD) and current consumption of built-in CR oscillator (ICSV) to the specified
value.
• Refer to “4. AC Characteristics (1) Clock Timing” for FCH and FCL.
• Refer to “4. AC Characteristics (2) Source Clock/Machine Clock” for FMP and FMPL.
34
MB95150M Series
4. AC Characteristics
(1) Clock Timing
(Vcc = 2.4 V to 5.5 V, Vss = 0.0 V, TA = − 40 °C to + 85 °C)
Parameter
SymCondiPin name
bol
tions
FCH
X0, X1
Clock frequency
FCL
X0A, X1A
⎯
Clock cycle time
Input clock pulse width
Input clock rise time and
fall time
tHCYL
X0, X1
Value
Unit
Remarks
16.25
MHz
When using main
oscillation circuit
⎯
32.50
MHz When using external clock
3.00
⎯
10.00
MHz Main PLL multiplied by 1
3.00
⎯
8.13
MHz Main PLL multiplied by 2
3.00
⎯
6.50
MHz Main PLL multiplied by 2.5
3.00
⎯
4.06
MHz Main PLL multiplied by 4
⎯
32.768
⎯
kHz
When using sub
oscillation circuit
⎯
32.768
⎯
kHz
When using sub PLL
61.5
⎯
1000
ns
When using oscillation
circuit
30.8
⎯
1000
ns
When using external clock
Min
Typ
Max
1.00
⎯
1.00
tLCYL
X0A, X1A
⎯
30.5
⎯
µs
When using sub clock
tWH1
tWL1
X0
61.5
⎯
⎯
ns
tWH2
tWL2
X0A
⎯
15.2
⎯
µs
When using external clock
Duty ratio is about 30% to
70%.
tCR
tCF
X0, X0A
⎯
⎯
5
ns
When using external clock
35
MB95150M Series
• Input wave form for using external clock (main clock)
tHCYL
tWH1
tWL1
tCR
tCF
0.8 VCC 0.8 VCC
X0
0.2 VCC
0.2 VCC
0.2 VCC
• Figure of main clock input port external connection
When using a crystal or
ceramic oscillator
When using external clock
Microcontroller
Microcontroller
X0
X1
X0
X1
Open
FCH
FCH
C1
C2
• Input wave form for using external clock (sub clock)
tLCYL
tWH2
tCR
tWL2
tCF
0.8 VCC 0.8 VCC
X0A
0.2 VCC
0.2 VCC
0.2 VCC
• Figure of sub clock input port external connection
When using a crystal or
ceramic oscillator
Microcontroller
X0A
X1A
When using external clock
Microcontroller
X0A
FCL
X1A
Open
FCL
C1
36
C2
MB95150M Series
(2) Source Clock/Machine Clock
(Vcc = 5.0 V ± 10%, Vss = 0.0 V, TA = − 40 °C to + 85 °C)
Parameter
Source clock
cycle time*1
(Clock before
setting division)
Source clock
frequency
Machine clock
cycle time*2
(Minimum
instruction
execution time)
Machine clock
frequency
Sym- Pin Condibol name tions
tSCLK
⎯
FSPL
⎯
FMP
FMPL
⎯
Remarks
Typ
Max
61.5
⎯
2000
When using main clock
ns Min : FCH = 8.125 MHz, PLL multiplied by 2
Max : FCH = 1 MHz, divided by 2
7.6
⎯
61.0
When using sub clock
µs Min : FCL = 32 kHz, PLL multiplied by 4
Max : FCL = 32 kHz, divided by 2
0.50
⎯
16.25
MHz When using main clock
16.384 ⎯ 131.072 kHz When using sub clock
When using main clock
ns Min : FSP = 16.25 MHz, no division
Max : FSP = 0.5 MHz, divided by 16
When using sub clock
976.5
µs Min : FSPL = 131 kHz, no division
Max : FSPL = 16 kHz, divided by 16
16.250 MHz When using main clock
61.5
⎯
7.6
⎯
0.031
⎯
1.024
⎯ 131.072 kHz When using sub clock
⎯
⎯
Unit
Min
⎯
FSP
tMCLK
Value
32000
*1 : Clock before setting division due to machine clock division ratio selection bit (SYCC : DIV1 and DIV0) . This
source clock is divided by the machine clock division ratio selection bit (SYCC : DIV1 and DIV0) , and it
becomes the machine clock. Further, the source clock can be selected as follows.
• Main clock divided by 2
• PLL multiplication of main clock (select from 1, 2, 2.5, 4 multiplication)
• Sub clock divided by 2
• PLL multiplication of sub clock (select from 2, 3, 4 multiplication)
*2 : Operation clock of the microcontroller. Machine clock can be selected as follows.
• Source clock (no division)
• Source clock divided by 4
• Source clock divided by 8
• Source clock divided by 16
• Outline of clock generation block
FCH
(main oscillation)
Divided by 2
Main PLL
×1
×2
× 2.5
×4
SCLK
( source clock )
FCL
(sub oscillation)
Divided by 2
Sub PLL
×2
×3
×4
Division
circuit
×1
× 1/4
× 1/8
× 1/16
MCLK
( machine clock )
Clock mode select bit
( SYCC : SCS1, SCS0 )
37
MB95150M Series
• Operating voltage - Operating frequency (When TA = − 40 °C to + 85 °C)
• MB95156M/F156M/F156N/F156J
Main clock mode and main PLL mode
operation guarantee range
Sub PLL, sub clock mode and
watch mode operation guarantee range
5.5
2.4
16.384 kHz
32 kHz
131.072 kHz
Operating voltage (V)
Operating voltage (V)
5.5
3.5
2.4
0.5 MHz 3 MHz
10 MHz
16.25 MHz
PLL operation guarantee range
Main clock operation guarantee range
PLL operation guarantee range
Source clock frequency (FSPL)
Source clock frequency (FSP)
• Operating voltage - Operating frequency (When TA = + 5 °C to + 35 °C)
• MB95FV100D-103
Main clock mode and main PLL mode
operation guarantee range
Sub PLL, sub clock mode and
watch mode operation guarantee range
5.5
2.7
16.384 kHz
32 kHz
131.072 kHz
PLL operation guarantee range
Source clock frequency (FSPL)
38
Operating voltage (V)
Operating voltage (V)
5.5
3.5
2.7
0.5MHz 3 MHz
10 MHz
16.25 MHz
PLL operation guarantee range
Main clock operation guarantee range
Source clock frequency (FSP)
MB95150M Series
• Main PLL operation frequency
[MHz]
16.25
16
15
×4
12
Source clock frequency (FSP)
× 2.5
10
×1
×2
7.5
6
5
3
0
3
4
4.062
5
6.4
6.5
8
8.125
10 [MHz]
Main clock frequency (FMP)
39
MB95150M Series
(3) External Reset
(Vcc = 5.0 V ± 10%, Vss = 0.0 V, TA = − 40 °C to + 85 °C)
Parameter
Symbol
RST “L” level
pulse width
tRSTL
Pin
name
Value
Conditions
RST
⎯
Min
Max
2 tMCLK*1
⎯
Unit
Remarks
ns
At normal
operating
Oscillation time of oscillator*2
+ 100
⎯
µs
At stop mode,
sub clock mode,
sub sleep mode,
and watch mode
100
⎯
µs
At time-base
timer mode
*1 : Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
*2 : Oscillation time of oscillator is the time that the amplitude reaches 90 %. In the crystal oscillator, the oscillation
time is between several ms and tens of ms. In ceramic oscillators, the oscillation time is between hundreds of
µs and several ms. In the external clock, the oscillation time is 0 ms.
• At normal operating
tRSTL
RST
0.2 VCC
0.2 VCC
• At stop mode, sub clock mode, sub sleep mode, watch mode, and power-on
RST
tRSTL
0.2 VCC
0.2 VCC
90% of
amplitude
X0
Internal
operating
clock
100 µs
Oscillation time Oscillation stabilization wait time
of oscillator
Execute instruction
Internal reset
40
MB95150M Series
(4) Power-on Reset
(Vss = 0.0 V, TA = − 40 °C to + 85 °C)
Parameter
Symbol
Power supply rising
time
tR
Power supply cutoff
time
tOFF
Pin
name
VCC
tR
Conditions
Value
Unit
Min
Max
⎯
50
ms
1
⎯
ms
⎯
Remarks
Waiting time until
power-on
tOFF
2.5 V
VCC
0.2 V
0.2 V
0.2 V
Note : Sudden change of power supply voltage may activate the power-on reset function. When changing power
supply voltages during operation, set the slope of rising within 30 mV/ms as shown below.
VCC
Limiting the slope of rising within
30 mV/ms is recommended.
2.3 V
Hold condition in stop mode
VSS
41
MB95150M Series
(5) Peripheral Input Timing
(Vcc = 5.0 V ± 10%, Vss = 0.0 V, TA = − 40 °C to + 85 °C)
Parameter
Symbol
Pin name
Conditions
Peripheral input “H” pulse width
tILIH
Peripheral input “L” pulse width
tIHIL
INT00 to INT07,
EC0, EC1, TRG0/ADTG
⎯
Value
Max
2 tMCLK*
⎯
ns
2 tMCLK*
⎯
ns
* : Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
tILIH
INT00 to INT07,
EC0, EC1,
TRG0/ADTG
42
tIHIL
0.8 VCC 0.8 VCC
0.2 VCC
Unit
Min
0.2 VCC
MB95150M Series
(6) UART/SIO, Serial I/O Timing
(Vcc = 5.0 V ± 10%, Vss = 0.0 V, TA = − 40 °C to + 85 °C)
Parameter
Symbol
Pin name
Conditions
Serial clock cycle time
tSCYC
UCK0
UCK ↓ → UO time
tSLOV
UCK0, UO0
Valid UI → UCK ↑
tIVSH
UCK0, UI0
UCK ↑ → valid UI hold time
tSHIX
UCK0, UI0
Internal
clock
operation
Output pin : CL = 80 pF
+ 1TTL.
Serial clock “H” pulse width
tSHSL
UCK0
Serial clock “L” pulse width
tSLSH
UCK0
UCK ↓ → UO time
tSLOV
UCK0, UO0
Valid UI → UCK ↑
tIVSH
UCK0, UI0
UCK ↑ → valid UI hold time
tSHIX
UCK0, UI0
External
clock
operation
Output pin : CL = 80 pF
+ 1TTL.
Value
Unit
Min
Max
4 tMCLK*
⎯
ns
− 190
+ 190
ns
2 tMCLK*
⎯
ns
2 tMCLK*
⎯
ns
4 tMCLK*
⎯
ns
4 tMCLK*
⎯
ns
⎯
190
ns
2 tMCLK*
⎯
ns
2 tMCLK*
⎯
ns
* : Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
• Internal shift clock mode
tSCYC
UCK0
2.4 V
0.8 V
0.8 V
tSLOV
UO0
2.4 V
0.8 V
tIVSH
UI0
tSHIX
0.8 VCC 0.8 VCC
0.2 VCC 0.2 VCC
• External shift clock mode
tSLSH
tSHSL
0.8 VCC 0.8 VCC
UCK0
0.2 VCC 0.2 VCC
tSLOV
UO0
UI0
2.4 V
0.8 V
tIVSH
tSHIX
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
43
MB95150M Series
(7) LIN-UART Timing
Sampling at the rising edge of sampling clock*1 and prohibited serial clock delay*2
(ESCR register : SCES bit = 0, ECCR register : SCDE bit = 0)
(Vcc = 5.0 V ± 10%, Vss = 0.0 V, TA = −40 °C to + 85 °C)
Parameter
Serial clock cycle time
SymPin name
bol
tSCYC
SCK ↓ → SOT delay time
tSLOVI
Valid SIN → SCK ↑
tIVSHI
SCK ↑ → valid SIN hold time
tSHIXI
Serial clock “L” pulse width
tSLSH
Serial clock “H” pulse width
tSHSL
Value
Conditions
Max
5 tMCLK*3
⎯
ns
+ 95
ns
⎯
ns
⎯
ns
3 tMCLK*3 − tR
⎯
ns
* + 95
⎯
ns
SCK
Internal clock
SCK, SOT
−95
operation output pin :
SCK, SIN CL = 80 pF + 1 TTL. tMCLK*3 + 190
SCK, SIN
0
SCK
SCK
Unit
Min
t
MCLK 3
SCK ↓ → SOT delay time
tSLOVE SCK, SOT
Valid SIN → SCK ↑
tIVSHE
SCK, SIN
SCK ↑ → valid SIN hold time
tSHIXE
SCK, SIN
SCK fall time
tF
SCK
⎯
10
ns
SCK rise time
tR
SCK
⎯
10
ns
External clock
operation output pin :
CL = 80 pF + 1 TTL.
⎯
* + 95
MCLK 3
ns
190
⎯
ns
tMCLK*3 + 95
⎯
ns
2t
*1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the
serial clock.
*2 : Serial clock delay function is used to delay half clock for the output signal of serial clock.
*3 : Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
44
MB95150M Series
• Internal shift clock mode
tSCYC
2.4 V
SCK
0.8 V
0.8 V
tSLOVI
2.4 V
SOT
0.8 V
tIVSHI
tSHIXI
0.8 VCC 0.8 VCC
SIN
0.2 VCC 0.2 VCC
• External shift clock mode
tSHSL
tSLSH
SCK
0.8 VCC
0.2 VCC
tF
SOT
0.8 VCC
0.2 VCC
tR
tSLOVE
2.4 V
0.8 V
tIVSHE
SIN
tSHIXE
0.8 VCC 0.8 VCC
0.2 VCC 0.2 VCC
45
MB95150M Series
Sampling at the falling edge of sampling clock*1 and prohibited serial clock delay*2
(ESCR register : SCES bit = 1, ECCR register : SCDE bit = 0)
(VCC = 5.0 V ± 10%, VSS = 0.0 V, TA = −40 °C to + 85 °C)
Symbol
Pin name
Serial clock cycle time
tSCYC
SCK
SCK↑→ SOT delay time
tSHOVI
SCK, SOT
Parameter
Value
Conditions
Internal clock
operation output pin :
SCK, SIN CL = 80 pF + 1 TTL.
SCK, SIN
t
Unit
Min
Max
5 tMCLK*3
⎯
ns
−95
+ 95
ns
⎯
ns
0
⎯
ns
* + 190
MCLK 3
Valid SIN→SCK↓
tIVSLI
SCK↓→ valid SIN hold time
tSLIXI
Serial clock “H” pulse width
tSHSL
SCK
3 tMCLK*3 − tR
⎯
ns
Serial clock “L” pulse width
tSLSH
SCK
tMCLK*3 + 95
⎯
ns
SCK, SOT
⎯
SCK↑ →SOT delay time
tSHOVE
Valid SIN→SCK↓
tIVSLE
SCK↓→ valid SIN hold time
tSLIXE
External clock
SCK, SIN operation output pin :
SCK, SIN CL = 80 pF + 1 TTL.
* + 95
MCLK 3
ns
190
⎯
ns
tMCLK*3 + 95
⎯
ns
2t
SCK fall time
tF
SCK
⎯
10
ns
SCK rise time
tR
SCK
⎯
10
ns
*1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of
the serial clock.
*2 : Serial clock delay function is used to delay half clock for the output signal of serial clock.
*3 : Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
46
MB95150M Series
• Internal shift clock mode
tSCYC
2.4 V
SCK
2.4 V
0.8 V
tSHOVI
2.4 V
SOT
0.8 V
tIVSLI
tSLIXI
0.8 VCC 0.8 VCC
SIN
0.2 VCC 0.2 VCC
• External shift clock mode
tSHSL
SCK
0.8 VCC
tSLSH
0.8 VCC
0.2 VCC
tR
SOT
0.2 VCC
0.2 VCC
tF
tSHOVE
2.4 V
0.8 V
tIVSLE
SIN
tSLIXE
0.8 VCC 0.8 VCC
0.2 VCC 0.2 VCC
47
MB95150M Series
Sampling at the rising edge of sampling clock*1 and enabled serial clock delay*2
(ESCR register : SCES bit = 0, ECCR register : SCDE bit = 1)
(VCC = 5.0 V ± 10%, VSS = 0.0 V, TA = −40 °C to + 85 °C)
Symbol
Pin name
Serial clock cycle time
tSCYC
SCK
SCK↑→ SOT delay time
tSHOVI
SCK, SOT
Parameter
Value
Conditions
Valid SIN→SCK↓
tIVSLI
SCK, SIN
SCK↓→ valid SIN hold time
tSLIXI
SCK, SIN
SOT→SCK↓ delay time
tSOVLI
SCK, SOT
Internal clock
operation output pin :
CL = 80 pF + 1 TTL.
Unit
Min
Max
5 tMCLK*3
⎯
ns
−95
+ 95
ns
⎯
ns
0
⎯
ns
⎯
4 tMCLK*3
ns
* + 190
MCLK 3
t
*1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of
the serial clock.
*2 : Serial clock delay function is used to delay half clock for the output signal of serial clock.
*3 : Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
tSCYC
2.4 V
SCK
0.8 V
SOT
2.4 V
0.8 V
2.4 V
0.8 V
tIVSLI
SIN
48
0.8 V
tSHOVI
tSOVLI
0.8 VCC
0.2 VCC
tSLIXI
0.8 VCC
0.2 VCC
MB95150M Series
Sampling at the falling edge of sampling clock*1 and enabled serial clock delay*2
(ESCR register : SCES bit = 1, ECCR register : SCDE bit = 1)
(VCC = 5.0 V ± 10%, VSS = 0.0 V, TA = −40 °C to + 85 °C)
Symbol
Pin name
Serial clock cycle time
tSCYC
SCK↓→SOT delay time
tSLOVI
Parameter
Value
Conditions
Unit
Min
Max
SCK
5 tMCLK*3
⎯
ns
SCK, SOT
−95
+ 95
ns
⎯
ns
0
⎯
ns
⎯
4 tMCLK*3
ns
Valid SIN→SCK↑
tIVSHI
SCK↑ → valid SIN hold time
tSHIXI
Internal clock
SCK, SIN operation output pin :
CL = 80 pF + 1 TTL.
SCK, SIN
SOT→SCK↑ delay time
tSOVHI
SCK, SOT
t
* + 190
MCLK 3
*1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the
serial clock.
*2 : Serial clock delay function is used to delay half clock for the output signal of serial clock.
*3 : Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
tSCYC
2.4 V
SCK
2.4 V
0.8 V
tSOVHI
SOT
2.4 V
0.8 V
2.4 V
0.8 V
tIVSHI
SIN
tSLOVI
0.8 VCC
0.2 VCC
tSHIXI
0.8 VCC
0.2 VCC
49
MB95150M Series
(8) Low Voltage Detection
(Vss = 0.0 V, TA = −40 °C to + 85 °C)
Parameter
Symbol
Conditions
Value
Min
Typ
Max
Unit
Remarks
Release voltage
VDL+
2.52
2.70
2.88
V
At power-supply rise
Detection voltage
VDL-
2.42
2.60
2.78
V
At power-supply fall
Hysteresis width
VHYS
70
100
⎯
mV
Power-supply start voltage
Voff
⎯
⎯
2.3
V
Power-supply end voltage
Von
4.9
⎯
⎯
V
0.3
⎯
⎯
µs
Slope of power supply that reset
release signal generates
⎯
3000
⎯
µs
Slope of power supply that reset
release signal generates within
rating (VDL+)
300
⎯
⎯
µs
Slope of power supply that reset
detection signal generates
⎯
300
⎯
µs
Slope of power supply that reset
detection signal generates within
rating (VDL-)
Power-supply voltage
change time
(at power supply rise)
tr
⎯
Power-supply voltage
change time
(at power supply fall)
tf
Reset release delay time
td1
⎯
⎯
400
µs
Reset detection delay time
td2
⎯
⎯
30
µs
Current consumption
ILVD
⎯
38
50
µA
Current consumption of low
voltage detection circuit only
VCC
Von
Voff
VDL+
time
tr
tf
VHYS
VDL-
Internal reset signal
time
td2
50
td1
MB95150M Series
(9) Clock Supervisor Clock
(Vcc = 5.0 V ± 10%, Vss = 0.0 V, TA = −40 °C to + 85 °C)
Parameter
Symbol
Oscillation frequency
fOUT
Oscillation start time
twk
Current consumption
ICSV
Conditions
⎯
Value
Unit
Min
Typ
Max
50
100
200
kHz
⎯
⎯
10
µs
⎯
20
36
µA
Remarks
Current consumption of built-in
CR oscillator, at 100 kHz oscillation
51
MB95150M Series
5. A/D Converter
(1) A/D Converter Electrical Characteristics
(Vcc = 4.0 V to 5.5 V, Vss = 0.0 V, TA = − 40 °C to + 85 °C)
Parameter
Symbol
Resolution
Total error
Linearity error
⎯
Differential linear error
Unit
Min
Typ
Max
⎯
⎯
10
bit
− 3.0
⎯
+ 3.0
LSB
− 2.5
⎯
+ 2.5
LSB
− 1.9
⎯
+ 1.9
LSB
Remarks
Zero transition voltage
VOT
VSS − 1.5 LSB VSS + 0.5 LSB VSS + 2.5 LSB
V
Full-scale transition
voltage
VFST
VCC − 3.5 LSB VCC − 1.5 LSB VCC + 0.5 LSB
V
0.9
⎯
16500
µs
4.5 V ≤ VCC ≤ 5.5 V
1.8
⎯
16500
µs
4.0 V ≤ VCC < 4.5 V
0.6
⎯
∞
µs
4.5 V ≤ VCC ≤ 5.5 V,
At external impedance <
5.4 kΩ
1.2
⎯
∞
µs
4.0 V ≤ VCC < 4.5 V,
At external impedance <
2.4 kΩ
Compare time
Sampling time
52
Value
⎯
⎯
Analog input current
IAIN
−0.3
⎯
+ 0.3
µA
Analog input voltage
VAIN
VSS
⎯
VCC
V
MB95150M Series
(2) Notes on Using A/D Converter
• About the external impedance of analog input and its sampling time
A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling
time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting A/
D conversion precision. Therefore, to satisfy the A/D conversion precision standard, consider the relationship
between the external impedance and minimum sampling time and either adjust the register value and operating
frequency or decrease the external impedance so that the sampling time is longer than the minimum value.
Also, if the sampling time cannot be sufficient, connect a capacitor of about 0.1 µF to the analog input pin.
• Analog input equivalent circuit
R
Analog input
Comparator
C
During sampling : ON
R
2.0 kΩ (Max)
8.2 kΩ (Max)
4.5 V ≤ VCC ≤ 5.5 V
4.0 V ≤ VCC < 4.5 V
C
16 pF (Max)
16 pF (Max)
Note : The values are reference values.
• The relationship between external impedance and minimum sampling time
(External impedance = 0 kΩ to 20 kΩ)
100
90
80
70
60
50
40
30
20
10
0
VCC ≥ 4.5 V
VCC ≥ 4.0 V
0
2
4
6
8
10
12
14
External impedance [kΩ]
External impedance [kΩ]
(External impedance = 0 kΩ to 100 kΩ)
20
18
16
14
12
10
8
6
4
2
0
VCC ≥ 4.5 V
VCC ≥ 4.0 V
0
Minimum sampling time [µs]
1
2
3
4
Minimum sampling time [µs]
• About errors
As |VCC − VSS| becomes smaller, values of relative errors grow larger.
53
MB95150M Series
(3) Definition of A/D Converter Terms
• Resolution
The level of analog variation that can be distinguished by the A/D converter.
When the number of bits is 10, analog voltage can be divided into 210 = 1024.
• Linearity error (unit : LSB)
The deviation between the value along a straight line connecting the zero transition point
(“00 0000 0000” ← → “00 0000 0001”) of a device and the full-scale transition point
(“11 1111 1111” ← → “11 1111 1110”) compared with the actual conversion values obtained.
• Differential linear error (Unit : LSB)
Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal value.
• Total error (unit: LSB)
Difference between actual and theoretical values, caused by a zero transition error, full-scale transition error,
linearity error, quantum error, and noise.
Ideal I/O characteristics
Total error
VFST
3FFH
3FFH
3FEH
1.5 LSB
3FDH
004H
003H
002H
VOT
Digital output
Digital output
3FEH
3FDH
Actual conversion
characteristic
{1 LSB × (N − 1) + 0.5 LSB}
004H
003H
002H
1 LSB
VNT
Actual conversion
characteristic
Ideal characteristics
001H
001H
0.5 LSB
VSS
Analog input
1 LSB =
VCC − Vss
1024
(V)
VCC
VSS
VCC
Analog input
Total error of VNT − {1 LSB × (N − 1) + 0.5 LSB}
=
[LSB]
digital output N
1 LSB
N : A/D converter digital output value
VNT : A voltage at which digital output transits from (N − 1) H to NH
(Continued)
54
MB95150M Series
(Continued)
Full-scale transition error
Zero transition error
004H
Ideal characteristics
3FFH
Digital output
Digital output
Actual conversion
characteristic
003H
002H
Ideal
characteristics
Actual conversion
characteristic
Actual conversion
characteristic
3FEH
VFST
(measurement
value)
3FDH
001H
Actual conversion
characteristic
3FCH
VOT (measurement value)
VSS
VCC
VSS
Analog input
Analog input
Differential linear error
Linearity error
Actual conversion
characteristic
3FFH
3FEH
Actual conversion
characteristic
VFST
(measurement
value)
VNT
004H
Actual conversion
characteristic
003H
Digital output
Digital output
Ideal characteristics
(N+1)H
{1 LSB × N + VOT}
3FDH
VCC
NH
(N-1)H
VNT
Actual conversion
characteristic
Ideal characteristics
002H
(N-2)H
001H
V (N+1)T
VOT (measurement value)
VSS
VCC
Analog input
Linearity error in = VNT − {1 LSB × N + VOT}
digital output N
1 LSB
VSS
Analog input
Differential linear error =
in digital output N
V (N + 1) T − VNT
1 LSB
VCC
−1
N : A/D converter digital output value
VNT : A voltage at which digital output transits from (N − 1) H to NH
VOT (Ideal value) = VSS + 0.5 LSB [V]
VFST (Ideal value) = VCC − 1.5 LSB [V]
55
MB95150M Series
6. Flash Memory Program/Erase Characteristics
Parameter
Value
Unit
Remarks
15.0*2
s
Excludes 00H programming prior erasure.
32
3600
µs
Excludes system-level overhead.
10000
⎯
⎯
cycle
Power supply voltage at erase/
program
4.5
⎯
5.5
V
Flash memory data retention
time
20*3
⎯
⎯
year
Min
Typ
Max
Chip erase time
⎯
1.0*1
Byte programming time
⎯
Erase/program cycle
Average TA = +85 °C
*1 : TA = + 25 °C, VCC = 5.0 V, 10000 cycles
*2 : TA = + 85 °C, VCC = 4.5 V, 10000 cycles
*3 : This value comes from the technology qualification (using Arrhenius equation to translate high temperature
measurements into normalized value at +85 °C) .
56
MB95150M Series
■ EXAMPLE CHARACTERISTICS
• Power supply current temperature (Flash memory product)
ICC − VCC
TA = + 25 °C, FMP = 2, 4, 8, 10, 16 MHz (divided by 2)
Main clock mode, at external clock operating
ICC − TA
VCC = 5.5 V, FMP = 10, 16 MHz (divided by 2)
Main clock mode, at external clock operating
16
16
FMP = 16 MHz
12
10
10
FMP = 10MHz
FMP = 8MHz
8
6
ICC[mA]
ICC[mA]
12
6
FMP = 4MHz
4
2
FMP = 2MHz
2
2
3
4
Vcc [V]
5
0
−50 −35 −20
6
ICC − VCC
TA = + 25 °C, FMP = 2, 4, 8, 10, 16 MHz (divided by 2)
Main clock mode + AD operation,
at external clock operating
−5 +10 +25 +40 +55 +70 +85 +100
TA [°C]
ICC − TA
VCC = 5.5 V, FMP = 10, 16 MHz (divided by 2)
Main clock mode + AD operation,
at external clock operating
16
16
FMP = 16 MHz
14
FMP = 16 MHz
14
12
10
FMP = 10MHz
FMP = 8MHz
8
6
ICC[mA]
12
ICC[mA]
FMP = 10 MHz
8
4
0
FMP = 4MHz
4
FMP = 10 MHz
10
8
6
4
FMP = 2MHz
2
2
0
2
3
4
Vcc [V]
5
0
−50 −35 −20
6
ICCS − VCC
TA = + 25 °C, FMP = 2, 4, 8, 10, 16 MHz (divided by 2)
Main sleep mode, at external clock operating
16
16
14
14
12
12
10
10
8
6
FMP= 16MHz
FMP = 10MHz
FMP = 8MHz
FMP = 4MHz
FMP = 2MHz
4
2
0
2
3
4
Vcc [V]
5
6
−5 +10 +25 +40 +55 +70 +85 +100
TA [°C]
ICCS − TA
VCC = 5.5 V, FMP = 10, 16 MHz (divided by 2)
Main sleep mode, at external clock operating
ICCS[mA]
ICCS[mA]
FMP = 16 MHz
14
14
8
6
FMP = 16 MHz
4
FMP = 10 MHz
2
0
−50 −35 −20
−5
+10 +25 +40 +55 +70 +85 +100
TA [°C]
(Continued)
57
MB95150M Series
ICCMPLL − VCC
TA = + 25 °C, FMP = 2, 4, 8, 10, 16 MHz
(Main PLL multiplied by 2.5)
Main PLL mode, at external clock operating
16
16
14
14
FMP = 16 MHz
10
FMP = 10 MHz
FMP = 8 MHz
8
6
10
6
FMP = 4 MHz
4
2
FMP = 2 MHz
2
0
−50 −35 −20
0
3
4
Vcc [V]
5
6
80
80
70
70
60
60
50
50
40
30
30
20
10
10
0
−50 −35 −20 −5 +10 +25 +40 +55 +70 +85 +100
TA [°C]
0
4
Vcc [V]
5
6
ICCLS − TA
VCC = 5.5 V, FMPL = 16 kHz (divided by 2)
Sub sleep mode, at external clock operating
80
80
70
70
60
60
50
50
ICCLS[µA]
ICCLS[µA]
ICCLS − VCC
TA = + 25 °C, FMPL = 16 kHz (divided by 2)
Sub sleep mode, at external clock operating
40
30
40
30
20
20
10
10
0
2
3
4
Vcc [V]
5
+10 +25 +40 +55 +70 +85 +100
TA [°C]
40
20
3
−5
ICCL − TA
VCC = 5.5 V, FMPL = 16 kHz (divided by 2)
Sub clock mode, at external clock operating
ICCL[µA]
ICCL[µA]
ICCL − VCC
TA = + 25 °C, FMPL = 16 kHz (divided by 2)
Sub clock mode, at external clock operating
2
FMP = 10 MHz
8
4
2
FMP = 16 MHz
12
ICCMPLL[mA]
12
ICCMPLL[mA]
ICCMPLL − TA
VCC = 5.5 V, FMP = 10, 16 MHz (Main PLL multiplied by 2.5)
Main PLL mode, at external clock operating
6
0
−50 −35 −20 −5 +10 +25 +40 +55 +70 +85 +100
TA [°C]
(Continued)
58
MB95150M Series
ICCT − TA
VCC = 5.5 V, FMPL = 16 kHz (divided by 2)
Clock mode, at external clock operating
20
20
16
16
12
12
ICCT[µA]
ICCT[µA]
ICCT − VCC
TA = + 25 °C, FMPL = 16 kHz (divided by 2)
Clock mode, at external clock operating
8
8
4
4
0
−50 −35 −20
0
2
3
4
Vcc [V]
5
6
ICCSPLL − TA
VCC = 5.5 V, FMPL = 16 kHz (divided by 2)
Sub PLL mode, at external clock operating
500
500
400
400
ICCSPLL[µA]
ICCSPLL[µA]
ICCSPLL − VCC
TA = + 25 °C, FMPL = 128 kHz (Main PLL multiplied by 4)
Sub PLL mode, at external clock operating
300
200
300
200
100
100
0
−50 −35 −20 −5 +10 +25 +40 +55 +70 +85 +100
TA [°C]
0
2
3
4
Vcc [V]
5
6
ICTS − VCC
TA = + 25 °C, FMP = 2, 4, 8, 10, 16 MHz (divided by 2)
Time-base timer mode, at external clock operating
ICTS − TA
VCC = 5.5 V, FMP = 10, 16 MHz (divided by 2)
Time-base timer mode, at external clock operating
1.4
1.4
1.2
FMP = 16 MHz
1.2
FMP = 16 MHz
1
0.8
FMP = 10 MHz
0.6
FMP = 8 MHz
0.4
FMP = 4 MHz
0.2
FMP = 2 MHz
0
2
3
4
Vcc [V]
5
6
ICTS[mA]
1
ICTS[mA]
−5 +10 +25 +40 +55 +70 +85 +100
TA [°C]
FMP = 10 MHz
0.8
0.6
0.4
0.2
0
−50 −35 −20 −5
+10 +25 +40 +55 +70 +85 +100
TA [°C]
(Continued)
59
MB95150M Series
(Continued)
ICCH − TA
VCC = 5.5 V, FMP = stop
Sub stop mode, at external clock stopping
20
20
16
16
ICCH[µA]
ICCH[µA]
ICCH − VCC
TA = + 25 °C, FMP = stop
Sub stop mode, at external clock stopping
12
8
8
4
4
0
0
2
3
4
Vcc [V]
60
12
5
6
−50 −35 −20
−5
+10 +25 +40 +55 +70 +85 +100
TA [°C]
MB95150M Series
• Input voltage (Flash memory product)
VIH1 − VCC and VIL − VCC
TA = + 25 °C
VIHS1 − VCC and VILS − VCC
TA = + 25 °C
5
5
4
4
VIHS1 / VILS [V]
VIH1 / VIL [V]
VIHS1
VIH1
3
VIL
2
1
3
2
VILS
1
0
0
2
3
4
5
6
2
3
VCC [V]
5
6
VIHS2 − VCC and VILS − VCC
TA = + 25 °C
5
5
4
4
VIHS2 / VILS [V]
VIH2 / VIL [V]
VIH2 − VCC and VIL − VCC
TA = + 25 °C
4
VCC [V]
VIH2
3
VIL
2
VIHS2
3
2
VILS
1
1
0
0
2
3
4
VCC [V]
5
6
2
VIHA − VCC and VILA − VCC
TA = + 25 °C
3
4
VCC [V]
5
6
VIHM − VCC and VILM − VCC
TA = + 25 °C
5
5
VIHA
4
VIHM / VILM [V]
VIHA / VILA [V]
4
VILA
3
2
3
VIHM
2
VILM
1
1
0
0
2
3
4
VCC [V]
5
6
2
3
4
VCC [V]
5
6
61
MB95150M Series
• Output voltage (Flash memory product)
(VCC-VOH) − IOH
TA = + 25 °C
VOL − IOL
TA = + 25 °C
Vcc = 2.5 [V] 2.7 [V] 3.0 [V] Vcc = 3.5 [V]
1.2
Vcc = 4.0 [V]
1
1
Vcc = 4.5 [V]
Vcc = 5.0 [V]
Vcc = 5.5 [V]
0.8
0.6
Vcc = 2.5 [V]
0.4
0.2
0.2
0
−2
−4
−6
IOH [mA]
−8
0
−10
0
2
4
• Pull-up (Flash memory product)
RPULL − VCC
TA = + 25 °C
250
RPULL [kΩ]
200
150
100
50
0
2
62
Vcc = 3.5 [V]
Vcc = 4.0 [V]
Vcc = 4.5 [V]
Vcc = 5.0 [V]
Vcc = 5.5 [V]
0.6
0.4
0
Vcc = 2.7 [V] Vcc = 3.0 [V]
0.8
VOL [V]
Vcc-VOH [V]
1.2
3
4
VCC [V]
5
6
6
IOL [mA]
8
10
MB95150M Series
■ MASK OPTION
Part number
MB95156M
MB95F156M
MB95F156N
MB95F156J
MB95FV100D-103
Specifying procedure
Specify when
ordering MASK
Setting disabled
Setting disabled
Dual-system
clock mode
Dual-system
clock mode
Changing by the switch on
MCU board
No.
1
Clock mode select
• Single-system clock mode
• Dual-system clock mode
2
Low voltage detection reset*
• With low voltage detection reset
• Without low voltage detection
reset
Specify when
ordering MASK
Specified by
part number
Changing by the switch on
MCU board
3
Clock supervisor*
• With clock supervisor
• Without clock supervisor
Specify when
ordering MASK
Specified by
part number
Changing by the switch on
MCU board
Specified by
part number
MCU board switch sets as
follows ;
• With clock supervisor :
Without reset output
• Without clock supervisor :
With reset output
4
Reset output*
• With reset output
• Without reset output
5
Fixed to oscillation Fixed to oscillation
Fixed to oscillation stabilizaOscillation stabilization wait time stabilization wait
stabilization wait time
tion wait time of (214−2) /FCH
time of (214 − 2) /FCH of (214−2) /FCH
Specify when
ordering MASK
* : Refer to table below about clock mode select, low voltage detection reset, clock supervisor select and reset output.
Part number
MB95156M
Clock mode select
Dual-system
MB95F156M
MB95F156N
Dual-system
MB95F156J
Single-system
MB95FV100D-103
Dual-system
Low voltage detection reset Clock supervisor Reset output
No
No
Yes
Yes
No
Yes
Yes
Yes
No
No
No
Yes
Yes
No
Yes
Yes
Yes
No
No
No
Yes
Yes
No
Yes
Yes
Yes
No
No
No
Yes
Yes
No
Yes
Yes
Yes
No
63
MB95150M Series
■ ORDERING INFORMATION
Part number
MB95156MPMT
MB95F156MPMT
MB95F156NPMT
MB95F156JPMT
48-pin plastic LQFP
(FPT-48P-M26)
MB95156MPMC
MB95F156MPMC
MB95F156NPMC
MB95F156JPMC
52-pin plastic LQFP
(FPT-52P-M01)
MB2146-303A
(MB95FV100D-103PBT)
64
Package
MCU board
224-pin plastic PFBGA
(BGA-224P-M08)
(
)
MB95150M Series
■ PACKAGE DIMENSIONS
48-pin plastic LQFP
Lead pitch
0.50 mm
Package width ×
package length
7 × 7 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.70 mm MAX
Weight
0.17 g
Code
(Reference)
P-LFQFP48-7×7-0.50
(FPT-48P-M26)
48-pin plastic LQFP
(FPT-48P-M26)
Note 1) * : These dimensions include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
9.00±0.20(.354±.008)SQ
+0.40
+.016
* 7.00 –0.10 .276 –.004 SQ
36
0.145±0.055
(.006±.002)
25
37
24
0.08(.003)
Details of "A" part
+0.20
1.50 –0.10
+.008
INDEX
48
13
"A"
0˚~8˚
LEAD No.
1
0.50(.020)
(Mounting height)
.059 –.004
0.10±0.10
(.004±.004)
(Stand off)
12
0.20±0.05
(.008±.002)
0.08(.003)
0.25(.010)
M
0.60±0.15
(.024±.006)
C
2003 FUJITSU LIMITED F48040S-c-2-2
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html
(Continued)
65
MB95150M Series
(Continued)
52-pin plastic LQFP
Lead pitch
0.65 mm
Package width ×
package length
10.0 × 10.0 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.70 mm Max
Code
(Reference)
P-LQFP52-10×10-0.65
(FPT-52P-M01)
52-pin plastic LQFP
(FPT-52P-M01)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
12.00±0.20(.472±.008)SQ
* 10.00±0.10(.394±.004)SQ
0.145±0.055
(.006±.002)
39
27
40
26
Details of "A" part
0.10(.004)
+0.20
1.50 –0.10
.059
+.008
–.004
INDEX
0˚~8˚
52
14
(Mounting height)
0.10±0.10
(.004±.004)
(Stand off)
"A"
LEAD No.
1
13
0.65(.026)
0.30
.012
C
+0.065
–0.035
+.0027
–.0014
0.13(.005)
M
2005 FUJITSU LIMITED F52001S-c-1-1
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html
66
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
0.25(.010)
Dimensions in mm (inches).
Note: The values in parentheses are reference values
MB95150M Series
■ MAIN CHANGES IN THIS EDITION
Page
Section
⎯
⎯
Change Results
Added the part numbers.
MB95156M (MASK ROM Product)
■ PROGRAMMING FLASH MEMORY
MICROCONTROLLERS USING
PARALLEL PROGRAMMER
• Programming Method
Changed as follows
“2) Load program data to programmer addresses 7800H to
7FFFFH.”
→ “2) Load program data to programmer addresses 18000H
to 1FFFFH.”
21
■ I/O MAP
Reset factor register
• Changed the register name to “Reset source register.”
• Changed the item "R/W” as follows.
“R” → “R/W”
35
4. AC Characteristics (1) Clock Timing
Added the Main PLL multiplied by 4.
(2) Source Clock/Machine Clock
37
Changed source clock cycle time (when using main clock) .
Min : FCH = 10 MHz, PLL multiplied by 1
→ Min : FCH = 8.125 MHz, PLL multiplied by 2
39
Changed the figure of “ • Main PLL operation frequency”.
15
57 to 62 ■ EXAMPLE CHARACTERISTICS
Added the ■ EXAMPLE CHARACTERISTICS.
The vertical lines marked in the left side of the page show the changes.
67
MB95150M Series
The information for microcontroller supports is shown in the following homepage.
http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html
FUJITSU LIMITED
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representatives before ordering.
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circuit examples, in this document are presented solely for the
purpose of reference to show examples of operations and uses of
Fujitsu semiconductor device; Fujitsu does not warrant proper
operation of the device with respect to use based on such
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device based on such information, you must assume any
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Please note that Fujitsu will not be liable against you and/or any
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Edited
Business Promotion Dept.
F0708