LMH0056 www.ti.com SNLS236C – AUGUST 2006 – REVISED APRIL 2013 LMH0056 HD/SD SDI Reclocker with 4:1 Input Multiplexer Check for Samples: LMH0056 FEATURES DESCRIPTION • The LMH0056 HD/SD SDI Reclocker with 4:1 Input Multiplexer retimes serial digital video data conforming to the SMPTE 292M and SMPTE 259M (A & C) standards. The LMH0056 operates at serial data rates of 143 Mbps, 270 Mbps, 1.483 Gbps and 1.485 Gbps. The LMH0056 supports DVB-ASI operation at 270 Mbps. The LMH0056 includes an integrated 4:1 input multiplexer for selecting one of four input data streams for retiming. 1 2 • • • • • • • • • • • • • • • • • Supports SMPTE 292M and SMPTE 259M (A & C) Serial Digital Video Standards Supports 143 Mbps, 270 Mbps, 1.483 Gbps, and 1.485 Gbps Serial Data Rate Operation Supports DVB-ASI at 270 Mbps Single 3.3V Supply Operation 360 mW Typical Power Consumption Integrated 4:1 Multiplexed Input Two Differential, Reclocked Outputs Choice of Second Reclocked Output or LowJitter, Differential, Data-Rate Clock Output Single 27 MHz External Crystal or Reference Clock Input Manual Rate Select Input SD/HD Operating Rate Indicator Output Lock Detect Indicator Output Output Mute Function for Data and Clock Auto/Manual Reclocker Bypass Differential LVPECL Compatible Serial Data Inputs and Outputs LVCMOS Control Inputs and Indicator Outputs 48-Pin WQFN Package Industrial Temperature Range: -40°C to +85°C The LMH0056 automatically detects the incoming data rate and adjusts itself to retime the incoming data to suppress accumulated jitter. The LMH0056 recovers the serial data-rate clock and optionally provides it as an output. The LMH0056 has two differential serial data outputs; the second output may be selected as a low-jitter, data-rate clock output. Controls and indicators are: serial clock or second serial data output select, manual rate select input, SD/HD rate indicator output, lock detect output, auto/manual data bypass and output mute. The serial data inputs, outputs, and serial data-rate clock outputs are differential LVPECL compatible. The CML serial data and serial data-rate clock outputs are suitable for driving 100Ω differentially terminated networks. The control logic inputs and outputs are LVCMOS compatible. The LMH0056 is powered from a single 3.3V supply. Power dissipation is typically 360 mW. The device is housed in a 48-pin WQFN package. APPLICATIONS • SDTV/HDTV Serial Digital Video Interfaces for: – Digital Video Routers and Switchers – Digital Video Processing and Editing Equipment – DVB-ASI Equipment – Video Standards and Format Converters 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2006–2013, Texas Instruments Incorporated LMH0056 SNLS236C – AUGUST 2006 – REVISED APRIL 2013 www.ti.com Typical Application LMH0044 Equalizer LMH0002 Cable Driver LMH0056 Reclocker Crosspoint LMH0044 Equalizer LMH0002 Cable Driver LMH0044 Equalizer Crosspoint LMH0044 Equalizer LMH0002 Cable Driver LMH0056 Reclocker LMH0044 Equalizer LMH0002 Cable Driver Crosspoint LMH0044 Equalizer LMH0044 Equalizer Crosspoint LMH0044 Equalizer Block Diagram SCO_EN BYPASS/ AUTO BYPASS RATE0 SD/ HD CONTROL LOGIC LOCK DETECT RATE1 VCCO BYPASS 50 50 XTAL IN/EXT CLK XTAL OUT LOOP FILTER 1 SCO/SDO2 VCO / PLL SCO/SDO2 LOOP FILTER 2 O/P MUTE VCCO SDI0 SDI0 50 50 SDI1 SDI1 SDO RETIMER / FIFO SDO SDI2 SDI2 SDI3 SDI3 SEL0 SEL1 2 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LMH0056 LMH0056 www.ti.com SNLS236C – AUGUST 2006 – REVISED APRIL 2013 43 42 41 40 39 38 SCO_EN LF1 44 VEE LF2 45 VEE RATE0 46 VEE RATE1 47 VEE SEL0 48 VEE SEL1 Connection Diagram 37 SDI0 1 36 SD/HD SDI0 2 35 VCC VCC 3 34 VCC SDI1 4 33 SDO SDI1 5 32 SDO VCC 6 31 VCC SDI2 7 30 VCC SDI2 8 29 SCO/SDO2 VCC 9 28 SCO/SDO2 SDI3 10 27 VEE SDI3 11 26 VEE VCC 12 25 VEE 20 21 22 VEE XTAL OUT 23 24 LOCK DET 19 VEE 18 VEE O/P MUTE 17 VEE 16 XTAL IN/ EXT CLK 15 VEE 14 VCC VEE 13 BYPASS/ AUTOBYPASS LMH0056 (top view) The exposed die attach pad is the primary negative electrical terminal for this device. It must be connected to the negative power supply voltage. Figure 1. 48-Pin WQFN Package See Package Number RHS0048A PIN DESCRIPTIONS Pin No. Name Description 1 SDI0 Data Input 0 True 2 SDI0 Data Input 0 Complement 3 VCC Positive power supply input 4 SDI1 Data Input 1 True 5 SDI1 Data Input 1 Complement 6 VCC Positive power supply input 7 SDI2 Data Input 2 True 8 SDI2 Data Input 2 Complement 9 VCC Positive power supply input 10 SDI3 Data Input 3 True 11 SDI3 Data Input 3 Complement 12 VCC Positive power supply input 13 VEE Negative power supply input 14 VCC Positive power supply input 15 BYPASS/AUTO BYPASS Bypass/Auto Bypass mode select Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LMH0056 3 LMH0056 SNLS236C – AUGUST 2006 – REVISED APRIL 2013 www.ti.com PIN DESCRIPTIONS (continued) Pin No. Name Description 16 OUTPUT MUTE Data and Clock Output Mute input (active low) 17 VEE Negative power supply input 18 XTAL IN/EXT CLK Crystal or External Oscillator input 19 VEE Negative power supply input 20 VEE Negative power supply input 21 VEE Negative power supply input 22 XTAL OUT Crystal Oscillator output 23 VEE Negative power supply input 24 LOCK DETECT PLL Lock Detect output (active high) 25 VEE Negative power supply input 26 VEE Negative power supply input 27 VEE Negative power supply input 28 SCO/SDO2 Serial Clock or Serial Data Output 2 Complement 29 SCO/SDO2 Serial Clock or Serial Data Output 2 True 30 VCC Positive power supply input 31 VCC Positive power supply input 32 SDO Data Output Complement 33 SDO Data Output True 34 VCC Positive power supply input 35 VCC Positive power supply input 36 SD/HD Data Rate Range output 37 SCO_EN Serial Clock or Serial Data 2 Output select (active high enables serial clock output) 38 VEE Negative power supply input 39 VEE Negative power supply input 40 VEE Negative power supply input 41 VEE Negative power supply input 42 VEE Negative power supply input 43 LF1 Loop Filter 44 LF2 Loop Filter 45 RATE 0 Data Rate select input 46 RATE 1 Data Rate select input 47 SEL0 Data Input select input 48 SEL1 Data Input select input VEE Connect exposed DAP to negative power supply (ground) DAP These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 4 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LMH0056 LMH0056 www.ti.com SNLS236C – AUGUST 2006 – REVISED APRIL 2013 Absolute Maximum Ratings (1) (2) Supply Voltage (VCC–VEE) 4.0V VEE−0.15V to VCC+0.15V Logic Supply Voltage (Vi) Logic Input Current (single input): Vi = VEE−0.15V −5 mA Vi = VCC+0.15V +5 mA VEE−0.15V to VCC+0.15V Logic Output Voltage (Vo) Logic Output Source/Sink Current ±8 mA VCC to VCC−2.0V Serial Data Input Voltage (VSDI) Serial Data Output Sink Current (ISDO) 24 mA Package Thermal Resistance θJA 48-pin WQFN 26.1°C/W θJC 48-pin WQFN 1.9°C/W Storage Temp. Range −65°C to +150°C Junction Temperature +150°C Lead Temperature (Soldering 4 Sec) +260°C (Pb-free) ESD Rating (HBM) 8 kV ESD Rating (MM) 400V ESD Rating (CDM) (1) (2) 1250V “Absolute Maximum Ratings” are those parameter values beyond which the life and operation of the device cannot be ensured. The stating herein of these maximums shall not be construed to imply that the device can or should be operated at or beyond these values. The table of “Electrical Characteristics” specifies acceptable device operating conditions. It is anticipated that this device will not be offered in a military qualified version. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications. Recommended Operating Conditions Supply Voltage (VCC–VEE) 3.3V ±5% Logic Input Voltage VEE to VCC Differential Serial Input Voltage 800 mV ±10% Serial Data or Clock Output Sink Current (ISO) 16 mA max. −40°C to +85°C Operating Free Air Temperature (TA) Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LMH0056 5 LMH0056 SNLS236C – AUGUST 2006 – REVISED APRIL 2013 www.ti.com DC Electrical Characteristics Over Supply Voltage and Operating Temperature ranges, unless otherwise specified. Symbol Parameter Conditions Reference Min Typ Max Units 2 VCC V VEE 0.8 V VIH Input Voltage High Level VIL Input Voltage Low Level IIH Input Current High Level VIH = VCC 1 65 µA IIL Input Current Low Level VIL = VEE −1 −25 µA VOH Output Voltage High Level IOH = −2 mA VOL Output Voltage Low Level VSDID Serial Input Voltage, Differential VCMI Input Common Mode Voltage VSDOD Serial Output Voltage, Differential 100Ω differential load VCMO Output Common Mode Voltage 100Ω differential load Power Supply Current, 3.3V supply, Total 1485 Mbps, NTSC color bar pattern ICC (1) (2) 6 Logic inputs (1) (2) Logic outputs 2 V IOL = +2 mA SDI SDO, SCO VEE + 0.6 V 200 1600 mVP-P VCC−1.6 VCC−0.2 V 880 mVP-P 720 800 VCC− VSDOD 109 V mA Current flow into device pins is defined as positive. Current flow out of device pins is defined as negative. All voltages are referenced to VEE (equal to zero volts). Typical values are stated for: VCC = +3.3V, TA = +25°C. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LMH0056 LMH0056 www.ti.com SNLS236C – AUGUST 2006 – REVISED APRIL 2013 AC Electrical Characteristics Over Supply Voltage and Operating Temperature ranges, unless otherwise specified. Symbol Parameter Conditions BRSD Serial Data Rate SMPTE 259M, A BRSD Serial Data Rate SMPTE 259M, C BRSD Serial Data Rate SMPTE 292M TOLJIT Serial Input Jitter Tolerance 143 or 270 Mbps (2) (3) (4) TOLJIT Serial Input Jitter Tolerance 143 or 270 Mbps (2) (5) (6) TOLJIT Serial Input Jitter Tolerance 1483 or 1485 Mbps (2) (5) (3) TOLJIT Serial Input Jitter Tolerance 1483 or 1485 Mbps (2) (5) (6) tJIT Serial Data Output Jitter 143 Mbps (5) (7) tJIT Serial Data Output Jitter tJIT BWLOOP Reference (1) Min SDI, SDO SDI Typ Max Units 143 Mbps 270 Mbps 1483, 1485 Mbps >6 UIP-P >0.6 UIP-P >6 UIP-P >0.6 SDO UIP-P 0.02 0.08 UIP-P 270 Mbps (5) (7) 0.02 0.08 UIP-P Serial Data Output Jitter 1483 or 1485 Mbps (5) (7) 0.05 0.1 UIP-P Loop Bandwidth 270 Mbps, <0.1dB Peaking 300 kHz 1485 Mbps, <0.1dB Peaking 2.0 MHz FCO Serial Clock Output Frequency 143 Mbps data rate 143 MHz FCO Serial Clock Output Frequency 270 Mbps data rate 270 MHz FCO Serial Clock Output Frequency 1483 Mbps data rate 1483 MHz FCO Serial Clock Output Frequency 1485 Mbps data rate 1485 tJIT Serial Clock Output Jitter 2 Serial Clock Output Alignment with respect to Data Interval SDO, SCO Serial Clock Output Duty Cycle TACQ Acquisition Time SCO SCO Auto-Rate Detect Mode (8) (9) Fixed Rate Mode (8) (9) 40 45 MHz 3 psRMS 60 % 55 % 10 16 ms 1 6 ms 1.5 3 ns 1500 ps 270 ps ns tr, tf Input rise/fall time 10%–90% Logic inputs tr, tf Input rise/fall time 20%–80%, 143 or 270 Mbps SDI tr, tf Input rise/fall time 20%–80%, 1483 or 1485 Mbps tr, tf Output rise/fall time 10%–90% Logic outputs 1.5 3 tr, tf Output rise/fall time 20%–80% (10) SDO, SCO 90 130 FREF Reference Clock Frequency 27 MHz FTOL Reference Clock Frequency Tolerance ±50 ppm (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) ps Typical values are stated for: VCC = +3.3V, TA = +25°C. Peak-to-peak amplitude with sinusoidal modulation per SMPTE RP 184-1996 paragraph 4.1. The test data signal shall be color bars. Refer to “A1” in Figure 1 of SMPTE RP 184-1996. Characterized to the limitations of SDI test equipment. This parameter is specified by characterization over voltage and temperature limits. Refer to “A2” in Figure 1 of SMPTE RP 184-1996. Serial Data Output Jitter is total output jitter with 0.2UIP-P input jitter. Spec is specified by design. Measured from first SDI transition until Lock Detect (LD) output goes high (true). RL = 100Ω differential. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LMH0056 7 LMH0056 SNLS236C – AUGUST 2006 – REVISED APRIL 2013 www.ti.com DEVICE DESCRIPTION The LMH0056 HD/SD SDI Reclocker with 4:1 Input Multiplexer is used in many types of digital video signal processing equipment. Supported serial digital video standards are SMPTE 259M (A & C) and SMPTE 292M. Corresponding serial data rates are 143 Mbps, 270 Mbps, 1.483 Gbps and 1.485 Gbps. DVB-ASI data at 270 Mbps may also be retimed. The LMH0056 retimes the serial data stream to suppress accumulated jitter. It provides two low-jitter, differential, serial data outputs. The second output may be selected to output either serial data or a low-jitter serial data-rate clock. Controls and indicators are: serial data-rate clock or second serial data output select, manual rate select input, SD/HD rate output, lock detect output, auto/manual data bypass and output mute. Serial data inputs are CML and LVPECL compatible. Serial data and data-rate clock outputs are differential CML and produce LVPECL compatible levels. The output buffer design can drive AC or DC-coupled, terminated 100Ω differential loads. The differential output level is 800 mVP-P ±10% into 100Ω AC or DC-coupled differential loads. Logic inputs and outputs are LVCMOS compatible. The device package is a 48–pin WQFN with an exposed die attach pad. The exposed die attach pad is electrically connected to device ground (VEE) and is the primary negative electrical terminal for the device. This terminal must be connected to the negative power supply or circuit ground. Serial Data Inputs, Serial Data and Clock Outputs SERIAL DATA INPUT AND OUTPUTS The differential serial data inputs, SDI0-SDI3, accept serial digital video data at the rates specified in Table 1. The serial data inputs are differential LVPECL compatible. These inputs are intended to be DC interfaced to devices such as the LMH0034 adaptive cable equalizer. These inputs are not internally terminated or biased. The inputs may be AC-coupled if a suitable input bias voltage is provided. The LMH0056 provides four independent, multiplexed data inputs. The active input channel is selected via the SEL0 and SEL1 pins, as shown in Table 2. Figure 2 shows the equivalent input circuit for SDI[3:0] and SDI[3:0]. The LMH0056 has two, retimed, differential, serial data outputs, SDO and SCO/SDO2. These outputs provide low jitter, differential, retimed data to devices such as the LMH0002 cable driver or the LMH0031 deserializer. Output SCO/SDO2 is multiplexed and can provide either a second serial data output or a serial data-rate clock output. Figure 3 shows the equivalent output circuit for SDO, SDO, SCO/SDO2, and SCO/SDO2. The SCO_EN input controls the operating mode for the SCO/SDO2 output. When the SCO_EN input is high the SCO/SDO2 output provides a serial data-rate clock. When SCO_EN is low, the SCO/SDO2 output provides retimed serial data. Both differential serial data outputs, SDO and SCO/SDO2, are muted when the MUTE input is a logic low level. SCO/SDO2 also mutes when the Bypass mode is activated when this output is operating as the serial clock output. When muted, SDO and SDO (or SDO2 and SDO2) will assume opposite differential output levels. The CML serial data outputs are differential LVPECL compatible. These outputs have internal 50Ω pull-ups and are suitable for driving AC or DC-coupled, 100Ω center-tapped, AC grounded or 100Ω un-center-tapped, differentially terminated networks. 8 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LMH0056 LMH0056 www.ti.com SNLS236C – AUGUST 2006 – REVISED APRIL 2013 VCC 20 k: 1 pF 80 k: VCC 2 k: VCC 2 k: SDI[3:0] SDI[3:0] Figure 2. Equivalent SDI Input Circuit (SDI[3:0], SDI[3:0]) VCC VCC VCC 50: 50: SDO, SCO/SDO2 SDO, SCO/SDO2 Figure 3. Equivalent SDO Output Circuit (SDO, SDO, SCO/SDO2, SCO/SDO2) OPERATING SERIAL DATA RATES This device operates at serial data rates of 143 Mbps, 270 Mbps, 1483 Mbps and 1485 Mbps. The device does not lock to harmonics of these rates. The device does not lock and automatically enters the reclocker bypass mode for the following data rates: 177 Mbps, 360 Mbps, and 540 Mbps. SERIAL DATA CLOCK/SERIAL DATA 2 OUTPUT The Serial Data Clock/Serial Data 2 Output is controlled by the SCO_EN input and provides either a second retimed serial data output or a low jitter differential clock output appropriate to the serial data rate being processed. When operating as a serial clock output, the rising edge of the clock will be positioned within the corresponding serial data bit interval within 10% of the center of the data interval. Differential output SCO/SDO2 functions as the second serial data output when the SCO_EN input is a logic-low level. This output functions as the serial data-rate clock output when the SCO_EN input is a logic-high level. The SCO_EN input has an internal pull-down device and the default state of SCO_EN is low (serial data output 2 enabled). SCO/SDO2 is muted when the MUTE input is a logic low level. When the Bypass mode is activated and this output is functioning as a serial clock output, the output will also be muted. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LMH0056 9 LMH0056 SNLS236C – AUGUST 2006 – REVISED APRIL 2013 www.ti.com Control Inputs and Indicator Outputs SERIAL DATA RATE SELECTOR The Serial Data Rate Selector (RATE [1:0]) permits the user to fix the operating serial data rate. The pins have internal pull-downs which maintain a logic-low input condition unless externally driven to a logic-high condition. This input also serves to place the device in a test mode. The codes shown in Table 1 select the desired operating serial data rate. The LMH0056 then enters either the Auto-Rate Detect mode or a single operating rate. Selecting the 270 Mbps rate mode may also be used when reclocking DVB-ASI data. DVB-ASI data is MPEG2 coded data that is transmitted in 8B10B coding. The device will reclock this data without harmonic locking. Table 1. Data Rate Select Input Codes RATE [1:0] Code Data Rate or Mode Comments 00 Auto-Rate Detect mode 143 Mbps rate operation supported only in ARD mode 01 270 Mbps May be used to support DVB-ASI operation 10 1483/1485 Mbps SERIAL DATA INPUT SELECTOR The Serial Data Input Selector (SEL [1:0]) allows the user to select the active input channel. Table 2 shows the input selected for a given state of SEL [1:0]. Table 2. Data Input Select Codes SEL [1:0] Code Selected Input 00 SDI0 01 SDI1 10 SDI2 11 SDI3 LOCK DETECT The Lock Detect (LD) output, when high, indicates that data is being received and the PLL is locked. LD may be connected to the MUTE input to mute the data and clock outputs when no data signal is being received. See Table 3. MUTE The MUTE input, when low, mutes the serial data and clock outputs. It may be connected to Lock Detect or externally driven to mute or un-mute the outputs. If MUTE is connected to LD, then the data and clock outputs are muted when the PLL is not locked. This function overrides the Bypass function: see Table 3. MUTE has an internal pull-up device to enable the output by default. BYPASS/AUTO BYPASS The Bypass/Auto Bypass input, when high, forces the device to output the data without reclocking it. When this input is low, the device automatically bypasses the reclocking function when the device is in an unlocked condition or the detected data rate is a rate which the device does not support. See Table 3. BYPASS/AUTO BYPASS has an internal pull-down device. 10 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LMH0056 LMH0056 www.ti.com SNLS236C – AUGUST 2006 – REVISED APRIL 2013 Table 3. Control Functionality LOCK DETECT OUTPUT MUTE BYPASS/AUTO BYPASS 0 1 0 PLL unlocked, reclocker bypassed DEVICE STATUS 1 1 0 PLL locked to supported data rate, reclocker not bypassed X 0 X Outputs muted 0 LOCK DETECT X Outputs muted 1 LOCK DETECT 0 PLL locked to supported data rate, reclocker not bypassed 1 LOCK DETECT 1 PLL locked to supported data rate, reclocker bypassed X 1 1 Outputs not muted, reclocker bypassed SD/HD The SD/HD output indicates whether the LMH0056 is processing SD or HD data rates. It may be used to control another device such as the LMH0002 cable driver. When this output is high it indicates that the data rate is 270 Mbps (or 143 Mbps). When low, the indicated data rate is 1483 or 1485 Mbps. The SD/HD output is a registered function and is only valid when the PLL is locked and the Lock Detect output is high. When the PLL is not locked (the Lock Detect output is low), the SD/HD output defaults to HD (low). The SD/HD output is undefined for a short time after lock detect assertion or de-assertion due to a data rate change on SDI. See Figure 4 for a timing diagram showing the relationship between SDI, Lock Detect, and SD/HD. SDI NO DATA 270 MBPS DATA TACQ NO DATA 1485 MBPS DATA T2 TACQ NO DATA T2 Lock Detect T1 T1 T1 SD/HD SDI NO DATA 143 MBPS DATA 270 MBPS DATA 1485 MBPS DATA TACQ TACQ 270 MBPS DATA TACQ T2 T2 TACQ T2 Lock Detect T1 T1 T1 T1 T1 T1 SD/HD TACQ = Acquisition Time, defined in the AC Electrical Characteristics Table T1 = Time from Lock Detect assertion or deassertion until SD/HD output is valid, typically 37 ns (one 27 MHz clock period) T2 = Time from SDI input change until Lock Detect de-assertion, 1 ms maximum. SD/HD output is not valid during this time. Figure 4. SDI, Lock Detect, and SD/HD Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LMH0056 11 LMH0056 SNLS236C – AUGUST 2006 – REVISED APRIL 2013 www.ti.com SCO_EN Input SCO_EN enables the SCO/SDO2 differential output to function either as a serial data-rate clock or second serial data output. SCO/SDO2 functions as a serial data-rate clock when SCO_EN is high. This pin has an internal pull-down device. The default state (low) enables the SCO/SDO2 output as a second serial data output. CRYSTAL OR EXTERNAL CLOCK REFERENCE The LMH0056 uses a 27 MHz crystal or external clock signal as a timing reference input. A 27 MHz parallel resonant crystal and load network may be connected to the XTAL IN/EXT CLK and XTAL OUT pins. Alternatively, a 27 MHz LVCMOS compatible clock signal may be input to XTAL IN/EXT CLK. Parameters for a suitable crystal are given in Table 4. Table 4. Crystal Parameters Parameter Value Frequency 27 MHz Frequency Stability ±50 ppm @ recommended drive level Operating Mode Fundamental mode, Parallel Resonant Load Capacitance 20 pF Shunt Capacitance 7 pF Series Resistance 40Ω max. Recommended Drive Level 100 µW Maximum Drive Level 500 µW Operating Temperature Range −10°C to +60°C 12 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LMH0056 LMH0056 www.ti.com SNLS236C – AUGUST 2006 – REVISED APRIL 2013 APPLICATION INFORMATION Figure 5 shows an application circuit for the LMH0056. SCO_EN RATE0 RATE1 56 nF SEL0 SEL1 5 6 7 100: 8 9 Differential Data Input 2 10 11 100: 12 Differential Data Input 3 44 45 43 LF1 42 VEE 41 VEE 40 VEE 39 VEE 38 VEE 37 SCO_EN LF2 RATE0 RATE1 SDI1 SDI1 VCC LMH0056 SDI2 SDI2 VCC SDI3 SDI3 VCC VEE Differential Data Input 1 4 SDI0 VCC VCC 36 SD/ HD 35 VCC 34 VCC 33 SDO 32 SDO 31 VCC 30 VCC 29 SCO/SDO2 28 SCO/SDO2 27 VEE 26 VEE 25 V VCC 15 BP/ AUTO-BP 16 OP MUTE 17 V EE 18 XTAL IN/EXT CLK 19 VEE 20 VEE 21 VEE 22 XTAL OUT 23 VEE 24 LOCK DET 3 100: SDI0 SD/ HD Data Output Clock Output or 2nd Data Output EE DAP 14 1 2 13 100: Differential Data Input 0 SEL0 SEL1 47 46 VCC 48 VCC 27 MHz LOCK DET BP/ AUTO-BP OP MUTE 39 pF 39 pF Figure 5. Application Circuit Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LMH0056 13 LMH0056 SNLS236C – AUGUST 2006 – REVISED APRIL 2013 www.ti.com REVISION HISTORY Changes from Revision B (April 2013) to Revision C • 14 Page Changed layout of National Data Sheet to TI format .......................................................................................................... 13 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LMH0056 PACKAGE OPTION ADDENDUM www.ti.com 15-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) LMH0056SQ/NOPB ACTIVE WQFN RHS 48 1000 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 L056 LMH0056SQE/NOPB ACTIVE WQFN RHS 48 250 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 L056 LMH0056SQX/NOPB ACTIVE WQFN RHS 48 2500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 L056 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. 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Addendum-Page 1 Samples PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing LMH0056SQ/NOPB WQFN RHS 48 LMH0056SQE/NOPB WQFN RHS LMH0056SQX/NOPB WQFN RHS SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 1000 330.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1 48 250 178.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1 48 2500 330.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMH0056SQ/NOPB WQFN RHS 48 1000 367.0 367.0 38.0 LMH0056SQE/NOPB WQFN RHS 48 250 213.0 191.0 55.0 LMH0056SQX/NOPB WQFN RHS 48 2500 367.0 367.0 38.0 Pack Materials-Page 2 MECHANICAL DATA RHS0048A SQA48A (Rev B) www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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