NTLJD3181PZ Power MOSFET −20 V, −4.0 A, mCoolt Dual P−Channel, ESD, 2x2 mm WDFN Package Features • WDFN 2x2 mm Package with Exposed Drain Pads for Excellent • • • • • Thermal Conduction Lowest RDS(on) Solution in 2x2 mm Package Footprint Same as SC−88 Package Low Profile (< 0.8 mm) for Easy Fit in Thin Environments ESD Protected This is a Pb−Free Device http://onsemi.com V(BR)DSS RDS(on) MAX ID MAX (Note 1) 100 mW @ −4.5 V −20 V −4.0 A 144 mW @ −2.5 V 200 mW @ −1.8 V D1 Applications D2 • Optimized for Battery and Load Management Applications in Portable Equipment G1 • Li−Ion Battery Charging and Protection Circuits • High Side Load Switch MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Parameter Drain−to−Source Voltage Gate−to−Source Voltage Continuous Drain Current (Note 1) Power Dissipation (Note 1) Symbol Value Unit VDSS −20 V VGS ±8.0 V ID −3.2 A Steady State TA = 25°C TA = 85°C −2.3 t≤5s TA = 25°C −4.0 Steady State PD 1.5 ID −2.2 Power Dissipation (Note 2) Pulsed Drain Current S2 P−CHANNEL MOSFET P−CHANNEL MOSFET D2 TA = 85°C TA = 25°C WDFN6 CASE 506AN Pin 1 A 0.71 W IDM −16 A TJ, TSTG −55 to 150 °C Source Current (Body Diode) (Note 2) IS −1.0 A Lead Temperature for Soldering Purposes (1/8″ from case for 10 s) TL 260 °C tp = 10 ms Operating Junction and Storage Temperature Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Surface Mounted on FR4 Board using 1 in sq pad size (Cu area = 1.127 in sq [2 oz] including traces). 2. Surface Mounted on FR4 Board using the minimum recommended pad size of 30 mm2, 2 oz Cu. 1 2 JEMG G 3 6 5 4 JE = Specific Device Code M = Date Code G = Pb−Free Package (Note: Microdot may be in either location) W PIN CONNECTIONS −1.6 PD MARKING DIAGRAM D1 2.3 TA = 25°C Steady State S1 TA = 25°C t≤5s Continuous Drain Current (Note 2) G2 D1 S1 1 G1 2 6 D1 5 G2 4 S2 D2 D2 3 (Top View) ORDERING INFORMATION Device Package Shipping† NTLJD3181PZTAG WDFN6 3000/Tape & Reel (Pb−Free) NTLJD3181PZTBG WDFN6 3000/Tape & Reel (Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2008 December, 2008 − Rev. 0 1 Publication Order Number: NTLJD3181PZ/D NTLJD3181PZ THERMAL RESISTANCE RATINGS Parameter Symbol Max Junction−to−Ambient – Steady State (Note 3) RqJA 83 Junction−to−Ambient – Steady State Min Pad (Note 4) RqJA 177 Junction−to−Ambient – t ≤ 5 s (Note 3) RqJA 54 Unit SINGLE OPERATION (SELF−HEATED) °C/W DUAL OPERATION (EQUALLY HEATED) Junction−to−Ambient – Steady State (Note 3) RqJA 58 Junction−to−Ambient – Steady State Min Pad (Note 4) RqJA 133 Junction−to−Ambient – t ≤ 5 s (Note 3) RqJA 40 3. Surface Mounted on FR4 Board using 1 in sq pad size (Cu area = 1.127 in sq [2 oz] including traces). 4. Surface Mounted on FR4 Board using the minimum recommended pad size (30 mm2, 2 oz Cu). http://onsemi.com 2 °C/W NTLJD3181PZ MOSFET ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Symbol Test Conditions Min Drain−to−Source Breakdown Voltage V(BR)DSS VGS = 0 V, ID = −250 mA −20 Drain−to−Source Breakdown Voltage Temperature Coefficient V(BR)DSS/TJ ID = −250 mA, Ref to 25°C Parameter Typ Max Unit OFF CHARACTERISTICS Zero Gate Voltage Drain Current IDSS Gate−to−Source Leakage Current VDS = −16 V, VGS = 0 V V 13 mV/°C TJ = 25°C −1.0 TJ = 85°C −10 IGSS VDS = 0 V, VGS = ±8.0 V VGS(TH) VGS = VDS, ID = −250 mA mA ±10 mA −1.0 V ON CHARACTERISTICS (Note 5) Gate Threshold Voltage Gate Threshold Temperature Coefficient Drain−to−Source On−Resistance VGS(TH)/TJ RDS(on) Forward Transconductance gFS −0.4 2.0 mV/°C VGS = −4.5 V, ID = −2.0 A 68 100 mW VGS = −2.5 V, ID = −2.0 A 90 144 VGS = −1.8 V, ID = −1.7 A 125 200 VDS = −5.0 V, ID = −2.0 A 6.5 S 450 pF CHARGES, CAPACITANCES AND GATE RESISTANCE CISS Input Capacitance Output Capacitance COSS Reverse Transfer Capacitance CRSS VGS = 0 V, f = 1.0 MHz, VDS = −10 V 90 62 Total Gate Charge QG(TOT) 5.2 Threshold Gate Charge QG(TH) 0.3 Gate−to−Source Charge QGS Gate−to−Drain Charge QGD 1.5 td(ON) 6.6 VGS = −4.5 V, VDS = −10 V, ID = −3.8 A 7.8 nC 0.84 SWITCHING CHARACTERISTICS (Note 6) Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time tr td(OFF) VGS = −4.5 V, VDD = −5.0 V, ID = −2.0 A, RG = 2.0 W tf ns 9.0 14 12.5 DRAIN−SOURCE DIODE CHARACTERISTICS Forward Recovery Voltage Reverse Recovery Time VSD TJ = 25°C −0.73 TJ = 125°C −0.62 tRR Charge Time ta Discharge Time tb Reverse Recovery Time VGS = 0 V, IS = −1.0 A −1.0 V 23 VGS = 0 V, dISD/dt = 100 A/ms, IS = −1.0 A QRR 13 10 5. Pulse Test: Pulse Width v 300 ms, Duty Cycle v 2%. 6. Switching characteristics are independent of operating junction temperatures. http://onsemi.com 3 ns 10 nC NTLJD3181PZ TYPICAL PERFORMANCE CURVES (TJ = 25°C unless otherwise noted) −ID, DRAIN CURRENT (AMPS) −2.0 V 6 −1.8 V −1.6 V 4 −1.4 V 2 −1.2 V 0 RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) 8 TJ = 25°C −2.2 V VGS = −2.5 V to −5 V −1.0 V 0 1 2 3 4 5 VDS ≥ 5 V 6 4 TJ = 25°C 2 TJ = 125°C 0 0 0.5 TJ = 125°C 0.08 0.06 TJ = 25°C 0.04 TJ = −55°C 0.02 2.0 2.5 4.0 6.0 8.0 TJ = 25°C 0.28 0.24 VGS = −1.8 V 0.20 0.16 VGS = −2.5 V 0.12 0.08 VGS = −4.5 V 0.04 0 1.5 100000 −IDSS, LEAKAGE (nA) 1.25 1.0 0.75 25 50 75 100 4.5 5.5 6.5 7.5 Figure 4. On−Resistance versus Drain Current and Gate Voltage VGS = 0 V ID = −2 A VGS = −4.5 V 0 3.5 2.5 −ID, DRAIN CURRENT (AMPS) Figure 3. On−Resistance versus Drain Current −25 3 0.32 −ID, DRAIN CURRENT (AMPS) RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) 2 Figure 2. Transfer Characteristics 0.1 0.5 −50 1.5 Figure 1. On−Region Characteristics VGS = −4.5 V 1.5 1 −VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) 0.12 1.75 TJ = −55°C −VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) −ID, DRAIN CURRENT (AMPS) 8 125 150 10000 TJ = 150°C 1000 100 TJ = 125°C 0 4 8 12 16 TJ, JUNCTION TEMPERATURE (°C) −VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−to−Source Leakage Current versus Voltage http://onsemi.com 4 20 NTLJD3181PZ TYPICAL PERFORMANCE CURVES (TJ = 25°C unless otherwise noted) TJ = 25°C VGS = 0 V -V GS, GATE-TO-SOURCE VOLTAGE (VOLTS) C, CAPACITANCE (pF) 600 Ciss 400 200 Coss 0 0 Crss 5 10 15 DRAIN−TO−SOURCE VOLTAGE (VOLTS) 20 Figure 7. Capacitance Variation 4 3 VGS QGS 2 QGD 1 0 ID = −3.8 A TJ = 25°C 0 1 3 5 2 4 QG, TOTAL GATE CHARGE (nC) 6 2 100 −IS, SOURCE CURRENT (AMPS) VDD = −5.0 V ID = −2.0 A VGS = −4.5 V td(off) tf tr 10 td(on) 1 10 RG, GATE RESISTANCE (OHMS) VGS = 0 V TJ = 25°C 1.5 1 0.5 0 0 100 Figure 9. Resistive Switching Time Variation versus Gate Resistance 0.6 0.2 0.4 0.8 −VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS) 10 100 ms 1 ms 10 ms 1 0.1 0.01 VGS = 20 V SINGLE PULSE TC = 25°C RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 1.0 Figure 10. Diode Forward Voltage versus Current 100 −ID, DRAIN CURRENT (AMPS) t, TIME (ns) QT Figure 8. Gate−To−Source and Drain−To−Source Voltage versus Total Charge 1000 1 5 dc 1 10 −VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 11. Maximum Rated Forward Biased Safe Operating Area http://onsemi.com 5 100 NTLJD3181PZ EFFECTIVE TRANSIENT THERMAL RESISTANCE TYPICAL PERFORMANCE CURVES (TJ = 25°C unless otherwise noted) 1000 100 D = 0.5 0.2 0.1 10 *See Note 2 on Page 1 P(pk) 0.05 0.02 1 0.01 t1 t2 DUTY CYCLE, D = t1/t2 SINGLE PULSE 0.1 0.000001 0.00001 0.0001 0.001 0.01 t, TIME (s) 0.1 Figure 12. Thermal Response http://onsemi.com 6 1 D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) − TA = P(pk) RqJA(t) 10 100 1000 NTLJD3181PZ PACKAGE DIMENSIONS WDFN6, 2x2 CASE 506AN−01 ISSUE D D ÇÇ ÇÇÇ ÇÇ ÉÉÉ ÉÉ A B EXPOSED Cu PLATING PIN ONE REFERENCE ÍÍÍ ÍÍÍ NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30 mm FROM THE TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. MOLD CMPD DETAIL B OPTIONAL CONSTRUCTIONS E DIM A A1 A3 b D D2 E E2 e F K L L1 0.10 C 0.10 C TOP VIEW L1 DETAIL A A3 DETAIL B 0.10 C L L OPTIONAL CONSTRUCTIONS A 0.08 C NOTE 4 A1 C SIDE VIEW 0.10 C A SOLDERMASK DEFINED MOUNTING FOOTPRINT SEATING PLANE 1.74 B 1 3 1.10 6X DETAIL A E2 6 K 4 2X 0.77 D2 F D2 L MILLIMETERS MIN MAX 0.70 0.80 0.00 0.05 0.20 REF 0.25 0.35 2.00 BSC 0.57 0.67 2.00 BSC 0.90 1.10 0.65 BSC 0.15 BSC 0.25 REF 0.20 0.30 --0.10 6X 0.47 2.30 0.10 C A B PACKAGE OUTLINE b 0.10 C A e 0.05 C 1 B NOTE 3 6X BOTTOM VIEW 0.35 0.65 PITCH DIMENSIONS: MILLIMETERS mCool is a trademark of Semiconductor Components Industries, LLC (SCILLC). ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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