Cypress CY8C20424-12LQXIT Capsense psoc programmable system-on-chip Datasheet

CY8C20224, CY8C20324
CY8C20424, CY8C20524
CapSense™ PSoC® Programmable
System-on-Chip™
Features
■
Low Power, Configurable CapSense™
❐ Configurable capacitive sensing elements
❐ 2.4V to 5.25V operating voltage
❐ Low operating current
• Active 1.5 mA (at 3.0V, 12 MHz)
• Sleep 2.8 μA (at 3.3V)
❐ Supports up to 25 capacitive buttons
❐ Supports one slider
❐ Up to 10 cm proximity sensing
❐ Supports up to 28 General Purpose IO (GPIO) pins
• Drive LEDs and other outputs
❐ Configurable LED behavior (fading, strobing)
❐ LED color mixing (RBG LEDs)
❐ Pull Up, High Z, Open Drain, and CMOS drive modes on all
GPIO
❐ Internal ±5.0% 6 or12 MHz main oscillator
❐ Internal low speed oscillator at 32 kHz
❐ Low external component count
• No external crystal or oscillator components
• No external voltage regulator required
■
High Performance CapSense
❐ Ultra fast scan speed—1 kHz (nominal)
❐ Reliable finger detection through 5 mm thick acrylic
❐ Excellent EMI and AC noise immunity
■
Industry Best Flexibility
❐ 8K Flash program storage 50,000 Erase and Write cycles
❐ 512 bytes SRAM data storage
❐ Bootloader for ease of field reprogramming
❐ Partial Flash updates
❐ Flexible Flash protection modes
❐ Interrupt controller
❐ In-System Serial Programming (ISSP)
❐ Free complete development tool (PSoC Designer™)
❐ Full Featured, In-Circuit Emulator and Programmer
• Full speed emulation
• Complex breakpoint structure
• 128K trace memory
■
Additional System Resources
❐ Configurable communication speeds
2
❐ I C Slave
❐ SPI Master and SPI Slave
❐ Watchdog and Sleep timers
❐ Internal voltage reference
❐ Integrated supervisory circuit
Logic Block Diagram
Port 3
Port 2
Port 1
Port 0
3V LDO
PSoC
CORE
System Bus
Global Analog Interconnect
SRAM
512 Bytes
SROM
Flash 8K
CPU Core
(M8C)
Interrupt
Controller
Sleep and
Watchdog
6/12 MHz Internal Main Oscillator
ANALOG
SYSTEM
I2C Slave/SPI
Master-Slave
CapSense
Basic
Block
Analog
Ref.
POR and LVD
System Resets
Analog
Mux
SYSTEM RESOURCES
Cypress Semiconductor Corporation
Document Number: 001-41947 Rev. *D
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised April 15, 2009
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The PSoC family consists of many mixed-signal arrays with
on-chip controller devices. These devices are designed to
replace multiple traditional MCU based system components with
one, low cost single chip programmable component. A PSoC
device includes configurable analog and digital blocks, and
programmable interconnect. This architecture allows the user to
create customized peripheral configurations, to match the
requirements of each individual application. Additionally, a fast
CPU, Flash program memory, SRAM data memory, and configurable IO are included in a range of convenient pinouts.
The PSoC architecture for this device family is comprised of
three main areas: Core, System Resources, and CapSense
Analog System. A common, versatile bus allows connection
between IO and the analog system. Each PSoC device includes
a dedicated CapSense block that provides sensing and scanning
control circuitry for capacitive sensing applications. Depending
on the PSoC package, up to 28 general purpose IO (GPIO) are
also included. The GPIO provide access to the MCU and analog
mux.
Figure 1. Analog System Block Diagram
IDAC
Analog Global Bus
PSoC® Functional Overview
Vr
Reference
Buffer
Comparator
Cinternal
Mux
Mux
Refs
PSoC Core
The PSoC Core is a powerful engine that supports a rich
instruction set. It encompasses SRAM for data storage, an
interrupt controller, sleep and watchdog timers, and IMO
(internal main oscillator) and ILO (internal low speed oscillator).
The CPU core, called the M8C, is a powerful processor with
speeds up to 12 MHz. The M8C is a 2-MIPS, 8-bit Harvard
architecture microprocessor.
Cap Sense Counters
CSCLK
IMO
System Resources provide additional capability, such as a
configurable I2C slave or SPI master-slave communication
interface and various system resets supported by the M8C.
The Analog System is composed of the CapSense PSoC block
and an internal 1.8V analog reference. Together, they support
capacitive sensing of up to 28 inputs.
CapSense Analog System
The Analog System contains the capacitive sensing hardware.
Several hardware algorithms are supported. This hardware
performs capacitive sensing and scanning without requiring
external components. Capacitive sensing is configurable on
each GPIO pin. Scanning of enabled CapSense pins are
completed quickly and easily across multiple ports.
CapSense
Clock Select
Relaxation
Oscillator
(RO)
Analog Multiplexer System
The Analog Mux Bus connects to every GPIO pin. Pins are
connected to the bus individually or in any combination. The bus
also connects to the analog system for analysis with the
CapSense block comparator.
Switch control logic enables selected pins to precharge
continuously under hardware control. This enables capacitive
measurement for applications such as touch sensing. The
Analog Multiplexer System in the device family is optimized for
basic CapSense functionality. It supports sensing of CapSense
buttons, proximity sensors, and a single slider. Other multiplexer
applications include:
■
Capacitive slider interface.
■
Chip-wide mux that allows analog input from any IO pin.
■
Crosspoint connection between any IO pin combinations.
When designing capacitive sensing applications, refer to the
latest signal to noise signal level requirements application notes,
which are found in http://www.cypress.com > DESIGN
RESOURCES > Application Notes. In general, and unless
otherwise noted in the relevant application notes, the minimum
signal-to-noise ratio (SNR) requirement for CapSense
applications is 5:1.
Document Number: 001-41947 Rev. *D
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Typical Application
Figure 2 illustrates a typical application: CapSense multimedia
keys for a notebook computer with a slider, four buttons, and four
LEDs.
Figure 2. CapSense Multimedia Button-Board Application
Getting Started
The quickest way to understand PSoC silicon is to read this data
sheet and then use the PSoC Designer Integrated Development
Environment (IDE). This data sheet is an overview of the PSoC
integrated circuit and presents specific pin, register, and
electrical specifications.
For in depth information, along with detailed programming information, see the PSoC® Programmable System-on-Chip
Technical Reference Manual for CY8C28xxx PSoC devices.
For up-to-date ordering, packaging, and electrical specification
information, see the latest PSoC device data sheets on the web
at www.cypress.com/psoc.
Application Notes
Additional System Resources
System Resources, some of which are previously listed, provide
additional capability useful to complete systems. Additional
resources include low voltage detection and power on reset.
Brief statements describing the merits of each system resource
follow.
■
The I2C slave and SPI master-slave module provides 50, 100,
or 400 kHz communication over two wires. SPI communication
over three or four wires runs at speeds of 46.9 kHz to 3 MHz
(lower for a slower system clock).
■
Low Voltage Detection (LVD) interrupts signal the application
of falling voltage levels, while the advanced POR (Power On
Reset) circuit eliminates the need for a system supervisor.
■
An internal 1.8V reference provides an absolute reference for
capacitive sensing.
■
The 5V maximum input, 3V fixed output, low dropout regulator
(LDO) provides regulation for IOs. A register controlled bypass
mode allows the user to disable the LDO.
Application notes are an excellent introduction to the wide variety
of possible PSoC designs. They are located here:
www.cypress.com/psoc. Select Application Notes under the
Documentation tab.
Development Kits
PSoC Development Kits are available online from Cypress at
www.cypress.com/shop and through a growing number of
regional and global distributors, which include Arrow, Avnet,
Digi-Key, Farnell, Future Electronics, and Newark.
Training
Free PSoC technical training (on demand, webinars, and
workshops) is available online at www.cypress.com/training. The
training covers a wide variety of topics and skill levels to assist
you in your designs.
Cypros Consultants
Certified PSoC Consultants offer everything from technical
assistance to completed PSoC designs. To contact or become a
PSoC Consultant go to www.cypress.com/cypros.
Solutions Library
Visit our growing library of solution focused designs at
www.cypress.com/solutions. Here you can find various application designs that include firmware and hardware design files
that enable you to complete your designs quickly.
Technical Support
For assistance with technical issues, search KnowledgeBase
articles and forums at www.cypress.com/support. If you cannot
find an answer to your question, call technical support at
1-800-541-4736.
Document Number: 001-41947 Rev. *D
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Development Tools
PSoC Designer is a Microsoft® Windows-based, integrated
development
environment
for
the
Programmable
System-on-Chip (PSoC) devices. The PSoC Designer IDE runs
on Windows XP or Windows Vista.
This system provides design database management by project,
an integrated debugger with In-Circuit Emulator, in-system
programming support, and built-in support for third-party
assemblers and C compilers.
PSoC Designer also supports C language compilers developed
specifically for the devices in the PSoC family.
PSoC Designer Software Subsystems
System-Level View
A drag-and-drop visual embedded system design environment
based on PSoC Express. In the system level view you create a
model of your system inputs, outputs, and communication interfaces. You define when and how an output device changes state
based upon any or all other system devices. Based upon the
design, PSoC Designer automatically selects one or more PSoC
Mixed-Signal Controllers that match your system requirements.
PSoC Designer generates all embedded code, then compiles
and links it into a programming file for a specific PSoC device.
Chip-Level View
The chip-level view is a more traditional integrated development
environment (IDE) based on PSoC Designer 4.4. Choose a base
device to work with and then select different onboard analog and
digital components called user modules that use the PSoC
blocks. Examples of user modules are ADCs, DACs, Amplifiers,
and Filters. Configure the user modules for your chosen
application and connect them to each other and to the proper
pins. Then generate your project. This prepopulates your project
with APIs and libraries that you can use to program your
application.
The device editor also supports easy development of multiple
configurations and dynamic reconfiguration. Dynamic
configuration allows for changing configurations at run time.
Hybrid Designs
You can begin in the system-level view, allow it to choose and
configure your user modules, routing, and generate code, then
switch to the chip-level view to gain complete control over
on-chip resources. All views of the project share a common code
editor, builder, and common debug, emulation, and programming
tools.
Document Number: 001-41947 Rev. *D
Code Generation Tools
PSoC Designer supports multiple third party C compilers and
assemblers. The code generation tools work seamlessly within
the PSoC Designer interface and have been tested with a full
range of debugging tools. The choice is yours.
Assemblers. The assemblers allow assembly code to merge
seamlessly with C code. Link libraries automatically use absolute
addressing or are compiled in relative mode, and linked with
other software modules to get absolute addressing.
C Language Compilers. C language compilers are available
that support the PSoC family of devices. The products allow you
to create complete C programs for the PSoC family devices.
The optimizing C compilers provide all the features of C tailored
to the PSoC architecture. They come complete with embedded
libraries providing port and bus operations, standard keypad and
display support, and extended math functionality.
Debugger
The PSoC Designer Debugger subsystem provides hardware
in-circuit emulation, allowing you to test the program in a physical
system while providing an internal view of the PSoC device.
Debugger commands allow the designer to read and program
and read and write data memory, read and write IO registers,
read and write CPU registers, set and clear breakpoints, and
provide program run, halt, and step control. The debugger also
allows the designer to create a trace buffer of registers and
memory locations of interest.
Online Help System
The online help system displays online, context-sensitive help
for the user. Designed for procedural and quick reference, each
functional subsystem has its own context-sensitive help. This
system also provides tutorials and links to FAQs and an Online
Support Forum to aid the designer in getting started.
In-Circuit Emulator
A low cost, high functionality In-Circuit Emulator (ICE) is
available for development support. This hardware has the
capability to program single devices.
The emulator consists of a base unit that connects to the PC by
way of a USB port. The base unit is universal and operates with
all PSoC devices. Emulation pods for each device family are
available separately. The emulation pod takes the place of the
PSoC device in the target board and performs full speed
(24 MHz) operation.
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Designing with PSoC Designer
The development process for the PSoC device differs from that
of a traditional fixed function microprocessor. The configurable
analog and digital hardware blocks give the PSoC architecture a
unique flexibility that pays dividends in managing specification
change during development and by lowering inventory costs.
These configurable resources, called PSoC Blocks, have the
ability to implement a wide variety of user-selectable functions.
The PSoC development process can be summarized in the
following four steps:
1. Select components
2. Configure components
3. Organize and Connect
4. Generate, Verify, and Debug
Select Components
Both the system-level and chip-level views provide a library of
prebuilt, pretested hardware peripheral components. In the
system-level view, these components are called “drivers” and
correspond to inputs (a thermistor, for example), outputs (a
brushless DC fan, for example), communication interfaces
(I2C-bus, for example), and the logic to control how they interact
with one another (called valuators).
In the chip-level view, the components are called “user modules”.
User modules make selecting and implementing peripheral
devices simple, and come in analog, digital, and mixed signal
varieties.
Configure Components
Each of the components you select establishes the basic register
settings that implement the selected function. They also provide
parameters and properties that allow you to tailor their precise
configuration to your particular application. For example, a Pulse
Width Modulator (PWM) User Module configures one or more
digital PSoC blocks, one for each 8 bits of resolution. The user
module parameters permit you to establish the pulse width and
duty cycle. Configure the parameters and properties to
correspond to your chosen application. Enter values directly or
by selecting values from drop-down menus.
Both the system-level drivers and chip-level user modules are
documented in data sheets that are viewed directly in PSoC
Designer. These data sheets explain the internal operation of the
component and provide performance specifications. Each data
sheet describes the use of each user module parameter or driver
Document Number: 001-41947 Rev. *D
property, and other information you may need to successfully
implement your design.
Organize and Connect
You can build signal chains at the chip level by interconnecting
user modules to each other and the IO pins, or connect system
level inputs, outputs, and communication interfaces to each
other with valuator functions.
In the system-level view, selecting a potentiometer driver to
control a variable speed fan driver and setting up the valuators
to control the fan speed based on input from the pot selects,
places, routes, and configures a programmable gain amplifier
(PGA) to buffer the input from the potentiometer, an analog to
digital converter (ADC) to convert the potentiometer’s output to
a digital signal, and a PWM to control the fan.
In the chip-level view, perform the selection, configuration, and
routing so that you have complete control over the use of all
on-chip resources.
Generate, Verify, and Debug
When you are ready to test the hardware configuration or move
on to developing code for the project, perform the “Generate
Application” step. This causes PSoC Designer to generate
source code that automatically configures the device to your
specification and provides the software for the system.
Both system-level and chip-level designs generate software
based on your design. The chip-level design provides application
programming interfaces (APIs) with high level functions to
control and respond to hardware events at run-time and interrupt
service routines that you can adapt as needed. The system-level
design also generates a C main() program that completely
controls the chosen application and contains placeholders for
custom code at strategic positions allowing you to further refine
the software without disrupting the generated code.
A complete code development environment allows you to
develop and customize your applications in C, assembly
language, or both.
The last step in the development process takes place inside
PSoC Designer’s Debugger subsystem. The Debugger
downloads the and HEX image to the ICE where it runs at full
speed. Debugger capabilities rival those of systems costing
many times more. In addition to traditional single-step,
run-to-breakpoint and watch-variable features, the Debugger
provides a large trace buffer and allows you define complex
breakpoint events that include monitoring address and data bus
values, memory locations and external signals.
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Document Conventions
Units of Measure
Acronyms Used
A units of measure table is located in the Electrical Specifications
section. Table 7 on page 13 lists all the abbreviations used to
measure the PSoC devices.
The following table lists the acronyms that are used in this
document.
Table 1. List of Acronyms
Acronym
Description
AC
Alternating Current
API
Application Programming Interface
CPU
Central Processing Unit
DC
Direct Current
GPIO
General Purpose IO
GUI
Graphical User Interface
ICE
In-Circuit Emulator
ILO
Internal Low Speed Oscillator
IMO
Internal Main Oscillator
IO
Input And Output
LSb
Least Significant Bit
LVD
Low Voltage Detect
MSb
Most Significant Bit
POR
Power On Reset
PPOR
Precision Power On Reset
PSoC®
Programmable System-on-Chip®
SLIMO
Slow IMO
SRAM
Static Random Access Memory
Document Number: 001-41947 Rev. *D
Numeric Naming
Hexadecimal numbers are represented with all letters in
uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or
‘3Ah’). Hexadecimal numbers may also be represented by a ‘0x’
prefix, the C coding convention. Binary numbers have an
appended lowercase ‘b’ (for example, 01010100b’ or
‘01000011b’). Numbers not indicated by an ‘h’, ‘b’, or 0x are
decimal.
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Pinouts
This section describes, lists, and illustrates the CY8C20224, CY8C20324, CY8C20424, and CY8C20524 PSoC device pins and pinout
configurations.
The PSoC device is available in a variety of packages which are listed and illustrated in the following tables. Every port pin (labeled
with a “P”) is capable of Digital IO and connection to the common analog bus. However, Vss, Vdd, and XRES are not capable of Digital
IO.
16-Pin Part Pinout
P0[1], AI
P0[3], AI
P0[7], AI
Vdd
15
14
13
12
QFN
11
(T o p V ie w )
6
7
8
Vss
AI, DATA, I2C SDA, P1[0]
10
9
5
1
2
3
4
AI, SPI CLK, P1[3]
A I, P 2 [1 ]
A I, I2 C S C L , S P I S S , P 1 [7 ]
A I, I2 C S D A , S P I M IS O , P 1 [5 ]
CLK, I2C SCL, SPI MOSI P1[1]
A I, P 2 [5 ]
16
Figure 3. CY8C20224 16-Pin PSoC Device
P 0 [4 ], A I
XRES
P 1 [4 ], A I, E X T C L K
P 1 [2 ], A I
Table 2. 16-Pin Part Pinout (COL)
Pin No.
1
2
3
Digital
IO
IO
IOH
Analog
I
I
I
Name
P2[5]
P2[1]
P1[7]
4
IOH
I
P1[5]
5
6
IOH
IOH
I
I
P1[3]
P1[1]
IOH
I
Vss
P1[0]
IOH
IOH
I
I
7
8
9
10
11
12
13
14
15
16
Power
Input
IO
I
Power
IO
IO
IO
I
I
I
P1[2]
P1[4]
XRES
P0[4]
Vdd
P0[7]
P0[3]
P0[1]
Description
I2C SCL, SPI SS
I2C SDA, SPI MISO
SPI CLK
CLK[1], I2C SCL, SPI MOSI
Ground connection
DATA[1], I2C SDA
Optional external clock input (EXTCLK)
Active high external reset with internal pull down
Supply voltage
Integrating input
Integrating input
A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive
Note
1. These are the ISSP pins, that are not High Z at POR (Power On Reset). Refer the PSoC Programmable System-on-Chip Technical Reference Manual for details.
Document Number: 001-41947 Rev. *D
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24-Pin Part Pinout
20
19
10
11
12
P0[7], AI
Vdd
P0[6], AI
P0[1], AI
P0[3], AI
P0[5], AI
23
22
21
18
17
16
15
14
13
P0[4], AI
P0[2], AI
P0[0], AI
P2[0], AI
XRES
P1[6], AI
AI, EXTCLK, P1[4]
Vss
AI, DATA*, I2C SDA, P1[0]
AI, P1[2]
7
8
9
1
2
QFN
3
4 (Top View)
5
6
NC
P2[5]
P2[3]
P2[1]
P1[7]
P1[5]
P1[3]
AI, CLK*, I2C SCL
SPI MOSI, P1[1]
AI,
AI,
AI,
AI, I2C SCL, SPI SS,
AI, I2C SDA, SPI MISO,
AI, SPI CLK,
24
Figure 4. CY8C20324 24-Pin PSoC Device
Table 3. 24-Pin Part Pinout (QFN [2])
Pin No.
1
2
3
4
Digital
IO
IO
IO
IOH
Analog
I
I
I
I
Name
P2[5]
P2[3]
P2[1]
P1[7]
5
IOH
I
P1[5]
6
7
IOH
IOH
I
I
P1[3]
P1[1]
IOH
I
NC
Vss
P1[0]
IOH
IOH
IOH
I
I
I
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
CP
Power
Input
IO
IO
IO
IO
IO
I
I
I
I
I
Power
IO
IO
IO
IO
I
I
I
I
Power
P1[2]
P1[4]
P1[6]
XRES
P2[0]
P0[0]
P0[2]
P0[4]
P0[6]
Vdd
P0[7]
P0[5]
P0[3]
P0[1]
Vss
Description
I2C SCL, SPI SS
I2C SDA, SPI MISO
SPI CLK
CLK[1], I2C SCL, SPI MOSI
No connection
Ground connection
DATA[1], I2C SDA
Optional external clock input (EXTCLK)
Active high external reset with internal pull down
Supply voltage
Integrating input
Integrating input
Center pad is connected to ground
A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive
Note
2. The center pad on the QFN package is connected to ground (Vss) for best mechanical, thermal, and electrical performance. If not connected to ground, it is
electrically floated and not connected to any other signal.
Document Number: 001-41947 Rev. *D
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28-Pin Part Pinout
Figure 5. CY8C20524 28-Pin PSoC Device
Table 4. 28-Pin Part Pinout (SSOP)
Pin No.
1
2
3
4
5
6
7
8
9
10
Digital
Analog
IO
I
IO
I
IO
I
IO
I
IO
I
IO
I
IO
I
IO
I
Power
IOH
I
Name
P0[7]
P0[5]
P0[3]
P0[1]
P2[7]
P2[5]
P2[3]
P2[1]
Vss
P1[7]
11
IOH
I
P1[5]
12
13
IOH
IOH
I
I
P1[3]
P1[1]
14
15
IOH
I
Vss
P1[0]
IOH
IOH
IOH
I
I
I
16
17
18
19
20
21
22
23
24
25
26
27
28
Power
Input
IO
IO
IO
IO
IO
IO
IO
IO
I
I
I
I
I
I
I
I
Power
P1[2]
P1[4]
P1[6]
XRES
P2[0]
P2[2]
P2[4]
P2[6]
P0[0]
P0[2]
P0[4]
P0[6]
Vdd
Description
Integrating Input
Integrating Input
Ground connection
I2C SCL, SPI SS
I2C SDA, SPI MISO
SPI CLK
CLK[1], I2C SCL, SPL MOSI
Ground connection
Data[1], I2C SDA
Optional External Clock Input (EXTCLK)
Active high external reset with internal pull down
Supply voltage
A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive
Document Number: 001-41947 Rev. *D
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32-Pin Part Pinout
Vdd
P0[6], AI
P0[4], AI
P0[2], AI
26
25
15
16
P0[7], AI
29
27
P0[5], AI
30
28
Vss
P0[3], AI
31
9
11
12
13
14
AI, CLK*, I2C SCL, SPI MOSI, P1[1]
Vss
AI, DATA*, I2C SDA, P1[0]
AI, P1[2]
AI, EXTCLK, P1[4]
AI, P1[6]
A I, I2 C S C L
Q FN
(T o p V ie w )
24
23
22
21
20
19
18
17
10
A I, P 3 [1 ]
S P I S S , P 1 [7 ]
1
2
3
4
5
6
7
8
AI, SPI CLK, P1[3]
P 0 [1 ]
P 2 [7 ]
P 2 [5 ]
P 2 [3 ]
P 2 [1 ]
P 3 [3 ]
AI, I2C SDA, SPI MISO, P1[5]
A I,
A I,
A I,
A I,
A I,
A I,
32
Figure 6. CY8C20424 32-Pin PSoC Device
P 0 [0 ], A I
P 2 [6 ], A I
P 2 [4 ], A I
P 2 [2 ], A I
P 2 [0 ], A I
P 3 [2 ], A I
P 3 [0 ], A I
XRES
Table 5. 32-Pin Part Pinout (QFN [2])
Pin No.
Digital
Analog
Name
1
IO
I
P0[1]
2
IO
I
P2[7]
3
IO
I
P2[5]
4
IO
I
P2[3]
5
IO
I
P2[1]
6
IO
I
P3[3]
7
IO
I
P3[1]
8
IOH
I
P1[7]
I2C SCL, SPI SS
9
IOH
I
P1[5]
I2C SDA, SPI MISO
10
IOH
I
P1[3]
SPI CLK
11
IOH
I
P1[1]
CLK[1], I2C SCL, SPI MOSI
12
Power
Vss
13
IOH
I
P1[0]
14
IOH
I
P1[2]
15
IOH
I
P1[4]
16
IOH
I
P1[6]
17
Input
XRES
18
IO
I
P3[0]
19
IO
I
P3[2]
20
IO
I
P2[0]
21
IO
I
P2[2]
22
IO
I
P2[4]
23
IO
I
P2[6]
24
IO
I
P0[0]
25
IO
I
P0[2]
Document Number: 001-41947 Rev. *D
Description
Integrating Input
Ground connection
DATA[1], I2C SDA
Optional external clock input (EXTCLK)
Active high external reset with internal pull down
Page 10 of 34
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CY8C20424, CY8C20524
Table 5. 32-Pin Part Pinout (QFN [2]) (continued)
Pin No.
Digital
Analog
Name
26
IO
I
P0[4]
27
IO
I
P0[6]
28
Power
Vdd
29
IO
I
P0[7]
30
IO
I
P0[5]
31
IO
I
P0[3]
Description
Supply voltage
Integrating input
32
Power
Vss
Ground connection
CP
Power
Vss
Center pad is connected to ground
A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive
48-Pin OCD Part Pinout
The 48-Pin QFN part table and pin diagram is for the CY8C20024 On-Chip Debug (OCD) PSoC device. This part is only used for
in-circuit debugging. It is NOT available for production.
NC
NC
38
37
22
23
24
NC
AI, P1[2]
20
21
AI, DATA*, I2C SDA, P1[0]
HCLK
18
19
CCLK
17
15
16
AI, CLK*, I2C SCL, SPI MOSI, P1[1]
Vss
AI, SPI CLK, P1[3]
(Top View)
36
35
34
33
32
31
30
29
28
27
26
25
P0[4], AI
P0[2], AI
P0[0], AI
P2[6], AI
P2[4], AI
P2[2], AI
P2[0], AI
P3[2], AI
P3[0], AI
XRES
P1[6], AI
P1[4], EXTCLK, AI
NC
NC
OCDO
Vdd
P0[6], AI
NC
OCDE
42
41
40
39
P0[7], AI
43
P0[5], AI
45
44
46
OCD
QFN
13
14
1
2
3
4
5
6
7
8
9
10
11
12
NC
NC
NC
AI, P0[1]
AI, P2[7]
AI, P2[5]
AI, P2[3]
AI, P2[1]
AI, P3[3]
AI, P3[1]
AI, I2C SCL, SPI SS, P1[7]
AI, I2C SDA, SPI MISO, P1[5]
NC
NC
48
47
NC
Vss
P0[3], AI
Figure 7. CY8C20024 OCD PSoC Device
Table 6. 48-Pin OCD Part Pinout (QFN [2])
Pin No.
Digital
Analog
Name
2
IO
I
P0[1]
3
IO
I
P2[7]
4
IO
I
P2[5]
5
IO
I
P2[3]
6
IO
I
P2[1]
7
IO
I
P3[3]
8
IO
I
P3[1]
9
IOH
I
P1[7]
1
NC
Document Number: 001-41947 Rev. *D
Description
No connection
Integrating Input
I2C SCL, SPI SS
Page 11 of 34
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CY8C20424, CY8C20524
Table 6. 48-Pin OCD Part Pinout (QFN [2]) (continued)
Pin No.
Digital
Analog
Name
10
IOH
I
P1[5]
Description
2
I C SDA, SPI MISO
11
NC
No connection
12
NC
No connection
13
NC
No connection
14
NC
No connection
15
IOH
I
P1[3]
SPI CLK
16
IOH
I
P1[1]
CLK[1], I2C SCL, SPI MOSI
17
Power
Vss
Ground connection
18
CCLK
OCD CPU clock output
19
HCLK
OCD high speed clock output
DATA[1], I2C SDA
20
IOH
I
P1[0]
21
IOH
I
P1[2]
22
NC
No connection
23
NC
No connection
24
NC
No connection
25
IOH
I
P1[4]
26
IOH
I
P1[6]
27
Input
XRES
28
IO
I
P3[0]
29
IO
I
P3[2]
30
IO
I
P2[0]
31
IO
I
P2[2]
32
IO
I
P2[4]
33
IO
I
P2[6]
34
IO
I
P0[0]
35
IO
I
P0[2]
36
IO
I
P0[4]
Optional external clock input (EXTCLK)
Active high external reset with internal pull down
37
NC
No connection
38
NC
No connection
NC
No connection
39
40
IO
41
I
Power
P0[6]
Vdd
42
43
OCD odd data output
OCDE
OCD even data IO
44
IO
I
P0[7]
45
IO
I
P0[5]
46
IO
I
P0[3]
47
Power
48
CP
Power
Supply voltage
OCDO
Integrating input
Vss
Ground connection
NC
No connection
Vss
Center pad is connected to ground
A = Analog, I = Input, O = Output, NC = No Connection H = 5 mA High Output Drive.
Document Number: 001-41947 Rev. *D
Page 12 of 34
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CY8C20224, CY8C20324
CY8C20424, CY8C20524
Electrical Specifications
This section presents the DC and AC electrical specifications of the CY8C20224, CY8C20324, CY8C20424, and CY8C20524 PSoC
devices. For the latest electrical specifications, visit the web at http://www.cypress.com/psoc.
Specifications are valid for -40oC ≤ TA ≤ 85oC and TJ ≤ 100oC as specified, except where noted.
Refer to Table 17 on page 19 for the electrical specifications on the internal main oscillator (IMO) using SLIMO mode.
Figure 8. Voltage versus CPU Frequency and IMO Frequency Trim Options
5.25
5.25
SLIMO SLIMO SLIMO
Mode=1 Mode=1 Mode=0
4.75
Vdd Voltage
Vdd Voltage
lid ng
Va rati n
pe gio
Re
O
4.75
3.60
3.00
3.00
2.70
2.70
2.40
2.40
750 kHz
3 MHz
6 MHz
SLIMO SLIMO
Mode=1 Mode=0
750 kHz
12 MHz
3 MHz
SLIMO
Mode=1
SLIMO
Mode=0
6 MHz
12 MHz
IMO Frequency
CPU Frequency
The following table lists the units of measure that are used in this section.
Table 7. Units of Measure
Symbol
oC
dB
fF
Hz
KB
Kbit
kHz
kΩ
MHz
MΩ
μA
μF
μH
μs
μV
μVrms
Unit of Measure
degree Celsius
decibels
femto farad
hertz
1024 bytes
1024 bits
kilohertz
kilohm
megahertz
megaohm
microampere
microfarad
microhenry
microsecond
microvolts
microvolts root-mean-square
Document Number: 001-41947 Rev. *D
Symbol
μW
mA
ms
mV
nA
ns
nV
Ω
pA
pF
pp
ppm
ps
sps
s
V
Unit of Measure
microwatts
milli-ampere
milli-second
milli-volts
nanoampere
nanosecond
nanovolts
ohm
picoampere
picofarad
peak-to-peak
parts per million
picosecond
samples per second
sigma: one standard deviation
volts
Page 13 of 34
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CY8C20424, CY8C20524
Absolute Maximum Ratings
Table 8. Absolute Maximum Ratings
Symbol
TSTG
Description
Storage Temperature
Min
-55
Typ
25
Max
+100
TA
Vdd
VIO
Ambient Temperature with Power Applied
Supply Voltage on Vdd Relative to Vss
DC Input Voltage
–
–
–
VIOZ
DC Voltage Applied to Tri-state
IMIO
ESD
LU
Maximum Current into any Port Pin
Electro Static Discharge Voltage
Latch-up Current
-40
-0.5
Vss 0.5
Vss 0.5
-25
2000
–
–
–
–
+85
+6.0
Vdd +
0.5
Vdd +
0.5
+50
–
200
mA
V
mA
Min
-40
-40
Typ
–
–
Max
+85
+100
Units
oC
oC
–
Units
o
C
Notes
Higher storage temperatures
reduces data retention time.
Recommended storage temperature is +25oC ± 25oC. Extended
duration storage temperatures
above 65oC degrades reliability.
o
C
V
V
V
Human Body Model ESD.
Operating Temperature
Table 9. Operating Temperature
Symbol
TA
TJ
Description
Ambient Temperature
Junction Temperature
Document Number: 001-41947 Rev. *D
Notes
The temperature rise from ambient
to junction is package specific. See
Table 32 on page 29. The user must
limit the power consumption to
comply with this requirement.
Page 14 of 34
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CY8C20424, CY8C20524
DC Electrical Characteristics
DC Chip Level Specifications
Table 10 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to
5V, 3.3V, or 2.7V at 25°C. These are for design guidance only.
Table 10. DC Chip Level Specifications
Symbol
Description
Vdd
Supply Voltage
IDD12
Supply Current, IMO = 12 MHz
Min
2.40
–
Typ
–
1.5
Max
5.25
2.5
IDD6
Supply Current, IMO = 6 MHz
–
1
1.5
ISB27
Sleep (Mode) Current with POR, LVD, Sleep
Timer, WDT, and Internal Slow Oscillator Active.
Mid Temperature Range.
Sleep (Mode) Current with POR, LVD, Sleep
Timer, WDT, and Internal Slow Oscillator Active.
–
2.6
4
–
2.8
5
ISB
Units
Notes
V
mA Conditions are Vdd = 3.0V,
TA = 25oC, CPU = 12 MHz.
mA Conditions are Vdd = 3.0V,
TA = 25oC, CPU = 6 MHz.
μA Vdd = 2.55V, 0oC ≤ TA ≤ 40oC.
μA
Vdd = 3.3V, -40oC ≤ TA ≤ 85oC.
DC General Purpose IO Specifications
Unless otherwise noted, Table 11 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges:
4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively.
Typical parameters apply to 5V, 3.3V, and 2.7V at 25°C. These are for design guidance only.
Table 11. 5V and 3.3V DC GPIO Specifications
Symbol
Description
Min
Typ
Max
Units
4
5.6
8
kΩ
High Output Voltage
Port 0, 2, or 3 Pins
Vdd - 0.2
–
–
V
IOH < 10 μA, Vdd > 3.0V, maximum
of 20 mA source current in all IOs.
VOH2
High Output Voltage
Port 0, 2, or 3 Pins
Vdd - 0.9
–
–
V
IOH = 1 mA, Vdd > 3.0V, maximum
of 20 mA source current in all IOs.
VOH3
High Output Voltage
Port 1 Pins with LDO Regulator Disabled
Vdd - 0.2
–
–
V
IOH < 10 μA, Vdd > 3.0V, maximum
of 10 mA source current in all IOs.
VOH4
High Output Voltage
Port 1 Pins with LDO Regulator Disabled
Vdd - 0.9
–
–
V
IOH = 5 mA, Vdd > 3.0V, maximum
of 20 mA source current in all IOs.
VOH5
High Output Voltage
Port 1 Pins with 3.0V LDO Regulator Enabled
2.7
3.0
3.3
V
IOH<10 uA, Vdd > 3.1V, maximum
of 4 IOs all sourcing 5 mA.
VOH6
High Output Voltage
Port 1 Pins with 3.0V LDO Regulator Enabled
2.2
–
–
V
IOH = 5 mA, Vdd > 3.1V, maximum
of 20 mA source current in all IOs.
VOH7
High Output Voltage
Port 1 Pins with 2.4V LDO Regulator Enabled
2.1
2.4
2.7
V
IOH < 10 μA, Vdd > 3.0V, maximum
of 20 mA source current in all IOs.
VOH8
High Output Voltage
Port 1 Pins with 2.4V LDO Regulator Enabled
2.0
–
–
V
IOH < 200 μA, Vdd > 3.0V,
maximum of 20 mA source current
in all IOs.
VOH9
High Output Voltage
Port 1 Pins with 1.8V LDO Regulator Enabled
1.6
1.8
2.0
V
IOH < 10 μA
3.0V ≤ Vdd ≤ 3.6V
0oC ≤ TA ≤ 85oC
Maximum of 20 mA source current
in all IOs.
RPU
Pull Up Resistor
VOH1
Document Number: 001-41947 Rev. *D
Notes
Page 15 of 34
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CY8C20424, CY8C20524
Table 11. 5V and 3.3V DC GPIO Specifications (continued)
Symbol
Description
Min
Typ
Max
Units
Notes
1.5
–
–
V
IOH < 100 μA
3.0V ≤ Vdd ≤ 3.6V
0oC ≤ TA ≤ 85oC
Maximum of 20 mA source current
in all IOs.
VOH10
High Output Voltage
Port 1 Pins with 1.8V LDO Regulator Enabled
VOL
Low Output Voltage
–
–
0.75
V
IOL = 20 mA, Vdd > 3.0V,
maximum of 60 mA sink current on
even port pins (for example, P0[2]
and P1[4]) and 60 mA sink current
on odd port pins (for example,
P0[3] and P1[5]).
VIL
Input Low Voltage
–
–
0.8
V
3.0V ≤ Vdd ≤ 5.25V
VIH
Input High Voltage
2.0
–
V
3.0V ≤ Vdd ≤ 5.25V
VH
Input Hysteresis Voltage
–
140
–
mV
IIL
Input Leakage (Absolute Value)
–
1
–
nA
Gross tested to 1 μA
CIN
Capacitive Load on Pins as Input
0.5
1.7
5
pF
Package and pin dependent
temperature = 25oC
COUT
Capacitive Load on Pins as Output
0.5
1.7
5
pF
Package and pin dependent
temperature = 25oC
Min
Typ
Max
Units
4
5.6
8
kΩ
Table 12. 2.7V DC GPIO Specifications
Symbol
Description
Notes
RPU
Pull Up Resistor
VOH1
High Output Voltage
Port 1 Pins with LDO Regulator Disabled
Vdd - 0.2
–
–
V
IOH < 10 μA, maximum of 10 mA
source current in all IOs.
VOH2
High Output Voltage
Port 1 Pins with LDO Regulator Disabled
Vdd - 0.5
–
–
V
IOH = 2 mA, maximum of 10 mA
source current in all IOs.
VOL
Low Output Voltage
–
–
0.75
V
IOL = 10 mA, maximum of 30 mA
sink current on even port pins (for
example, P0[2] and P1[4]) and 30
mA sink current on odd port pins
(for example, P0[3] and P1[5]).
VOLP1
Low Output Voltage Port 1 Pins
–
–
0.4
V
IOL=5 mA
Maximum of 50 mA sink current on
even port pins (for example, P0[2]
and P3[4]) and 50 mA sink current
on odd port pins (for example,
P0[3] and P2[5]).
2.4V ≤ Vdd ≤ 3.0V
VIL
Input Low Voltage
–
–
0.75
V
2.4V ≤ Vdd ≤ 3.0V
VIH1
Input High Voltage
1.4
–
–
V
2.4V ≤ Vdd ≤ 2.7V
VIH2
Input High Voltage
1.6
–
–
V
2.7V ≤ Vdd ≤ 3.0V
VH
Input Hysteresis Voltage
–
60
–
mV
IIL
Input Leakage (Absolute Value)
–
1
–
nA
Gross tested to 1 μA
CIN
Capacitive Load on Pins as Input
0.5
1.7
5
pF
Package and pin dependent
temperature = 25oC
COUT
Capacitive Load on Pins as Output
0.5
1.7
5
pF
Package and pin dependent
temperature = 25oC
Document Number: 001-41947 Rev. *D
Page 16 of 34
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CY8C20424, CY8C20524
DC Analog Mux Bus Specifications
Table 13 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and
-40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters
apply to 5V, 3.3V, or 2.7V at 25°C. These are for design guidance only.
Table 13. DC Analog Mux Bus Specifications
Symbol
RSW
Description
Switch Resistance to Common Analog Bus
Min
–
Typ
–
Max
400
800
Units
Ω
Ω
Notes
Vdd ≥ 2.7V
2.4V ≤ Vdd ≤ 2.7V
DC Low Power Comparator Specifications
Table 14 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and
-40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters
apply to 5V at 25°C. These are for design guidance only.
Table 14. DC Low Power Comparator Specifications
Symbol
VREFLPC
ISLPC
VOSLPC
Description
Low power comparator (LPC) reference
voltage range
LPC supply current
LPC voltage offset
Min
0.2
Typ
–
Max
Vdd – 1
Units
V
–
–
10
2.5
40
30
μA
mV
Notes
DC POR and LVD Specifications
Table 15 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and
-40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters
apply to 5V, 3.3V, or 2.7V at 25°C. These are for design guidance only.
Table 15. DC POR and LVD Specifications
Symbol
Description
Vdd Value for PPOR Trip
VPPOR0 PORLEV[1:0] = 00b
VPPOR1 PORLEV[1:0] = 01b
VPPOR2 PORLEV[1:0] = 10b
VLVD0
VLVD1
VLVD2
VLVD3
VLVD4
VLVD5
VLVD6
VLVD7
Vdd Value for LVD Trip
VM[2:0] = 000b
VM[2:0] = 001b
VM[2:0] = 010b
VM[2:0] = 011b
VM[2:0] = 100b
VM[2:0] = 101b
VM[2:0] = 110b
VM[2:0] = 111b
Min
Typ
Max
Units
–
–
–
2.36
2.60
2.82
2.40
2.65
2.95
V
V
V
2.39
2.54
2.75
2.85
2.96
–
–
4.52
2.45
2.71
2.92
3.02
3.13
–
–
4.73
2.51[3]
2.78[4]
2.99[5]
3.09
3.20
–
–
4.83
V
V
V
V
V
V
V
V
Notes
Vdd is greater than or equal to 2.5V
during startup, reset from the XRES
pin, or reset from Watchdog.
Notes
3. Always greater than 50 mV above VPPOR (PORLEV = 00) for falling supply.
4. Always greater than 50 mV above VPPOR (PORLEV = 01) for falling supply.
5. Always greater than 50 mV above VPPOR (PORLEV = 10) for falling supply.
Document Number: 001-41947 Rev. *D
Page 17 of 34
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CY8C20224, CY8C20324
CY8C20424, CY8C20524
DC Programming Specifications
Table 16 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and
-40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters
apply to 5V, 3.3V, or 2.7V at 25°C. These are for design guidance only.
Table 16. DC Programming Specifications
Symbol
Description
VddIWRITE Supply Voltage for Flash Write Operations
IDDP
Supply Current During Programming or Verify
VILP
Input Low Voltage During Programming or
Verify
VIHP
Input High Voltage During Programming or
Verify
IILP
Input Current when Applying Vilp to P1[0] or
P1[1] During Programming or Verify
IIHP
Input Current when Applying Vihp to P1[0] or
P1[1] During Programming or Verify
VOLV
Output Low Voltage During Programming or
Verify
VOHV
Output High Voltage During Programming or
Verify
FlashENPB Flash Endurance (per block)
FlashENT Flash Endurance (total)[6]
FlashDR
Flash Data Retention
Min
2.70
–
–
Typ
–
5
–
Max
–
25
0.8
Units
V
mA
V
2.2
–
–
V
–
–
0.2
mA
–
–
1.5
mA
–
–
V
Vdd
–1.0
50,000
1,800,0
00
10
–
Vss +
0.75
Vdd
–
–
–
–
–
–
–
–
Years
Notes
Driving internal pull down
resistor.
Driving internal pull down
resistor.
V
Erase/write cycles per block.
Erase/write cycles.
Note
6. A maximum of 36 x 50,000 block endurance cycles is allowed. This is balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2 blocks of
25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36x50,000 and that no single block ever sees
more than 50,000 cycles).
Document Number: 001-41947 Rev. *D
Page 18 of 34
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CY8C20424, CY8C20524
AC Electrical Characteristics
AC Chip Level Specifications
Table 17 and Table 18 list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to
5.25V and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C respectively. Typical
parameters apply to 5V, 3.3V, or 2.7V at 25°C. These are for design guidance only.
Table 17. 5V and 3.3V AC Chip-Level Specifications
Symbol
FCPU1
F32K1
FIMO12
Description
CPU Frequency (3.3V Nominal)
Internal Low Speed Oscillator Frequency
Internal Main Oscillator Stability for 12 MHz
(Commercial Temperature)[7]
Min
0.75
15
11.4
Typ
–
32
12
Max
12.6
64
12.6
Units
MHz
kHz
MHz
FIMO6
Internal Main Oscillator Stability for 6 MHz
(Commercial Temperature)
5.70
6.0
6.30
MHz
DCIMO
TRAMP
TXRST
Duty Cycle of IMO
Supply Ramp Time
External Reset Pulse Width
40
0
10
50
–
–
60
–
–
%
μs
μs
Notes
12 MHz only for SLIMO Mode = 0
Trimmed for 3.3V operation using
factory trim values.
See Figure 8 on page 13, SLIMO
Mode = 0.
Trimmed for 3.3V operation using
factory trim values.
See Figure 8 on page 13, SLIMO
Mode = 1.
Table 18. 2.7V AC Chip Level Specifications
Symbol
FCPU1A
FCPU1B
F32K1
FIMO12
Description
CPU Frequency (2.7V Nominal)
CPU Frequency (2.7V Minimum)
Internal Low Speed Oscillator Frequency
Internal Main Oscillator Stability for 12 MHz
(Commercial Temperature)[7]
Min
0.75
0.75
8
11.0
Typ
–
–
32
12
Max
3.25
6.3
96
12.9
Units
MHz
MHz
kHz
MHz
FIMO6
Internal Main Oscillator Stability for 6 MHz
(Commercial Temperature)
5.60
6.0
6.40
MHz
DCIMO
TRAMP
TXRST
Duty Cycle of IMO
Supply Ramp Time
External Reset Pulse Width
40
0
10
50
–
–
60
–
–
%
μs
μs
Notes
2.4V < Vdd < 3.0V.
2.7V < Vdd < 3.0V.
Trimmed for 2.7V operation using
factory trim values.
See Figure 8 on page 13, SLIMO
Mode = 0.
Trimmed for 2.7V operation using
factory trim values.
See Figure 8 on page 13, SLIMO
Mode = 1.
Note
7. 0 to 70 °C ambient, Vdd = 3.3 V.
Document Number: 001-41947 Rev. *D
Page 19 of 34
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AC General Purpose IO Specifications
Table 19 and Table 20 list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to
5.25V and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C respectively. Typical
parameters apply to 5V, 3.3V, or 2.7V at 25°C. These are for design guidance only.
Table 19. 5V and 3.3V AC GPIO Specifications
Symbol
Description
FGPIO
GPIO Operating Frequency
TRise023 Rise Time, Strong Mode, Cload = 50 pF
Ports 0, 2, 3
TRise1
Rise Time, Strong Mode, Cload = 50 pF
Port 1
TFall
Fall Time, Strong Mode, Cload = 50 pF
All Ports
Min
0
15
Typ
–
–
Max
6
80
Units
MHz
ns
Notes
Normal Strong Mode, Port 1.
Vdd = 3.0 to 3.6V and 4.75V to 5.25V,
10% - 90%
Vdd = 3.0 to 3.6V, 10% - 90%
10
–
50
ns
10
–
50
ns
Description
GPIO Operating Frequency
Min
0
Typ
–
Max
1.5
Units
MHz
Notes
Normal Strong Mode, Port 1.
TRise023 Rise Time, Strong Mode, Cload = 50 pF
Ports 0, 2, 3
TRise1
Rise Time, Strong Mode, Cload = 50 pF
Port 1
TFall
Fall Time, Strong Mode, Cload = 50 pF
All Ports
15
–
100
ns
Vdd = 2.4 to 3.0V, 10% - 90%
10
–
70
ns
Vdd = 2.4 to 3.0V, 10% - 90%
10
–
70
ns
Vdd = 2.4 to 3.0V, 10% - 90%
Vdd = 3.0 to 3.6V and 4.75V to 5.25V,
10% - 90%
Table 20. 2.7V AC GPIO Specifications
Symbol
FGPIO
Figure 9. GPIO Timing Diagram
90%
GPIO
Pin
Output
Voltage
10%
TFall
TRise023
TRise1
AC Comparator Amplifier Specifications
Table 21 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to
5V, 3.3V, or 2.7V at 25°C. These are for design guidance only.
Table 21. AC Operational Amplifier Specifications
Symbol
TCOMP
Description
Comparator Response Time, 50 mV
Overdrive
Document Number: 001-41947 Rev. *D
Min
Typ
Max
100
200
Units
ns
ns
Notes
Vdd ≥ 3.0V
2.4V < Vcc < 3.0V
Page 20 of 34
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AC Analog Mux Bus Specifications
Table 22 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C respectively. Typical parameters apply to
5V, 3.3V, or 2.7V at 25°C. These are for design guidance only.
Table 22. AC Analog Mux Bus Specifications
Symbol
FSW
Description
Switch Rate
Min
–
Typ
–
Max
3.17
Units
MHz
Notes
AC Low Power Comparator Specifications
Table 23 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to
5V at 25°C. These are for design guidance only.
Table 23. AC Low Power Comparator Specifications
Symbol
TRLPC
Description
LPC response time
Min
–
Typ
–
Max
50
Units
μs
Notes
≥ 50 mV overdrive comparator
reference set within VREFLPC.
AC External Clock Specifications
Table 24, Table 25, and Table 26 list the guaranteed maximum and minimum specifications for the voltage and temperature ranges:
4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively.
Typical parameters apply to 5V, 3.3V, or 2.7V at 25°C. These are for design guidance only.
Table 24. 5V AC External Clock Specifications
Min
Typ
Max
Units
FOSCEXT
Symbol
Frequency
Description
0.750
–
12.6
MHz
Notes
–
High Period
38
–
5300
ns
–
Low Period
38
–
–
ns
–
Power Up IMO to Switch
150
–
–
μs
Min
Typ
Max
Units
Notes
Maximum CPU frequency is 12
MHz at 3.3V. With the CPU clock
divider set to 1, the external clock
must adhere to the maximum
frequency and duty cycle requirements.
Table 25. 3.3V AC External Clock Specifications
Symbol
Description
FOSCEXT
Frequency with CPU Clock divide by 1
0.750
–
12.6
MHz
–
High Period with CPU Clock divide by 1
41.7
–
5300
ns
–
Low Period with CPU Clock divide by 1
41.7
–
–
ns
–
Power Up IMO to Switch
150
–
–
μs
Document Number: 001-41947 Rev. *D
Page 21 of 34
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Table 26. 2.7V AC External Clock Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
0
FOSCEXT1A Frequency with CPU Clock divide by 1
(2.7V Nominal)
0.75
–
3.08
MHz
2.4V < Vdd < 3.0V. Maximum CPU
frequency is 3 MHz at 2.7V. With the
CPU clock divider set to 1, the external
clock must adhere to the maximum
frequency and duty cycle requirements.
FOSCEXT1B Frequency with CPU Clock divide by 1
(2.7V Minimum)
0.75
–
6.30
MHz
2.7V < Vdd < 3.0V. Maximum CPU
frequency is 3 MHz at 2.7V. With the
CPU clock divider set to 1, the external
clock must adhere to the maximum
frequency and duty cycle requirements.
FOSCEXT2A Frequency with CPU Clock divide by 2 or
greater (2.7V Nominal)
1.5
–
6.35
MHz
2.4V < Vdd < 3.0V. If the frequency of
the external clock is greater than 3
MHz, the CPU clock divider is set to 2
or greater. In this case, the CPU clock
divider ensures that the fifty percent
duty cycle requirement is met.
FOSCEXT2B Frequency with CPU Clock divide by 2 or
greater (2.7V Minimum)
1.5
–
12.6
MHz
2.7V < Vdd < 3.0V. If the frequency of
the external clock is greater than 3
MHz, the CPU clock divider is set to 2
or greater. In this case, the CPU clock
divider ensures that the fifty percent
duty cycle requirement is met.
–
High Period with CPU Clock divide by 1
160
–
5300
ns
–
Low Period with CPU Clock divide by 1
160
–
–
ns
–
Power Up IMO to Switch
150
–
–
μs
AC Programming Specifications
Table 27 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C respectively. Typical parameters apply to
5V, 3.3V, or 2.7V at 25°C. These are for design guidance only.
Table 27. AC Programming Specifications
Symbol
TRSCLK
TFSCLK
TSSCLK
THSCLK
FSCLK
TERASEB
TWRITE
TDSCLK
TDSCLK3
TDSCLK2
Description
Rise Time of SCLK
Fall Time of SCLK
Data Set up Time to Falling Edge of SCLK
Data Hold Time from Falling Edge of SCLK
Frequency of SCLK
Flash Erase Time (Block)
Flash Block Write Time
Data Out Delay from Falling Edge of SCLK
Data Out Delay from Falling Edge of SCLK
Data Out Delay from Falling Edge of SCLK
Document Number: 001-41947 Rev. *D
Min
1
1
40
40
0
–
–
–
–
–
Typ
–
–
–
–
–
15
30
–
–
–
Max
20
20
–
–
8
–
–
45
50
70
Units
ns
ns
ns
ns
MHz
ms
ms
ns
ns
ns
Notes
3.6 < Vdd
3.0 ≤ Vdd ≤ 3.6
2.4 ≤ Vdd ≤ 3.0
Page 22 of 34
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AC SPI Specifications
Table 28 and Table 29 list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to
5.25V and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical
parameters apply to 5V, 3.3V, or 2.7V at 25°C. These are for design guidance only.
Table 28. 5V and 3.3V AC SPI Specifications
Symbol
Description
Min
Typ
Max
Units
FSPIM
Maximum Input Clock Frequency Selection,
Master
–
–
6.3
MHz
FSPIS
Maximum Input Clock Frequency Selection,
Slave
–
–
2.05
MHz
TSS
Width of SS_ Negated Between Transmissions
50
–
–
ns
Notes
Output clock frequency is half of
input clock rate.
Table 29. 2.7V AC SPI Specifications
Description
Min
Typ
Max
Units
FSPIM
Symbol
Maximum Input Clock Frequency Selection,
Master
–
–
3.15
MHz
FSPIS
Maximum Input Clock Frequency Selection,
Slave
–
–
1.025
MHz
TSS
Width of SS_ Negated Between Transmissions
50
–
–
ns
Notes
Output clock frequency is half of
input clock rate
AC I2C Specifications
Table 30 and Table 31 list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to
5.25V and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C respectively. Typical
parameters apply to 5V, 3.3V, or 2.7V at 25°C. These are for design guidance only.
Table 30. AC Characteristics of the I2C SDA and SCL Pins for Vdd ≥ 3.0V
Symbol
FSCLI2C
Description
SCL Clock Frequency
Standard Mode
Min
Max
0
100
Fast Mode
Min
Max
0
400
Units
kHz
THDSTAI2C Hold Time (repeated) START
Condition. After this period, the
first clock pulse is generated.
2
LOW Period of the SCL Clock
TLOWI C
4.0
–
0.6
–
μs
4.7
–
1.3
–
μs
HIGH Period of the SCL Clock
4.0
–
0.6
–
μs
4.7
–
0.6
–
μs
0
–
0
–
μs
–
ns
THIGHI2C
TSUSTAI2C Setup Time for a Repeated
START Condition
2
THDDATI C Data Hold Time
TSUDATI2C Data Setup Time
250
–
100[8]
TSUSTOI2C Setup Time for STOP Condition
4.0
–
0.6
–
μs
4.7
–
1.3
–
μs
–
–
0
50
ns
TBUFI2C
TSPI2C
Bus Free Time Between a STOP
and START Condition
Pulse Width of spikes are
suppressed by the input filter
Notes
Note
8. A Fast Mode I2C bus device is used in a Standard Mode I2C bus system but the requirement tSU; DAT Š 250 ns is met. This automatically is the case if the device
does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line trmax
+ tSU; DAT = 1000 + 250 = 1250 ns (according to the Standard Mode I2C bus specification) before the SCL line is released.
Document Number: 001-41947 Rev. *D
Page 23 of 34
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Table 31. 2.7V AC Characteristics of the I2C SDA and SCL Pins (Fast Mode Not Supported)
Symbol
FSCLI2C
Standard Mode
Min
Max
0
100
Description
SCL Clock Frequency.
Fast Mode
Min
Max
–
–
Units
kHz
THDSTAI C Hold Time (repeated) START
Condition. After this period, the
first clock pulse is generated.
LOW Period of the SCL Clock.
TLOWI2C
4.0
–
–
–
μs
4.7
–
–
–
μs
HIGH Period of the SCL Clock.
4.0
–
–
–
μs
TSUSTAI C Setup Time for a Repeated
START Condition.
2
THDDATI C Data Hold Time.
4.7
–
–
–
μs
0
–
–
–
μs
TSUDATI C Data Setup Time.
250
–
–
–
ns
Setup Time for STOP Condition.
4.0
–
–
–
μs
Bus Free Time Between a STOP
and START Condition.
Pulse Width of spikes are
suppressed by the input filter.
4.7
–
–
–
μs
–
–
–
–
ns
2
2
THIGHI C
2
2
TSUSTOI2C
TBUFI2C
TSPI2C
Notes
Figure 10. Definition for Timing for Fast or Standard Mode on the I2C Bus
SDA
T LOWI2C
T SUDATI2C
T HDSTAI2C
T SPI2C
T BUFI2C
SCL
S
T HDSTAI2C T HDDATI2C T HIGHI2C
Document Number: 001-41947 Rev. *D
T SUSTAI2C
Sr
T SUSTOI2C
P
S
Page 24 of 34
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Packaging Dimensions
This section illustrates the packaging specifications for the CY8C20224, CY8C20324, CY8C20424, and CY8C20524 PSoC devices,
along with the thermal impedances for each package.
Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of
the emulation tools’ dimensions, refer to the document titled PSoC Emulator Pod Dimensions at
http://www.cypress.com/design/MR10161.
Figure 11. 16-Pin (3x3 mm x 0.6 MAX) COL
001-09116 *D
Document Number: 001-41947 Rev. *D
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Figure 12. 24-Pin (4x4 x 0.6 mm) QFN
19
24
18
1
13
6
12
7
NO TES :
1.
H A T C H IS S O L D E R A B L E E X P O S E D M E T A L .
2 . R E F E R E N C E J E D E C # M O -2 4 8
3 . U N IT P A C K A G E W E IG H T : 0 .0 2 4 g ra m s
4 . A L L D IM E N S IO N S A R E IN M IL L IM E T E R S
001-13937 *B
CYPRESS
C O M P A N Y C O N F ID E N T IA L
Figure 13. 28-Pin (210-Mil) SSOP
51-85079 *C
Document Number: 001-41947 Rev. *D
Page 26 of 34
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Figure 14. 32-Pin (5x5 mm 0.60 MAX) QFN
001-06392 *A
Figure 15. 32-Pin (5X5X 0.60 Max) QFN
001-48913 *A
Document Number: 001-41947 Rev. *D
Page 27 of 34
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Figure 16. 48-Pin (7x7 mm) QFN
001-12919 *A
Important For information on the preferred dimensions for mounting the QFN packages, see the following application note at
http://www.amkor.com/products/notes_papers/MLFAppNote.pdf.
It is important to note that pinned vias for thermal conduction are not required for the low power 24, 32, and 48-pin QFN PSoC devices.
Document Number: 001-41947 Rev. *D
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Thermal Impedances
Table 32. Thermal Impedances Per Package
Package
16 COL
24 QFN[10]
28 SSOP
32 QFN[10]
48 QFN[10]
Typical θJA [9]
46 oC/W
25 oC/W
96 oC/W
27 oC/W
28 oC/W
Solder Reflow Peak Temperature
Table 33 lists the minimum solder reflow peak temperature to achieve good solderability.
Table 33. Solder Reflow Peak Temperature
Package
Minimum Peak Temperature [11]
Maximum Peak Temperature
16 COL
240oC
260oC
24 QFN
240oC
260oC
28 SSOP
240oC
260oC
32 QFN
240oC
260oC
48 QFN
240oC
260oC
Notes
9. TJ = TA + Power x θJA.
10. To achieve the thermal impedance specified for the QFN package, the center thermal pad is soldered to the PCB ground plane.
11. Higher temperatures is required based on the solder melting point. Typical temperatures for solder are 220 ± 5oC with Sn-Pb or 245 ± 5oC with Sn-Ag-Cu paste. Refer
to the solder manufacturer specifications.
Document Number: 001-41947 Rev. *D
Page 29 of 34
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Development Tool Selection
Software
Development Kits
PSoC Designer™
All development kits are sold at the Cypress Online Store.
At the core of the PSoC development software suite is PSoC
Designer. This is used by thousands of PSoC developers. This
robust software is facilitating PSoC designs for half a decade.
PSoC Designer is available free of charge at
http://www.cypress.com under DESIGN RESOURCES >>
Software and Drivers.
CY3215-DK Basic Development Kit
PSoC Programmer
PSoC Programmer is flexible enough and is used on the bench
in development and is also suitable for factory programming.
PSoC Programmer works either as a standalone programming
application or operates directly from PSoC Designer or PSoC
Express. PSoC Programmer software is compatible with both
PSoC ICE Cube In-Circuit Emulator and PSoC MiniProg. PSoC
programmer
is
available
free
of
charge
at
http://www.cypress.com/psocprogrammer.
C Compilers
PSoC Designer comes with a free HI-TECH C Lite C compiler.
The HI-TECH C Lite compiler is free, supports all PSoC devices,
integrates fully with PSoC Designer and PSoC Express, and
runs on Windows versions up to 32-bit Vista. Compilers with
additional features are available at additional cost from their
manufactures.
■
HI-TECH C PRO for the PSoC is available from
http://www.htsoft.com.
■
ImageCraft Cypress Edition Compiler is available from
http://www.imagecraft.com.
Document Number: 001-41947 Rev. *D
The CY3215-DK is for prototyping and development with PSoC
Designer. This kit supports in-circuit emulation and the software
interface enables users to run, halt, and single step the
processor and view the content of specific memory locations.
PSoC Designer supports the advance emulation features also.
The kit includes:
■
PSoC Designer Software CD
■
ICE-Cube In-Circuit Emulator
■
ICE Flex-Pod for CY8C29x66 Family
■
Cat-5 Adapter
■
Mini-Eval Programming Board
■
110 ~ 240V Power Supply, Euro-Plug Adapter
■
iMAGEcraft C Compiler (Registration Required)
■
ISSP Cable
■
USB 2.0 Cable and Blue Cat-5 Cable
■
2 CY8C29466-24PXI 28-PDIP Chip Samples
CY3210-ExpressDK PSoC Express Development Kit
The CY3210-ExpressDK is for advanced prototyping and
development with PSoC Express (used with ICE-Cube In-Circuit
Emulator). It provides access to I2C buses, voltage reference,
switches, upgradeable modules, and more. The kit includes:
■
PSoC Express Software CD
■
Express Development Board
■
Four Fan Modules
■
Two Proto Modules
■
MiniProg In-System Serial Programmer
■
MiniEval PCB Evaluation Board
■
Jumper Wire Kit
■
USB 2.0 Cable
■
Serial Cable (DB9)
■
110 ~ 240V Power Supply, Euro-Plug Adapter
■
2 CY8C24423A-24PXI 28-PDIP Chip Samples
■
2 CY8C27443-24PXI 28-PDIP Chip Samples
■
2 CY8C29466-24PXI 28-PDIP Chip Samples
Page 30 of 34
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Evaluation Tools
Device Programmers
All evaluation tools are sold at the Cypress Online Store.
All device programmers are purchased from the Cypress Online
Store.
CY3210-MiniProg1
CY3216 Modular Programmer
The CY3210-MiniProg1 kit enables the user to program PSoC
devices via the MiniProg1 programming unit. The MiniProg is a
small, compact prototyping programmer that connects to the PC
via a provided USB 2.0 cable. The kit includes:
■
MiniProg Programming Unit
■
MiniEval Socket Programming and Evaluation Board
■
28-Pin CY8C29466-24PXI PDIP PSoC Device Sample
■
28-Pin CY8C27443-24PXI PDIP PSoC Device Sample
■
PSoC Designer Software CD
■
Getting Started Guide
■
USB 2.0 Cable
CY3210-PSoCEval1
The CY3210-PSoCEval1 kit features an evaluation board and
the MiniProg1 programming unit. The evaluation board includes
an LCD module, potentiometer, LEDs, and plenty of breadboarding space to meet all of your evaluation needs. The kit
includes:
■
Evaluation Board with LCD Module
■
MiniProg Programming Unit
■
28-Pin CY8C29466-24PXI PDIP PSoC Device Sample (2)
■
PSoC Designer Software CD
■
Getting Started Guide
■
USB 2.0 Cable
The CY3216 Modular Programmer kit features a modular
programmer and the MiniProg1 programming unit. The modular
programmer includes three programming module cards and
supports multiple Cypress products. The kit includes:
■
Modular Programmer Base
■
Three Programming Module Cards
■
MiniProg Programming Unit
■
PSoC Designer Software CD
■
Getting Started Guide
■
USB 2.0 Cable
CY3207ISSP In-System Serial Programmer (ISSP)
The CY3207ISSP is a production programmer. It includes
protection circuitry and an industrial case that is more robust than
the MiniProg in a production programming environment.
Note that CY3207ISSP needs special software and is not
compatible with PSoC Programmer. The kit includes:
■
CY3207 Programmer Unit
■
PSoC ISSP Software CD
■
110 ~ 240V Power Supply, Euro-Plug Adapter
■
USB 2.0 Cable
CY3214-PSoCEvalUSB
The CY3214-PSoCEvalUSB evaluation kit features a
development board for the CY8C24794-24LFXI PSoC device.
Special features of the board include both USB and capacitive
sensing development and debugging support. This evaluation
board also includes an LCD module, potentiometer, LEDs, an
enunciator and plenty of bread boarding space to meet all of your
evaluation needs. The kit includes:
■
PSoCEvalUSB Board
■
LCD Module
■
MIniProg Programming Unit
■
Mini USB Cable
■
PSoC Designer and Example Projects CD
■
Getting Started Guide
■
Wire Pack
Document Number: 001-41947 Rev. *D
Page 31 of 34
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CY8C20224, CY8C20324
CY8C20424, CY8C20524
Accessories (Emulation and Programming)
Table 34. Emulation and Programming Accessories
Part Number
Pin Package
Flex-Pod Kit [12]
Foot Kit [13]
Prototyping
Module
Adapter [14]
CY8C20224-12LKXI
16 COL
Not available
Not available
CY3210-20X34
-
CY8C20324-12LQXI
24 QFN
CY3250-20334QFN
CY3250-24QFN-FK
CY3210-20X34
AS-24-28-01ML-6
CY8C20524-12PVXI
28 SSOP
CY3250-20534
CY3250-28SSOP-FK
CY3210-20X34
-
CY8C20424-12LKXI
32 QFN
CY3250-20434QFN
CY3250-32QFN-FK
CY3210-20X34
AS-32-28-03ML-6
Third Party Tools
Build a PSoC Emulator into Your Board
Several tools are specially designed by the following third party
vendors to accompany PSoC devices during development and
production. Specific details of each of these tools are found at
http://www.cypress.com under DESIGN RESOURCES >>
Evaluation Boards.
For details on emulating the circuit before going to volume
production using an on-chip debug (OCD) non-production PSoC
device, refer application note AN2323 “Build a PSoC Emulator
into Your Board”.
Notes
12. Flex-Pod kit includes a practice flex-pod and a practice PCB, in addition to two flex-pods.
13. Foot kit includes surface mount feet that is soldered to the target PCB.
14. Programming adapter converts non-DIP package to DIP footprint. Specific details and ordering information for each of the adapters is found at
http://www.emulation.com.
Document Number: 001-41947 Rev. *D
Page 32 of 34
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CY8C20224, CY8C20324
CY8C20424, CY8C20524
Ordering Information
Table 35 lists the CY8C20224, CY8C20324, CY8C20424, and CY8C20524 PSoC devices key package features and ordering codes.
Table 35. PSoC Device Key Features and Ordering Information
Maximum Maximum Maximum
Flash
SRAM Number of Number of Number of
(Bytes) (Bytes)
Buttons
Sliders
LEDs
Ordering
Code
Package
Configurable
LED Behavior
(Fade, Strobe)
Proximity
Sensing
16-Pin (3x3 mm 0.60 MAX) CY8C20224-12LKXI
COL
8K
512
10
1
13
Yes
Yes
16-Pin (3x3 mm 0.60 MAX) CY8C20224-12LKXIT
COL (Tape and Reel)
8K
512
10
1
13
Yes
Yes
24-Pin (4x4 mm 0.60 MAX) CY8C20324-12LQXI
QFN
8K
512
17
1
20
Yes
Yes
24-Pin (4x4 mm 0.60 MAX) CY8C20324-12LQXIT
QFN (Tape and Reel)
8K
512
17
1
20
Yes
Yes
28-Pin (210-Mil) SSOP
CY8C20524-12PVXI
8K
512
21
1
24
Yes
Yes
28-Pin (210-Mil) SSOP
(Tape and Reel)
CY8C20524-12PVXIT
8K
512
21
1
24
Yes
Yes
32-Pin (5x5 mm 0.60 MAX) CY8C20424-12LKXI
QFN
8K
512
25
1
28
Yes
Yes
32-Pin (5x5 mm 0.60 MAX) CY8C20424-12LKXIT
QFN (Tape and Reel)
8K
512
25
1
28
Yes
Yes
32-Pin (5X5 mm 0.60
MAX) QFN (Sawn)
CY8C20424-12LQXI
8K
512
25
1
28
Yes
Yes
32-Pin (5X5 mm 0.60
MAX) QFN (Sawn)
CY8C20424-12LQXIT
8K
512
25
1
28
Yes
Yes
Note For Die sales information, contact a local Cypress sales office or Field Applications Engineer (FAE).
Figure 17. Ordering Code Definitions
CY 8 C 20 xxx- 12 xx
Package Type:
Thermal Rating:
PX = PDIP Pb-Free
C = Commercial
SX = SOIC Pb-Free
I = Industrial
PVX = SSOP Pb-Free
E = Extended
LFX/LKX/LQX= QFN Pb-Free
AX = TQFP Pb-Free
Speed: 12 MHz
Part Number
Family Code
Technology Code: C = CMOS
Marketing Code: 8 = Cypress PSoC
Company ID: CY = Cypress
Document Number: 001-41947 Rev. *D
Page 33 of 34
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CY8C20224, CY8C20324
CY8C20424, CY8C20524
Document History Page
Document Title: CY8C20224, CY8C20324, CY8C20424, CY8C20524, CapSense™ PSoC® Programmable
System-on-Chip™
Document Number: 001-41947
Revision ECN No.
Orig. of
Change
Submission
Date
Description of Change
**
1734104
YHW/AESA
See ECN
*A
2542938
RLRM/AESA
07/28/2008
New parts and document (Revision **).
*B
2610469
SNV/PYRS
11/20/08
Updated VOH5, VOH7, and VOH9 specifications.
*C
2634376
DRSW
01/12/09
Removed the part number CY3250-20234QFN from the
'CY8C20224-12LKXI' flex-pod kit
Changed title from CapSense™ Multimedia PSoC® Mixed-Signal Array to
CapSense™ Multimedia PSoC® Programmable System-on-Chip™
Added -12 to the CY8C20524 parts in the Ordering Information table
Updated ‘Development Tools’ and ‘Designing with PSoC Designer’ sections
on pages 4 and 5
Updated ‘Development Tools Selection’ section on page 30
Changed status from ‘Preliminary’ to ‘Final’
Changed 16-Pin from QFN to COL
*D
2693024
DPT/PYRS
04/16/2009
Corrected Ordering Information format. Updated package diagram
001-13937 to Rev *B. Updated data sheet template.
Added 32-Pin Sawn QFN package diagram
Added devices CY8C20424-12LQXI and CY8C20424-12LQXIT in the
Ordering Information table
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at cypress.com/sales.
Products
PSoC Solutions
PSoC
psoc.cypress.com
Clocks & Buffers
clocks.cypress.com
General
Low Power/Low Voltage
psoc.cypress.com/solutions
psoc.cypress.com/low-power
Wireless
wireless.cypress.com
Precision Analog
Memories
memory.cypress.com
LCD Drive
psoc.cypress.com/lcd-drive
image.cypress.com
CAN 2.0b
psoc.cypress.com/can
USB
psoc.cypress.com/usb
Image Sensors
psoc.cypress.com/precision-analog
© Cypress Semiconductor Corporation, 2008-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-41947 Rev. *D
Revised April 15, 2009
Page 34 of 34
PSoC Designer™ and Programmable System-on-Chip™ are trademarks and PSoC® is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced
herein are property of the respective corporations. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights
to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. All products and company names mentioned in this document
may be the trademarks of their respective holders.
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