LINER LTC1416 Low power 14-bit, 400ksps sampling adc Datasheet

LTC1416
Low Power 14-Bit, 400ksps
Sampling ADC
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FEATURES
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DESCRIPTIO
The LTC ®1416 is a 2.2µs, 400ksps, 14-bit sampling A/D
converter that draws only 70mW from ±5V supplies. This
easy-to-use device includes a high dynamic range sampleand-hold and a precision reference. Two digitally selectable power shutdown modes provide flexibility for low
power systems.
Sample Rate: 400ksps
Power Dissipation: 70mW
Guaranteed ± 1.5LSB DNL, ± 2LSB INL (Max)
80.5dB S/(N + D) and 93dB THD at 100kHz
80dB S/(N + D) and 90dB THD at Nyquist
Nap and Sleep Shutdown Modes
Operates with Internal or External Reference
True Differential Inputs Reject Common Mode Noise
15MHz Full Power Bandwidth Sampling
±2.5V Bipolar Input Range
28-Pin SSOP Package
The LTC1416’s full-scale input range is ±2.5V. Maximum
DC specifications include ±2LSB INL, ±1.5LSB DNL over
temperature. Outstanding AC performance includes 80.5dB
S/(N + D) and 93dB THD with a 100kHz input, and 80dB
S/(N + D) and 90dB THD at the Nyquist input frequency of
200kHz.
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APPLICATIO S
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The unique differential input sample-and-hold can acquire single-ended or differential input signals up to its
15MHz bandwidth. The 60dB common mode rejection
allows users to eliminate ground loops and common
mode noise by measuring signals differentially from the
source.
Telecommunications
Digital Signal Processing
Multiplexed Data Acquisition Systems
High Speed Data Acquisition
Spectrum Analysis
Imaging Systems
The ADC has a µP compatible, 14-bit parallel output
port. There is no pipeline delay in the conversion
results. A separate convert start input and a data ready
signal (BUSY) ease connections to FIFOs, DSPs and
microprocessors.
, LTC and LT are registered trademarks of Linear Technology Corporation.
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TYPICAL APPLICATIO
Effective Bits and
Signal-to-(Noise + Distortion)
vs Input Frequency
Complete, 70mW, 14-Bit ADC with 80.5dB S/(N + D)
10µF
DVDD
AVDD
REFCOMP
22µF
BUFFER
4k
TIMING
AND
LOGIC
2.5V
REFERENCE
VREF
1µF
VSS
10µF –5V
AGND
DGND
•
•
•
D13 (MSB)
D0 (LSB)
BUSY
CS
CONVST
RD
SHDN
1416 TA01
EFFECTIVE BITS
OUTPUT
BUFFERS
14-BIT ADC
S/H
AIN–
86
80
74
68
62
NYQUIST
FREQUENCY
SIGNAL/(NOISE + DISTORTION) (dB)
LTC1416
14
AIN+
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
fSAMPLE = 400kHz
1k
10k
100k
INPUT FREQUENCY (Hz)
1M 2M
1416 TA02
1
LTC1416
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ABSOLUTE
PACKAGE/ORDER I FOR ATIO
RATI GS
AVDD = DVDD = VDD (Notes 1, 2)
ORDER
PART NUMBER
TOP VIEW
Supply Voltage (VDD) ................................................ 6V
Negative Supply Voltage (VSS) ............................... – 6V
Total Supply Voltage (VDD to VSS) .......................... 12V
Analog Input Voltage
(Note 3) ......................... (VSS – 0.3V) to (VDD + 0.3V)
Digital Input Voltage (Note 4) ..........(VSS – 0.3V) to 10V
Digital Output Voltage ....... (VSS – 0.3V) to (VDD + 0.3V)
Power Dissipation ............................................. 500mW
Operating Temperature Range
Commercial ............................................ 0°C to 70°C
Industrial ........................................... – 40°C to 85°C
Storage Temperature Range ................ – 65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
AIN+ 1
28 AVDD
AIN– 2
27 DVDD
VREF 3
26 VSS
REFCOMP 4
LTC1416CG
LTC1416IG
25 BUSY
AGND 5
24 CS
D13(MSB) 6
23 CONVST
D12 7
22 RD
D11 8
21 SHDN
D10 9
20 D0
D9 10
19 D1
D8 11
18 D2
D7 12
17 D3
D6 13
16 D4
DGND 14
15 D5
G PACKAGE
28-LEAD PLASTIC SSOP
TJMAX = 110°C, θJA = 95°C/W
Consult factory for Military grade parts and for A grade parts.
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CO VERTER CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. With Internal Reference (Notes 5, 6)
PARAMETER
CONDITIONS
MIN
Resolution (No Missing Codes)
Integral Linearity Error
(Note 7)
MAX
13
●
Differential Linearity Error
TYP
UNITS
Bits
●
±0.8
±2
LSB
●
±0.7
±1.5
LSB
●
±5
±20
LSB
±60
±40
LSB
LSB
Offset Error
(Note 8)
Full-Scale Error
Internal Reference
External Reference = 2.5V
±20
±10
Full-Scale Tempco
IOUT(REF) = 0
±15
ppm/°C
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A ALOG I PUT
The ● denotes specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER
CONDITIONS
VIN
Analog Input Range (Note 9)
4.75V ≤ VDD ≤ 5.25V, – 5.25V ≤ VSS ≤ – 4.75V
●
IIN
Analog Input Leakage Current
CS = High
●
CIN
Analog Input Capacitance
Between Conversions
During Conversions
t ACQ
Sample-and-Hold Acquisition Time
(Note 9)
t AP
Sample-and-Hold Aperture Delay Time
tjitter
Sample-and-Hold Aperture Delay Time Jitter
CMRR
2
Analog Input Common Mode Rejection Ratio
MIN
TYP
15
5
●
100
= AIN
+ ) < 2.5V
UNITS
V
±1
–1.5
– 2.5V < (AIN–
MAX
±2.5
µA
pF
pF
400
ns
ns
2
psRMS
60
dB
LTC1416
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DY A IC ACCURACY
The ● denotes specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
S/(N + D)
Signal-to-(Noise + Distortion) Ratio
100kHz Input Signal
200kHz Input Signal
●
MIN
TYP
77
80.5
80
THD
Total Harmonic Distortion
100kHz Input Signal, First 5 Harmonics
200kHz Input Signal, First 5 Harmonics
●
– 93
– 90
– 86
dB
dB
SFDR
Spurious-Free Dynamic Range
100kHz Input Signal
●
– 95
– 86
dB
IMD
Intermodulation Distortion
fIN1 = 87.01172kHz, fIN2 = 113.18359kHz
UNITS
dB
dB
– 90
Full Power Bandwidth
S/(N + D) ≥ 77dB
Full Linear Bandwidth
MAX
dB
15
MHz
0.8
MHz
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I TER AL REFERE CE CHARACTERISTICS
The ● denotes specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. (Note 5)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VREF Output Voltage
IOUT = 0
2.480
2.500
2.520
V
VREF Output Tempco
IOUT = 0
±15
ppm/°C
VREF Line Regulation
4.75V ≤ VDD ≤ 5.25V
– 5.25V ≤ VSS ≤ – 4.75V
0.05
0.05
LSB/V
LSB/V
VREF Output Resistance
– 0.1mA ≤ IOUT ≤ 0.1mA
COMP Output Voltage
IOUT = 0
4
kΩ
4.06
V
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DIGITAL I PUTS A D DIGITAL OUTPUTS
The ● denotes specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER
CONDITIONS
VIH
High Level Input Voltage
VDD = 5.25V
●
VIL
Low Level Input Voltage
VDD = 4.75V
●
0.8
V
IIN
Digital Input Current
VIN = 0V to VDD
●
±10
µA
CIN
Digital Input Capacitance
VOH
High Level Output Voltage
VOL
Low Level Output Voltage
MIN
VDD = 4.75V
IOUT = – 10µA
IOUT = – 200µA
●
VDD = 4.75V
IOUT = 160µA
IOUT = 1.6mA
●
TYP
MAX
UNITS
2.4
V
5
pF
4.5
V
V
4.0
0.05
0.10
0.4
V
V
IOZ
Hi-Z Output Leakage D13 to D0
VOUT = 0V to VDD, CS High
●
±10
µA
COZ
Hi-Z Output Capacitance D13 to D0
CS High (Note 9 )
●
15
pF
ISOURCE
Output Source Current
VOUT = 0V
– 10
mA
ISINK
Output Sink Current
VOUT = VDD
10
mA
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POWER REQUIRE E TS
The ● denotes specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER
CONDITIONS
VDD
Positive Supply Voltage
(Note 10)
VSS
Negative Supply Voltage
(Note 10)
IDD
Positive Supply Current
Nap Mode
Sleep Mode
SHDN = 0V, CS = 0V
SHDN = 0V, CS = 5V
MIN
●
TYP
MAX
UNITS
4.75
5.25
V
– 4.75
– 5.25
V
7
1
1
10
1.6
mA
mA
µA
3
LTC1416
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POWER REQUIRE E TS
The ● denotes specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL
PARAMETER
ISS
Negative Supply Current
Nap Mode
Sleep Mode
SHDN = 0V, CS = 0V
SHDN = 0V, CS = 5V
Power Dissipation
Power Dissipation, Nap Mode
Power Dissipation, Sleep Mode
SHDN = 0V, CS = 0V
SHDN = 0V, CS = 5V
PDISS
CONDITIONS
TYP
MAX
●
MIN
7
20
15
10
UNITS
mA
µA
µA
●
70
4
0.1
100
6
mW
mW
mW
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TI I G CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5, see Figures 15 to 21)
SYMBOL
PARAMETER
CONDITIONS
fSAMPLE(MAX)
Maximum Sampling Frequency
●
400
tCONV
Conversion Time
●
1.5
tACQ
Acquisition Time
tACQ+CONV
Acquisition + Conversion Time
t1
CS to RD Setup Time
t2
t3
t4
SHDN↑ to CONVST↓ Wake-Up Time
CS = 0V (Note 10)
t5
CONVST Low Time
(Notes 10, 11)
t6
CONVST to BUSY Delay
CL = 25pF
(Note 9)
MIN
TYP
MAX
1.9
2.2
µs
●
100
400
ns
●
2
2.5
µs
kHz
(Notes 9, 10)
●
0
ns
CS↓ to CONVST↓ Setup Time
(Notes 9, 10)
●
10
ns
CS↓ to SHDN↓ Setup Time
(Notes 9, 10)
●
10
ns
●
40
400
Data Ready Before BUSY↑
25
(Note 9)
●
t8
Delay Between Conversions
t9
Wait Time RD↓ After BUSY↑
t10
Data Access Time After RD↓
(Note 10)
50
75
50
100
40
ns
–5
ns
CL = 25pF
15
25
35
ns
ns
20
35
50
ns
ns
8
20
25
30
ns
ns
ns
●
0°C ≤ TA ≤ 70°C
– 40°C ≤ TA ≤ 85°C
ns
ns
●
CL = 100pF
Bus Relinquish Time
ns
ns
●
●
t11
ns
ns
●
t7
UNITS
●
●
t12
RD Low Time
●
t 10
ns
t13
CONVST High Time
●
40
ns
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to ground with DGND and
AGND wired together unless otherwise noted.
Note 3: When these pin voltages are taken below VSS or above VDD, they
will be clamped by internal diodes. This product can handle input currents
greater than 100mA below VSS or above VDD without latchup.
Note 4: When these pin voltages are taken below VSS, they will be clamped
by internal diodes. This product can handle input currents greater than
100mA below VSS without latchup. These pins are not clamped to VDD.
Note 5: VDD = 5V, VSS = – 5V, fSAMPLE = 400kHz, t r = t f = 5ns unless
otherwise specified.
Note 6: Linearity, offset and full-scale specifications apply for a singleended AIN+ input with AIN– grounded.
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Note 7: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 8: Bipolar offset is the offset voltage measured from – 0.5LSB when
the output code flickers between 0000 0000 0000 00 and
1111 1111 1111 11.
Note 9: Guaranteed by design, not subject to test.
Note 10: Recommended operating conditions.
Note 11: The falling CONVST edge starts a conversion. If CONVST returns
high at a critical point during the conversion it can create small errors. For
best results ensure that CONVST returns high either within 900ns after the
start of the conversion or after BUSY rises.
LTC1416
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TYPICAL PERFORMANCE CHARACTERISTICS
S/(N + D) vs Input Frequency
and Amplitude
AMPLITUDE (dB BELOW THE FUNDAMENTAL)
VIN = 0dB
80
80
70
VIN = –20dB
60
50
40
30
VIN = –60dB
20
70
60
50
40
30
20
10
10
0
0
1k
10k
100k
INPUT FREQUENCY (Hz)
1k
1M 2M
10k
100k
INPUT FREQUENCY (Hz)
Spurious-Free Dynamic Range
vs Input Frequency
–20
–30
–40
–50
–60
–70
–80
–90
1M 2M
1k
–50
–60
–70
10k
100k
INPUT FREQUENCY (Hz)
1M 2M
1416 G03
Differential Nonlinearity
vs Output Code
1.0
VOUT = ±2.5V
VREF = 2.5V
0.5
–40
DNL ERROR (LSB)
–20
–40
2ND
–110
fSAMPLE = 400kHz
fa=87.01171876kHz
fb=113.1835938kHz
–20
–30
3RD
THD
–100
0
–10
AMPLITUDE (dB)
SPURIOUS-FREE DYNAMIC RANGE (dB)
–10
Intermodulation Distortion Plot
0
–60
–80
–100
0
–0.5
–80
–120
–90
–100
1k
10k
100k
INPUT FREQUENCY (Hz)
1M 2M
–140
0 20 40 60 80 100 120 140 160 180 200
FREQUENCY (Hz)
1416 G04
–1.0
0
–0.5
–20
–30
–40
–50
–60
–70
–80
4096
8192
12288
16384
OUTPUT CODE
1416 G07
16384
80
–10
DGND (VIN = 100mV)
VSS (VIN = 10mV)
–90
–100
0
12288
Input Common Mode Rejection
vs Input Frequency
COMMON MODE REJECTION (dB)
AMPLITUDE OF
POWER SUPPLY FEEDTHROUGH (dB)
0.5
8192
1416 G06
Power Supply Feedthrough
vs Ripple Frequency
VOUT = ±2.5V
VREF = 2.5V
4096
OUTPUT CODE
0
1.0
0
1416 G05
Integral Nonlinearity
vs Output Code
–1.0
0
1416 G02
1416 G01
INL ERROR (LSB)
Distortion vs Input Frequency
90
SIGNAL-TO-NOISE RATIO (dB)
SIGNAL/(NOISE + DISTORTION) (dB)
90
Signal-to-Noise Ratio
vs Input Frequency
VDD (VIN = 10mV)
70
60
50
40
30
20
10
0
1k
10k
100k
RIPPLE FREQUENCY (Hz)
1M 2M
1416 G08
1k
10k
100k
INPUT FREQUENCY (Hz)
1M 2M
1416 G09
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LTC1416
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PI FU CTIO S
AIN+ (Pin 1): ±2.5V Positive Analog Input.
AIN– (Pin 2): ±2.5V Negative Analog Input.
VREF (Pin 3): 2.5V Reference Output. Bypass to AGND
with 1µF.
REFCOMP (Pin 4): 4.06V Reference Output. Bypass to
AGND with 22µF tantalum in parallel with 0.1µF
ceramic, or 22µF ceramic.
AGND (Pin 5): Analog Ground.
D13 to D6 (Pins 6 to 13): Three-State Data Outputs.
DGND (Pin 14): Digital Ground for Internal Logic. Tie to
AGND.
D5 to D0 (Pins 15 to 20): Three-State Data Outputs.
SHDN (Pin 21): Power Shutdown Input. Low selects
shutdown. Shutdown mode selected by CS. CS = 0 for
nap mode and CS = 1 for sleep mode.
RD (Pin 22): Read Input. This enables the output
drivers when CS is low.
CONVST (Pin 23): Conversion Start Signal. This active
low signal starts a conversion on its falling edge.
CS (Pin 24): The Chip Select input must be low for the
ADC to recognize CONVST and RD inputs. CS also sets
the shutdown mode when SHDN goes low. CS and
SHDN low select the quick wake-up nap mode. CS high
and SHDN low select sleep mode.
BUSY (Pin 25): The BUSY output shows the converter
status. It is low when a conversion is in progress. Data
is valid on the rising edge of BUSY.
VSS (Pin 26): – 5V Negative Supply. Bypass to AGND
with 10µF tantalum in parallel with 0.1µF ceramic, or
10µF ceramic.
DVDD (Pin 27): 5V Positive Supply. Tie to Pin 28.
AVDD (Pin 28): 5V Positive Supply. Bypass to AGND
with 10µF tantalum in parallel with 0.1µF ceramic, or
10µF ceramic.
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FU CTIO AL BLOCK DIAGRA
CSAMPLE
AIN+
AVDD
DVDD
CSAMPLE
AIN–
VSS
4k
VREF
ZEROING SWITCHES
2.5V REF
+
REF AMP
COMP
14-BIT CAPACITIVE DAC
–
REFCOMP
(4.06V)
SUCCESSIVE APPROXIMATION
REGISTER
AGND
DGND
INTERNAL
CLOCK
OUTPUT LATCHES
•
•
•
D13
D0
CONTROL LOGIC
SHDN CONVST
6
14
RD
CS
BUSY
1416 BD
LTC1416
TEST CIRCUITS
Load Circuits for Access Timing
Load Circuits for Output Float Delay
5V
5V
1k
1k
DBN
DBN
DBN
1k
CL
1k
CL
(A) Hi-Z TO VOH AND VOL TO VOH
DBN
(B) Hi-Z TO VOL AND VOH TO VOL
1416 TC01
(A) VOH TO Hi-Z
100pF
100pF
(B) VOL TO Hi-Z
1416 TC02
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APPLICATIONS INFORMATION
CONVERSION DETAILS
The LTC1416 uses a successive approximation algorithm
and an internal sample-and-hold circuit to convert an
analog signal to a 14-bit parallel output. The ADC is
complete with a precision reference and an internal clock.
The control logic provides easy interface to microprocessors and DSPs. (Please refer to the Digital Interface
section for the data format.)
AIN+
CSAMPLE+
SAMPLE
HOLD
AIN–
CSAMPLE–
SAMPLE
HOLD
HOLD
ZEROING SWITCHES
CDAC+
HOLD
+
VDAC+
CDAC–
COMP
–
VDAC–
14
SAR
OUTPUT
LATCH
•
•
•
D13
D0
1416 F01
Figure 1. Simplified Block Diagram
Conversion start is controlled by the CS and CONVST
inputs. At the start of the conversion, the successive
approximation register (SAR) is reset. Once a conversion
cycle has begun, it cannot be restarted.
During the conversion, the internal differential 14-bit
capacitive DAC output is sequenced by the SAR from the
most significant bit (MSB) to the least significant bit
(LSB). Referring to Figure 1, the AIN+ and AIN– inputs are
connected to the sample-and-hold capacitors (CSAMPLE)
during the acquire phase and the comparator offset is
nulled by the zeroing switches. In this acquire phase, a
minimum delay of 400ns will provide enough time for the
sample-and-hold capacitors to acquire the analog signal.
During the convert phase the comparator zeroing switches
open, putting the comparator into compare mode. The
input switches connect the CSAMPLE capacitors to ground,
transferring the differential analog input charge onto the
summing junction. This input charge is successively compared with the binary-weighted charges supplied by the
differential capacitive DAC. Bit decisions are made by the
high speed comparator. At the end of a conversion, the
differential DAC output balances the AIN+ and AIN– input
charges. The SAR contents (a 14-bit data word) which
represents the difference of AIN+ and AIN– are loaded into
the 14-bit output latches.
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LTC1416
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APPLICATIONS INFORMATION
DYNAMIC PERFORMANCE
Signal-to-Noise Ratio
The LTC1416 has excellent high speed sampling capability. FFT (Fast Fourier Transform) test techniques are used
to test the ADC’s frequency response, distortion and noise
at the rated throughput. By applying a low distortion sine
wave and analyzing the digital output using an FFT algorithm, the ADC’s spectral content can be examined for
frequencies outside the fundamental. Figure 2 shows a
typical LTC1416 FFT plot.
The Signal-to-Noise plus Distortion Ratio [S/(N + D)] is the
ratio between the RMS amplitude of the fundamental input
frequency to the RMS amplitude of all other frequency
components at the A/D output. The output is band limited
to frequencies from above DC and below half the sampling
frequency. Figure 2a shows a typical spectral content with
a 400kHz sampling rate and a 100kHz input. The dynamic
performance is excellent for input frequencies up to and
beyond the Nyquist limit of 200kHz, Figure 2b.
0
fSAMPLE = 400kHz
fIN = 101.5625kHz
SFDR = 95.2dB
SINAD = 80.5dB
AMPLITUDE (dB)
–20
–40
Effective Number of Bits
The Effective Number of Bits (ENOBs) is a measurement of
the resolution of an ADC and is directly related to the
S/(N + D) by the equation:
–60
–80
ENOB = [S/(N + D) – 1.76]/6.02
–100
–120
–140
0
25
50
75
100 125 150 175 200
FREQUENCY (kHz)
1416 F02a
where ENOB is the Effective Number of Bits of resolution
and S/(N + D) is expressed in dB. At the maximum
sampling rate of 400kHz, the LTC1416 maintains near
ideal ENOBs up to the Nyquist input frequency of 200kHz
(refer to Figure 3).
Figure 2a. LTC1416 Nonaveraged, 4096 Point FFT,
Input Frequency = 100kHz
AMPLITUDE (dB)
–40
EFFECTIVE BITS
fSAMPLE = 400kHz
fIN = 189.9414kHz
SFDR = 94.8dB
SINAD = 80.2dB
–20
–60
–80
–100
–120
NYQUIST
FREQUENCY
fSAMPLE = 400kHz
1k
–140
0
25
50
75
100 125 150 175 200
86
80
74
68
62
SIGNAL/(NOISE + DISTORTION) (dB)
0
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
10k
100k
INPUT FREQUENCY (Hz)
1M 2M
1416 TA02
FREQUENCY (kHz)
1416 F02b
Figure 2b. LTC1416 Nonaveraged, 4096 Point FFT,
Input Frequency = 190kHz
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Figure 3. Effective Bits and Signal/(Noise + Distortion)
vs Input Frequency
LTC1416
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APPLICATIONS INFORMATION
Total Harmonic Distortion (THD) is the ratio of the RMS
sum of all harmonics of the input signal to the fundamental
itself. The out-of-band harmonics alias into the frequency
band between DC and half the sampling frequency. THD is
expressed as:
THD = 20 log
V22 + V32 + V42 + ...Vn2
V1
AMPLITUDE (dB BELOW THE FUNDAMENTAL)
where V1 is the RMS amplitude of the fundamental frequency and V2 through Vn are the amplitudes of the
second through Nth harmonics. THD versus input frequency is shown in Figure 4. The LTC1416 has good
distortion performance up to the Nyquist frequency and
beyond.
difference frequencies of mfa ± nfb, where m and n = 0, 1,
2, 3, etc. For example, the 2nd order IMD terms include (fa
+ fb). If the two input sine waves are equal in magnitude,
the value (in decibels) of the 2nd order IMD products can
be expressed by the following formula:
(
)
IMD fa + fb = 20 log
(
)
Amplitude at fa + fb
Amplitude at fa
0
–20
AMPLITUDE (dB)
Total Harmonic Distortion
fSAMPLE = 400kHz
fa=87.01171876kHz
fb=113.1835938kHz
–40
–60
–80
–100
0
–10
–120
–20
–140
–30
0 20 40 60 80 100 120 140 160 180 200
FREQUENCY (Hz)
–40
–50
1416 G05
–60
Figure 5. Intermodulation Distortion Plot
–70
–80
–90
3RD
THD
Peak Harmonic or Spurious Noise
2ND
–100
–110
1k
10k
100k
INPUT FREQUENCY (Hz)
1M 2M
1416 G03
Figure 4. Distortion vs Input Frequency
Intermodulation Distortion
If the ADC input signal consists of more than one spectral
component, the ADC transfer function nonlinearity can
produce intermodulation distortion (IMD) in addition to
THD. IMD is the change in one sinusoidal input caused by
the presence of another sinusoidal input at a different
frequency.
If two pure sine waves of frequencies fa and fb are applied
to the ADC input, nonlinearities in the ADC transfer
function can create distortion products at the sum and
The peak harmonic or spurious noise is the largest spectral component excluding the input signal and DC. This
value is expressed in decibels relative to the RMS value of
a full-scale input signal.
Full-Power and Full-Linear Bandwidth
The full-power bandwidth is that input frequency at which
the amplitude of the reconstructed fundamental is
reduced by 3dB for a full-scale input signal. The full-linear
bandwidth is the input frequency at which the S/(N + D)
has dropped to 77dB (12.5 effective bits). The LTC1416
has been designed to optimize input bandwidth, allowing
the ADC to undersample input signals with frequencies
above the converter’s Nyquist frequency. The noise floor
stays very low at high frequencies; S/(N + D) becomes
dominated by distortion at frequencies far beyond Nyquist.
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Driving the Analog Input
The differential analog inputs of the LTC1416 are easy to
drive. The inputs may be driven differentially or as a singleended input (i.e., the AIN– input is grounded). The AIN+ and
AIN– inputs are sampled at the same instant. Any unwanted signal that is common mode to both inputs will be
reduced by the common mode rejection of the sampleand-hold circuit. The inputs draw only one small current
spike while charging the sample-and-hold capacitors at
the end of conversion. During conversion, the analog
inputs draw only a small leakage current. If the source
impedance of the driving circuit is low, then the LTC1416
inputs can be driven directly. As source impedance
increases so will acquisition time (see Figure 6). For
minimum acquisition time, with high source impedance, a
buffer amplifier should be used. The only requirement
is that the amplifier driving the analog input(s) must
settle after the small current spike before the next
conversion starts (settling time must be 400ns for full
throughput rate).
ACQUISITION TIME (µs)
The best choice for an op amp to drive LTC1416 will
depend on the application. Generally, applications fall into
two categories: AC applications where dynamic specifications are most critical and time domain applications where
DC accuracy and settling time are most critical. The
following list is a summary of the op amps that are suitable
for driving the LTC1416. More detailed information is
available in the Linear Technology Databooks and the
LinearViewTM CD-ROM.
LT ®1220: 30MHz unity-gain bandwidth voltage feedback
amplifier. ±5V to ±15V supplies, excellent DC specifications.
LT1223: 100MHz video current feedback amplifier. 6mA
supply current, ±5V to ±15V supplies, low distortion at
frequencies above 400kHz, low noise, good for AC applications.
10
1
LT1227: 140MHz video current feedback amplifier. 10mA
supply current, ±5V to ±15V supplies, lowest distortion at
frequencies above 400kHz, low noise, best for AC applications.
0.1
0.01
10
frequency. For example, if an amplifier is used in a gain of
1 and has a unity-gain bandwidth of 50MHz, then the
output impedance at 50MHz should be less than 100Ω.
The second requirement is that the closed-loop bandwidth
must be greater than 10MHz to ensure adequate smallsignal settling for full throughput rate. If slower op amps
are used, more settling time can be provided by increasing
the time between conversions.
100
1k
10k
SOURCE RESISTANCE (Ω)
100k
LT1229/LT1230: Dual and quad 100MHz current feedback
amplifiers. ±2V to ±15V supplies, low noise, good AC
specs, 6mA supply current each amplifier.
1416 F06
Figure 6. Acquisition Time vs Source Resistance
Choosing an Input Amplifier
Choosing an input amplifier is easy if a few requirements
are taken into consideration. First, to limit the magnitude
of the voltage spike seen by the amplifier from charging the
sampling capacitor, choose an amplifier that has a low
output impedance (<100Ω) at the closed-loop bandwidth
10
LT1360: 50MHz voltage feedback amplifier. 3.8mA supply
current, good AC and DC specs, ±5V to ±15V supplies.
LT1363: 70MHz, 1000V/µs op amps. 6.3mA supply current, good AC and DC specs.
LT1364/LT1365: Dual and quad 70MHz, 100V/µs op amps.
6.3mA supply current per amplifier.
LinearView is a trademark of Linear Technology Corporation.
LTC1416
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Input Filtering
The noise and the distortion of the input amplifier and
other circuitry must be considered since they will add to
the LTC1416 noise and distortion. The small-signal bandwidth of the sample-and-hold circuit is 15MHz. Any noise
or distortion products that are present at the analog inputs
will be summed over this entire bandwidth. Noisy input
circuitry should be filtered prior to the analog inputs to
minimize noise. A simple 1-pole RC filter is sufficient for
many applications. For example, Figure 7 shows a 1000pF
capacitor from AIN+ to ground and a 200Ω source resistor
to limit the input bandwidth to 800kHz. The 1000pF
capacitor also acts as a charge reservoir for the input
sample-and-hold and isolates the ADC input from sampling glitch sensitive circuitry. High quality capacitors and
resistors should be used since these components can add
distortion. NPO and silver mica type dielectric capacitors
have excellent linearity. Carbon surface mount resistors
can also generate distortion from self-heating and from
damage that may occur during soldering. Metal film
surface mount resistors are much less susceptible to both
problems.
ANALOG
INPUT
200Ω
1000pF
1
AIN+
2
AIN–
3
4
22µF
5
accommodate other input ranges often with little or no
additional circuitry. The following sections describe the
reference and input circuitry and how they affect the input
range.
Internal Reference
The LTC1416 has an on-chip, temperature compensated,
curvature corrected, bandgap reference that is factory
trimmed to 2.500V. It is connected internally to a reference
amplifier and is available at VREF (Pin 3). See Figure 8a. A
4k resistor is in series with the output so that it can be
easily overdriven by an external reference or other circuitry (see Figure 8b). The reference amplifier gains the
voltage at the VREF pin by 1.625 to create the required
internal reference voltage. This provides buffering between the VREF pin and the high speed capacitive DAC. The
2.5V
4.0625V
R1
4k
3
VREF
4
REFCOMP
BANDGAP
REFERENCE
REF
AMP
R2
80k
22µF
5
LTC1416
AGND
R3
128k
LTC1416
VREF
1416 F08a
REFCOMP
Figure 8a. LTC1416 Reference Circuit
AGND
1416 F07
Figure 7. RC Input Filter
5V
Input Range
The ±2.5V input range of the LTC1416 is optimized for low
noise and low distortion. Most op amps also perform best
over this same range, allowing direct coupling to the
analog inputs and eliminating the need for special translation circuitry.
Some applications may require other input ranges. The
LTC1416 differential inputs and reference circuitry can
VIN
ANALOG
INPUT
LT1019A-2.5
VOUT
1
AIN+
2
AIN–
3
4
22µF
5
LTC1416
VREF
REFCOMP
AGND
1416 F08b
Figure 8b. Using the LT1019-2.5 as an External Reference
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The VREF pin can be driven with a DAC or other means
shown in Figure 9. This is useful in applications where the
peak input signal amplitude may vary. The input span of
the ADC can then be adjusted to match the peak input
signal, maximizing the signal-to-noise ratio. The filtering
of the internal LTC1416 reference amplifier will limit the
bandwidth and settling time of this circuit. A settling time
of 5ms should be allowed for after a reference adjustment.
LTC1450
1
ANALOG
INPUT
AIN+
2
AIN–
1.25V TO 3V
3
4
22µF
80
COMMON MODE REJECTION (dB)
reference amplifier compensation pin, REFCOMP (Pin 4),
must be bypassed with a capacitor to ground. The reference amplifier is stable with capacitors of 1µF or greater.
For the best noise performance, a 22µF ceramic or 22µF
tantalum in parallel with a 0.1µF ceramic is recommended.
70
60
50
40
30
20
10
0
1k
10k
100k
INPUT FREQUENCY (Hz)
1416 G09
Figure 10a. CMRR vs Input Frequency
ANALOG INPUT
LTC1416
±2.5V
VREF
1
AIN+
2
AIN–
3
0V TO 5V
4
REFCOMP
22µF
5
AGND
5
VREF
Differential Inputs
The LTC1416 has a unique differential sample-and-hold
circuit that allows rail-to-rail inputs. The ADC will always
convert the difference of AIN+ – AIN– independent of the
common mode voltage. The common mode rejection
holds up to extremely high frequencies (see Figure 10a).
The only requirement is that both inputs cannot exceed the
AVDD or AVSS power supply voltages. Integral nonlinearity
errors (INL) and differential nonlinearity errors (DNL) are
independent of the common mode voltage, however, the
bipolar zero error (BZE) will vary. The change in BZE is
typically less than 0.1% of the common mode voltage.
Dynamic performance is also affected by the common
mode voltage. THD will degrade as the inputs approach
either power supply rail, from 90dB with a common mode
of 0V to 79dB with a common mode of 2.5V or – 2.5V.
Differential inputs allow greater flexibility for accepting
different input ranges. Figure 10b shows a circuit that
12
LTC1416
REFCOMP
AGND
1416 F10b
1416 F09
Figure 9. Driving VREF with a DAC
1M 2M
Figure 10b. Selectable 0V to 5V or ±2.5V Input Range
converts a 0V to 5V analog input signal with no additional
translation circuitry.
Full-Scale and Offset Adjustment
Figure 11a shows the ideal input/output characteristics for
the LTC1416. The code transitions occur midway between
successive integer LSB values (i.e., – FS + 0.5LSB, – FS +
1.5LSB, – FS + 2.5LSB, . . . FS – 1.5LSB, FS – 0.5LSB). The
output is two’s complement binary with 1LSB = FS –
(– FS)/16384 = 5V/16384 = 305.2µV.
In applications where absolute accuracy is important,
offset and full-scale errors can be adjusted to zero. Offset
error must be adjusted before full-scale error. Figure 11b
shows the extra components required for full-scale error
adjustment. Zero offset is achieved by adjusting the offset
applied to the AIN– input. For zero offset error, apply
– 152µV (i.e., – 0.5LSB) at AIN+ and adjust the offset at the
AIN– input until the output code flickers between 0000
LTC1416
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0000 0000 00 and 1111 1111 1111 11. For full-scale
adjustment, an input voltage of 2.499544V (FS/2 – 1.5LSB)
is applied to AIN and R2 is adjusted until the output code
flickers between 0111 1111 1111 10 and 0111 1111
1111 11.
011...111
OUTPUT CODE
011...110
000...001
000...000
111...111
111...110
100...001
BOARD LAYOUT AND BYPASSING
100...000
FS – 1LSB
– (FS – 1LSB)
INPUT VOLTAGE (AIN+ – AIN–)
1416 F11a
Figure 11a. LTC1416 Transfer Characteristics
–5V
R3
24k
R1
50k
applications, however, do not have a –5V supply readily
available and most ADCs have inadequate PSRR to sufficiently attenuate the noise created by a switching or
charge pump supply. The LTC1416’s excellent PSRR
makes it possible to achieve good performance, even at 14
bits, using a switch based regulator for a –5V supply.
Figure 12a shows a circuit using an LT1373 configured as
a Cuk converter creating –5V from a 5V supply. The circuit
shown in Figure 12b uses an LT1054 regulated charge
pump to provide –5V. This circuit has the advantage of
reduced board space and fewer passive components. (For
further details refer to Linear Technology Magazine, June
1997, Page 29.)
ANALOG
INPUT
R4
100Ω
1
AIN+
2
AIN–
3
R5 R2
47k 50k
R6
24k
4
5
22µF
LTC1416
VREF
REFCOMP
AGND
1416 F11b
Figure 11b. Offset and Full-Scale Adjust Circuit
Generating a – 5V Supply
There are several advantages to using ±5V supplies rather
than a single 5V supply. A larger signal magnitude is
possible which increases the dynamic range and
improves the signal-to-noise ratio. Operating on ±5V
supplies also offers increased headroom which eases the
requirements for signal conditioning circuitry, avoids the
limitations of rail-to-rail operation and widens the selection of high performance operational amplifiers. Some
Wire wrap boards are not recommended for high resolution or high speed A/D converters. To obtain the best
performance from the LTC1416, a printed circuit board
with ground plane is required. Layout for the printed
circuit board should ensure that digital and analog signal
lines are separated as much as possible. In particular, care
should be taken not to run any digital track alongside an
analog signal track or underneath the ADC. The analog
input should be screened by AGND.
An analog ground plane separate from the logic system
ground should be established under and around the ADC
(see Figure 13). Pin 5 (AGND), Pins 14 and 19 (ADC’s
DGND) and all other analog grounds should be connected
to this single analog ground point. The REFCOMP bypass
capacitor and the DVDD bypass capacitor should also be
connected to this analog ground plane. No other digital
grounds should be connected to this analog ground plane.
Low impedance analog and digital power supply common
returns are essential to low noise operation of the ADC and
the foil width for these tracks should be as wide as
possible. In applications where the ADC data outputs and
control signals are connected to a continuously active
microprocessor bus, it is possible to get errors in the
conversion results. These errors are due to feedthrough
from the microprocessor to the successive approximation
comparator. The problem can be eliminated by forcing the
microprocessor into a Wait state during conversion or by
using three-state buffers to isolate the ADC data bus. The
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5V
1µF CER
1
AIN+
AVDD
2
AIN–
DVDD
VREF
VSS
3
4
C5
5
6
7
8
9
10
11
12
13
14
COMP
BUSY
AGND
CS
CONVST
D13 (MSB)
RD
D12
SHDN
D11
D10
D0
LTC1416
D9
D1
D8
D2
D7
D3
D6
D4
DGND
D5
2 L1 3
C7
1
–5V
28
27
26
CUK*
CONVERTER
25
24
5
23
C8
22µF
10V
TANT
MICROPROCESSOR/
MICROCONTROLLER
INTERFACE
22
21
+
4
7
6
VIN
S/S
C10
10µF
CER
VSW
U2
LT1373
GND
GND S
20
4
NFB
VC
8
R4
4.99k
1%
3
1
C12
0.1µF
D1
R3
4.99k
19
C9
0.01µF
18
C11
100µF
10V
TANT
+
ANALOG
INPUT
C6
R5
4.99k
1%
R6
499Ω
1%
1416 F12a
17
C5 = 22µF CERAMIC
C6, C7 = 10µF CERAMIC
L1 = OCTAPAC CTX-100-1
D1 = 1N5818
16
15
Figure 12a. Using the LT1373 to Generate a – 5V Supply
5V
–5V
C6
ANALOG
INPUT
1µF CER
1
AIN+
AVDD
2
AIN–
DVDD
3
4
C5
5
6
7
8
9
10
11
12
13
14
VREF
VSS
BUSY
COMP
CS
AGND
D13 (MSB)
CONVST
D12
RD
D11
SHDN
D0
D10
LTC1416
D9
D1
D8
D2
D7
D3
D6
D4
DGND
D5
28
C2
2µF
27
1
C7
26
2
25
C1
10µF
TANT
24
23
22
+
FB/SHDN
V+
7
OSC
U1
LT1054
3
6
VREF
GND
4
5
CAP –
VOUT
MICROPROCESSOR/
MICROCONTROLLER
INTERFACE
20
19
18
17
C5 = 22µF CERAMIC
C6, C7 = 10µF CERAMIC
15
Figure 12b. Using the LT1054 to Generate a – 5V Supply
14
8
+
CAP+
21
16
C4
100µF
TANT
R1, 30.1k
C3
0.002µF
R2, 120k
1416 F12b
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1
AIN+
AIN–
ANALOG
INPUT
CIRCUITRY
+
–
2
DIGITAL
SYSTEM
LTC1416
REFCOMP
AGND
5
4
VSS
26
22µF
10µF
AVDD
DVDD
DGND
28
27
14
10µF
1416 F13
Figure 13. Power Supply Grounding Practice.
traces connecting the pins and bypass capacitors must be
kept short and should be made as wide as possible.
The LTC1416 has differential inputs to minimize noise
coupling. Common mode noise on the AIN+ and AIN– leads
will be rejected by the input CMRR. The AIN– input can be
used as a ground sense for the AIN+ input; the LTC1416
will hold and convert the difference voltage between AIN+
and AIN– . The leads to AIN+ (Pin 1) and AIN– (Pin 2) should
be kept as short as possible. In applications where this is
not possible, the AIN+ and AIN– traces should be run side
by side to equalize coupling.
Supply Bypassing
High quality, low series resistance ceramic, bypass
capacitors should be used at the VDD (10µF) and REFCOMP
(22µF) pins as shown in the Typical Application on the first
page of this data sheet. Surface mount ceramic capacitors
such as Murata GRM235Y5V106Z016 provide excellent
bypassing in a small board space. Alternatively tantalum
capacitors in parallel with 0.1µF ceramic capacitors can be
used. Bypass capacitors must be located as close to the
pins as possible. The traces connecting the pins and the
bypass capacitors must be kept short and should be made
as wide as possible.
Example Layout
Figures 14a, 14b, 14c and 14d show the schematic and
layout of an evaluation board. The layout demonstrates the
proper use of decoupling capacitors and ground plane
with a 2-layer printed circuit board.
DIGITAL INTERFACE
The A/D converter is designed to interface with microprocessors as a memory mapped device. The CS and RD
control inputs are common to all peripheral memory
interfacing. A separate CONVST is used to initiate a conversion.
Internal Clock
The A/D converter has an internal clock that eliminates the
need for synchronization between the external clock and
the CS and RD signals found in other ADCs. The internal
clock is factory trimmed to achieve a typical conversion
time of 1.8µs, and a maximum conversion time over the
full operating temperature range of 2.2µs. No external
adjustments are required. The guaranteed maximum
acquisition time is 400ns. In addition, a throughput time
of 2.5µs and a minimum sampling rate of 400ksps is
guaranteed.
Power Shutdown
The LTC1416 provides two power shutdown modes—nap
mode and sleep mode to save power during inactive
periods. The nap mode reduces the power by 95% and
leaves only the digital logic and reference powered up. The
wake-up time from nap to active is 400ns. In sleep mode,
the reference is shut down and only a small current of
120µA remains. Wake-up time from sleep mode is much
slower since the reference circuit must power up and
settle to 0.005% for full 14-bit accuracy. Sleep mode
wake-up time is dependent on the value of the capacitor
connected to the REFCOMP (Pin 4). The wake-up time is
20ms with the recommended 22µF capacitor.
15
CLK
A–
A+
VLOGIC
JP5A
JP5B
JP5C
1
JP2
RD
CS
2
C8
1µF
10V
3
3
HC14
U7B
C11
1000pF
R15
51Ω
D15
SS12
R16
51Ω
SHDN
HC14
U7A
JP4
DGND
R19
51Ω
R18
10k
R17
10k
VOUT
GND TABGND
2
4
VIN
LT1121-5
NOTES: UNLESS OTHERWISE SPECIFIED
ALL RESISTOR VALUES IN OHMS, 5%
J7
J5
AGND
J2
J4
GND
+VIN
1
U2
4
C2
22µF
10V
VREF
JP3
C13
22µF
10 V
+
VCC
4
1
8
R20
1M
VCC
C9
10µF
10V
C3
VSS
0.1µF
V–
C4
0.1µF
U3
7 LT1363
–
6
3 +
V+
2
VOUT
VCC
C12
0.1µF
R14
20Ω
+
4
3
2
1
14
5
26
27
28
21
22
23
24
25
U4
LTC1416
DATA READY
DGND
AGND
VSS
DVDD
AVDD
SHDN
RD
CONVST
CS
BUSY
REFCOMP
VREF
AIN–
AIN+
C10
10µF
10V
B10
9
5
GND
VOUT
U7F
1
U7C
9
8
7
6
5
4
3
2
11
1
9
8
7
6
5
4
3
2
11
D7
D6
D5
D4
D3
D2
D1
D0
0E
6
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
U6
74HC574
Q7
Q6
D7
D6
Q4
D4
Q5
Q3
D5
Q2
D3
Q1
Q0
D2
D1
D0
0E
U5
74HC574
C1
22µF
10V
R21
1k
12
13
14
15
16
17
18
19
12
13
14
15
16
17
18
19
D06
D07
D08
D09
D10
D11
D12
D13
D05
D04
D03
D02
D01
D00
11
U7E
D[00:13]
D13
U7G
HC14
GND
7
VCC
14
HC14
12
HC14
C6
15pF
9
HC14
U7D
HC14
8
10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D07
D06
D05
D04
D03
D02
D01
D00
RDY
D13
D13
D12
D11
D10
DGND
HEADER
18-PIN
DGND
J6-18
RDY
D13
D13
D12
D11
D10
D09
D08
D07
D06
D05
D04
D03
D02
D01
D00
J6-17
J6-16
J6-15
J6-2
J6-1
J6-4
J6-3
J6-6
J6-5
J6-8
J6-7
J6-10
J6-9
J6-12
J6-11
J6-14
J6-13
R13, 1.2k D13
R12, 1.2k D12
D12
D13
R11, 1.2k D11
R10, 1.2k D10
R9, 1.2k
R8, 1.2k
R7, 1.2k
R6, 1.2k
R5, 1.2k
R4, 1.2k
R3, 1.2k
R2, 1.2k
R1, 1.2k
R0, 1.2k
D11
D10
D09
D08
D07
D06
D05
D04
D03
D02
D01
D00
D09
5
VSS
20 B00
13
B06
B07
B08
B09
B10
B11
B12
D14
SS12
1
D08
VLOGIC
B[00:13]
VIN
U1
79L05
19 B01
18 B02
17 B03
16 B04
15 B05
13 B06
12 B07
11 B08
10 B09
B11
B12
8
B13
7
2
6
C15
0.1µF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
–VIN
J1
–7V TO
–15V
Figure 14a. Suggested Evaluation Circuit Schematic
C5
10µF
10V
VSS
C14
0.1µF
VLOGIC
1416 F14a
JP1
LED
D13
D12
D11
D10
D09
D08
D07
D06
D05
D04
D03
D02
D01
D00
U
U
W
J3
7V TO
15V
APPLICATIONS INFORMATION
U
16
+
VCC
LTC1416
LTC1416
U
W
U
U
APPLICATIONS INFORMATION
Figure 14b. Suggested Evaluation Circuit Board—
Component Side Silkscreen
Figure 14c. Suggested Evaluation Circuit Board—
Component Side Layout
CS
t3
SHDN
1416 F15a
Figure 15a. CS to SHDN Timing
SHDN
t4
CONVST
1416 F15b
Figure 15b. SHDN to CONVST Wake-Up Timing
Figure 14d. Suggested Evaluation Circuit Board—
Solder Side Layout
17
LTC1416
U
U
W
U
APPLICATIONS INFORMATION
Shutdown is controlled by Pin 21 (SHDN), the ADC is in
shutdown when it is low. The shutdown mode is selected
with Pin 20 (CS), low selects nap.
starts the conversion and reads the output with the RD
signal. Conversions are started by the MPU or DSP (no
external sample clock).
Timing and Control
In slow memory mode, the processor applies a logic low
to RD (= CONVST), starting the conversion. BUSY goes
low, forcing the processor into a Wait state. The previous
conversion result appears on the data outputs. When the
conversion is complete, the new conversion results
appear on the data outputs; BUSY goes high releasing the
processor, and the processor takes RD (= CONVST) back
high and reads the new conversion data.
Conversion start and data read operations are controlled
by three digital inputs: CONVST, CS and RD. A logic “0”
applied to the CONVST pin will start a conversion after the
ADC has been selected (i.e., CS is low). Once initiated, it
cannot be restarted until the conversion is complete.
Converter status is indicated by the BUSY output. BUSY is
low during a conversion.
In ROM mode, the processor takes RD (= CONVST) low,
starting a conversion and reading the previous conversion
result. After the conversion is complete, the processor can
read the new result and initiate another conversion.
Figures 16 through 21 show several different modes of
operation. In modes 1a and 1b (Figures 17 and 18), CS and
RD are both tied low. The falling edge of CONVST starts the
conversion. The data outputs are always enabled and data
can be latched with the BUSY rising edge. Mode 1a shows
operation with a narrow logic low CONVST pulse. Mode 1b
shows a narrow logic high CONVST pulse.
CS
t2
In mode 2 (Figure 19), CS is tied low. The falling edge of
CONVST signal again starts the conversion. Data outputs
are in three-state until read by the MPU with the RD signal.
Mode 2 can be used for operation with a shared MPU data
bus.
CONVST
t1
RD
1416 F16
In slow memory and ROM modes (Figures 20 and 21), CS
is tied low and CONVST and RD are tied together. The MPU
Figure 16. CS to CONVST Setup Timing
t CONV
CS = RD = 0
(SAMPLE N)
t5
CONVST
t6
t8
BUSY
t7
DATA
DATA (N – 1)
DB13 TO DB0
DATA N
DB13 TO DB0
DATA (N + 1)
DB13 TO DB0
1416 F17
Figure 17. Mode 1a. CONVST Starts a Conversion. Data Outputs Always Enabled
(CONVST =
18
)
LTC1416
U
U
W
U
APPLICATIONS INFORMATION
tCONV
CS = RD = 0
t8
t5
t13
CONVST
t6
t6
t6
BUSY
t7
DATA (N – 1)
DB13 TO DB0
DATA
DATA N
DB13 TO DB0
DATA (N + 1)
DB13 TO DB0
1416 F18
Figure 18. Mode 1b. CONVST Starts a Conversion. Data Outputs Always Enabled
(CONVST =
)
t13
(SAMPLE N)
tCONV
t5
CS = 0
t8
CONVST
t6
BUSY
t9
t 12
t 11
RD
t 10
DATA N
DB13 TO DB0
DATA
1416 F19
Figure 19. Mode 2. CONVST Starts a Conversion. Data Is Read by RD
t8
t CONV
CS = 0
(SAMPLE N)
RD = CONVST
t6
t 11
BUSY
t 10
DATA
t7
DATA (N – 1)
DB13 TO DB0
DATA N
DB13 TO DB0
DATA N
DB13 TO DB0
DATA (N + 1)
DB13 TO DB0
1416 F20
Figure 20. Slow Memory Mode Timing
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
19
LTC1416
U
U
W
U
APPLICATIONS INFORMATION
t CONV
CS = 0
t8
(SAMPLE N)
RD = CONVST
t6
t 11
BUSY
t 10
DATA N
DB13 TO DB0
DATA (N – 1)
DB13 TO DB0
DATA
1416 F21
Figure 21. ROM Mode Timing
U
PACKAGE DESCRIPTIO
Dimensions in inches (millimeters) unless otherwise noted.
G Package
28-Lead Plastic SSOP (0.209)
(LTC DWG # 05-08-1640)
5.20 – 5.38**
(0.205 – 0.212)
1.73 – 1.99
(0.068 – 0.078)
10.07 – 10.33*
(0.397 – 0.407)
28 27 26 25 24 23 22 21 20 19 18 17 16 15
0° – 8°
0.55 – 0.95
(0.022 – 0.037)
0.13 – 0.22
(0.005 – 0.009)
0.65
(0.0256)
BSC
0.25 – 0.38
NOTE: DIMENSIONS ARE IN MILLIMETERS
(0.010 – 0.015)
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.152mm (0.006") PER SIDE
**DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.254mm (0.010") PER SIDE
7.65 – 7.90
(0.301 – 0.311)
0.05 – 0.21
(0.002 – 0.008)
1 2 3 4 5 6 7 8 9 10 11 12 13 14
G28 SSOP 1098
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DESCRIPTION
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Low Power, ±10V Inputs
LTC1606
16-Bit, 250ksps ADC
±10V Inputs, Pin Compatible with the LTC1605
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16-Bit, 500ksps ADC
16-Bit, No Missing Codes, Pin Compatible with the LTC1604
20
Linear Technology Corporation
1416fa LT/LCG 0600 2K REV A • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408)432-1900 ● FAX: (408) 434-0507 ● www.linear-tech.com
 LINEAR TECHNOLOGY CORPORATION 1997