MOTOROLA MC145532 Adpcm transcoder Datasheet

 Order this document
by MC145532/D
SEMICONDUCTOR TECHNICAL DATA
Conforms to G.721–1988 and T1.301–1987
The MC145532 Adaptive Differential Pulse Code Modulation (ADPCM)
Transcoder provides a low–cost, full–duplex, single–channel transcoder to
(from) a 64 kbps PCM channel from (to) either a 16 kbps, 24 kbps, 32 kbps, or
64 kbps channel.
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Complies with CCITT Recommendation G.721–1988
Complies with the American National Standard (T1.301–1987)
Full–Duplex, Single–Channel Operation
Mu–Law or A–Law Coding is Pin Selectable
Synchronous or Asynchronous Operation
Easily Interfaces with Any Member of Motorola’s PCM Codec–Filter
Mono–Circuit Family or Other Industry Standard Codec
Serial PCM and ADPCM Data Transfer Rate from 64 kbps to 5.12 Mbps
Power–Down Capability for Low Current Consumption
The Reset State, an Option Specified in the Standards, is Automatically
Initiated When the RESET Pin is Released
Simple Time Slot Assignment Timing for Transcoder Applications
Single 5 V Power Supply
16–Pin Package
The MC145536EVK is the Evaluation Platform for the MC145532 and Also
Includes the MC145480 5 V PCM Codec–Filter
DW SUFFIX
SOG PACKAGE
CASE 751G
16
1
L SUFFIX
CERAMIC PACKAGE
CASE 620
16
1
ORDERING INFORMATION
MC145532DW SOG Package
MC145532L
Ceramic Package
PIN ASSIGNMENT
MODE
1
16
VDD
DDO
2
15
EDO
DOE
3
14
EOE
DDC
4
13
EDC
DDI
5
12
EDI
DIE
6
11
EIE
RESET
7
10
SPC
VSS
8
9
APD
BLOCK DIAGRAM
DDO
EDO
I/O DATA BUS
EDE
DOE
S REG
REG
LATCH
S REG
DDC
EDC
DDI
EDI
S REG
DIE
MODE
LATCH
DIGITAL
SIGNAL
PROCESSOR
REG
S REG
EIE
RESET
APD
SPC
VSS
VDD
REV 1
9/95 (Replaces NP470)

Motorola, Inc. 1995
MOTOROLA
MC145532
1
DEVICE DESCRIPTION
An Adaptive Differential PCM (ADPCM) transcoder is used
to reduce the data rate required to transmit a PCM encoded
voice signal while maintaining the voice fidelity and intelligibility of the PCM signal.
The transcoder is used on 64 kbps data streams which
represent either voice or voice band data signals that have
been digitized by a codec (e.g., MC145557). The transcoder
uses a filter to attempt to predict the next PCM input value
based on previous PCM input values. The error between the
predicted and the true PCM input value is the information
that is sent to the other end of the line. Hence the word differential, since the ADPCM data stream is the difference between the true PCM input value and the predicted value. The
term “adaptive” applies to the filter that is performing the prediction. It is adaptive in that its transfer function changes
based on the PCM input data. That is, it adapts to the statistics of the signals presented to it.
PIN DESCRIPTIONS
ENCODER INPUT
DECODER INPUT
DDI
Decoder Data Input (Pin 5)
ADPCM data to be decoded are applied to this input pin,
which operates in conjunction with DDC and DIE to enter the
data in a serial format.
DDC
Decoder Data Clock (Pin 4)
Data applied to DDI are latched into the transcoder on the
falling edge of DDC and data are output from DDO on the rising edge of DDC. The frequency of DDC may be as low as
64 kHz or as high as 5.12 MHz.
DIE
Decoder Input Enable (Pin 6)
The beginning of a new ADPCM word is indicated by a rising edge applied to this input. Data are serially clocked into
DDI on the subsequent falling edges of DDC following the
DIE rising edge. The frequency of DIE may not exceed
8 kHz.
DECODER OUTPUT
EDI
Encoder Data Input (Pin 12)
DDO
Decoder Data Output (Pin 2)
PCM data to be encoded are applied to this input pin which
operates synchronously with EDC and EIE to enter the data
in a serial format.
PCM data are available in a serial format from this output,
which operates in conjunction with DDC and DOE. DDO is a
three–state output that remains at a high–impedance state
except when presenting data.
EDC
Encoder Data Clock (Pin 13)
Data applied to EDI are latched into the transcoder on a
falling edge of EDC and data are output from EDO on a rising
edge of this input pin. The frequency of EDC may be as low
as 64 kHz or as high as 5.12 MHz.
DOE
Decoder Output Enable (Pin 3)
Each ADPCM word is requested by a rising edge on this
input which causes the DDO pin to provide the data when
clocked by DDC. One DOE must occur for each DIE.
CONTEXT
EIE
Encoder Input Enable (Pin 11)
MODE
Mode Select (Pin 1)
The beginning of a new PCM word is indicated to the
transcoder by a rising edge applied to this input. The frequency of EIE may not exceed 8 kHz.
A logic 0 applied to this input makes the transcoder compatible with Mu–255 companding and D3 data format. A
logic 1 applied to this pin makes the transcoder compatible
with A–Law companding with even bit inversion data format.
ENCODER OUTPUT
EDO
Encoder Data Output (Pin 15)
ADPCM data are available in a serial format from this output, which operates synchronously with EDC and EOE. EDO
is a three–state output which remains in a high–impedance
state, except when presenting data.
EOE
Encoder Output Enable (Pin 14)
Each ADPCM word is requested by a rising edge on this
input, which causes the EDO pin to provide the data when
clocked by EDC. One EOE must occur for each EIE.
MC145532
2
SPC
Signal Processor Clock (Pin 10)
This input is typically clocked with a 20.48 MHz clock signal which is used as the digital signal processor master
clock. This pin has a CMOS compatible input.
RESET
Reset (Pin 7)
A logic 0 applied to this input forces the transcoder into a
low power dissipation mode. A rising edge on this pin causes
power to be restored and the optional transcoder RESET
state (specified in the standards) to be forced. Valid data is
available at the output pins four input enables after a rising
edge on this pin. This pin has a CMOS compatible input.
MOTOROLA
APD
Absolute Power Down (Pin 9)
Note that only a 32 kbps encoding rate can be specified
when using short frame mode on the encoder input.
A logic 1 applied to this input forces the transcoder into a
power saving mode. This pin has a CMOS compatible input.
ENCODER INPUT — LONG FRAME
POWER SUPPLY
VDD
Positive Power Supply (Pin 16)
The most positive power supply pin, normally 5 V.
VSS
Negative Power Supply (Pin 8)
The most negative power supply pin, normally 0 V.
FUNCTIONAL DESCRIPTION
Figure 2 shows the clock, enable, and data signals for the
encoder input in long frame mode. In this mode, the data is
captured by the MC145532 on the falling edge of EDC.
The determination of the encoding rate is made based on
the number of falling EDC edges seen by the MC145532
while EIE is high. Four edges implies a 32 kbps encoding
rate, three edges implies a 24 kbps encoding rate, two edges
implies a 16 kbps rate, and from five to eight inclusive imply
a 64 kbps rate. The encoding rate may be changed on a
frame–by–frame basis. The encoded word is available at
EDO (via EOE and EDC) from 250 µs to 375 µs after it is requested.
ENCODING/DECODING RATES
ENCODER OUTPUT — SHORT FRAME
The MC145532 allows for the encoding and decoding of
data at one of four rates on a sample–by–sample basis.
Each data sample that is provided to the part is accompanied
by an indication of the rate at which it is to be encoded or
decoded. The width of the enable pulse determines the
encoding/decoding rate chosen for each sample.
The 64 kbps rate allows for PCM data to be passed directly
through the part. The 32 kbps rate is either the G.721–1988
or the T1.301–1987 standard, depending on the state of the
mode pin. The 24 kbps encoding rate is compliant with
CCITT G.723–1988 and G.726. The 16 kbps rate is a modified quantizer from the 32 kbps technique and is not a standard.
Figure 3 shows the timing of the encoder output in short
frame mode. The length of the LSB is always one half of an
EDC cycle.
The EDO will provide the correct number of bits for the encoding rate that was selected for this frame of data on the
encoder input pins. The data is loaded into the MC145532
during one frame, encoded on the next frame, and read during the third frame.
TIMING
Figures 1 through 8 show the timing of the input and output
pins. The MC145532 determines the mode of the timing signals, either short or long frame, for each enable, independent
of the mode of any previous enables. A transition from short
frame to long frame mode or vice versa will cause at least
one frame of data to be destroyed. Each of the four sets of
I/O pins determines its mode independent of the other sets.
Thus the encoder input could be operating with long frame
timing and the output could be operating with short frame timing. Note that the short frame timing on the input enables can
only be used with the 32 kbps transcoding rate. The number
of data clock falling edges enclosed by the input enable line
(EIE or DIE) determines both the short frame or long frame
mode and the transcoding rate. The mode of the input or output is determined each frame. In all modes, the data is captured by the MC145532 on the falling edge of either EDC or
DDC.
ENCODER INPUT — SHORT FRAME
Figure 1 shows the timing of the encoder data clock
(EDC), the encoder input enable (EIE), and the encoder data
input (EDI) pins in short frame operation.
The determination of short frame mode is made by the
MC145532 based on one falling EDC edge while EIE is high.
MOTOROLA
ENCODER OUTPUT — LONG FRAME
Figure 4 shows the timing of the encoder output in long
frame mode. The enable must be wider than two falling
edges of the EDC to be in long frame mode. If the enable falls
before the correct number of bits have been presented to the
output (EDO), the transcoder will complete the presentation
of the bits to the output with the LSB being one half of an
EDC period wide. If the enable falls after the one half EDC
period of the LSB, then the LSB will be extended up to the full
EDC clock period and the subsequent data will be a recirculation of the previous data, which repeats until the enable pin
falls. This is shown on the second enable for the 16 kbps encoding rate example in Figure 4.
DECODER INPUT — SHORT FRAME
Figure 5 shows the timing of the decoder data clock, the
decoder input enable, and the decoder data input pins in
short frame operation. Note that in this mode only a 32 kbps
decoding rate can be selected.
DECODER INPUT — LONG FRAME
Figure 6 shows the clock, enable, and data signals for the
decoder input in long frame mode.
The determination of the decoding rate is made based on
the number of falling DDC edges seen by the MC145532
while DIE is high. Four edges implies a 32 kbps decoding
rate, three edges implies a 24 kbps decoding rate, two edges
implies a 16 kbps rate, and from five to eight edges inclusive
imply a 64 kbps rate. The decoding rate may be changed on
a frame–by–frame basis.
MC145532
3
seen while DOE is high. The enable can be used to extend
the LSB to a full DDC period and/or cause the eight bits of
data to be recirculated to the output pin until the enable falls.
DECODER OUTPUT — SHORT FRAME
Figure 7 shows the timing of the decoder output in short
frame mode.
The DDO will provide the 8–bit PCM word for the decoding
rate that was selected for this frame of data on the decoder
input pins. The data is loaded into the MC145532 during one
frame, decoded on the next frame, and read during the third
frame.
STANDARDS INFORMATION
The following standards apply to the MC145532:
T1.301–1987 — 32 kbps ADPCM
T1.303–1988 — 24 kbps ADPCM
CCITT G.721–1988, G.723–1988, and G.726 — 32 kbps
and 24 kbps
DECODER OUTPUT — LONG FRAME
CCITT, ITU–T, TIA, and EIA documents may be obtained
by contacting Global Engineering Documents in the USA at
(800) 854–7179, or internationally at (303) 397–7956.
Figure 8 shows the timing of the decoder output in long
frame mode. Note that at least eight bits are presented to the
output, provided that at least two falling edges of DDC are
ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to VSS)
Rating
Symbol
Value
Unit
VDD
– 0.5 to + 7.0
V
V
– 0.5 to VDD + 0.5
V
DC Supply Voltage
Voltage, Any Pin to VSS
DC Current, Any Pin
Iin
± 10
mA
Operating Temperature
TA
– 40 to + 85
°C
Tstg
– 85 to + 150
°C
Storage Temperature
This device contains circuitry to protect
against damage due to high static voltages or
electric fields; however, it is advised that
normal precautions be taken to avoid application of any voltage higher than maximum
rated voltages to this high impedance circuit.
For proper operation it is recommended that
Vin and Vout be constrained to the range VSS ≤
(Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an
appropriate logic voltage level (e.g., either VSS
or VDD).
RECOMMENDED OPERATING CONDITIONS (TA = – 40 to + 85°C)
Parameter
Symbol
Min
Max
Unit
DC Supply Voltage
VDD
4.50
5.50
V
Power Dissipation
PD
—
0.28
W
Symbol
Min
Max
Unit
DIGITAL CHARACTERISTICS (VDD = 5.0 V, TA = – 40 to + 85°C)
Parameter
High Level Input Voltage
Mode, DOE, DDC, DDI, DIE, EIE, EDI, EDC, EOE
VIH
2.0
—
V
Low Level Input Voltage
Mode, DOE, DDC, DDI, DIE, EIE, EDI, EDC, EOE
VIL
—
0.8
V
High Level Input Voltage
RESET, APD, SPC
VIH
0.7 VDD
—
V
Low Level Input Voltage
RESET, APD, SPC
VIL
—
0.3 VDD
V
Input Current
Iin
—
± 1.0
µA
Input Capacitance
Cin
—
10
pF
High Level Output Voltage (IOH = – 2.0 mA)
DDO, EDO
VOH
4.6
—
V
Low Level Output Voltage (IOL = 2.0 MA)
DDO, EDO
VOL
—
0.4
V
Output Leakage Current (VDD = 5.5 V)
DDO, EDO
Ilkg
—
± 5.0
µA
Min
Max
Unit
SPC Frequency
19.990
23
MHz
SPC Duty Cycle
45
55
%
SWITCHING CHARACTERISTICS (VDD = 5.0 V, TA = – 40 to + 85°C)
Parameter
MC145532
4
MOTOROLA
ENCODER INPUT — SHORT FRAME (VDD = 5.0 V, TA = – 40 to + 85°C)
Symbol
Min
Max
Unit
Enable Low Setup Time
Parameter
tsu(EIE)L
15
—
ns
Enable Low Hold Time
th(EIE)H
30
—
ns
Enable Valid Time
tV(EIE)
15
—
ns
Enable Hold Time
th(EIE)
15
—
ns
Data Valid Time
tv(EDI)
15
—
ns
Data Hold Time
th(EDI)
15
—
ns
1
EDC
2
3
4
5
6
7
8
EIE
LSB
MSB
EDI
LSB
MSB
EDC
th(EIE)H
tsu(EIE)L
tv(EIE)
EIE
th(EIE)
EDI
MSB
tv(EDI)
th(EDI)
Figure 1. Encoder Input Timing — Short Frame
MOTOROLA
MC145532
5
ENCODER INPUT — LONG FRAME (VDD = 5.0 V, TA = – 40 to + 85°C)
Parameter
Symbol
Min
Max
Unit
th(EIE)L
30
—
ns
Enable Valid Time
tv(EIE)
15
—
ns
Data Valid Time
tv(EDI)
15
—
ns
Data Hold Time
th(EDI)
15
—
ns
Enable Low Hold Time
1
EDC
2
3
4
5
6
7
8
EIE 32 kbps
EIE 24 kbps
EIE 16 kbps
EIE 64 kbps
LSB
EDI
MSB
LSB
MSB
EDC
th(EIE)L
tv(EIE)
EIE
th(EDI)
tv(EDI)
EDI
MSB
Figure 2. Encoder Input Timing — Long Frame
MC145532
6
MOTOROLA
ENCODER OUTPUT — SHORT FRAME (VDD = 5.0 V, TA = – 40 to + 85°C)
Symbol
Min
Max
Unit
Enable Low Hold Time
Parameter
th(EOE)L
30
—
ns
Enable Valid Time
tv(EOE)
15
—
ns
Enable Hold Time
th(EOE)
15
—
ns
Data Valid Time
tv(EDO)
—
40
ns
Data Three–State Time (with 150 pF Load)
tz(EDO)
1
30
ns
1
EDC
EOE
2
3
4
5
6
7
*
8
@
LSB
EDO
LSB
MSB
MSB
* 32 kbps transcoding rate selected for this frame at EIE
@ 64 kbps transcoding rate selected for this frame at EIE
EDC
th(EOE)L
tv(EOE)
th(EOE)
EOE
tx(EDO)
tv(EDO)
EDO
MSB
LSB
Figure 3. Encoder Output Timing — Short Frame
MOTOROLA
MC145532
7
ENCODER OUTPUT — LONG FRAME (VDD = 5.0 V, TA = – 40 to + 85°C)
Symbol
Min
Max
Unit
Enable Low Hold Time
Parameter
th(EOE)L
30
—
ns
Enable Valid Time
tv(EOE)
15
—
ns
Enable to Data Time (Whichever Edge Occurs Last)
tEOE–EDO
—
40
ns
Clock to Data Time (Whichever Edge Occurs Last)
tEDC–EDO
—
45
ns
EDC
1
2
3
4
5
6
7
8
*
EOE
32 kbps
EDO
MSB
LSB
*
MSB
EOE
24 kbps
EDO
MSB
MSB
#
@
EOE
16 kbps
EDO
MSB
MSB
MSB
MSB
EOE
64 kbps
EDO
MSB
MSB
* EDO Driver is controlled by EOE
# EDO completes the presentation of data
@ Data recirculates
EDC
th(EOE)L
tv(EOE)
EOE
tEOE–EDO
tEDC–EDO
EDO
MSB
Figure 4. Encoder Output Timing — Long Frame
MC145532
8
MOTOROLA
DECODER INPUT — SHORT FRAME (VDD = 5.0 V, TA = – 40 to + 85°C)
Symbol
Min
Max
Unit
Enable Low Setup Time to Falling DDC
Parameter
tsu(DIE)L
15
—
ns
Enable Low Hold Time from Falling DDC
th(DIE)H
30
—
ns
Enable Valid Time to Falling DDC
tv(DIE)
15
—
ns
Enable Hold Time from Falling DDC
th(DIE)
15
—
ns
Data Valid Time Before Falling DDC
tv(DDI)
15
—
ns
Data Hold Time from Falling DDC
th(DDI)
15
—
ns
1
DDC
2
3
4
5
6
7
8
DIE
MSB
DDI
MSB
1
2
DDC
th(DIE)H
tv(DIE)
th(DIE)
tsu(DIE)L
DIE
tv(DDI)
th(DDI)
MSB
DDI
Figure 5. Decoder Input Timing — Short Frame
MOTOROLA
MC145532
9
DECODER INPUT — LONG FRAME (VDD = 5.0 V, TA = – 40 to + 85°C)
Symbol
Min
Max
Unit
Enable Hold Time from Falling DDC
Parameter
th(DIE)
30
—
ns
Enable Valid Time to Falling DDC
tv(DIE)
15
—
ns
Data Valid Time to Falling DDC
tv(DDI)
15
—
ns
Data Hold Time from Falling DDC
th(DDI)
15
—
ns
DDC
1
2
3
4
5
6
7
8
DIE
32 kbps
DDI
MSB
LSB
MSB
DIE
24 kbps
DDI
MSB
MSB
MSB
MSB
DIE
16 kbps
DDI
DIE
64 kbps
DDI
MSB
MSB
DDC
th(DIE)
tv(DIE)
DIE
th(DDI)
tv(DDI)
DDI
MSB
Figure 6. Decoder Input Timing — Long Frame
MC145532
10
MOTOROLA
DECODER OUTPUT — SHORT FRAME (VDD = 5.0 V, TA = – 40 to + 85°C)
Symbol
Min
Max
Unit
Enable Low Hold Time
Parameter
th(DOE)L
30
—
ns
Enable Valid Time
tv(DOE)
15
—
ns
Enable Hold Time
th(DOE)
15
—
ns
Rising Edge of DDC to Valid DDO
tv(DDO)
—
40
ns
Delay Time from 8th DDC Low to DDO Output Disabled
tz(DDO)
—
30
ns
DDC
1
2
3
4
5
6
7
8
DOE
LSB
DDO
MSB
LSB
MSB
DDC
th(DOE)L
tv(DOE)
th(DOE)
DOE
tz(DDO)
tv(DDO)
DDO
MSB
LSB
Figure 7. Decoder Output Timing — Short Frame
MOTOROLA
MC145532
11
DECODER OUTPUT — LONG FRAME (VDD = 5.0 V, TA = – 40 to + 85°C)
Symbol
Min
Max
Unit
Enable Low Hold Time
Parameter
th(DOE)L
30
—
ns
Enable Valid Time
tv(DOE)
15
—
ns
Rising Edge of DDE to Valid DDO (When DDC is High)
tDOE–DDO
—
40
ns
Rising Edge of DDC to Valid DDO (When DOE is High)
tDDC–DDO
—
45
ns
tz(DDO)
0
30
ns
Delay Time from 8th DDC Low or DOE Low to DDO Output Disabled
1
DDC
2
3
4
5
6
7
8
DOE
MSB
DDO
MSB
DDC
th(DOE)L
tv(DOE)
DOE
tDOE–DDO
tDDC–DDO
DDO
MSB
Figure 8. Decoder Output Timing — Long Frame
MC145532
12
MOTOROLA
MC145532
PCM Y BUS OUT
TS 1
ADPCM Z BUS IN
TS 3
MODE
DDO
DOE
DDC
VDD
EDO
EOE
EDC
DDI
DIE
RESET
VSS
EDI
1.544 MHz
MC145532
VDD
POWER–DOWN
PCM Y BUS IN
TS 3
+5V
EDO
EOE
EDC
TS 2
PCM X BUS IN
EDI
DDI
DIE
RESET
VSS
TS 4
ADPCM Z BUS OUT
TS 1
EIE
SPC
APD
MODE
DDO
DOE
DDC
PCM X BUS OUT
TS 3
+5V
TS 1
EIE
SPC
APD
20.48 MHz
1.544 MHz
TS 1
TS 2
TS 3
TS 4
PCM BUS OUT
PCM BUS IN
DDO y
1
2
3
5
6
7
8
DDO x
1
2
3
4
5
6
7
8
EDI y
1
2
3
4
5
6
7
8
1
2
3
EDI x
1
2
3
ADPCM BUS OUT EDO zy
1
2
3
EDO zx
ADPCM BUS IN
4
4
5
6
7
1
2
3
8
4
4
DDI zy
DDI zx
4
Figure 9. ADPCM Transcoder Application
MOTOROLA
MC145532
13
MC145503
ANALOG OUT
ANALOG IN
+5V
–5V
ADPCM IN
VAG
RxO
VDD
RDD
+Tx
RCE
Txl
RDC
–Tx
TDC
Mu/A
PDI
VSS
TDD
TDE
VLS
MC145532
+5V
TSm1 TSm
+5V
DDO
VDD
EDO
DOE
EOE
TSm
DDC
DDI
EDC
EDI
1.544 MHz
DIE
EIE
SPC
APD
MODE
RESET
VSS
ADPCM OUT
20.48 MHz
POWER–DOWN
1.544 MHz = RDC = DDC
= TDE = EDC
1
2
3
4
5
6
7
8
TSm1 = RCE = TDE
1
2
3
ADPCM OUT = EDO
1
2
3
DDO = RDD
1
2
3
ADPCM IN = DDI
1
2
3
EDI = TDD
4
5
6
5
6
7
8
TSm = EIE = EOE
= DIE = DOE
4
4
7
8
4
Figure 10. ADPCM Transcoder/Codec Application
MC145532
14
MOTOROLA
MC145557
–5V
VBB
GNDA
VFRO
VCC
ANALOG OUT
+5V
FSR
DR
BCLKR
MCLKR
+5V
1
DX
BCLKX
MCLKX
MC145532
VDD
MODE
2
Tx TIME SLOT
FSX
8 kHz
+5V
ADPCM OUT
EDO
EOE
EDC
EDI
DDI
DIE
RESET
VSS
POWER–DOWN
ANALOG IN
VFXI–
GSX
TSX
DDO
DOE
DDC
2.048 MHz
ADPCM IN
2.048 MHz
= MCLKR = BCLKR = DDC
= MCLKX = BCLKX = EDC
VFXI+
EIE
SPC
APD
3
20.48 MHz
4
5
6
7
8
8 kHz = DOE = DIE = FSR
= EOE = EIE = FSX
EDI = DX
1
2
3
ADPCM OUT = EDO
1
2
3
DDO = DR
1
2
3
ADPCM IN = DDI
1
2
3
4
5
6
7
8
4
5
6
7
8
4
4
Figure 11. ADPCM Transcoder/Codec Application (A–Law)
MOTOROLA
MC145532
15
PACKAGE DIMENSIONS
DW SUFFIX
SOG PACKAGE
CASE 751G–02
–A–
16
9
–B–
8X
P
0.010 (0.25)
1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN
EXCESS OF D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
M
B
M
8
16X
J
D
0.010 (0.25)
M
T A
B
S
S
F
DIM
A
B
C
D
F
G
J
K
M
P
R
R X 45 _
C
–T–
14X
G
M
SEATING
PLANE
K
MILLIMETERS
MIN
MAX
10.15
10.45
7.40
7.60
2.35
2.65
0.35
0.49
0.50
0.90
1.27 BSC
0.25
0.32
0.10
0.25
0_
7_
10.05
10.55
0.25
0.75
INCHES
MIN
MAX
0.400
0.411
0.292
0.299
0.093
0.104
0.014
0.019
0.020
0.035
0.050 BSC
0.010
0.012
0.004
0.009
0_
7_
0.395
0.415
0.010
0.029
L SUFFIX
CERAMIC PACKAGE
CASE 620–09
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.
-A16
9
1
8
-BL
C
-TK
SEATING
PLANE
F
M
N
E
J 16 PL
G
D 16 PL
0.25 (0.010)
0.25 (0.010)
M
T A
M
T B
S
DIM
A
B
C
D
E
F
G
J
K
L
M
N
INCHES
MIN
MAX
0.750 0.770
0.240 0.290
—
0.165
0.015 0.021
0.050 BSC
0.055 0.070
0.100 BSC
0.009
0.011
—
0.200
0.300 BSC
0°
15°
0.015 0.035
MILLIMETERS
MIN
MAX
19.05 19.55
7.36
6.10
4.19
—
0.53
0.39
1.27 BSC
1.77
1.40
2.54 BSC
0.27
0.23
5.08
—
7.62 BSC
15°
0°
0.39
0.88
S
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51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298
MC145532
16
◊
*MC145532/D*
MC145532/D
MOTOROLA