CY62128B MoBL 128K x 8 Static RAM Functional Description[1] Features • Temperature Ranges The CY62128B is a high-performance CMOS static RAM organized as 131,072 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE1), an active HIGH Chip Enable (CE2), an active LOW Output Enable (OE), and three-state drivers. This device has an automatic power-down feature that reduces power consumption by more than 75% when deselected. — Commercial: 0°C to 70°C — Industrial: –40°C to 85°C — Automotive: –40°C to 125°C • 4.5V – 5.5V operation • CMOS for optimum speed/power Writing to the device is accomplished by taking Chip Enable One (CE1) and Write Enable (WE) inputs LOW and Chip Enable Two (CE2) input HIGH. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A16). • Low active power (70 ns, LL version, Commercial, Industrial) — 82.5 mW (max.) (15 mA) • Low standby power (70 ns, LL version, Commercial, Industrial) Reading from the device is accomplished by taking Chip Enable One (CE1) and Output Enable (OE) LOW while forcing Write Enable (WE) and Chip Enable Two (CE2) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. — 110 µW (max.) (15 µA) • Automatic power-down when deselected • TTL-compatible inputs and outputs The eight input/output pins (I/O0 through I/O7) are placed in a high-impedance state when the device is deselected (CE1 HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or during a write operation (CE1 LOW, CE2 HIGH, and WE LOW). • Easy memory expansion with CE1, CE2, and OE options The CY62128B is available in a standard 450-mil-wide SOIC, 32-pin TSOP type I and STSOP packages. Logic Block Diagram I/O 0 INPUT BUFFER I/O 1 512x 256x 8 ARRAY I/O 2 SENSE AMPS ROW DECODER A0 A1 A2 A3 A4 A5 A6 A7 A8 I/O 3 I/O 4 I/O 5 COLUMN DECODER CE1 CE2 WE I/O 6 POWER DOWN A9 A 10 A 11 A 12 A 13 A 14 A 15 A 16 I/O 7 OE Note: 1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com. Cypress Semiconductor Corporation Document #: 38-05300 Rev. *C • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised February 14, 2005 CY62128B MoBL Product Portfolio Power Dissipation VCC Range (V) Standby, ISB2 (µA) Min. Typ.[2] Max. 4.5 5.0 5.5 55 7.5 20 2.5 Industrial 70 6 15 2.5 15 Automotive 70 6 25 2.5 25 Product CY62128BLL Operating, ICC (mA) Speed (ns) Industrial Typ.[2] Max. Typ.[2] Max. 15 Pin Configurations Top View SOIC NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GN G gnc g G ND A4 A5 A6 A7 A12 A14 A16 NC VCC A15 CE2 WE A13 A8 A9 A11 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Reverse TSOP I Top View (not to scale) 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 A3 A11 A2 A9 A1 A8 A13 A0 I/O0 WE I/O1 CE2 A15 I/O2 GND VCC NC I/O3 A16 I/O4 A14 I/O5 A12 I/O6 A7 I/O7 A6 CE1 A5 A10 A4 OE 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 STSOP Top View (not to scale) VCC A15 CE2 WE A13 A8 A9 A11 OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3 A11 A9 A8 A13 WE CE2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 TSOP I Top View (not to scale) 32 31 30 29 28 27 26 25 25 24 23 22 21 20 19 18 17 OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3 Pin Definitions Input A0-A16. Address Inputs Input/Output I/O0-I/O7. Data lines. Used as input or output lines depending on operation Input/Control WE. Write Enable, Active LOW. When selected LOW, a WRITE is conducted. When selected HIGH, a READ is conducted. Input/Control CE1. Chip Enable 1, Active LOW. Input/Control CE2. Chip Enable 2, Active HIGH. Input/Control OE. Output Enable, Active LOW. Controls the direction of the I/O pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input data pins Ground GND. Ground for the device Power Supply VCC. Power supply for the device Notes: 2. Typical values are included for reference only and are not tested or guaranteed. Typical values are an average of the distribution across normal production variations as measured at VCC = 5.0V, TA = 25°C, and tAA = 70 ns. Document #: 38-05300 Rev. *C Page 2 of 11 CY62128B MoBL Maximum Ratings Current into Outputs (LOW)......................................... 20 mA (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –65°C to +150°C Static Discharge Voltage........................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current..................................................... > 200 mA Ambient Temperature with Power Applied............................................. –55°C to +125°C Operating Range Supply Voltage on VCC to Relative GND[3] .... –0.5V to +7.0V Range DC Voltage Applied to Outputs in High-Z State[3] ....................................–0.5V to VCC + 0.5V DC Input Voltage[3] .................................–0.5V to VCC + 0.5V Ambient Temperature (TA)[4] VCC 0°C to +70°C 5V ± 10% Commercial Industrial –40°C to +85°C 5V ± 10% Automotive –40°C to +125°C 5V ± 10% Electrical Characteristics Over the Operating Range CY62128B-55 Parameter Description Test Conditions VOH Output HIGH Voltage VCC = Min., IOH = –1.0 mA VOL Output LOW Voltage VCC = Min., IOL = 2.1 mA VIH Input HIGH Voltage VIL Input LOW Voltage[3] IIX Input Load Current GND ≤ VI ≤ VCC Min. CY62128B-70 Typ.[2] Max. 2.4 Output Leakage Current GND ≤ VI ≤ VCC, Output Disabled IOS Output Short Circuit Current[5] VCC = Max., VOUT = GND ICC VCC Operating Supply Current VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC ISB1 Automatic CE Power-down Current —TTL Inputs Max. VCC, CE1 ≥ VIH or CE2 < VIL, VIN ≥ VIH or VIN ≤ VIL, f = fMAX Automatic CE Power-down Current —CMOS Inputs Industrial Max. VCC, CE1 ≥ VCC – 0.3V, Commercial or CE2 ≤ 0.3V, Automotive VIN ≥ VCC – 0.3V, or VIN ≤ 0.3V, f = 0 ISB2 Typ.[2] Max. 2.4 Unit V 0.4 0.4 V V 2.2 VCC + 0.3 2.2 VCC + 0.3 –0.3 0.8 –0.3 0.8 V –1 +1 –1 +1 µA –10 +10 µA –1 +1 µA –10 +10 µA –300 mA mA Automotive IOZ Min. –1 +1 Automotive –300 Industrial, Commercial 7.5 20 6 15 6 25 mA 0.1 2 0.1 1 mA 0.1 2 mA 2.5 15 µA 2.5 25 µA Automotive Industrial Commercial Automotive 2.5 15 Thermal Resistance[6] Parameter ΘJA ΘJC Description Test Conditions Thermal Resistance Test conditions follow standard test (Junction to Ambient) methods and procedures for Thermal Resistance measuring thermal impedance, per EIA / JESD51. (Junction to Case) 32 SOIC 32 TSOP 32 STSOP 32 RTSOP Unit 66.17 97.44 105.14 97.44 °C/W 30.87 26.05 14.09 26.05 °C/W Note: 3. VIL (min.) = –2.0V for pulse durations of less than 20 ns. 4. TA is the “Instant On” case temperature. 5. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds. 6. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-05300 Rev. *C Page 3 of 11 CY62128B MoBL Capacitance[6] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions Max. TA = 25°C, f = 1 MHz, VCC = 5.0V Unit 9 pF 9 pF \ AC Test Loads and Waveforms R1 1800Ω 5V R1 1800Ω 5V OUTPUT VCC OUTPUT 100 pF INCLUDING JIG AND SCOPE (a) R2 990Ω 5 pF INCLUDING JIG AND SCOPE (b) R2 990 Ω GND ALL INPUT PULSES 90% 90% 10% 10% Fall TIme: 1 V/ns Rise TIme: 1 V/ns Equivalent to: THÉVENIN EQUIVALENT 639 Ω 1.77V OUTPUT Data Retention Characteristics (Over the Operating Range for “LL” version only) Parameter Description Conditions Min. Typ. Max. 2.0 Unit VDR VCC for Data Retention ICCDR Data Retention Current tCDR Chip Deselect to Data Retention Time 0 ns tR Operation Recovery Time 70 ns VCC = VDR = 2.0V, CE1 ≥ VCC – 0.3V, or CE2 ≤ 0.3V, VIN ≥ VCC – 0.3V or, VIN ≤ 0.3V V 1.5 15 µA Data Retention Waveform VCC VCC, min. tCDR DATA RETENTION MODE VDR > 2 V VCC, min. tR CE1 or CE2 Document #: 38-05300 Rev. *C Page 4 of 11 CY62128B MoBL Switching Characteristics[7] Over the Operating Range 62128B-55 Parameter Description Min. Max. 62128B-70 Min. Max. Unit READ CYCLE tRC Read Cycle Time 55 70 tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE1 LOW to Data Valid, CE2 HIGH to Data Valid 55 70 ns tDOE OE LOW to Data Valid 20 35 ns tLZOE OE LOW to Low Z tHZOE OE HIGH to High Z[8, 9] 25 ns tLZCE CE1 LOW to Low Z, CE2 HIGH to Low Z[9] 55 5 70 5 0 5 tHZCE CE1 HIGH to High Z, CE2 LOW to High tPU CE1 LOW to Power-up, CE2 HIGH to Power-up tPD CE1 HIGH to Power-down, CE2 LOW to Power-down ns 5 20 0 ns 25 ns 70 ns 0 55 ns ns 0 20 Z[8, 9] ns ns WRITE CYCLE[10] tWC Write Cycle Time 55 70 ns tSCE CE1 LOW to Write End, CE2 HIGH to Write End 45 60 ns tAW Address Set-up to Write End 45 60 ns tHA Address Hold from Write End 0 0 ns tSA Address Set-up to Write Start 0 0 ns tPWE WE Pulse Width 45 50 ns tSD Data Set-up to Write End 25 30 ns tHD Data Hold from Write End 0 0 ns 5 5 ns tLZWE tHZWE WE HIGH to Low Z[9] WE LOW to High Z[8, 9] 20 25 ns Switching Waveforms Read Cycle No.1[12, 13] tRC ADDRESS tOHA DATA OUT tAA PREVIOUS DATA VALID DATA VALID Notes: 7. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 100-pF load capacitance. 8. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage. 9. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 10. The internal write time of the memory is defined by the overlap of CE1 LOW, CE2 HIGH, and WE LOW. CE1 and WE must be LOW and CE2 HIGH to initiate a write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 11. No input may exceed VCC + 0.5V. 12. Device is continuously selected. OE, CE1 = VIL, CE2 = VIH. 13. WE is HIGH for read cycle. Document #: 38-05300 Rev. *C Page 5 of 11 CY62128B MoBL Switching Waveforms (continued) Read Cycle No. 2 (OE Controlled)[13, 14] ADDRESS tRC CE1 CE2 tACE OE tHZOE tDOE DATA OUT tHZCE tLZOE HIGH IMPEDANCE DATA VALID tLZCE VCC SUPPLY CURRENT HIGH IMPEDANCE tPD tPU 50% 50% ICC ISB Write Cycle No. 1 (CE1 or CE2 Controlled)[15, 16] tWC ADDRESS tSCE CE1 CE2 tSA tSCE tAW tHA tPWE WE tSD DATA I/O tHD DATA VALID Notes: 14. Address valid prior to or coincident with CE1 transition LOW and CE2 transition HIGH. 15. Data I/O is high impedance if OE = VIH. 16. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE going HIGH, the output remains in a high-impedance state. Document #: 38-05300 Rev. *C Page 6 of 11 CY62128B MoBL Switching Waveforms (continued) Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[15, 16] tWC ADDRESS tSCE CE1 CE2 tSCE tAW tHA tSA tPWE WE OE tSD DATA I/O tHD DATAIN VALID NOTE 17 tHZOE Write Cycle No.3 (WE Controlled, OE LOW)[15, 16] tWC ADDRESS tSCE CE1 CE2 tSCE tAW tSA tHA tPWE WE tSD DATAI/O NOTE 17 tHD DATA VALID tHZWE tLZWE Note: 17. During this period the I/Os are in the output state and input signals should not be applied. Document #: 38-05300 Rev. *C Page 7 of 11 CY62128B MoBL Truth Table CE1 CE2 OE WE I/O0–I/O7 Mode Power H X X X High Z Power-down Standby (ISB) X L X X High Z Power-down Standby (ISB) L H L H Data Out Read Active (ICC) L H X L Data In Write Active (ICC) L H H H High Z Selected, Outputs Disabled Active (ICC) Ordering Information Speed (ns) 55 70 Ordering Code Package Name Package Type Operating Range CY62128BLL-55SI S34 32-Lead 450-Mil SOIC CY62128BLL-55SXI S34 32-Lead 450-Mil SOIC (Pb-free) CY62128BLL-55SC S34 32-Lead 450-Mil SOIC Commercial CY62128BLL-55SXC S34 32-Lead 450-Mil SOIC (Pb-free) Commercial CY62128BLL-55ZI Z32 32-Lead TSOP Type I CY62128BLL-55ZXI Z32 CY62128BLL-55ZAI ZA32 Industrial Industrial Industrial 32-Lead TSOP Type I (Pb-free) Industrial 32-Lead STSOP Type I Industrial CY62128BLL-55ZAXI ZA32 32-Lead STSOP Type I (Pb-free) Industrial CY62128BLL-55ZRI ZR32 32-Lead Reverse TSOP Type I Industrial CY62128BLL-70SI S34 32-Lead 450-Mil SOIC I Industrial CY62128BLL-70SXI S34 32-Lead 450-Mil SOIC I (Pb-free) Industrial CY62128BLL-70SC S34 32-Lead 450-Mil SOIC I Commercial CY62128BLL-70SXC S34 32-Lead 450-Mil SOIC I (Pb-free) Commercial CY62128BLL-70SE S34 32-Lead 450-Mil SOIC I Automotive CY62128BLL-70SXE S34 32-Lead 450-Mil SOIC I (Pb-free) Automotive CY62128BLL-70ZI Z32 32-Lead TSOP Type I Industrial CY62128BLL-70ZXI Z32 32-Lead TSOP Type I (Pb-free) Industrial CY62128BLL-70ZC Z32 32-Lead TSOP Type I Commercial CY62128BLL-70ZXC Z32 32-Lead TSOP Type I (Pb-free) Commercial CY62128BLL-70ZE Z32 32-Lead TSOP Type I Automotive CY62128BLL-70ZXE Z32 32-Lead TSOP Type I (Pb-free) Automotive CY62128BLL-70ZAI ZA32 32-Lead STSOP Type I Industrial CY62128BLL-70ZAXI ZA32 32-Lead STSOP Type I (Pb-free) Industrial CY62128BLL-70ZAE ZA32 32-Lead STSOP Type I Automotive CY62128BLL-70ZAXE ZA32 32-Lead STSOP Type I (Pb-free) Automotive CY62128BLL-70ZRXE ZR32 32-Lead Reverse TSOP Type I (Pb-free) Automotive Document #: 38-05300 Rev. *C Page 8 of 11 CY62128B MoBL Package Diagrams 32-Lead (450 MIL) Molded SOIC S34 16 1 0.546[13.868] 0.566[14.376] 0.440[11.176] 0.450[11.430] 17 32 0.793[20.142] 0.817[20.751] 0.006[0.152] 0.012[0.304] 0.101[2.565] 0.111[2.819] 0.118[2.997] MAX. 0.004[0.102] 0.050[1.270] BSC. 0.004[0.102] MIN. 0.014[0.355] 0.020[0.508] 0.023[0.584] 0.039[0.990] SEATING PLANE 0.047[1.193] 0.063[1.600] 51-85081-*B 32-Lead Thin Small Outline Package Type I (8x20 mm) Z32 51-85056-*D Document #: 38-05300 Rev. *C Page 9 of 11 CY62128B MoBL Package Diagrams (continued) 32-Lead Shrunk Thin Small Outline Package (8x13.4 mm) ZA32 51-85094-*D 32-Lead Reverse Thin Small Outline Package ZR32 51-85089-*C MoBL is a registered trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-05300 Rev. *C Page 10 of 11 © Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY62128B MoBL Document History Page Document Title: CY62128B MoBL 128K x 8 Static RAM Document Number: 38-05300 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 116566 06/20/02 DSG *A 126601 06/09/03 JUI Changed CE to CE1 and added CE2 ≤ 0.3V in Data Retention Characteristics table Removed these part numbers from Ordering Information table: CY62128BLL-55ZC, CY62128BLL-55ZAC, CY62128BLL-55ZRC, CY62128BLL-70ZAC, CY62128BLL-70ZRI, CY62128BLL-70ZRC *B 239134 See ECN AJU Added Thermal Resistance table Added Automotive product information *C 321335 See ECN AJU Added Pb-free package information Document #: 38-05300 Rev. *C Changed from Spec number: 38-00524 to 38-05300 Page 11 of 11