Hitachi HD6433801H Single-chip microcomputer Datasheet

Hitachi Single-Chip Microcomputer
H8/3802 Series
H8/3802
H8/3801
H8/3800
HD6473802, HD6433802
HD6433801
HD6433800
Hardware Manual
ADE-602-203A
Rev. 2.0
1/9/01
Hitachi Ltd.
Cautions
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List of Items Revised or Added for This Version
Section
Page
Item
Description
1.1 Overview
3
Table 1.1 Features
Description of time
specification amended
2.8.1 Memory Map
46
Figure 2.16(2) H8/3801 Memory
Map
Figure amended
47
Figure 2.16(3) H8/3800 Memory
Map
Figure amended
3.3.1 Overview
60
Table 3.2 Interrupt Sources and
Their Priorities
Amended
3.3.2 Interrupt Control
Registers
61
Table 3.3 Interrupt Control
Registers
Initial values amended
1. IRQ edge select register (IEGR) Bits 4 to 2 amended
62
2. Interrupt enable register 1
(IENR1)
Bits 6, 4, and 3 amended
63 to 65
3. Interrupt enable register 2
(IENR2)
Bits 5, 4, and 1 amended
65
4. Interrupt request register 1
(IRR1)
Bits 6, 4, and 3 amended
67, 68
5. Interrupt request register 2
(IRR2)
Bits 5, 4, and 1 amended
3.3.5 Interrupt
Operations
74
Figure 3.3 Flow up to Interrupt
Acceptance
Figure amended
3.4.2 Notes on
Rewriting Port Mode
Registers
79
Table 3.5 Conditions under which IRREC2 flag condition
Interrupt Request Flag is Set to 1 amended
3.4.3 Interrupt
Request Flag Clearing
Methods
80
3.4.3 Interrupt Request Flag
Clearing Method
Description added
4.5.1 Definition of Oscillation
Setting Standby Time
Description added
4.5 Note on Oscillators 90 to 92
4.5.2 Notes on Use of Crystal
Oscillator Element(Excluding
Ceramic Oscillator Element)
5.1 Overview
95
5.3.3 Oscillator Setting 103
Time after Standby
Mode is Cleared
Table 5.2 Internal State in Each
Operating Mode
Note 7 amended
Table 5.4 Clock Frequency and
Setting Time
Changed
Section
Page
Item
Description
5.5.2 Clearing
Subsleep Mode
108
• Clearing by interrupt
Description amended
5.6 Subactive Mode
109
5.6.1 Transition to Subactive Mode Description amended
6.3.1 Writing and
Verifying
122
Figure 6.4 High-Speed,HighWrite time tOPW amended
Reliability Programming Flow Chart
8.1 Overview
131, 132
Table 8.1 Port Functions
Other function of port 3
and description of port 9
amended
8.2.2 Register
Configuration and
Description
133
Table 8.2 Port 3 Registers
Amended and register
added
134
1. Port data register 3 (PDR3)
Bit 0 and description
amended
2. Port control register 3 (PCR3)
Bit 0 and description
amended
3. Port pull-up control register 3
(PUCR3)
Bit 0 and description
amended
135, 136
4. Port mode register 3 (PMR3)
Bits 5 to 3 and 0, and
description amended
136
5. Port mode register 2 (PMR2)
Added
139
Table 8.5 Port 4 Register
Initial value amended
140, 141
3. Port mode register 2 (PMR2)
Bits 2 and 1, and
description amended
8.3.3 Pin Functions
141
Table 8.6 Port 4 Pin Functions
Description amended
8.7.2 Register
Configuration and
Description
155
Table 8.17 Port 8 Registers
Initial value amended
156
1. Port data register 8 (PDR8)
Bits 7 to 1 amended
2. Port control register 8 (PCR8)
Bits 7 to 1 amended
8.8.1 Overview
Description amended
Table 8.20 Port 9 Registers
Initial value amended
159
2. Port mode register 9 (PMR9)
Bit 2 amended, description
added, and Note changed
165
Table 8.26 Port B Register
Initial values added
8.3.2 Register
Configuration and
Description
8.8 Port 9
158
8.8.2 Register
Configuration and
Description
8.10.2 Register
Configuration and
Description
Section
Page
Item
Description
8.11.2 Register
Configuration and
Descriptions
168, 169
Serial Port Control Register
(SPCR)
Bits 4, 1, and 0, and
description amended
8.12 Application Note
170
8.12.1 How to Handle an Unused
Pin
Description added
9.1 Overview
171
Table 9.1 Timer Functions
Internal clock of
asynchronous event
counter amended
9.2.1 Overview
174
Table 9.2 Timer A Registers
Initial value amended
9.2.2 Register
Descriptions
174
1. Timer mode register A (TMA)
Bits 7 to 5 amended
9.2.5 Application Note
178
9.2.5 Application Note
Description added
9.3.4 Operation
192
1. Timer F operation
Description amended
a. Operation in 16-bit timer mode
9.3.5 Application Note
196, 197
Description added
3. Clear timer FH, timer FL
interrupt request flags (IRRTFH,
IRRTFL), timer overflow flags H, L
(OVFH, OVFL) and compare match
flags H, L (CMFH, CMFL)
4. Timer counter (TCF) read/write
9.4.2 Register
Configurations
202
5. Input pin edge selection register Bit name amended
(AEGSR)
204
6. Event counter control register
(ECCR)
Bit name, R/W form, and
description amended
205
7. Event counter control/status
register (ECCSR)
Bit name, R/W form, and
description amended
10.1.4 Register
Configuration
220
Table 10.2 Registers
Initial value of serial port
control register amended
10.2 Register
Descriptions
227
10.2.6 Serial control register 3
(SCR3)
Description of bit 5
amended
240
10.2.10 Serial Port Control
Register (SPCR)
Bits 4, 1, and 0, and
description amended
286, 287
12.2.2 A/D Mode Register (AMR)
Bit 6 amended
12.6 Application Notes 294
12.6 Application Notes
4th note added
13.1.4 Register
Configuration
Table 13.2 LCD Controller/Driver
Registers
Initial values amended
12.2 Register
Descriptions
297
Section
Page
Item
Description
13.2 Register
Descriptions
298
13.2.1 LCD Port Control Register
(LPCR)
Bit 4 amended
302
13.2.3 LCD Control Register 2
(LCR2)
Bits 4 to 0 amended
14.1 H8/3802 Series
Absolute Maximum
Ratings
313
Table 14.1 Absolute Maximum
Ratings
Input voltage amended
14.2.2 DC
Characteristics
318 to
321
Table 14.2 DC Characteristics
Added and amended
14.2.3 AC
Characteristics
323
Table 14.3 Control Signal Timing
Amended
14.2.4 A/D Converter
Characteristics
325
Table 14.5 A/D Converter
Characteristics
Test conditions amended
14.3 Operation Timing 329
Figure 14.5 SCI3 Synchronous
Mode Input/Output Timing
Reference figure in note
amended
14.6 Usage Note
331
14.6 Usage Note
Added
B.2 Functions
356
SPCR
Initial values and R/W
forms amended
357
AEGSR
R/W form of bit 0 amended
358
ECCR
R/W form of bit 0 amended
359
ECCSR
R/W form of bit 5 amended
366
TMA
Initial values and R/W
forms of bits 7 to 5
amended
368
TCRF
Description of bits 6 to 4
amended
371
LPCR
Initial value and R/W form
of bit 4 amended
372
LCR
Description of bits 3 to 0
amended
373
LCR2
Initial values and R/W
forms of bits 4 to 0
amended
374
AMR
Initial value and R/W form
of bit 6 amended
375
ADRRH
R/W forms amended
376
PMR2
Initial values and R/W
forms amended
377
PMR3
R/W forms amended
Section
Page
Item
Description
B.2 Functions
380
PDR3
Initial value amended and
description added
PDR4
Descriptions added
PDR5
Description added
PDR6
Description added
PDR7
Description added
PDR8
Initial values amended and
description added
PDR9
Description added
PDRA
Description added
PDRB
Description added
PUCR3
Initial value and R/W form
amended
383
PCR3
Initial value and R/W form
amended
385
PCR8
Initial values and R/W
forms amended
PMR9
Initial value and R/W form
of bit 2 amended
PCRA
Initial values of bits 7 to 4
amended
PMRB
Initial values of bits 7 to 4
and 2 to 0 amended
389
IEGR
Initial values and R/W
forms of bits 7, 4 to 2 and
description of bit 1
amended
390
IENR1
Initial values and R/W
forms of bits 6, 4, and 3
amended
391
IENR2
Initial values and R/W
forms of bits 5, 4, and 1
amended
392
IRR1
Initial values and R/W
forms of bits 6, 4, and 3
amended
393
IRR2
Initial values and R/W
forms of bits 5, 4, and 1
amended
381
382
386
Section
Page
Item
Description
Figure C.1(b) Port 3 Block
Diagram (Pin P35)
Added
399
Figure C.1(c) Port 3 Block
Diagram (Pins P34 and P33)
Pin P3 5 deleted
C.7 Block Diagrams of 409
Port 9
Figure C.7(a) Port 9 Block
Diagram (Pins P91 and P90)
Figure amended
C.1 Block Diagrams of 398
Port 3
Preface
The H8/300L Series of single-chip microcomputers has the high-speed H8/300L CPU at its core,
with many necessary peripheral functions on-chip. The H8/300L CPU instruction set is
compatible with the H8/300 CPU.
The H8/3802 Series has a system-on-a-chip architecture that includes such peripheral functions as
an LCD controller/driver, three timers, a two-channel 10-bit PWM, a serial communication
interface, and an A/D converter. This allows H8/3802 Series devices to be used as embedded
microcomputers in systems requiring LCD display.
This manual describes the hardware of the H8/3802 Series. For details on the H8/3802 Series
instruction set, refer to the H8/300L Series Programming Manual.
Contents
Section 1 Overview ..............................................................................................................
1.1
1.2
1.3
Overview............................................................................................................................
Internal Block Diagram......................................................................................................
Pin Arrangement and Functions.........................................................................................
1.3.1 Pin Arrangement ...................................................................................................
1.3.2 Pin Functions ........................................................................................................
1
1
5
6
6
8
Section 2 CPU........................................................................................................................ 11
2.1
2.2
2.3
2.4
2.5
2.6
2.7
Overview............................................................................................................................
2.1.1 Features .................................................................................................................
2.1.2 Address Space.......................................................................................................
2.1.3 Register Configuration..........................................................................................
Register Descriptions .........................................................................................................
2.2.1 General Registers..................................................................................................
2.2.2 Control Registers ..................................................................................................
2.2.3 Initial Register Values ..........................................................................................
Data Formats......................................................................................................................
2.3.1 Data Formats in General Registers .......................................................................
2.3.2 Memory Data Formats..........................................................................................
Addressing Modes..............................................................................................................
2.4.1 Addressing Modes ................................................................................................
2.4.2 Effective Address Calculation ..............................................................................
Instruction Set ....................................................................................................................
2.5.1 Data Transfer Instructions ....................................................................................
2.5.2 Arithmetic Operations ..........................................................................................
2.5.3 Logic Operations ..................................................................................................
2.5.4 Shift Operations ....................................................................................................
2.5.5 Bit Manipulations .................................................................................................
2.5.6 Branching Instructions..........................................................................................
2.5.7 System Control Instructions..................................................................................
2.5.8 Block Data Transfer Instruction............................................................................
Basic Operational Timing ..................................................................................................
2.6.1 Access to On-Chip Memory (RAM, ROM) .........................................................
2.6.2 Access to On-Chip Peripheral Modules................................................................
CPU States .........................................................................................................................
2.7.1 Overview...............................................................................................................
2.7.2 Program Execution State ......................................................................................
2.7.3 Program Halt State................................................................................................
2.7.4 Exception-Handling State .....................................................................................
11
11
12
12
13
13
13
14
15
16
17
18
18
20
24
26
28
29
29
31
35
37
38
40
40
41
43
43
44
44
44
i
2.8
2.9
Memory Map......................................................................................................................
2.8.1 Memory Map ........................................................................................................
Application Notes ..............................................................................................................
2.9.1 Notes on Data Access ...........................................................................................
2.9.2 Notes on Bit Manipulation....................................................................................
2.9.3 Notes on Use of the EEPMOV Instruction ...........................................................
45
45
48
48
50
56
Section 3 Exception Handling .......................................................................................... 57
3.1
3.2
3.3
3.4
Overview............................................................................................................................
Reset...................................................................................................................................
3.2.1 Overview...............................................................................................................
3.2.2 Reset Sequence .....................................................................................................
3.2.3 Interrupt Immediately after Reset .........................................................................
Interrupts ............................................................................................................................
3.3.1 Overview...............................................................................................................
3.3.2 Interrupt Control Registers ...................................................................................
3.3.3 External Interrupts ................................................................................................
3.3.4 Internal Interrupts..................................................................................................
3.3.5 Interrupt Operations..............................................................................................
3.3.6 Interrupt Response Time.......................................................................................
Application Notes ..............................................................................................................
3.4.1 Notes on Stack Area Use ......................................................................................
3.4.2 Notes on Rewriting Port Mode Registers .............................................................
3.4.3 Interrupt Request Flag Clearing Method ..............................................................
57
57
57
57
59
59
59
61
70
71
72
77
78
78
79
80
Section 4 Clock Pulse Generators.................................................................................... 83
4.1
4.2
4.3
4.4
4.5
Overview............................................................................................................................
4.1.1 Block Diagram......................................................................................................
4.1.2 System Clock and Subclock..................................................................................
System Clock Generator ....................................................................................................
Subclock Generator............................................................................................................
Prescalers ...........................................................................................................................
Note on Oscillators ............................................................................................................
4.5.1 Definition of Oscillation Settling Standby Time ..................................................
4.5.2 Notes on Use of Crystal Oscillator Element
(Excluding Ceramic Oscillator Element)..............................................................
83
83
83
84
87
89
90
90
92
Section 5 Power-Down Modes ......................................................................................... 93
5.1
5.2
ii
Overview............................................................................................................................
5.1.1 System Control Registers......................................................................................
Sleep Mode ........................................................................................................................
5.2.1 Transition to Sleep Mode......................................................................................
5.2.2 Clearing Sleep Mode ............................................................................................
93
96
101
101
101
5.3
5.4
5.5
5.6
5.7
5.8
5.9
5.2.3 Clock Frequency in Sleep (Medium-Speed) Mode ..............................................
Standby Mode ....................................................................................................................
5.3.1 Transition to Standby Mode..................................................................................
5.3.2 Clearing Standby Mode ........................................................................................
5.3.3 Oscillator Settling Time after Standby Mode is Cleared......................................
5.3.4 Standby Mode Transition and Pin States..............................................................
5.3.5 Notes on External Input Signal Changes before/after Standby Mode..................
Watch Mode .......................................................................................................................
5.4.1 Transition to Watch Mode ....................................................................................
5.4.2 Clearing Watch Mode ...........................................................................................
5.4.3 Oscillator Settling Time after Watch Mode is Cleared ........................................
5.4.4 Notes on External Input Signal Changes before/after Watch Mode.....................
Subsleep Mode ...................................................................................................................
5.5.1 Transition to Subsleep Mode ................................................................................
5.5.2 Clearing Subsleep Mode .......................................................................................
Subactive Mode..................................................................................................................
5.6.1 Transition to Subactive Mode...............................................................................
5.6.2 Clearing Subactive Mode......................................................................................
5.6.3 Operating Frequency in Subactive Mode .............................................................
Active (Medium-Speed) Mode ..........................................................................................
5.7.1 Transition to Active (Medium-Speed) Mode........................................................
5.7.2 Clearing Active (Medium-Speed) Mode ..............................................................
5.7.3 Operating Frequency in Active (Medium-Speed) Mode ......................................
Direct Transfer ...................................................................................................................
5.8.1 Overview of Direct Transfer.................................................................................
5.8.2 Direct Transition Times........................................................................................
5.8.3 Notes on External Input Signal Changes before/after Direct Transition..............
Module Standby Mode.......................................................................................................
5.9.1 Setting Module Standby Mode .............................................................................
5.9.2 Clearing Module Standby Mode...........................................................................
102
102
102
102
103
104
105
107
107
107
107
107
108
108
108
109
109
109
109
110
110
110
110
111
111
112
114
115
115
115
Section 6 ROM ...................................................................................................................... 117
6.1
6.2
6.3
6.4
Overview............................................................................................................................
6.1.1 Block Diagram......................................................................................................
H8/3802 PROM Mode .......................................................................................................
6.2.1 Setting to PROM Mode ........................................................................................
6.2.2 Socket Adapter Pin Arrangement and Memory Map ...........................................
H8/3802 Programming.......................................................................................................
6.3.1 Writing and Verifying...........................................................................................
6.3.2 Programming Precautions.....................................................................................
Reliability of Programmed Data ........................................................................................
117
117
118
118
118
121
121
126
127
iii
Section 7 RAM ...................................................................................................................... 129
7.1
Overview............................................................................................................................ 129
7.1.1 Block Diagram...................................................................................................... 129
Section 8 I/O Ports ............................................................................................................... 131
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
iv
Overview............................................................................................................................
Port 3..................................................................................................................................
8.2.1 Overview...............................................................................................................
8.2.2 Register Configuration and Description ...............................................................
8.2.3 Pin Functions ........................................................................................................
8.2.4 Pin States ..............................................................................................................
8.2.5 MOS Input Pull-Up...............................................................................................
Port 4..................................................................................................................................
8.3.1 Overview...............................................................................................................
8.3.2 Register Configuration and Description ...............................................................
8.3.3 Pin Functions ........................................................................................................
8.3.4 Pin States ..............................................................................................................
Port 5..................................................................................................................................
8.4.1 Overview...............................................................................................................
8.4.2 Register Configuration and Description ...............................................................
8.4.3 Pin Functions ........................................................................................................
8.4.4 Pin States ..............................................................................................................
8.4.5 MOS Input Pull-Up...............................................................................................
Port 6..................................................................................................................................
8.5.1 Overview...............................................................................................................
8.5.2 Register Configuration and Description ...............................................................
8.5.3 Pin Functions ........................................................................................................
8.5.4 Pin States ..............................................................................................................
8.5.5 MOS Input Pull-Up...............................................................................................
Port 7..................................................................................................................................
8.6.1 Overview...............................................................................................................
8.6.2 Register Configuration and Description ...............................................................
8.6.3 Pin Functions ........................................................................................................
8.6.4 Pin States ..............................................................................................................
Port 8..................................................................................................................................
8.7.1 Overview...............................................................................................................
8.7.2 Register Configuration and Description ...............................................................
8.7.3 Pin Functions ........................................................................................................
8.7.4 Pin States ..............................................................................................................
Port 9..................................................................................................................................
8.8.1 Overview...............................................................................................................
8.8.2 Register Configuration and Description ...............................................................
8.8.3 Pin Functions ........................................................................................................
131
133
133
133
137
138
138
139
139
139
141
142
143
143
143
146
147
147
148
148
148
150
151
151
152
152
152
154
154
155
155
155
157
157
158
158
158
160
8.8.4 Pin States ..............................................................................................................
8.9 Port A .................................................................................................................................
8.9.1 Overview...............................................................................................................
8.9.2 Register Configuration and Description ...............................................................
8.9.3 Pin Functions ........................................................................................................
8.9.4 Pin States ..............................................................................................................
8.10 Port B .................................................................................................................................
8.10.1 Overview...............................................................................................................
8.10.2 Register Configuration and Description ...............................................................
8.10.3 Pin Functions ........................................................................................................
8.11 Input/Output Data Inversion Function ...............................................................................
8.11.1 Overview...............................................................................................................
8.11.2 Register Configuration and Descriptions..............................................................
8.11.3 Note on Modification of Serial Port Control Register..........................................
8.12 Application Note................................................................................................................
8.12.1 How to Handle an Unused Pin..............................................................................
160
161
161
161
163
164
165
165
165
167
168
168
168
169
170
170
Section 9 Timers ................................................................................................................... 171
9.1
9.2
9.3
9.4
Overview............................................................................................................................
Timer A..............................................................................................................................
9.2.1 Overview...............................................................................................................
9.2.2 Register Descriptions............................................................................................
9.2.3 Timer Operation....................................................................................................
9.2.4 Timer A Operation States .....................................................................................
9.2.5 Application Note...................................................................................................
Timer F...............................................................................................................................
9.3.1 Overview...............................................................................................................
9.3.2 Register Descriptions............................................................................................
9.3.3 CPU Interface........................................................................................................
9.3.4 Operation ..............................................................................................................
9.3.5 Application Notes .................................................................................................
Asynchronous Event Counter (AEC).................................................................................
9.4.1 Overview...............................................................................................................
9.4.2 Register Configurations ........................................................................................
9.4.3 Operation ..............................................................................................................
9.4.4 Asynchronous Event Counter Operation Modes ..................................................
9.4.5 Application Notes .................................................................................................
171
172
172
174
177
177
178
178
178
181
189
192
195
198
198
201
210
214
215
Section 10 Serial Communication Interface ................................................................. 217
10.1 Overview............................................................................................................................
10.1.1 Features .................................................................................................................
10.1.2 Block diagram.......................................................................................................
10.1.3 Pin configuration ..................................................................................................
217
217
219
220
v
10.2
10.3
10.4
10.5
10.1.4 Register configuration ..........................................................................................
Register Descriptions .........................................................................................................
10.2.1 Receive shift register (RSR) .................................................................................
10.2.2 Receive data register (RDR) .................................................................................
10.2.3 Transmit shift register (TSR)................................................................................
10.2.4 Transmit data register (TDR)................................................................................
10.2.5 Serial mode register (SMR) ..................................................................................
10.2.6 Serial control register 3 (SCR3)............................................................................
10.2.7 Serial status register (SSR) ...................................................................................
10.2.8 Bit rate register (BRR)..........................................................................................
10.2.9 Clock stop register 1 (CKSTPR1) ........................................................................
10.2.10 Serial Port Control Register (SPCR) ....................................................................
Operation............................................................................................................................
10.3.1 Overview...............................................................................................................
10.3.2 Operation in Asynchronous Mode........................................................................
10.3.3 Operation in Synchronous Mode ..........................................................................
10.3.4 Multiprocessor Communication Function ............................................................
Interrupts ............................................................................................................................
Application Notes ..............................................................................................................
220
221
221
221
222
222
223
226
230
234
239
240
241
241
245
254
261
268
269
Section 11 10-Bit PWM...................................................................................................... 275
11.1 Overview............................................................................................................................
11.1.1 Features .................................................................................................................
11.1.2 Block Diagram......................................................................................................
11.1.3 Pin Configuration..................................................................................................
11.1.4 Register Configuration..........................................................................................
11.2 Register Descriptions .........................................................................................................
11.2.1 PWM Control Register (PWCRm) .......................................................................
11.2.2 PWM Data Registers U and L (PWDRUm, PWDRLm)......................................
11.2.3 Clock Stop Register 2 (CKSTPR2) ......................................................................
11.3 Operation............................................................................................................................
11.3.1 Operation ..............................................................................................................
11.3.2 PWM Operation Modes........................................................................................
275
275
276
276
277
278
278
279
279
281
281
282
Section 12 A/D Converter.................................................................................................. 283
12.1 Overview............................................................................................................................
12.1.1 Features .................................................................................................................
12.1.2 Block Diagram......................................................................................................
12.1.3 Pin Configuration..................................................................................................
12.1.4 Register Configuration..........................................................................................
12.2 Register Descriptions .........................................................................................................
12.2.1 A/D Result Registers (ADRRH, ADRRL) ...........................................................
12.2.2 A/D Mode Register (AMR) ..................................................................................
vi
283
283
284
285
285
286
286
286
12.3
12.4
12.5
12.6
12.2.3 A/D Start Register (ADSR) ..................................................................................
12.2.4 Clock Stop Register 1 (CKSTPR1) ......................................................................
Operation............................................................................................................................
12.3.1 A/D Conversion Operation ...................................................................................
12.3.2 A/D Converter Operation Modes..........................................................................
Interrupts ............................................................................................................................
Typical Use ........................................................................................................................
Application Notes ..............................................................................................................
288
289
290
290
290
291
291
294
Section 13 LCD Controller/Driver .................................................................................. 295
13.1 Overview............................................................................................................................
13.1.1 Features .................................................................................................................
13.1.2 Block Diagram......................................................................................................
13.1.3 Pin Configuration..................................................................................................
13.1.4 Register Configuration..........................................................................................
13.2 Register Descriptions .........................................................................................................
13.2.1 LCD Port Control Register (LPCR)......................................................................
13.2.2 LCD Control Register (LCR)................................................................................
13.2.3 LCD Control Register 2 (LCR2) ..........................................................................
13.2.4 Clock Stop Register 2 (CKSTPR2) ......................................................................
13.3 Operation............................................................................................................................
13.3.1 Settings up to LCD Display..................................................................................
13.3.2 Relationship between LCD RAM and Display ....................................................
13.3.3 Operation in Power-Down Modes ........................................................................
13.3.4 Boosting the LCD Drive Power Supply................................................................
295
295
296
297
297
298
298
300
302
303
304
304
306
311
312
Section 14 Electrical Characteristics .............................................................................. 313
14.1 H8/3802 Series Absolute Maximum Ratings ....................................................................
14.2 H8/3802 Series Electrical Characteristics..........................................................................
14.2.1 Power Supply Voltage and Operating Range .......................................................
14.2.2 DC Characteristics ................................................................................................
14.2.3 AC Characteristics ................................................................................................
14.2.4 A/D Converter Characteristics..............................................................................
14.2.5 LCD Characteristics..............................................................................................
14.3 Operation Timing ...............................................................................................................
14.4 Output Load Circuit ...........................................................................................................
14.5 Resonator Equivalent Circuit .............................................................................................
14.6 Usage Note .........................................................................................................................
313
314
314
316
322
325
327
328
330
330
331
Appendix A CPU Instruction Set .................................................................................... 333
A.1
A.2
A.3
Instructions......................................................................................................................... 333
Operation Code Map.......................................................................................................... 341
Number of Execution States .............................................................................................. 343
vii
Appendix B Internal I/O Registers .................................................................................. 349
B.1
B.2
Addresses ........................................................................................................................... 349
Functions............................................................................................................................ 353
Appendix C I/O Port Block Diagrams ........................................................................... 397
C.1
C.2
C.3
C.4
C.5
C.6
C.7
C.8
C.9
Block Diagrams of Port 3 ..................................................................................................
Block Diagrams of Port 4 ..................................................................................................
Block Diagram of Port 5 ....................................................................................................
Block Diagram of Port 6 ....................................................................................................
Block Diagram of Port 7 ....................................................................................................
Block Diagrams of Port 8 ..................................................................................................
Block Diagrams of Port 9 ..................................................................................................
Block Diagram of Port A ...................................................................................................
Block Diagram of Port B ...................................................................................................
397
401
405
406
407
408
409
410
411
Appendix D Port States in the Different Processing States ..................................... 412
Appendix E List of Product Codes.................................................................................. 413
Appendix F Package Dimensions .................................................................................... 414
viii
Section 1 Overview
1.1
Overview
The H8/300L Series is a series of single-chip microcomputers (MCU: microcomputer unit), built
around the high-speed H8/300L CPU and equipped with peripheral system functions on-chip.
Within the H8/300L Series, the H8/3802 Series comprises single-chip microcomputers equipped
with a controller/driver. Other on-chip peripheral functions include three timers, a two-channel
10-bit pulse width modulator (PWM), a serial communication interface, and an A/D converter.
Together, these functions make the H8/3800 Series ideally suited for embedded applications in
systems requiring low power consumption and LCD display. Models in the H8/3802 Series are
the H8/3802, with on-chip 16-kbyte ROM and 1-kbyte RAM, the H8/3801, with 12-kbyte ROM
and 512 byte RAM, and the H8/3800, with 8-kbyte ROM and 512 byte RAM.
The H8/3802 is also available in a ZTAT™* version with on-chip PROM which can be
programmed as required by the user.
Table 1.1 summarizes the features of the H8/3802 Series.
Note: * ZTAT (Zero Turn Around Time) is a trademark of Hitachi, Ltd.
1
Table 1.1
Features
Item
Specification
CPU
High-speed H8/300L CPU
•
General-register architecture
General registers: Sixteen 8-bit registers (can be used as eight 16-bit
registers)
•
Operating speed
 Max. operating speed: 8 MHz
 Add/subtract: 0.25 µs (operating at 8 MHz)
 Multiply/divide: 1.75 µs (operating at 8 MHz)
 Can run on 32.768 kHz or 38.4 kHz subclock
•
Instruction set compatible with H8/300 CPU
 Instruction length of 2 bytes or 4 bytes
 Basic arithmetic operations between registers
 MOV instruction for data transfer between memory and registers
•
Typical instructions
 Multiply (8 bits × 8 bits)
 Divide (16 bits ÷ 8 bits)
 Bit accumulator
 Register-indirect designation of bit position
Interrupts
18 interrupt sources
•
11 external interrupt sources (IRQ 1, IRQ0, WKP 7 to WKP0, IRQAEC)
•
7 internal interrupt sources
Clock pulse generators Two on-chip clock pulse generators
Power-down modes
2
•
System clock pulse generator: 1.0 to 16 MHz
•
Subclock pulse generator: 32.768 kHz, 38.4 kHz
Seven power-down modes
•
Sleep (high-speed) mode
•
Sleep (medium-speed) mode
•
Standby mode
•
Watch mode
•
Subsleep mode
•
Subactive mode
•
Active (medium-speed) mode
Item
Specification
Memory
Large on-chip memory
I/O ports
Timers
•
H8/3802: 16-kbyte ROM, 1-kbyte RAM
•
H8/3801: 12-kbyte ROM, 512 byte RAM
•
H8/3800: 8-kbyte ROM, 512 byte RAM
50 pins
•
39 I/O pins
•
5 input pins
•
6 output pins
Three on-chip timers
•
Timer A: 8-bit timer
Count-up timer with selection of eight internal clock signals divided
from the system clock (ø)* and four clock signals divided from the
watch clock (øw)*
•
Asynchronous event counter: 16-bit timer
 Count-up timer able to count asynchronous external events
independently of the MCU's internal clocks
Asynchronous external events can be counted (both rising and falling
edge detection possible)
•
Timer F: 16-bit timer
 Can be used as two independent 8-bit timers
 Count-up by an event input from the four internal clocks
 Provision for toggle output by means of compare-match function
Serial communication
interface
•
10-bit PWM
Pulse-division PWM output for reduced ripple
Incorporates multiprocessor communication function
•
A/D converter
SCI3: 8-bit synchronous/asynchronous serial interface
Can be used as a 10-bit D/A converter by connecting to an external
low-pass filter.
Successive approximations using a resistance ladder
•
4-channel analog input pins
•
Conversion time: 31/ø or 62/ø per channel
3
Item
Specification
LCD
controller/driver
LCD controller/driver equipped with a maximum of 25 segment pins and four
common pins
Product lineup
•
Choice of four duty cycles (static, 1/2, 1/3, or 1/4)
•
Segment pins can be switched to general-purpose port function in 4-bit units
Product Code
Mask ROM
Version
ZTAT Version
Package
ROM/RAM Size
HD6433802H
HD6473802H
64-pin QFP (FP-64A)
ROM 16 kbytes
HD6433802FP
HD6473802FP
64-pin LQFP (FP-64E)
RAM 1 kbytes
HD6433802P
HD6473802P
64-pin DILP (DP-64S)
HD6433801H
—
64-pin QFP (FP-64A)
ROM 12 kbytes
HD6433801FP
—
64-pin LQFP (FP-64E)
RAM 512 bytes
HD6433801P
—
64-pin DILP (DP-64S)
HD6433800H
—
64-pin QFP (FP-64A)
ROM 8 kbytes
HD6433800FP
—
64-pin LQFP (FP-64E)
RAM 512 bytes
HD6433800P
—
64-pin DILP (DP-64S)
Note: * See section 4, Clock Pulse Generator, for the definition of ø and. ø w .
4
1.2
Internal Block Diagram
Figure 1.1 shows a block diagram of the H8/3802 Series.
System Clock
OSC
P31/TMOFL
P32/TMOFH
P33
P34
P35
P36/AEVH
P37/AEVL
Port 3
P40/SCK32
P41/RXD32
P42/TXD32
P43/IRQ0
Port 4
OSC1
OSC2
VSS = AVSS
VCC
RES
TEST
H8/300L
CPU
RAM
Port A
Sub Clock
OSC
x1
x2
PA3/COM4
PA2/COM3
PA1/COM2
PA0/COM1
IRQAEC
Port 9
Port 8
P80/SEG25
Port 7
Timer - A
P77/SEG24
P76/SEG23
P75/SEG22
P74/SEG21
P73/SEG20
P72/SEG19
P71/SEG18
P70/SEG17
LCD power
supply
Serial
communication
interface (SCI3)
V1
V2
V3
PB3/AN3/IRQ1
PB2/AN2
PB1/AN1
PB0/AN0
10-bit PWM1
Timer - F
10-bit PWM2
Port 6
P60/SEG9
P61/SEG10
P62/SEG11
P63/SEG12
P64/SEG13
P65/SEG14
P66/SEG15
P67/SEG16
AVcc
Asynchronous
counter (16 bit)
LCD
Controller
/Driver
P95
P94
P93
P92
P91/PWM2
P90/PWM1
Port B
Port 5
P50/WKP0/SEG1
P51/WKP1/SEG2
P52/WKP2/SEG3
P53/WKP3/SEG4
P54/WKP4/SEG5
P55/WKP5/SEG6
P56/WKP6/SEG7
P57/WKP7/SEG8
VSS
ROM
A/D
(10 bit)
Large-current (25 mA/pin) high-voltage open-drain pin (7 V)
Large-current (10 mA/pin) high-voltage open-drain pin (7 V)
High-voltage (7 V) input pin
Figure 1.1 Block Diagram
5
1.3
Pin Arrangement and Functions
1.3.1
Pin Arrangement
P50/WKP0/SEG1
P51/WKP1/SEG2
P52/WKP2/SEG3
P53/WKP3/SEG4
P54/WKP4/SEG5
P55/WKP5/SEG6
P56/WKP6/SEG7
P57/WKP7/SEG8
P60/SEG9
P61/SEG10
P62/SEG11
P63/SEG12
P64/SEG13
P65/SEG14
P66/SEG15
P67/SEG16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
The H8/3802 Series pin arrangement is shown in figures 1.2 and 1.3.
P90/PWM1
49
32
P70/SEG17
P91/PWM2
50
31
P71/SEG18
P92
51
30
P72/SEG19
P93
52
29
P73/SEG20
P94
53
28
P74/SEG21
P95
54
27
P75/SEG22
26
P76/SEG23
25
P77/SEG24
24
P80/SEG25
VSS
55
IRQAEC
56
P40/SCK32
57
P41/RXD32
58
23
PA0/COM1
P42/TXD32
59
22
PA1/COM2
P43/IRQ0
60
21
PA2/COM3
AVCC
61
20
PA3/COM4
PB0/AN0
62
19
V3
PB1/AN1
63
18
V2
PB2/AN2
64
17
V1
9
10
11
12
P32/TMOFH
P33
P34
16
8
RES
P31/TMOFL
VCC
7
TEST
15
6
OSC1
P37/AEVL
5
OSC2
14
4
VSS= AVSS
13
3
X2
P35
2
X1
P36/AEVH
1
PB3/IRQ1/AN3
FP–64A, FP–64E
(Top View)
Figure 1.2 Pin Arrangement (FP-64A, FP-64E: Top View)
6
P40/SCK32
1
64
IRQAEC
P41/RXD32
2
63
VSS
P42/TXD32
3
62
P95
P43/IRQ0
4
61
P94
AVCC
5
60
P93
PB0/AN0
6
59
P92
PB1/AN1
7
58
P91/PWM2
PB2/AN2
8
57
P90/PWM1
PB3/IRQ1/AN3
9
56
P50/WKP0/SEG1
X1
10
55
P51/WKP1/SEG2
X2
11
54
P52/WKP2/SEG3
VSS= AVSS
12
53
P53/WKP3/SEG4
OSC2
13
52
P54/WKP4/SEG5
OSC1
14
51
P55/WKP5/SEG6
TEST
15
50
P56/WKP6/SEG7
RES
16
49
P57/WKP7/SEG8
P31/TMOFL
17
48
P60/SEG9
P32/TMOFH
18
47
P61/SEG10
P33
19
46
P62/SEG11
P34
20
45
P63/SEG12
P35
21
44
P64/SEG13
P36/AEVH
22
43
P65/SEG14
P37/AEVL
23
42
P66/SEG15
VCC
24
41
P67/SEG16
V1
25
40
P70/SEG17
V2
26
39
P71/SEG18
V3
27
38
P72/SEG19
PA3/COM4
28
37
P73/SEG20
PA2/COM3
29
36
P74/SEG21
PA1/COM2
30
35
P75/SEG22
PA0/COM1
31
34
P76/SEG23
P80/SEG25
32
33
P77/SEG24
DP–64S
(Top View)
Figure 1.3 Pin Arrangement (DP-64S: Top View)
7
1.3.2
Pin Functions
Table 1.2 outlines the pin functions of the H8/3802 Series.
Table 1.2
Pin Functions
Pin No.
Type
FP-64A
FP-64E
DP-64S
I/O
Name and Functions
16
24
Input
Power supply: All VCC pins should be
connected to the system power supply.
VSS
4 (= AVSS)
55
12 (=
AVSS )
63
Input
Ground: All VSS pins should be
connected to the system power supply
(0 V).
AVCC
61
5
Input
Analog power supply: This is the
power supply pin for the A/D converter.
When the A/D converter is not used,
connect this pin to the system power
supply.
AVSS
4 (= VSS)
12 (= VSS) Input
Analog ground: This is the A/D
converter ground pin. It should be
connected to the system power supply
(0V).
V1
V2
V3
17
18
19
25
26
27
Input
LCD power supply: These are the
power supply pins for the LCD
controller/driver.
OSC 1
6
14
Input
OSC 2
5
13
X1
2
10
X2
3
11
RES
8
16
Input
Reset: When this pin is driven low, the
chip is reset
TEST
7
15
Input
Test pin: This pin is reserved and
cannot be used. It should be connected
to VSS.
Symbol
Power
VCC
source pins
Clock pins
System
control
8
These pins connect to a crystal or
Output ceramic oscillator, or can be used to
input an external clock. See section 4,
Clock Pulse Generators, for a typical
connection diagram.
Input
These pins connect to a 32.768-kHz or
Output 38.4-kHz crystal oscillator.
See section 4, Clock Pulse
Generators, for a typical connection
diagram.
Pin No.
Type
Symbol
FP-64A
FP-64E
DP-64S
I/O
Name and Functions
Interrupt
pins
IRQ0
IRQ1
60
1
4
9
Input
IRQ interrupt request 0 and 1: These
are input pins for edge-sensitive
external interrupts, with a selection of
rising or falling edge
IRQAEC
56
64
Input
Asynchronous event counter event
signal: This is an interrupt input pin for
enabling asynchronous event input.
WKP 7 to
WKP 0
41 to 48
49 to 56
Input
Wakeup interrupt request 0 to 7:
These are input pins for rising or fallingedge-sensitive external interrupts.
AEVL
AEVH
15
14
23
22
Input
Asynchronous event counter event
input: This is an event input pin for
input to the asynchronous event
counter.
TMOFL
9
17
Output Timer FL output: This is an output pin
for waveforms generated by the timer
FL output compare function.
TMOFH
10
18
Output Timer FH output: This is an output pin
for waveforms generated by the timer
FH output compare function.
10-bit
PWM pin
PWM1
PWM2
49
50
57
58
Output 10-bit PWM output: These are output
pins for waveforms generated by the
channel 1 and 2 10-bit PWMs.
I/O ports
P37 to P3 1 15 to 9
23 to 17
I/O
Port 3: This is an 7-bit I/O port. Input or
output can be designated for each bit by
means of port control register 3 (PCR3).
P43
4
Input
Port 4 (bit 3): This is a 1-bit input port.
P42 to P4 0 59 to 57
3 to 1
I/O
Port 4 (bits 2 to 0): This is a 3-bit I/O
port. Input or output can be designated
for each bit by means of port control
register 4 (PCR4).
P57 to P5 0 41 to 48
49 to 56
I/O
Port 5: This is an 8-bit I/O port. Input or
output can be designated for each bit by
means of port control register 5 (PCR5).
Timer pins
60
9
Pin No.
FP-64A
FP-64E
Type
Symbol
I/O ports
P67 to P6 0
33 to 40
P77 to P7 0
I/O
Name and Functions
41 to 48
I/O
Port 6: This is an 8-bit I/O port. Input or
output can be designated for each bit by
means of port control register 6 (PCR6).
25 to 32
33 to 40
I/O
Port 7: This is an 8-bit I/O port. Input or
output can be designated for each bit by
means of port control register 7 (PCR7).
P80
24
32
I/O
Port 8: This is an 8-bit I/O port. Input or
output can be designated for each bit by
means of port control register 8 (PCR8).
P95 to P9 0
54 to 49
62 to 57
Output Port 9: This is a 6-bit output port.
PA3 to PA 0 20 to 23
28 to 31
I/O
Port A: This is a 4-bit I/O port. Input or
output can be designated for each bit by
means of port control register A (PCRA).
PB3 to PB 0 1, 64 to 62 9 to 6
Input
Port B: This is a 4-bit input port.
Serial
communication
interface
(SCI)
RXD32
58
2
Input
SCI3 receive data input:
This is the SCI3 data input pin.
TXD32
59
3
Output SCI3 transmit data output:
This is the SCI3 data output pin.
SCK 32
57
1
I/O
SCI3 clock I/O:
This is the SCI3 clock I/O pin.
A/D
converter
AN3 to An0 1
64 to 62
9 to 6
Input
Analog input channels 3 to 0:
These are analog data input channels to
the A/D converter
LCD
controller/
driver
COM4 to
COM1
20 to 23
28 to 31
Output LCD common output: These are the
LCD common output pins.
SEG25 to
SEG1
24 to 48
32 to 56
Output LCD segment output: These are the
LCD segment output pins.
10
DP-64S
Section 2 CPU
2.1
Overview
The H8/300L CPU has sixteen 8-bit general registers, which can also be paired as eight 16-bit
registers. Its concise instruction set is designed for high-speed operation.
2.1.1
Features
Features of the H8/300L CPU are listed below.
• General-register architecture
Sixteen 8-bit general registers, also usable as eight 16-bit general registers
• Instruction set with 55 basic instructions, including:
 Multiply and divide instructions
 Powerful bit-manipulation instructions
• Eight addressing modes
 Register direct
 Register indirect
 Register indirect with displacement
 Register indirect with post-increment or pre-decrement
 Absolute address
 Immediate
 Program-counter relative
 Memory indirect
• 64-kbyte address space
• High-speed operation
 All frequently used instructions are executed in two to four states
 High-speed arithmetic and logic operations
 8- or 16-bit register-register add or subtract: 0.25 µs*
 8 × 8-bit multiply:
1.75 µs*
 16 ÷ 8-bit divide:
1.75 µs*
Note: * These values are at ø = 8 MHz.
• Low-power operation modes
SLEEP instruction for transfer to low-power operation
11
2.1.2
Address Space
The H8/300L CPU supports an address space of up to 64 kbytes for storing program code and
data.
See 2.8, Memory Map, for details of the memory map.
2.1.3
Register Configuration
Figure 2.1 shows the register structure of the H8/300L CPU. There are two groups of registers: the
general registers and control registers.
General registers (Rn)
7
0 7
0
R0H
R0L
R1H
R1L
R2H
R2L
R3H
R3L
R4H
R4L
R5H
R5L
R6H
R7H
R6L
(SP)
SP: Stack pointer
R7L
Control registers (CR)
15
0
PC
7 6 5 4 3 2 1 0
CCR I U H U N Z V C
PC: Program counter
CCR: Condition code register
Carry flag
Overflow flag
Zero flag
Negative flag
Half-carry flag
Interrupt mask bit
User bit
User bit
Figure 2.1 CPU Registers
12
2.2
Register Descriptions
2.2.1
General Registers
All the general registers can be used as both data registers and address registers.
When used as data registers, they can be accessed as 16-bit registers (R0 to R7), or the high bytes
(R0H to R7H) and low bytes (R0L to R7L) can be accessed separately as 8-bit registers.
When used as address registers, the general registers are accessed as 16-bit registers (R0 to R7).
R7 also functions as the stack pointer (SP), used implicitly by hardware in exception processing
and subroutine calls. When it functions as the stack pointer, as indicated in figure 2.2, SP (R7)
points to the top of the stack.
Lower address side [H'0000]
Unused area
SP (R7)
Stack area
Upper address side [H'FFFF]
Figure 2.2 Stack Pointer
2.2.2
Control Registers
The CPU control registers include a 16-bit program counter (PC) and an 8-bit condition code
register (CCR).
Program Counter (PC): This 16-bit register indicates the address of the next instruction the CPU
will execute. All instructions are fetched 16 bits (1 word) at a time, so the least significant bit of
the PC is ignored (always regarded as 0).
Condition Code Register (CCR): This 8-bit register contains internal status information,
including the interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and
carry (C) flags. These bits can be read and written by software (using the LDC, STC, ANDC,
ORC, and XORC instructions). The N, Z, V, and C flags are used as branching conditions for
conditional branching (Bcc) instructions.
13
Bit 7—Interrupt Mask Bit (I): When this bit is set to 1, interrupts are masked. This bit is set to 1
automatically at the start of exception handling. The interrupt mask bit may be read and written
by software. For further details, see section 3.3, Interrupts.
Bit 6—User Bit (U): Can be used freely by the user.
Bit 5—Half-Carry Flag (H): When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B
instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and is cleared to 0
otherwise.
The H flag is used implicitly by the DAA and DAS instructions.
When the ADD.W, SUB.W, or CMP.W instruction is executed, the H flag is set to 1 if there is a
carry or borrow at bit 11, and is cleared to 0 otherwise.
Bit 4—User Bit (U): Can be used freely by the user.
Bit 3—Negative Flag (N): Indicates the most significant bit (sign bit) of the result of an
instruction.
Bit 2—Zero Flag (Z): Set to 1 to indicate a zero result, and cleared to 0 to indicate a non-zero
result.
Bit 1—Overflow Flag (V): Set to 1 when an arithmetic overflow occurs, and cleared to 0 at other
times.
Bit 0—Carry Flag (C): Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by:
• Add instructions, to indicate a carry
• Subtract instructions, to indicate a borrow
• Shift and rotate instructions, to store the value shifted out of the end bit
The carry flag is also used as a bit accumulator by bit manipulation instructions.
Some instructions leave some or all of the flag bits unchanged.
Refer to the H8/300L Series Programming Manual for the action of each instruction on the flag
bits.
2.2.3
Initial Register Values
When the CPU is reset, the program counter (PC) is initialized to the value stored at address
H'0000 in the vector table, and the I bit in the CCR is set to 1. The other CCR bits and the general
registers are not initialized. In particular, the stack pointer (R7) is not initialized. The stack pointer
should be initialized by software, by the first instruction executed after a reset.
14
2.3
Data Formats
The H8/300L CPU can process 1-bit data, 4-bit (BCD) data, 8-bit (byte) data, and 16-bit (word)
data.
• Bit manipulation instructions operate on 1-bit data specified as bit n in a byte operand
(n = 0, 1, 2, ..., 7).
• All arithmetic and logic instructions except ADDS and SUBS can operate on byte data.
• The MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU (8 bits × 8 bits), and
DIVXU (16 bits ÷ 8 bits) instructions operate on word data.
• The DAA and DAS instructions perform decimal arithmetic adjustments on byte data in
packed BCD form. Each nibble of the byte is treated as a decimal digit.
15
2.3.1
Data Formats in General Registers
Data of all the sizes above can be stored in general registers as shown in figure 2.3.
Data Type
Register No.
Data Format
7
1-bit data
RnH
1-bit data
RnL
Byte data
RnH
Byte data
RnL
Word data
Rn
4-bit BCD data
RnH
4-bit BCD data
RnL
7
0
6
5
4
3
2
1
0
don’t care
7
don’t care
0
7
7
0
MSB
LSB
don’t care
6
5
3
2
1
0
don’t care
7
0
MSB
LSB
15
0
MSB
LSB
7
4
3
Upper digit
0
Lower digit
don’t care
7
don’t care
4
Upper digit
Notation:
RnH: Upper byte of general register
RnL: Lower byte of general register
MSB: Most significant bit
LSB: Least significant bit
Figure 2.3 Register Data Formats
16
4
0
3
Lower digit
2.3.2
Memory Data Formats
Figure 2.4 indicates the data formats in memory. The H8/300L CPU can access word data stored
in memory (MOV.W instruction), but the word data must always begin at an even address. If word
data starting at an odd address is accessed, the least significant bit of the address is regarded as 0,
and the word data starting at the preceding address is accessed. The same applies to instruction
codes.
Data Type
Address
Data Format
7
1-bit data
Address n
7
Byte data
Address n
MSB
Even address
MSB
Word data
Odd address
Byte data (CCR) on stack
Word data on stack
0
6
5
4
3
2
1
0
LSB
Upper 8 bits
Lower 8 bits
LSB
Even address
MSB
CCR
LSB
Odd address
MSB
CCR*
LSB
Even address
MSB
Odd address
LSB
CCR: Condition code register
Note: * Ignored on return
Figure 2.4 Memory Data Formats
When the stack is accessed using R7 as an address register, word access should always be
performed. When the CCR is pushed on the stack, two identical copies of the CCR are pushed to
make a complete word. When they are restored, the lower byte is ignored.
17
2.4
Addressing Modes
2.4.1
Addressing Modes
The H8/300L CPU supports the eight addressing modes listed in table 2.1. Each instruction uses a
subset of these addressing modes.
Table 2.1
Addressing Modes
No.
Address Modes
Symbol
1
Register direct
Rn
2
Register indirect
@Rn
3
Register indirect with displacement
@(d:16, Rn)
4
Register indirect with post-increment
Register indirect with pre-decrement
@Rn+
@–Rn
5
Absolute address
@aa:8 or @aa:16
6
Immediate
#xx:8 or #xx:16
7
Program-counter relative
@(d:8, PC)
8
Memory indirect
@@aa:8
1. Register Direct—Rn: The register field of the instruction specifies an 8- or 16-bit general
register containing the operand.
Only the MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU (8 bits × 8 bits), and
DIVXU (16 bits ÷ 8 bits) instructions have 16-bit operands.
2. Register Indirect—@Rn: The register field of the instruction specifies a 16-bit general
register containing the address of the operand in memory.
3. Register Indirect with Displacement—@(d:16, Rn): The instruction has a second word
(bytes 3 and 4) containing a displacement which is added to the contents of the specified
general register to obtain the operand address in memory.
This mode is used only in MOV instructions. For the MOV.W instruction, the resulting address
must be even.
18
4. Register Indirect with Post-Increment or Pre-Decrement—@Rn+ or @–Rn:
 Register indirect with post-increment—@Rn+
The @Rn+ mode is used with MOV instructions that load registers from memory.
The register field of the instruction specifies a 16-bit general register containing the address
of the operand. After the operand is accessed, the register is incremented by 1 for MOV.B
or 2 for MOV.W. For MOV.W, the original contents of the 16-bit general register must be
even.
 Register indirect with pre-decrement—@–Rn
The @–Rn mode is used with MOV instructions that store register contents to memory.
The register field of the instruction specifies a 16-bit general register which is decremented
by 1 or 2 to obtain the address of the operand in memory. The register retains the
decremented value. The size of the decrement is 1 for MOV.B or 2 for MOV.W. For
MOV.W, the original contents of the register must be even.
5. Absolute Address—@aa:8 or @aa:16: The instruction specifies the absolute address of the
operand in memory.
The absolute address may be 8 bits long (@aa:8) or 16 bits long (@aa:16). The MOV.B and bit
manipulation instructions can use 8-bit absolute addresses. The MOV.B, MOV.W, JMP, and
JSR instructions can use 16-bit absolute addresses.
For an 8-bit absolute address, the upper 8 bits are assumed to be 1 (H'FF). The address range is
H'FF00 to H'FFFF (65280 to 65535).
6. Immediate—#xx:8 or #xx:16: The instruction contains an 8-bit operand (#xx:8) in its second
byte, or a 16-bit operand (#xx:16) in its third and fourth bytes. Only MOV.W instructions can
contain 16-bit immediate values.
The ADDS and SUBS instructions implicitly contain the value 1 or 2 as immediate data. Some
bit manipulation instructions contain 3-bit immediate data in the second or fourth byte of the
instruction, specifying a bit number.
7. Program-Counter Relative—@(d:8, PC): This mode is used in the Bcc and BSR
instructions. An 8-bit displacement in byte 2 of the instruction code is sign-extended to 16 bits
and added to the program counter contents to generate a branch destination address. The
possible branching range is –126 to +128 bytes (–63 to +64 words) from the current address.
The displacement should be an even number.
8. Memory Indirect—@@aa:8: This mode can be used by the JMP and JSR instructions. The
second byte of the instruction code specifies an 8-bit absolute address. The word located at this
address contains the branch destination address.
The upper 8 bits of the absolute address are assumed to be 0 (H'00), so the address range is
from H'0000 to H'00FF (0 to 255). Note that with the H8/300L Series, the lower end of the
address area is also used as a vector area. See 3.3, Interrupts, for details on the vector area.
If an odd address is specified as a branch destination or as the operand address of a MOV.W
instruction, the least significant bit is regarded as 0, causing word access to be performed at the
address preceding the specified address. See 2.3.2, Memory Data Formats, for further information.
19
2.4.2
Effective Address Calculation
Table 2.2 shows how effective addresses are calculated in each of the addressing modes.
Arithmetic and logic instructions use register direct addressing (1). The ADD.B, ADDX, SUBX,
CMP.B, AND, OR, and XOR instructions can also use immediate addressing (6).
Data transfer instructions can use all addressing modes except program-counter relative (7) and
memory indirect (8).
Bit manipulation instructions can use register direct (1), register indirect (2), or 8-bit absolute
addressing (5) to specify the operand. Register indirect (1) (BSET, BCLR, BNOT, and BTST
instructions) or 3-bit immediate addressing (6) can be used independently to specify a bit position
in the operand.
20
21
4
3
2
rm
op
7 6
rm
4 3
4 3
rn
0
0
op
disp
7 6
rm
op
7 6
rm
4 3
4 3
0
0
15
op
7 6
rm
4 3
0
Register indirect with pre-decrement,
@–Rn
15
Register indirect with
post-increment, @Rn+
15
Register indirect with displacement,
@(d:16, Rn)
15
Register indirect, @Rn
op
8 7
Register direct, Rn
1
15
Addressing Mode and
Instruction Format
No.
Table 2.2 Effective Address Calculation
0
0
0
Contents (16 bits) of register
indicated by rm
0
1 or 2
Contents (16 bits) of register
indicated by rm
disp
Contents (16 bits) of register
indicated by rm
Contents (16 bits) of register
indicated by rm
3
rm
0
3
rn
Effective Address (EA)
0
15
15
15
15
0
0
0
0
Operand is contents of registers indicated by rm/rn
Incremented or decremented
by 1 if operand is byte size,
1 or 2
and by 2 if word size
15
15
15
15
Effective Address Calculation Method
22
7
6
5
No.
op
op
IMM
op
8 7
abs
op
8 7
IMM
abs
15
op
8 7
disp
Program-counter relative
@(d:8, PC)
15
#xx:16
15
Immediate
#xx:8
15
@aa:16
15
Absolute address
@aa:8
Addressing Mode and
Instruction Format
0
0
0
0
0
PC contents
Sign extension
15
disp
0
Effective Address Calculation Method
H'FF
8 7
0
0
15
0
Operand is 1- or 2-byte immediate data
15
15
Effective Address (EA)
23
Notation:
rm, rn: Register field
Operation field
op:
disp: Displacement
IMM: Immediate data
abs: Absolute address
op
8 7
abs
Memory indirect, @@aa:8
8
15
Addressing Mode and
Instruction Format
No.
0
15
abs
Memory contents (16 bits)
H'00
8 7
0
Effective Address Calculation Method
15
Effective Address (EA)
0
2.5
Instruction Set
The H8/300L Series can use a total of 55 instructions, which are grouped by function in table 2.3.
Table 2.3
Instruction Set
Function
Instructions
*1
Number
*1
Data transfer
MOV, PUSH , POP
1
Arithmetic operations
ADD, SUB, ADDX, SUBX, INC, DEC, ADDS, SUBS, DAA,
DAS, MULXU, DIVXU, CMP, NEG
14
Logic operations
AND, OR, XOR, NOT
4
Shift
SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR
8
Bit manipulation
BSET, BCLR, BNOT, BTST, BAND, BIAND, BOR, BIOR,
BXOR, BIXOR, BLD, BILD, BST, BIST
14
Branch
Bcc*2, JMP, BSR, JSR, RTS
5
System control
RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP
8
Block data transfer
EEPMOV
1
Total: 55
Notes: 1. PUSH Rn is equivalent to MOV.W Rn, @–SP.
POP Rn is equivalent to MOV.W @SP+, Rn. The same applies to the machine
language.
2. Bcc is a conditional branch instruction in which cc represents a condition code.
The following sections give a concise summary of the instructions in each category, and indicate
the bit patterns of their object code. The notation used is defined next.
24
Notation
Rd
General register (destination)
Rs
General register (source)
Rn
General register
(EAd), <EAd>
Destination operand
(EAs), <EAs>
Source operand
CCR
Condition code register
N
N (negative) flag of CCR
Z
Z (zero) flag of CCR
V
V (overflow) flag of CCR
C
C (carry) flag of CCR
PC
Program counter
SP
Stack pointer
#IMM
Immediate data
disp
Displacement
+
Addition
–
Subtraction
×
Multiplication
÷
Division
∧
AND logical
∨
OR logical
⊕
Exclusive OR logical
→
Move
~
Logical negation (logical complement)
:3
3-bit length
:8
8-bit length
:16
16-bit length
( ), < >
Contents of operand indicated by effective address
25
2.5.1
Data Transfer Instructions
Table 2.4 describes the data transfer instructions. Figure 2.5 shows their object code formats.
Table 2.4
Data Transfer Instructions
Instruction
Size*
Function
MOV
B/W
(EAs) → Rd, Rs → (EAd)
Moves data between two general registers or between a general
register and memory, or moves immediate data to a general
register.
The Rn, @Rn, @(d:16, Rn), @aa:16, #xx:16, @–Rn, and @Rn+
addressing modes are available for word data. The @aa:8
addressing mode is available for byte data only.
The @–R7 and @R7+ modes require word operands. Do not
specify byte size for these two modes.
POP
W
@SP+ → Rn
Pops a 16-bit general register from the stack. Equivalent to
MOV.W @SP+, Rn.
PUSH
W
Rn → @–SP
Pushes a 16-bit general register onto the stack. Equivalent to
MOV.W Rn, @–SP.
Notes: *
Size: Operand size
B:
Byte
W:
Word
Certain precautions are required in data access. See 2.9.1, Notes on Data Access, for details.
26
15
8
7
0
op
rm
15
8
8
Rm→Rn
7
0
op
15
rn
MOV
rm
rn
rm
rn
@Rm←→Rn
7
0
op
@(d:16, Rm)←→Rn
disp
15
8
7
0
op
rm
15
8
op
7
0
rn
15
@Rm+→Rn, or
Rn →@–Rm
rn
abs
8
@aa:8←→Rn
7
0
op
rn
@aa:16←→Rn
abs
15
8
op
7
0
rn
15
IMM
8
#xx:8→Rn
7
0
op
rn
#xx:16→Rn
IMM
15
8
op
7
0
1
1
1
rn
PUSH, POP
@SP+ → Rn, or
Rn → @–SP
Notation:
op:
Operation field
rm, rn: Register field
disp: Displacement
abs:
Absolute address
IMM: Immediate data
Figure 2.5 Data Transfer Instruction Codes
27
2.5.2
Arithmetic Operations
Table 2.5 describes the arithmetic instructions.
Table 2.5
Arithmetic Instructions
Instruction
Size*
Function
ADD SUB
B/W
Rd ± Rs → Rd, Rd + #IMM → Rd
Performs addition or subtraction on data in two general registers,
or addition on immediate data and data in a general register.
Immediate data cannot be subtracted from data in a general
register. Word data can be added or subtracted only when both
words are in general registers.
ADDX SUBX
B
Rd ± Rs ± C → Rd, Rd ± #IMM ± C → Rd
Performs addition or subtraction with carry or borrow on byte data
in two general registers, or addition or subtraction on immediate
data and data in a general register.
INC DEC
B
Rd ± 1 → Rd
Increments or decrements a general register by 1.
ADDS SUBS
W
Rd ± 1 → Rd, Rd ± 2 → Rd
Adds or subtracts 1 or 2 to or from a general register
DAA DAS
B
Rd decimal adjust → Rd
Decimal-adjusts (adjusts to 4-bit BCD) an addition or subtraction
result in a general register by referring to the CCR
MULXU
B
Rd × Rs → Rd
Performs 8-bit × 8-bit unsigned multiplication on data in two
general registers, providing a 16-bit result
DIVXU
B
Rd ÷ Rs → Rd
Performs 16-bit ÷ 8-bit unsigned division on data in two general
registers, providing an 8-bit quotient and 8-bit remainder
CMP
B/W
Rd – Rs, Rd – #IMM
Compares data in a general register with data in another general
register or with immediate data, and indicates the result in the
CCR. Word data can be compared only between two general
registers.
NEG
B
0 – Rd → Rd
Obtains the two’s complement (arithmetic complement) of data in a
general register
Notes: *
28
Size: Operand size
B:
Byte
W:
Word
2.5.3
Logic Operations
Table 2.6 describes the four instructions that perform logic operations.
Table 2.6
Logic Operation Instructions
Instruction
Size*
Function
AND
B
Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd
Performs a logical AND operation on a general register and
another general register or immediate data
OR
B
Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd
Performs a logical OR operation on a general register and another
general register or immediate data
XOR
B
Rd ⊕ Rs → Rd, Rd ⊕ #IMM → Rd
Performs a logical exclusive OR operation on a general register
and another general register or immediate data
NOT
B
~ Rd → Rd
Obtains the one’s complement (logical complement) of general
register contents
Notes: *
2.5.4
Size: Operand size
B:
Byte
Shift Operations
Table 2.7 describes the eight shift instructions.
Table 2.7
Shift Instructions
Instruction
Size*
Function
SHAL
SHAR
B
Rd shift → Rd
SHLL
SHLR
B
ROTL
ROTR
B
ROTXL
ROTXR
B
Notes: *
Performs an arithmetic shift operation on general register contents
Rd shift → Rd
Performs a logical shift operation on general register contents
Rd rotate → Rd
Rotates general register contents
Rd rotate through carry → Rd
Rotates general register contents through the C (carry) bit
Size: Operand size
B:
Byte
29
Figure 2.6 shows the instruction code format of arithmetic, logic, and shift instructions.
15
8
7
op
0
rm
15
8
7
0
op
15
7
op
0
rm
8
op
rn
7
7
op
0
rm
8
op
AND, OR, XOR (Rm)
0
IMM
8
op
rn
7
rn
15
ADD, ADDX, SUBX,
CMP (#XX:8)
IMM
8
15
MULXU, DIVXU
0
rn
15
ADDS, SUBS, INC, DEC,
DAA, DAS, NEG, NOT
rn
8
15
ADD, SUB, CMP,
ADDX, SUBX (Rm)
rn
AND, OR, XOR (#xx:8)
7
0
rn
SHAL, SHAR, SHLL, SHLR,
ROTL, ROTR, ROTXL, ROTXR
Notation:
Operation field
op:
rm, rn: Register field
IMM: Immediate data
Figure 2.6 Arithmetic, Logic, and Shift Instruction Codes
30
2.5.5
Bit Manipulations
Table 2.8 describes the bit-manipulation instructions. Figure 2.7 shows their object code formats.
Table 2.8
Bit-Manipulation Instructions
Instruction
Size*
Function
BSET
B
1 → (<bit-No.> of <EAd>)
Sets a specified bit in a general register or memory to 1. The bit
number is specified by 3-bit immediate data or the lower three bits
of a general register.
BCLR
B
0 → (<bit-No.> of <EAd>)
Clears a specified bit in a general register or memory to 0. The bit
number is specified by 3-bit immediate data or the lower three bits
of a general register.
BNOT
B
~ (<bit-No.> of <EAd>) → (<bit-No.> of <EAd>)
Inverts a specified bit in a general register or memory. The bit
number is specified by 3-bit immediate data or the lower three bits
of a general register.
BTST
B
~ (<bit-No.> of <EAd>) → Z
Tests a specified bit in a general register or memory and sets or
clears the Z flag accordingly. The bit number is specified by 3-bit
immediate data or the lower three bits of a general register.
BAND
B
C ∧ (<bit-No.> of <EAd>) → C
ANDs the C flag with a specified bit in a general register or
memory, and stores the result in the C flag.
BIAND
B
C ∧ [~ (<bit-No.> of <EAd>)] → C
ANDs the C flag with the inverse of a specified bit in a general
register or memory, and stores the result in the C flag.
The bit number is specified by 3-bit immediate data.
BOR
B
C ∨ (<bit-No.> of <EAd>) → C
ORs the C flag with a specified bit in a general register or memory,
and stores the result in the C flag.
BIOR
B
C ∨ [~ (<bit-No.> of <EAd>)] → C
ORs the C flag with the inverse of a specified bit in a general
register or memory, and stores the result in the C flag.
The bit number is specified by 3-bit immediate data.
Notes: *
Size: Operand size
B:
Byte
31
Instruction
Size*
Function
BXOR
B
C ⊕ (<bit-No.> of <EAd>) → C
XORs the C flag with a specified bit in a general register or
memory, and stores the result in the C flag.
BIXOR
B
C ⊕ [~(<bit-No.> of <EAd>)] → C
XORs the C flag with the inverse of a specified bit in a general
register or memory, and stores the result in the C flag.
The bit number is specified by 3-bit immediate data.
BLD
B
(<bit-No.> of <EAd>) → C
Copies a specified bit in a general register or memory to the C flag.
BILD
B
~ (<bit-No.> of <EAd>) → C
Copies the inverse of a specified bit in a general register or
memory to the C flag.
The bit number is specified by 3-bit immediate data.
BST
B
C → (<bit-No.> of <EAd>)
Copies the C flag to a specified bit in a general register or memory.
BIST
B
~ C → (<bit-No.> of <EAd>)
Copies the inverse of the C flag to a specified bit in a general
register or memory.
The bit number is specified by 3-bit immediate data.
Notes: *
Size: Operand size
B:
Byte
Certain precautions are required in bit manipulation. See 2.9.2, Notes on Bit Manipulation, for
details.
32
BSET, BCLR, BNOT, BTST
15
8
7
op
0
IMM
15
8
7
op
0
rm
15
8
Operand: register direct (Rn)
Bit No.: immediate (#xx:3)
rn
Operand: register direct (Rn)
Bit No.: register direct (Rm)
rn
7
0
rn
0
0
0
0 Operand: register indirect (@Rn)
IMM
0
0
0
0 Bit No.:
op
rn
0
0
0
0 Operand: register indirect (@Rn)
op
rm
0
0
0
0 Bit No.:
op
op
15
8
15
8
7
0
7
abs
IMM
15
8
0
Operand: absolute (@aa:8)
0
0
7
0 Bit No.:
immediate (#xx:3)
0
op
abs
op
register direct (Rm)
0
op
op
immediate (#xx:3)
rm
0
Operand: absolute (@aa:8)
0
0
0 Bit No.:
register direct (Rm)
BAND, BOR, BXOR, BLD, BST
15
8
7
op
0
IMM
15
8
7
op
op
15
8
Operand: register direct (Rn)
Bit No.: immediate (#xx:3)
rn
0
rn
0
0
0
0 Operand: register indirect (@Rn)
IMM
0
0
0
0 Bit No.:
7
0
op
abs
op
immediate (#xx:3)
IMM
0
Operand: absolute (@aa:8)
0
0
0 Bit No.:
immediate (#xx:3)
Notation:
op:
Operation field
rm, rn: Register field
abs:
Absolute address
IMM: Immediate data
Figure 2.7 Bit Manipulation Instruction Codes
33
BIAND, BIOR, BIXOR, BILD, BIST
15
8
7
op
0
IMM
15
8
7
op
op
15
8
Operand: register direct (Rn)
Bit No.: immediate (#xx:3)
rn
0
rn
0
0
0
0 Operand: register indirect (@Rn)
IMM
0
0
0
0 Bit No.:
7
0
op
abs
op
immediate (#xx:3)
IMM
0
Operand: absolute (@aa:8)
0
0
0 Bit No.:
immediate (#xx:3)
Notation:
op:
Operation field
rm, rn: Register field
abs:
Absolute address
IMM: Immediate data
Figure 2.7 Bit Manipulation Instruction Codes (cont)
34
2.5.6
Branching Instructions
Table 2.9 describes the branching instructions. Figure 2.8 shows their object code formats.
Table 2.9
Branching Instructions
Instruction
Size
Function
Bcc
—
Branches to the designated address if condition cc is true. The
branching conditions are given below.
Mnemonic
Description
Condition
BRA (BT)
Always (true)
Always
BRN (BF)
Never (false)
Never
BHI
High
C∨Z=0
BLS
Low or same
C∨Z=1
BCC (BHS)
Carry clear (high or same)
C=0
BCS (BLO)
Carry set (low)
C=1
BNE
Not equal
Z=0
BEQ
Equal
Z=1
BVC
Overflow clear
V=0
BVS
Overflow set
V=1
BPL
Plus
N=0
BMI
Minus
N=1
BGE
Greater or equal
N⊕V=0
BLT
Less than
N⊕V=1
BGT
Greater than
Z ∨ (N ⊕ V) = 0
BLE
Less or equal
Z ∨ (N ⊕ V) = 1
JMP
—
Branches unconditionally to a specified address
BSR
—
Branches to a subroutine at a specified address
JSR
—
Branches to a subroutine at a specified address
RTS
—
Returns from a subroutine
35
15
8
op
7
0
cc
15
disp
8
7
op
0
rm
15
Bcc
8
0
0
0
7
0
JMP (@Rm)
0
op
JMP (@aa:16)
abs
15
8
7
0
op
abs
15
8
JMP (@@aa:8)
7
0
op
disp
15
8
7
op
0
rm
15
BSR
8
0
0
0
7
0
JSR (@Rm)
0
op
JSR (@aa:16)
abs
15
8
7
op
0
abs
15
8
7
op
Notation:
op: Operation field
cc: Condition field
rm: Register field
disp: Displacement
abs: Absolute address
Figure 2.8 Branching Instruction Codes
36
JSR (@@aa:8)
0
RTS
2.5.7
System Control Instructions
Table 2.10 describes the system control instructions. Figure 2.9 shows their object code formats.
Table 2.10 System Control Instructions
Instruction
Size*
Function
RTE
—
Returns from an exception-handling routine
SLEEP
—
Causes a transition from active mode to a power-down mode. See
section 5, Power-Down Modes, for details.
LDC
B
Rs → CCR, #IMM → CCR
Moves immediate data or general register contents to the condition
code register
STC
B
CCR → Rd
Copies the condition code register to a specified general register
ANDC
B
CCR ∧ #IMM → CCR
Logically ANDs the condition code register with immediate data
ORC
B
CCR ∨ #IMM → CCR
Logically ORs the condition code register with immediate data
XORC
B
CCR ⊕ #IMM → CCR
Logically exclusive-ORs the condition code register with immediate
data
NOP
—
PC + 2 → PC
Only increments the program counter
Notes: *
Size: Operand size
B:
Byte
37
15
8
7
0
op
15
8
RTE, SLEEP, NOP
7
0
op
15
rn
8
7
LDC, STC (Rn)
0
op
IMM
ANDC, ORC,
XORC, LDC (#xx:8)
Notation:
op: Operation field
rn: Register field
IMM: Immediate data
Figure 2.9 System Control Instruction Codes
2.5.8
Block Data Transfer Instruction
Table 2.11 describes the block data transfer instruction. Figure 2.10 shows its object code format.
Table 2.11 Block Data Transfer Instruction
Instruction
Size
Function
EEPMOV
—
If R4L ≠ 0 then
repeat
until
@R5+ → @R6+
R4L – 1 → R4L
R4L = 0
else next;
Block transfer instruction. Transfers the number of data bytes
specified by R4L from locations starting at the address indicated by
R5 to locations starting at the address indicated by R6. After the
transfer, the next instruction is executed.
Certain precautions are required in using the EEPMOV instruction. See 2.9.3, Notes on Use of the
EEPMOV Instruction, for details.
38
15
8
7
0
op
op
Notation:
op: Operation field
Figure 2.10 Block Data Transfer Instruction Code
39
2.6
Basic Operational Timing
CPU operation is synchronized by a system clock (ø) or a subclock (øSUB). For details on these
clock signals see section 4, Clock Pulse Generators. The period from a rising edge of ø or øSUB to
the next rising edge is called one state. A bus cycle consists of two states or three states. The
cycle differs depending on whether access is to on-chip memory or to on-chip peripheral modules.
2.6.1
Access to On-Chip Memory (RAM, ROM)
Access to on-chip memory takes place in two states. The data bus width is 16 bits, allowing
access in byte or word size. Figure 2.11 shows the on-chip memory access cycle.
Bus cycle
T1 state
T2 state
ø or ø SUB
Internal address bus
Address
Internal read signal
Internal data bus
(read access)
Read data
Internal write signal
Internal data bus
(write access)
Write data
Figure 2.11 On-Chip Memory Access Cycle
40
2.6.2
Access to On-Chip Peripheral Modules
On-chip peripheral modules are accessed in two states or three states. The data bus width is 8 bits,
so access is by byte size only. This means that for accessing word data, two instructions must be
used. Figures 2.12 and 2.13 show the on-chip peripheral module access cycle.
Two-state access to on-chip peripheral modules
Bus cycle
T1 state
T2 state
ø or ø SUB
Internal address bus
Address
Internal read signal
Internal data bus
(read access)
Read data
Internal write signal
Internal data bus
(write access)
Write data
Figure 2.12 On-Chip Peripheral Module Access Cycle (2-State Access)
41
Three-state access to on-chip peripheral modules
Bus cycle
T1 state
T2 state
T3 state
ø or ø SUB
Internal
address bus
Address
Internal
read signal
Internal
data bus
(read access)
Read data
Internal
write signal
Internal
data bus
(write access)
Write data
Figure 2.13 On-Chip Peripheral Module Access Cycle (3-State Access)
42
2.7
CPU States
2.7.1
Overview
There are four CPU states: the reset state, program execution state, program halt state, and
exception-handling state. The program execution state includes active (high-speed or mediumspeed) mode and subactive mode. In the program halt state there are a sleep (high-speed or
medium-speed) mode, standby mode, watch mode, and sub-sleep mode. These states are shown in
figure 2.14. Figure 2.15 shows the state transitions.
CPU state
Reset state
The CPU is initialized
Program
execution state
Active
(high speed) mode
The CPU executes successive program
instructions at high speed,
synchronized by the system clock
Active
(medium speed) mode
The CPU executes successive
program instructions at
reduced speed, synchronized
by the system clock
Subactive mode
The CPU executes
successive program
instructions at reduced
speed, synchronized
by the subclock
Program halt state
A state in which some
or all of the chip
functions are stopped
to conserve power
Low-power
modes
Sleep (high-speed)
mode
Sleep (medium-speed)
mode
Standby mode
Watch mode
Subsleep mode
Exceptionhandling state
A transient state in which the CPU changes
the processing flow due to a reset or an interrupt
Note: See section 5, Power-Down Modes, for details on the modes and their transitions.
Figure 2.14 CPU Operation States
43
Reset cleared
Reset state
Exception-handling state
Reset occurs
Reset
occurs
Reset
occurs
Interrupt
source
occurs
Program halt state
Interrupt
source
occurs
Exceptionhandling
complete
Program execution state
SLEEP instruction executed
Figure 2.15 State Transitions
2.7.2
Program Execution State
In the program execution state the CPU executes program instructions in sequence.
There are three modes in this state, two active modes (high speed and medium speed) and one
subactive mode. Operation is synchronized with the system clock in active mode (high speed and
medium speed), and with the subclock in subactive mode. See section 5, Power-Down Modes for
details on these modes.
2.7.3
Program Halt State
In the program halt state there are five modes: two sleep modes (high speed and medium speed),
standby mode, watch mode, and subsleep mode. See section 5, Power-Down Modes for details on
these modes.
2.7.4
Exception-Handling State
The exception-handling state is a transient state occurring when exception handling is started by a
reset or interrupt and the CPU changes its normal processing flow. In exception handling caused
by an interrupt, SP (R7) is referenced and the PC and CCR values are saved on the stack.
For details on interrupt handling, see section 3.3, Interrupts.
44
2.8
Memory Map
2.8.1
Memory Map
The memory map of the H8/3802 is shown in figure 2.16 (1), that of the H8/3801 in figure 2.16
(2), and that of the H8/3800 in figure 2.16 (3).
H'0000
Interrupt vector area
H'0029
H'002A
16 kbytes
On-chip ROM
(16384 bytes)
H'3FFF
Not used
H'F740
LCD RAM
(13 bytes)
H'F74C
Not used
H'FB80
On-chip RAM
1024 bytes
H'FF7F
H'FF80
Internal I/O registers
(128 bytes)
H'FFFF
Figure 2.16 (1) H8/3802 Memory Map
45
H'0000
Interrupt vector area
H'0029
H'002A
12 kbytes
On-chip ROM
(12288 bytes)
H'2FFF
Not used
H'F740
LCD RAM
(13 bytes)
H'F74C
Not used
H'FD80
On-chip RAM
512 bytes
H'FF7F
H'FF80
Internal I/O registers
(128 bytes)
H'FFFF
Figure 2.16 (2) H8/3801 Memory Map
46
H'0000
Interrupt vector area
H'0029
H'002A
8 kbytes
On-chip ROM
(8192 bytes)
H'1FFF
Not used
H'F740
LCD RAM
(13 bytes)
H'F74C
Not used
H'FD80
On-chip RAM
512 bytes
H'FF7F
H'FF80
Internal I/O registers
(128 bytes)
H'FFFF
Figure 2.16 (3) H8/3800 Memory Map
47
2.9
Application Notes
2.9.1
Notes on Data Access
1. Access to Empty Areas:
The address space of the H8/300L CPU includes empty areas in addition to the RAM,
registers, and ROM areas available to the user. If these empty areas are mistakenly accessed
by an application program, the following results will occur.
Data transfer from CPU to empty area:
The transferred data will be lost. This action may also cause the CPU to misoperate.
Data transfer from empty area to CPU:
Unpredictable data is transferred.
2. Access to Internal I/O Registers:
Internal data transfer to or from on-chip modules other than the ROM and RAM areas makes
use of an 8-bit data width. If word access is attempted to these areas, the following results will
occur.
Word access from CPU to I/O register area:
Upper byte: Will be written to I/O register.
Lower byte: Transferred data will be lost.
Word access from I/O register to CPU:
Upper byte: Will be written to upper part of CPU register.
Lower byte: Unpredictable data will be written to lower part of CPU register.
Byte size instructions should therefore be used when transferring data to or from I/O registers
other than the on-chip ROM and RAM areas. Figure 2.17 shows the data size and number of
states in which on-chip peripheral modules can be accessed.
48
Access
States
Word
Byte
H'0000
Interrupt vector area
(42 bytes)
H'0029
H'002A
2
16 kbytes
On-chip ROM
*1
H'3FFF
Not used
—
—
—
H'F740
LCD RAM
(13 bytes)
2
H'F74C
—
Not used
—
—
H'FB80
On-chip RAM
2
1024 bytes
H'FF7F*2
H'FF80
Internal I/O registers
(128 bytes)
H'FF98 to H'FF9F
H'FFA8 to H'FFAF
H'FFFF
×
2
×
3
×
2
×
3
×
2
Notes: The example of the H8/3802 is shown here.
1. This address is H'3FFF in the H8/3802 (16-kbyte on-chip ROM), H'2FFF in the H8/3801
(12-kbyte on-chip ROM), H'1FFF in the H8/3800 (8-kbyte on-chip ROM).
2. This address is H'FD80 to H'FF7F in the H8/3801 and H8/3800 (512 bytes of on-chip RAM).
Figure 2.17 Data Size and Number of States for Access to and from
On-Chip Peripheral Modules
49
2.9.2
Notes on Bit Manipulation
The BSET, BCLR, BNOT, BST, and BIST instructions read one byte of data, modify the data,
then write the data byte again. Special care is required when using these instructions in cases
where two registers are assigned to the same address, in the case of registers that include writeonly bits, and when the instruction accesses an I/O port.
Order of Operation
Operation
1
Read
Read byte data at the designated address
2
Modify
Modify a designated bit in the read data
3
Write
Write the altered byte data to the designated address
1. Bit manipulation in two registers assigned to the same address
Example 1: timer load register and timer counter
Figure 2.18 shows an example in which two timer registers share the same address. When a bit
manipulation instruction accesses the timer load register and timer counter of a reloadable timer,
since these two registers share the same address, the following operations take place.
Order of Operation
Operation
1
Read
Timer counter data is read (one byte)
2
Modify
The CPU modifies (sets or resets) the bit designated in the instruction
3
Write
The altered byte data is written to the timer load register
The timer counter is counting, so the value read is not necessarily the same as the value in the
timer load register. As a result, bits other than the intended bit in the timer load register may be
modified to the timer counter value.
Read
Count clock
Timer counter
Reload
Write
Timer load register
Internal bus
Figure 2.18 Timer Configuration Example
50
Example 2: BSET instruction executed designating port 3
P3 7 and P36 are designated as input pins, with a low-level signal input at P37 and a high-level
signal at P3 6. The remaining pins, P35 to P31, are output pins and output low-level signals. In this
example, the BSET instruction is used to change pin P31 to high-level output.
[A: Prior to executing BSET]
P37
Input/output Input
P36
P35
P34
P33
P32
P31
—
Input
Output
Output
Output
Output
Output
—
Pin state
Low level High level Low level Low level Low level Low level Low level —
PCR3
0
0
1
1
1
1
1
1
PDR3
1
0
0
0
0
0
0
1
[B: BSET instruction executed]
BSET
#1
,
The BSET instruction is executed designating port 3.
@PDR3
[C: After executing BSET]
P37
Input/output Input
P36
P35
P34
P33
P32
P31
—
Input
Output
Output
Output
Output
Output
—
Pin state
Low level High level Low level Low level Low level Low level High level —
PCR3
0
0
1
1
1
1
1
1
PDR3
0
1
0
0
0
0
1
1
[D: Explanation of how BSET operates]
When the BSET instruction is executed, first the CPU reads port 3.
Since P37 and P36 are input pins, the CPU reads the pin states (low-level and high-level input).
P3 5 to P31 are output pins, so the CPU reads the value in PDR3. In this example PDR3 has a
value of H'81, but the value read by the CPU is H'41.
Next, the CPU sets bit 1 of the read data to 1, changing the PDR3 data to H'43. Finally, the CPU
writes this value (H'43) to PDR3, completing execution of BSET.
As a result of this operation, bit 1 in PDR3 becomes 1, and P3 1 outputs a high-level signal.
However, bits 7 and 6 of PDR3 end up with different values.
To avoid this problem, store a copy of the PDR3 data in a work area in memory. Perform the bit
manipulation on the data in the work area, then write this data to PDR3.
51
[A: Prior to executing BSET]
MOV. B
MOV. B
MOV. B
#81,
R0L,
R0L,
P37
Input/output Input
The PDR3 value (H'81) is written to a work area in memory
(RAM0) as well as to PDR3
R0L
@RAM0
@PDR3
P36
P35
P34
P33
P32
P31
—
Input
Output
Output
Output
Output
Output
—
Pin state
Low level High level Low level Low level Low level Low level Low level —
PCR3
0
0
1
1
1
1
1
1
PDR3
1
0
0
0
0
0
0
1
RAM0
1
0
0
0
0
0
0
1
[B: BSET instruction executed]
BSET
#1
,
The BSET instruction is executed designating the PDR3
work area (RAM0).
@RAM0
[C: After executing BSET]
MOV. B
MOV. B
The work area (RAM0) value is written to PDR3.
@RAM0, R0L
R0L, @PDR3
P37
Input/output Input
P36
P35
P34
P33
P32
P31
—
Input
Output
Output
Output
Output
Output
—
Pin state
Low level High level Low level Low level Low level Low level High level —
PCR3
0
0
1
1
1
1
1
1
PDR3
1
0
0
0
0
0
1
1
RAM0
1
0
0
0
0
0
1
1
52
2. Bit manipulation in a register containing a write-only bit
Example 3: BCLR instruction executed designating port 3 control register PCR3
As in the examples above, P37 and P36 are input pins, with a low-level signal input at P37 and a
high-level signal at P36. The remaining pins, P35 to P31, are output pins that output low-level
signals. In this example, the BCLR instruction is used to change pin P31 to an input port. It is
assumed that a high-level signal will be input to this input pin.
[A: Prior to executing BCLR]
P37
Input/output Input
P36
P35
P34
P33
P32
P31
—
Input
Output
Output
Output
Output
Output
—
Pin state
Low level High level Low level Low level Low level Low level Low level —
PCR3
0
0
1
1
1
1
1
1
PDR3
1
0
0
0
0
0
0
1
[B: BCLR instruction executed]
BCLR
#1
,
The BCLR instruction is executed designating PCR3.
@PCR3
[C: After executing BCLR]
P37
Input/output Output
P36
P35
P34
P33
P32
P31
—
Output
Output
Output
Output
Output
Input
—
Pin state
Low level High level Low level Low level Low level Low level High level —
PCR3
1
1
1
1
1
1
0
1
PDR3
1
0
0
0
0
0
0
1
[D: Explanation of how BCLR operates]
When the BCLR instruction is executed, first the CPU reads PCR3. Since PCR3 is a write-only
register, the CPU reads a value of H'FF, even though the PCR3 value is actually H'3F.
Next, the CPU clears bit 1 in the read data to 0, changing the data to H'FD. Finally, this value
(H'FD) is written to PCR3 and BCLR instruction execution ends.
As a result of this operation, bit 1 in PCR3 becomes 0, making P3 1 an input port. However, bits 7
and 6 in PCR3 change to 1, so that P3 7 and P36 change from input pins to output pins.
To avoid this problem, store a copy of the PCR3 data in a work area in memory. Perform the bit
manipulation on the data in the work area, then write this data to PCR3.
53
[A: Prior to executing BCLR]
MOV. B
MOV. B
MOV. B
#3F,
R0L,
R0L,
P37
Input/output Input
The PCR3 value (H'3F) is written to a work area in memory
(RAM0) as well as to PCR3.
R0L
@RAM0
@PCR3
P36
P35
P34
P33
P32
P31
—
Input
Output
Output
Output
Output
Output
—
Pin state
Low level High level Low level Low level Low level Low level Low level —
PCR3
0
0
1
1
1
1
1
1
PDR3
1
0
0
0
0
0
0
1
RAM0
0
0
1
1
1
1
1
1
[B: BCLR instruction executed]
BCLR
#1
,
The BCLR instruction is executed designating the PCR3
work area (RAM0).
@RAM0
[C: After executing BCLR]
MOV. B
MOV. B
The work area (RAM0) value is written to PCR3.
@RAM0, R0L
R0L, @PCR3
P37
Input/output Input
P36
P35
P34
P33
P32
P31
—
Input
Output
Output
Output
Output
Output
—
Pin state
Low level High level Low level Low level Low level Low level High level —
PCR3
0
0
1
1
1
1
0
1
PDR3
1
0
0
0
0
0
0
1
RAM0
0
0
1
1
1
1
0
1
54
Table 2.12 lists the pairs of registers that share identical addresses. Table 2.13 lists the registers
that contain write-only bits.
Table 2.12 Registers with Shared Addresses
Register Name
Abbreviation
Address
Port data register 3*
PDR3
H'FFD6
Port data register 4*
PDR4
H'FFD7
Port data register 5*
PDR5
H'FFD8
Port data register 6*
PDR6
H'FFD9
Port data register 7*
PDR7
H'FFDA
Port data register 8*
PDR8
H'FFDB
Port data register A*
PDRA
H'FFDD
Note: * Port data registers have the same addresses as input pins.
Table 2.13 Registers with Write-Only Bits
Register Name
Abbreviation
Address
Port control register 3
PCR3
H'FFE6
Port control register 4
PCR4
H'FFE7
Port control register 5
PCR5
H'FFE8
Port control register 6
PCR6
H'FFE9
Port control register 7
PCR7
H'FFEA
Port control register 8
PCR8
H'FFEB
Port control register A
PCRA
H'FFED
Timer control register F
TCRF
H'FFB6
PWM1 control register
PWCR1
H'FFD0
PWM1 data register U
PWDRU1
H'FFD1
PWM1 data register L
PWDRL1
H'FFD2
PWM2 control register
PWCR2
H'FFCD
PWM2 data register U
PWDRU2
H'FFCE
PWM2 data register L
PWDRL2
H'FFCF
55
2.9.3
Notes on Use of the EEPMOV Instruction
• The EEPMOV instruction is a block data transfer instruction. It moves the number of bytes
specified by R4L from the address specified by R5 to the address specified by R6.
R5 →
← R6
R5 + R4L →
← R6 + R4L
• When setting R4L and R6, make sure that the final destination address (R6 + R4L) does not
exceed H'FFFF. The value in R6 must not change from H'FFFF to H'0000 during execution of
the instruction.
R5 →
R5 + R4L →
56
← R6
H'FFFF
Not allowed
← R6 + R4L
Section 3 Exception Handling
3.1
Overview
Exception handling is performed in the H8/3802 Series when a reset or interrupt occurs. Table 3.1
shows the priorities of these two types of exception handling.
Table 3.1
Exception Handling Types and Priorities
Priority
Exception Source
Time of Start of Exception Handling
High
Reset
Exception handling starts as soon as the reset state is cleared
Interrupt
When an interrupt is requested, exception handling starts after
execution of the present instruction or the exception handling in
progress is completed
Low
3.2
Reset
3.2.1
Overview
A reset is the highest-priority exception. The internal state of the CPU and the registers of the onchip peripheral modules are initialized.
3.2.2
Reset Sequence
As soon as the RES pin goes low, all processing is stopped and the chip enters the reset state.
To make sure the chip is reset properly, observe the following precautions.
• At power on: Hold the RES pin low until the clock pulse generator output stabilizes.
• Resetting during operation: Hold the RES pin low for at least 10 system clock cycles.
Reset exception handling takes place as follows.
• The CPU internal state and the registers of on-chip peripheral modules are initialized, with the
I bit of the condition code register (CCR) set to 1.
• The PC is loaded from the reset exception handling vector address (H'0000 to H'0001), after
which the program starts executing from the address indicated in PC.
57
When system power is turned on or off, the RES pin should be held low.
Figure 3.1 shows the reset sequence starting from RES input.
Reset cleared
Program initial
instruction prefetch
Vector fetch Internal
processing
RES
ø
Internal
address bus
(1)
(2)
Internal read
signal
Internal write
signal
Internal data
bus (16-bit)
(2)
(1) Reset exception handling vector address (H'0000)
(2) Program start address
(3) First instruction of program
Figure 3.1 Reset Sequence
58
(3)
3.2.3
Interrupt Immediately after Reset
After a reset, if an interrupt were to be accepted before the stack pointer (SP: R7) was initialized,
PC and CCR would not be pushed onto the stack correctly, resulting in program runaway. To
prevent this, immediately after reset exception handling all interrupts are masked. For this reason,
the initial program instruction is always executed immediately after a reset. This instruction
should initialize the stack pointer (e.g. MOV.W #xx: 16, SP).
3.3
Interrupts
3.3.1
Overview
The interrupt sources include 11 external interrupts (WKP7 to WKP0, IRQ1 to IRQ0, IRQAEC)
and 7 internal interrupts from on-chip peripheral modules. Table 3.2 shows the interrupt sources,
their priorities, and their vector addresses. When more than one interrupt is requested, the interrupt
with the highest priority is processed.
The interrupts have the following features:
• Internal and external interrupts can be masked by the I bit in CCR. When the I bit is set to 1,
interrupt request flags can be set but the interrupts are not accepted.
• IRQAEC, IRQ1 to IRQ0, and WKP7 to WKP0 can be set to either rising edge sensing or falling
edge sensing.
59
Table 3.2
Interrupt Sources and Their Priorities
Interrupt Source
Interrupt
Vector Number
Vector Address
Priority
RES
Reset
0
H'0000 to H'0001
High
IRQ0
IRQ0
4
H'0008 to H'0009
IRQ1
IRQ1
5
H'000A to H'000B
IRQAEC
IRQAEC
6
H'000C to H'000D
WKP 0
WKP 1
WKP 2
WKP 3
WKP 4
WKP 5
WKP 6
WKP 7
WKP 0
WKP 1
WKP 2
WKP 3
WKP 4
WKP 5
WKP 6
WKP 7
9
H'0012 to H'0013
Timer A
Timer A overflow
11
H'0016 to H'0017
Asynchronous
event counter
Asynchronous event
counter overflow
12
H'0018 to H'0019
Timer FL
Timer FL compare match
Timer FL overflow
14
H'001C to H'001D
Timer FH
Timer FH compare match
Timer FH overflow
15
H'001E to H'001F
SCI3
SCI3 transmit end
SCI3 transmit data empty
SCI3 receive data full
SCI3 overrun error
SCI3 framing error
SCI3 parity error
18
H'0024 to H'0025
A/D
A/D conversion end
19
H'0026 to H'0027
(SLEEP instruction
executed)
Direct transfer
20
H'0028 to H'0029
Low
Note: Vector addresses H'0002 to H'0007, H'000E to H'0011, H'0014 to H'0015, H'001A to
H'001B, and H'0020 to H'0023 are reserved and cannot be used.
60
3.3.2
Interrupt Control Registers
Table 3.3 lists the registers that control interrupts.
Table 3.3
Interrupt Control Registers
Name
Abbreviation
R/W
Initial Value
Address
IRQ edge select register
IEGR
R/W
—
H'FFF2
Interrupt enable register 1
IENR1
R/W
—
H'FFF3
Interrupt enable register 2
IENR2
R/W
—
H'FFF4
Interrupt request register 1
IRR1
R/W*
—
H'FFF6
Interrupt request register 2
IRR2
R/W*
—
H'FFF7
Wakeup interrupt request register
IWPR
R/W*
H'00
H'FFF9
Wakeup edge select register
WEGR
R/W
H'00
H'FF90
Note: * Write is enabled only for writing of 0 to clear a flag.
1. IRQ edge select register (IEGR)
Bit
7
6
5
4
3
2
1
0
—
—
—
—
—
—
IEG1
IEG0
Initial value
1
1
1
—
—
—
0
0
Read/Write
—
—
—
W
W
W
R/W
R/W
IEGR is an 8-bit read/write register used to designate whether pins IRQ1 and IRQ0 are set to rising
edge sensing or falling edge sensing.
Bits 7 to 5: Reserved bits
Bits 7 to 5 are reserved; they are always read as 1 and cannot be modified.
Bits 4 to 2: Reserved bits
Bits 4 to 2 are reserved; only 0 can be written to these bits.
61
Bit 1: IRQ1 edge select (IEG1)
Bit 1 selects the input sensing of the IRQ1 pin.
Bit 1
IEG1
Description
0
Falling edge of IRQ1 pin input is detected
1
Rising edge of IRQ1 pin input is detected
(initial value)
Bit 0: IRQ0 edge select (IEG0)
Bit 0 selects the input sensing of pin IRQ0.
Bit 0
IEG0
Description
0
Falling edge of IRQ0 pin input is detected
1
Rising edge of IRQ0 pin input is detected
(initial value)
2. Interrupt enable register 1 (IENR1)
Bit
7
6
5
4
3
2
1
0
IENTA
—
IENWP
—
—
IENEC2
IEN1
IEN0
Initial value
0
—
0
—
—
0
0
0
Read/Write
R/W
W
R/W
W
W
R/W
R/W
R/W
IENR1 is an 8-bit read/write register that enables or disables interrupt requests.
Bit 7: Timer A interrupt enable (IENTA)
Bit 7 enables or disables timer A overflow interrupt requests.
Bit 7
IENTA
Description
0
Disables timer A interrupt requests
1
Enables timer A interrupt requests
Bit 6: Reserved bit
Bit 6 is reserved; only 0 can be written to this bit.
62
(initial value)
Bit 5: Wakeup interrupt enable (IENWP)
Bit 5 enables or disables WKP7 to WKP0 interrupt requests.
Bit 5
IENWP
Description
0
Disables WKP 7 to WKP 0 interrupt requests
1
Enables WKP 7 to WKP 0 interrupt requests
(initial value)
Bits 4 and 3: Reserved bits
Bits 4 and 3 are reserved; only 0 can be written to these bits.
Bit 2: IRQAEC interrupt enable (IENEC2)
Bit 2 enables or disables IRQAEC interrupt requests.
Bit 2
IENEC2
Description
0
Disables IRQAEC interrupt requests
1
Enables IRQAEC interrupt requests
(initial value)
Bits 1 and 0: IRQ1 and IRQ 0 interrupt enable (IEN1 and IEN0)
Bits 1 and 0 enable or disable IRQ1 and IRQ0 interrupt requests.
Bit n
IENn
Description
0
Disables interrupt requests from pin IRQn
1
Enables interrupt requests from pin IRQn
(initial value)
(n = 1 or 0)
3. Interrupt enable register 2 (IENR2)
Bit
7
6
5
4
3
2
1
0
IENDT
IENAD
—
—
—
IENEC
Initial value
0
0
—
—
0
0
—
0
Read/Write
R/W
R/W
W
W
R/W
R/W
W
R/W
IENTFH IENTFL
IENR2 is an 8-bit read/write register that enables or disables interrupt requests.
63
Bit 7: Direct transfer interrupt enable (IENDT)
Bit 7 enables or disables direct transfer interrupt requests.
Bit 7
IENDT
Description
0
Disables direct transfer interrupt requests
1
Enables direct transfer interrupt requests
(initial value)
Bit 6: A/D converter interrupt enable (IENAD)
Bit 6 enables or disables A/D converter interrupt requests.
Bit 6
IENAD
Description
0
Disables A/D converter interrupt requests
1
Enables A/D converter interrupt requests
(initial value)
Bits 5 and 4: Reserved bits
Bits 5 and 4 are reserved; only 0 can be written to these bits.
Bit 3: Timer FH interrupt enable (IENTFH)
Bit 3 enables or disables timer FH compare match and overflow interrupt requests.
Bit 3
IENTFH
Description
0
Disables timer FH interrupt requests
1
Enables timer FH interrupt requests
(initial value)
Bit 2: Timer FL interrupt enable (IENTFL)
Bit 2 enables or disables timer FL compare match and overflow interrupt requests.
Bit 2
IENTFL
Description
0
Disables timer FL interrupt requests
1
Enables timer FL interrupt requests
64
(initial value)
Bit 1: Reserved bit
Bit 1 is reserved; only 0 can be written to this bit.
Bit 0: Asynchronous event counter interrupt enable (IENEC)
Bit 0 enables or disables asynchronous event counter interrupt requests.
Bit 0
IENEC
Description
0
Disables asynchronous event counter interrupt requests
1
Enables asynchronous event counter interrupt requests
(initial value)
For details of SCI3 interrupt control, see 10.2.6. Serial control register 3 (SCR3).
4. Interrupt request register 1 (IRR1)
Bit
7
6
5
4
3
2
1
0
IRRTA
—
—
—
—
IRREC2
IRRI1
IRRI0
0
—
1
—
—
0
0
0
W
—
W
W
R/W *
Initial value
R/W *
Read/Write
R/W *
R/W *
Note: * Only a write of 0 for flag clearing is possible
IRR1 is an 8-bit read/write register, in which a corresponding flag is set to 1 when a timer A,
IRQAEC or IRQ1, IRQ0 interrupt is requested. The flags are not cleared automatically when an
interrupt is accepted. It is necessary to write 0 to clear each flag.
Bit 7: Timer A interrupt request flag (IRRTA)
Bit 7
IRRTA
Description
0
Clearing conditions:
When IRRTA = 1, it is cleared by writing 0
1
Setting conditions:
When the timer A counter value overflows from H'FF to H'00
(initial value)
Bits 6, 4, and 3: Reserved bits
Bits 6, 4, and 3 are reserved; only 0 can be written to these bits.
Bit 5: Reserved bit
Bit 5 is reserved; it is always read as 1 and cannot be modified.
65
Bit 2: IRQAEC interrupt request flag (IRREC2)
Bit 2
IRREC2
Description
0
Clearing conditions:
When IRREC2 = 1, it is cleared by writing 0
(initial value)
1
Setting conditions:
When pin IRQAEC is designated for interrupt input and the designated signal edge is
input
Bits 1 and 0: IRQ1 and IRQ 0 interrupt request flags (IRRI1 and IRRI0)
Bit n
IRRIn
Description
0
Clearing conditions:
When IRRIn = 1, it is cleared by writing 0
(initial value)
1
Setting conditions:
When pin IRQn is designated for interrupt input and the designated signal edge is
input
(n = 1 or 0)
66
5. Interrupt request register 2 (IRR2)
Bit
Initial value
Read/Write
7
6
5
4
IRRDT
IRRAD
—
—
0
0
—
—
R/W *
R/W *
W
W
3
2
IRRTFH IRRTFL
0
R/W *
0
R/W *
1
0
—
IRREC
—
0
W
R/W *
Note: * Only a write of 0 for flag clearing is possible
IRR2 is an 8-bit read/write register, in which a corresponding flag is set to 1 when a direct
transfer, A/D converter, Timer FH, or Timer FL asynchronous event counter interrupt is requested.
The flags are not cleared automatically when an interrupt is accepted. It is necessary to write 0 to
clear each flag.
Bit 7: Direct transfer interrupt request flag (IRRDT)
Bit 7
IRRDT
Description
0
Clearing conditions:
When IRRDT = 1, it is cleared by writing 0
(initial value)
1
Setting conditions:
When a direct transfer is made by executing a SLEEP instruction while DTON = 1 in
SYSCR2
Bit 6: A/D converter interrupt request flag (IRRAD)
Bit 6
IRRAD
Description
0
Clearing conditions:
When IRRAD = 1, it is cleared by writing 0
1
Setting conditions:
When A/D conversion is completed and ADSF is cleared to 0 in ADSR
(initial value)
Bits 5 and 4: Reserved bits
Bits 5 and 4 are reserved; only 0 can be written to these bits.
67
Bit 3: Timer FH interrupt request flag (IRRTFH)
Bit 3
IRRTFH
Description
0
Clearing conditions:
When IRRTFH = 1, it is cleared by writing 0
(initial value)
1
Setting conditions:
When TCFH and OCRFH match in 8-bit timer mode, or when TCF (TCFL, TCFH)
and OCRF (OCRFL, OCRFH) match in 16-bit timer mode
Bit 2: Timer FL interrupt request flag (IRRTFL)
Bit 2
IRRTFL
Description
0
Clearing conditions:
When IRRTFL= 1, it is cleared by writing 0
1
Setting conditions:
When TCFL and OCRFL match in 8-bit timer mode
(initial value)
Bit 1: Reserved bit
Bit 1 is reserved; only 0 can be written to this bit.
Bit 0: Asynchronous event counter interrupt request flag (IRREC)
Bit 0
IRREC
Description
0
Clearing conditions:
When IRREC = 1, it is cleared by writing 0
1
Setting conditions:
When ECH overflows in 16-bit counter mode, or ECH or ECL overflows in 8-bit
counter mode
68
(initial value)
6. Wakeup Interrupt Request Register (IWPR)
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
IWPF7
IWPF6
IWPF5
IWPF4
IWPF3
IWPF2
IWPF1
IWPF0
0
0
0
0
0
0
0
0
R/W *
R/W *
R/W *
R/W *
R/W *
R/W *
R/W *
R/W *
Note: * Only a write of 0 for flag clearing is possible
IWPR is an 8-bit read/write register containing wakeup interrupt request flags. When one of pins
WKP7 to WKP0 is designated for wakeup input and a rising or falling edge is input at that pin, the
corresponding flag in IWPR is set to 1. A flag is not cleared automatically when the
corresponding interrupt is accepted. Flags must be cleared by writing 0.
Bits 7 to 0: Wakeup interrupt request flags (IWPF7 to IWPF0)
Bit n
IWPFn
Description
0
Clearing conditions:
When IWPFn= 1, it is cleared by writing 0
(initial value)
1
Setting conditions:
When pin WKP n is designated for wakeup input and a rising or falling edge is input at
that pin
(n = 7 to 0)
69
7. Wakeup Edge Select Register (WEGR)
Bit
7
6
5
4
3
2
1
0
WKEGS7 WKEGS6 WKEGS5 WKEGS4 WKEGS3 WKEGS2 WKEGS1 WKEGS0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
WEGR is an 8-bit read/write register that specifies rising or falling edge sensing for pins WKPn.
WEGR is initialized to H'00 by a reset.
Bit n: WKPn edge select (WKEGSn)
Bit n selects WKPn pin input sensing.
Bit n
WKEGSn
Description
0
WKPn pin falling edge detected
1
WKPn pin rising edge detected
(initial value)
(n = 7 to 0)
3.3.3
External Interrupts
There are 11 external interrupts: WKP 7 to WKP0, IRQ1 to IRQ0, and IRQAEC.
1. Interrupts WKP 7 to WKP0
Interrupts WKP 7 to WKP0 are requested by either rising or falling edge input to pins WKP7 to
WKP0. When these pins are designated as pins WKP7 to WKP0 in port mode register 5 and a
rising or falling edge is input, the corresponding bit in IWPR is set to 1, requesting an interrupt.
Recognition of wakeup interrupt requests can be disabled by clearing the IENWP bit to 0 in
IENR1. These interrupts can all be masked by setting the I bit to 1 in CCR.
When WKP 7 to WKP0 interrupt exception handling is initiated, the I bit is set to 1 in CCR. Vector
number 9 is assigned to interrupts WKP7 to WKP0. All eight interrupt sources have the same
vector number, so the interrupt-handling routine must discriminate the interrupt source.
70
2. Interrupts IRQ 1 and IRQ 0
Interrupts IRQ 1 and IRQ 0 are requested by input signals to pins IRQ1 and IRQ0. These interrupts
are detected by either rising edge sensing or falling edge sensing, depending on the settings of bits
IEG1 and IEG0 in IEGR.
When these pins are designated as pins IRQ1 and IRQ0 in port mode register B and 2 and the
designated edge is input, the corresponding bit in IRR1 is set to 1, requesting an interrupt.
Recognition of these interrupt requests can be disabled individually by clearing bits IEN1 and
IEN0 to 0 in IENR1. These interrupts can all be masked by setting the I bit to 1 in CCR.
When IRQ 1 and IRQ 0 interrupt exception handling is initiated, the I bit is set to 1 in CCR. Vector
numbers 5 and 4 are assigned to interrupts IRQ1 and IRQ 0. The order of priority is from IRQ0
(high) to IRQ1 (low). Table 3.2 gives details.
3. IRQAEC Interrupt
The IRQAEC interrupt is requested by an input signal to pin IRQAEC. This interrupt is detected
by rising edge, falling edge, or both edge sensing, depending on the settings of bits AIAGS1 and
AIAGS0 in AEGSR.
When bit IENEC2 in IENR1 is 1 and the designated edge is input, the corresponding bit in IRR1 is
set to 1, requesting an interrupt.
When IRQAEC interrupt exception handling is initiated, the I bit is set to 1 in CCR. Vector
number 6 is assigned to the IRQAEC interrupt. Table 3.2 gives details.
3.3.4
Internal Interrupts
There are 7 internal interrupts that can be requested by the on-chip peripheral modules. When a
peripheral module requests an interrupt, the corresponding bit in IRR1 or IRR2 is set to 1.
Recognition of individual interrupt requests can be disabled by clearing the corresponding bit in
IENR1 or IENR2. All these interrupts can be masked by setting the I bit to 1 in CCR. When
internal interrupt handling is initiated, the I bit is set to 1 in CCR. Vector numbers from 20 to 18,
15, 14, 12, and 11 are assigned to these interrupts. Table 3.2 shows the order of priority of
interrupts from on-chip peripheral modules.
71
3.3.5
Interrupt Operations
Interrupts are controlled by an interrupt controller. Figure 3.2 shows a block diagram of the
interrupt controller. Figure 3.3 shows the flow up to interrupt acceptance.
Priority decision logic
Interrupt controller
External or
internal
interrupts
Interrupt
request
External
interrupts or
internal
interrupt
enable
signals
I
CCR (CPU)
Figure 3.2 Block Diagram of Interrupt Controller
Interrupt operation is described as follows.
• When an interrupt condition is met while the interrupt enable register bit is set to 1, an
interrupt request signal is sent to the interrupt controller.
• When the interrupt controller receives an interrupt request, it sets the interrupt request flag.
• From among the interrupts with interrupt request flags set to 1, the interrupt controller selects
the interrupt request with the highest priority and holds the others pending. (Refer to table 3.2
for a list of interrupt priorities.)
• The interrupt controller checks the I bit of CCR. If the I bit is 0, the selected interrupt request
is accepted; if the I bit is 1, the interrupt request is held pending.
72
• If the interrupt is accepted, after processing of the current instruction is completed, both PC
and CCR are pushed onto the stack. The state of the stack at this time is shown in figure 3.4.
The PC value pushed onto the stack is the address of the first instruction to be executed upon
return from interrupt handling.
• The I bit of CCR is set to 1, masking further interrupts.
• The vector address corresponding to the accepted interrupt is generated, and the interrupt
handling routine located at the address indicated by the contents of the vector address is
executed.
Notes:
1. When disabling interrupts by clearing bits in an interrupt enable register, or when clearing bits
in an interrupt request register, always do so while interrupts are masked (I = 1).
2. If the above clear operations are performed while I = 0, and as a result a conflict arises between
the clear instruction and an interrupt request, exception processing for the interrupt will be
executed after the clear instruction has been executed.
73
Program execution state
No
IRRI0 = 1
Yes
No
IEN0 = 1
Yes
IRRI1 = 1
No
Yes
IEN1 = 1
Yes
No
IRREC2 = 1
No
Yes
IENEC2 = 1
No
Yes
IRRDT = 1
No
Yes
IENDT = 1
Yes
No
I=0
Yes
PC contents saved
CCR contents saved
I←1
Branch to interrupt
handling routine
Notation:
PC: Program counter
CCR: Condition code register
I:
I bit of CCR
Figure 3.3 Flow up to Interrupt Acceptance
74
No
SP – 4
SP (R7)
CCR
SP – 3
SP + 1
CCR *
SP – 2
SP + 2
PCH
SP – 1
SP + 3
PCL
SP (R7)
SP + 4
Even address
Stack area
Prior to start of interrupt
exception handling
PC and CCR
saved to stack
After completion of interrupt
exception handling
Notation:
PCH: Upper 8 bits of program counter (PC)
Lower 8 bits of program counter (PC)
PCL:
CCR: Condition code register
Stack pointer
SP:
Notes: 1. PC shows the address of the first instruction to be executed upon
return from the interrupt handling routine.
2. Register contents must always be saved and restored by word access,
starting from an even-numbered address.
* Ignored on return.
Figure 3.4 Stack State after Completion of Interrupt Exception Handling
Figure 3.5 shows a typical interrupt sequence.
75
Figure 3.5 Interrupt Sequence
76
Internal data bus
(16 bits)
Internal write
signal
Internal read
signal
Internal
address bus
ø
Interrupt
request signal
(4)
Instruction
prefetch
(3)
Internal
processing
(5)
(1)
Stack access
(6)
(7)
(9)
Vector fetch
(8)
(10)
(9)
Prefetch instruction of
Internal
interrupt-handling routine
processing
(1) Instruction prefetch address (Instruction is not executed. Address is saved as PC contents, becoming return address.)
(2)(4) Instruction code (not executed)
(3) Instruction prefetch address (Instruction is not executed.)
(5) SP – 2
(6) SP – 4
(7) CCR
(8) Vector address
(9) Starting address of interrupt-handling routine (contents of vector)
(10) First instruction of interrupt-handling routine
(2)
(1)
Interrupt level
decision and wait for
end of instruction
Interrupt is
accepted
3.3.6
Interrupt Response Time
Table 3.4 shows the number of wait states after an interrupt request flag is set until the first
instruction of the interrupt handler is executed.
Table 3.4
Interrupt Wait States
Item
States
Total
Waiting time for completion of executing instruction*
1 to 13
15 to 27
Saving of PC and CCR to stack
4
Vector fetch
2
Instruction fetch
4
Internal processing
4
Note: * Not including EEPMOV instruction.
77
3.4
Application Notes
3.4.1
Notes on Stack Area Use
When word data is accessed in the H8/3802 Series, the least significant bit of the address is
regarded as 0. Access to the stack always takes place in word size, so the stack pointer (SP: R7)
should never indicate an odd address. Use PUSH Rn (MOV.W Rn, @–SP) or POP Rn (MOV.W
@SP+, Rn) to save or restore register values.
Setting an odd address in SP may cause a program to crash. An example is shown in figure 3.6.
SP →
SP →
PCH
PC L
R1L
PC L
SP →
H'FEFC
H'FEFD
H'FEFF
BSR instruction
SP set to H'FEFF
MOV. B R1L, @–R7
Stack accessed beyond SP
Contents of PCH are lost
Notation:
PCH: Upper byte of program counter
PCL: Lower byte of program counter
R1L: General register R1L
SP: Stack pointer
Figure 3.6 Operation when Odd Address is Set in SP
When CCR contents are saved to the stack during interrupt exception handling or restored when
RTE is executed, this also takes place in word size. Both the upper and lower bytes of word data
are saved to the stack; on return, the even address contents are restored to CCR while the odd
address contents are ignored.
78
3.4.2
Notes on Rewriting Port Mode Registers
When a port mode register is rewritten to switch the functions of external interrupt pins, the
following points should be observed.
When an external interrupt pin function is switched by rewriting the port mode register that
controls pins IRQAEC, IRQ1, IRQ0, WKP7 to WKP0, the interrupt request flag may be set to 1 at
the time the pin function is switched, even if no valid interrupt is input at the pin. Be sure to clear
the interrupt request flag to 0 after switching pin functions. Table 3.5 shows the conditions under
which interrupt request flags are set to 1 in this way.
Table 3.5
Conditions under which Interrupt Request Flag is Set to 1
Interrupt Request
Flags Set to 1
IRR1
Conditions
IRREC2
When the edge designated by AIEGS1 and AIEGS0 in AEGSR is input while
IENEC2 in IENRI is set to 1.
IRRI1
When PMRB bit IRQ1 is changed from 0 to 1 while pin IRQ1 is low and IEGR
bit IEG1 = 0.
When PMRB bit IRQ1 is changed from 1 to 0 while pin IRQ1 is low and IEGR
bit IEG1 = 1.
IRRI0
When PMR2 bit IRQ0 is changed from 0 to 1 while pin IRQ0 is low and IEGR
bit IEG0 = 0.
When PMR2 bit IRQ0 is changed from 1 to 0 while pin IRQ0 is low and IEGR
bit IEG0 = 1.
IWPR
IWPF7
When PMR5 bit WKP7 is changed from 0 to 1 while pin WKP 7 is low.
IWPF6
When PMR5 bit WKP6 is changed from 0 to 1 while pin WKP 6 is low.
IWPF5
When PMR5 bit WKP5 is changed from 0 to 1 while pin WKP 5 is low.
IWPF4
When PMR5 bit WKP4 is changed from 0 to 1 while pin WKP 4 is low.
IWPF3
When PMR5 bit WKP3 is changed from 0 to 1 while pin WKP 3 is low.
IWPF2
When PMR5 bit WKP2 is changed from 0 to 1 while pin WKP 2 is low.
IWPF1
When PMR5 bit WKP1 is changed from 0 to 1 while pin WKP 1 is low.
IWPF0
When PMR5 bit WKP0 is changed from 0 to 1 while pin WKP 0 is low.
Figure 3.7 shows the procedure for setting a bit in a port mode register and clearing the interrupt
request flag.
When switching a pin function, mask the interrupt before setting the bit in the port mode register.
After accessing the port mode register, execute at least one instruction (e.g., NOP), then clear the
interrupt request flag from 1 to 0. If the instruction to clear the flag is executed immediately after
the port mode register access without executing an intervening instruction, the flag will not be
cleared.
79
An alternative method is to avoid the setting of interrupt request flags when pin functions are
switched by keeping the pins at the high level so that the conditions in table 3.5 do not occur.
Interrupts masked. (Another possibility
is to disable the relevant interrupt in
interrupt enable register 1.)
CCR I bit ← 1
Set port mode register bit
After setting the port mode register bit,
first execute at least one instruction
(e.g., NOP), then clear the interrupt
request flag to 0
Execute NOP instruction
Clear interrupt request flag to 0
CCR I bit ← 0
Interrupt mask cleared
Figure 3.7 Port Mode Register Setting and Interrupt Request Flag Clearing Procedure
3.4.3
Interrupt Request Flag Clearing Method
Use the following recommended method for flag clearing in the interrupt request registers (IRR1,
IRR2, and IWPR).
Recommended Method: Perform flag clearing with only one instruction. Either a bit
manipulation instruction or a data transfer instruction in bytes can be used. Two examples of
coding for clearing IRRI1 (bit 1 in IRR1) are shown below:
• BCLR #1,@IRR1:8
• MOV.B R1L,@IRR1:8 (Set B’11111101 into R1L in advance)
Malfunction Example: When flag clearing is performed with several instructions, a flag, other
than the intended one, which was set while executing one of those instructions may be accidentally
cleared, and thus cause incorrect operations to occur.
An example of coding for clearing IRRI1 (bit 1 in IRR1), in which IRRI0 is also cleared and the
interrupt becomes invalid is shown below.
MOV.B @IRR1:8,R1L
At this point, IRRI0 is 0.
AND.B #B’11111101,R1L
IRRI0 becomes 1 here.
MOV.B R1L,@IRR1:8
IRRI0 is cleared to 0.
80
In the above example, an IRQ0 interrupt occurs while the AND.B instruction is executed. Since
not only the original target IRRI1, but also IRRI0 is cleared to 0, the IRQ0 interrupt becomes
invalid.
81
82
Section 4 Clock Pulse Generators
4.1
Overview
Clock oscillator circuitry (CPG: clock pulse generator) is provided on-chip, including both a
system clock pulse generator and a subclock pulse generator. The system clock pulse generator
consists of a system clock oscillator and system clock dividers. The subclock pulse generator
consists of a subclock oscillator circuit and a subclock divider.
4.1.1
Block Diagram
Figure 4.1 shows a block diagram of the clock pulse generators.
OSC 1
OSC 2
System clock
oscillator
øOSC
(f OSC)
øOSC/2
System clock
divider (1/2)
System
clock
divider
øOSC/128
øOSC/64
øOSC/32
øOSC/16
ø
Prescaler S
(13 bits)
System clock pulse generator
X1
X2
Subclock
oscillator
øW
(f W )
Subclock
divider
(1/2, 1/4, 1/8)
Subclock pulse generator
øW /2
øW /4
øW /8
ø/2
to
ø/8192
øW
øSUB
Prescaler W
(5 bits)
øW /2
øW /4
øW /8
to
øW /128
Figure 4.1 Block Diagram of Clock Pulse Generators
4.1.2
System Clock and Subclock
The basic clock signals that drive the CPU and on-chip peripheral modules are ø and øSUB. Four
of the clock signals have names: ø is the system clock, øSUB is the subclock, øOSC is the oscillator
clock, and ø W is the watch clock.
The clock signals available for use by peripheral modules are ø/2, ø/4, ø/8, ø/16, ø/32, ø/64, ø/128,
ø/256, ø/512, ø/1024, ø/2048, ø/4096, ø/8192, ø W , øW /2, øW /4, øW /8, øW /16, øW /32, øW /64, and
øW /128. The clock requirements differ from one module to another.
83
4.2
System Clock Generator
Clock pulses can be supplied to the system clock divider either by connecting a crystal or ceramic
oscillator, or by providing external clock input.
1. Connecting a crystal oscillator
Figure 4.2 shows a typical method of connecting a crystal oscillator.
R f = 1 MΩ ±20%
C1
OSC1
Rf
OSC2
C2
Frequency
Crystal
oscillator
C1, C2
Recommendation
value
4.19 MHz
NDK
12 pF ±20%
Figure 4.2 Typical Connection to Crystal Oscillator
Figure 4.3 shows the equivalent circuit of a crystal oscillator. An oscillator having the
characteristics given in table 4.1 should be used.
CS
LS
RS
OSC 1
OSC 2
C0
Figure 4.3 Equivalent Circuit of Crystal Oscillator
Table 4.1
Crystal Oscillator Parameters
Frequency (MHz)
4.193
RS max (Ω)
100
C0 max (pF)
16
84
2. Connecting a ceramic oscillator
Figure 4.4 shows a typical method of connecting a ceramic oscillator.
C1
OSC 1
OSC 2
R f = 1 MΩ ±20%
Frequency
Ceramic
oscillator
C1, C2
Recommendation
value
4.0 MHz
Murata
30 pF ±10%
Rf
C2
Figure 4.4 Typical Connection to Ceramic Oscillator
3. Notes on board design
When generating clock pulses by connecting a crystal or ceramic oscillator, pay careful attention
to the following points.
Avoid running signal lines close to the oscillator circuit, since the oscillator may be adversely
affected by induction currents. (See figure 4.5.)
The board should be designed so that the oscillator and load capacitors are located as close as
possible to pins OSC1 and OSC2.
To be avoided
Signal A Signal B
C1
OSC 1
OSC 2
C2
Figure 4.5 Board Design of Oscillator Circuit
85
4. External clock input method
Connect an external clock signal to pin OSC1, and leave pin OSC2 open. Figure 4.6 shows a
typical connection.
OSC 1
OSC 2
External clock input
Open
Figure 4.6 External Clock Input (Example)
Frequency
Oscillator Clock (øOSC)
Duty cycle
45% to 55%
Note: The circuit parameters above are recommended by the crystal or ceramic oscillator
manufacturer.
The circuit parameters are affected by the crystal or ceramic oscillator and floating
capacitance when designing the board. When using the oscillator, consult with the crystal
or ceramic oscillator manufacturer to determine the circuit parameters.
86
4.3
Subclock Generator
1. Connecting a 32.768 kHz/38.4 kHz crystal oscillator
Clock pulses can be supplied to the subclock divider by connecting a 32.768 kHz/38.4 kHz crystal
oscillator, as shown in figure 4.7. Follow the same precautions as noted under 3. notes on board
design for the system clock in 4.2.
C1
C1 = C 2 = 15 pF (typ.)
X1
Frequency
X2
Crystal oscillator
32.768 kHz Nihon Denpa Kogyo
C2
38.4 kHz
Products Name
MX73P
Seiko Instrument Inc. VTC-200
Figure 4.7 Typical Connection to 32.768 kHz/38.4 kHz Crystal Oscillator (Subclock)
Figure 4.8 shows the equivalent circuit of the 32.768 kHz/38.4 kHz crystal oscillator.
CS
LS
RS
X1
X2
C0
C0 = 1.5 pF typ
RS = 14 k Ω typ
f W = 32.768 kHz/38.4kHz
Figure 4.8 Equivalent Circuit of 32.768 kHz/38.4 kHz Crystal Oscillator
87
2. Pin connection when not using subclock
When the subclock is not used, connect pin X1 to GND and leave pin X2 open, as shown in
figure 4.9.
X1
GND
X2
Open
Figure 4.9 Pin Connection when not Using Subclock
3. External clock input
Connect the external clock to the X1 pin and leave the X2 pin open, as shown in figure 4.10.
VCC
X1
X2
External clock input
Open
Figure 4.10 Pin Connection when Inputting External Clock
Frequency
Subclock (øw)
Duty
45% to 55%
88
4.4
Prescalers
The H8/3802 Series is equipped with two on-chip prescalers having different input clocks
(prescaler S and prescaler W). Prescaler S is a 13-bit counter using the system clock (ø) as its
input clock. Its prescaled outputs provide internal clock signals for on-chip peripheral modules.
Prescaler W is a 5-bit counter using a 32.768 kHz or 38.4 kHz signal divided by 4 (ø W /4) as its
input clock. Its prescaled outputs are used by timer A as a time base for timekeeping.
1. Prescaler S (PSS)
Prescaler S is a 13-bit counter using the system clock (ø) as its input clock. It is incremented once
per clock period.
Prescaler S is initialized to H'0000 by a reset, and starts counting on exit from the reset state.
In standby mode, watch mode, subactive mode, and subsleep mode, the system clock pulse
generator stops. Prescaler S also stops and is initialized to H'0000.
The CPU cannot read or write prescaler S.
The output from prescaler S is shared by timer A, timer F, SCI3, the A/D converter, the LCD
controller, and the 10-bit PWM. The divider ratio can be set separately for each on-chip
peripheral function.
In active (medium-speed) mode the clock input to prescaler S is øosc/16, øosc/32, øosc/64, or
øosc/128.
2. Prescaler W (PSW)
Prescaler W is a 5-bit counter using a 32.768 kHz/38.4 kHz signal divided by 4 (øW /4) as its input
clock.
Prescaler W is initialized to H'00 by a reset, and starts counting on exit from the reset state.
Even in standby mode, watch mode, subactive mode, or subsleep mode, prescaler W continues
functioning so long as clock signals are supplied to pins X1 and X2.
Prescaler W can be reset by setting 1s in bits TMA3 and TMA2 of timer mode register A (TMA).
Output from prescaler W can be used to drive timer A, in which case timer A functions as a time
base for timekeeping.
89
4.5
Note on Oscillators
Oscillator characteristics are closely related to board design and should be carefully evaluated by
the user in mask ROM and ZTAT™ versions, referring to the examples shown in this section.
Oscillator circuit constants will differ depending on the oscillator element, stray capacitance in its
interconnecting circuit, and other factors. Suitable constants should be determined in consultation
with the oscillator element manufacturer. Design the circuit so that the oscillator element never
receives voltages exceeding its maximum rating.
PB3
X1
X2
Vss
OSC2
OSC1
TEST
(Vss)
Figure 4.11 Example of Crystal and Ceramic Oscillator Element Arrangement
4.5.1
Definition of Oscillation Settling Standby Time
Figure 4.12 shows the oscillation waveform (OSC2), system clock (ø), and microcomputer
operating mode when a transition is made from standby mode, watch mode, or subactive mode, to
active (high-speed/medium-speed) mode, with an oscillator element connected to the system clock
oscillator.
As shown in figure 4.12, as the system clock oscillator is halted in standby mode, watch mode,
and subactive mode, when a transition is made to active (high-speed/medium-speed) mode, the
sum of the following two times (oscillation settling time and standby time) is required.
90
1. Oscillation settling time (trc)
The time from the point at which the system clock oscillator oscillation waveform starts to change
when an interrupt is generated, until the amplitude of the oscillation waveform increases and the
oscillation frequency stabilizes.
2. Standby time
The time required for the CPU and peripheral functions to begin operating after the oscillation
waveform frequency and system clock have stabilized.
The standby time setting is selected with standby timer select bits 2 to 0 (STS2 to STS0) (bits 6 to
4 in system control register 1 (SYSCR1)).
Oscillation
waveform
(OSC2)
System clock
(ø)
Oscillation
settling time
Standby time
Operating
mode
Standby mode,
watch mode,
or subactive
mode
Oscillation settling standby time
Active (high-speed) mode or
active (medium-speed) mode
Interrupt accepted
Figure 4.12 Oscillation Settling Standby Time
When standby mode, watch mode, or subactive mode is cleared by an interrupt or reset, and a
transition is made to active (high-speed/medium-speed) mode, the oscillation waveform begins to
change at the point at which the interrupt is accepted. Therefore, when an oscillator element is
connected in standby mode, watch mode, or subactive mode, since the system clock oscillator is
halted, the time from the point at which this oscillation waveform starts to change until the
amplitude of the oscillation waveform increases and the oscillation frequency stabilizes—that is,
the oscillation settling time—is required.
91
The oscillation settling time in the case of these state transitions is the same as the oscillation
settling time at power-on (the time from the point at which the power supply voltage reaches the
prescribed level until the oscillation stabilizes), specified by "oscillation settling time trc" in the
AC characteristics.
Meanwhile, once the system clock has halted, a standby time of at least 8 states is necessary in
order for the CPU and peripheral functions to operate normally.
Thus, the time required from interrupt generation until operation of the CPU and peripheral
functions is the sum of the above described oscillation settling time and standby time. This total
time is called the oscillation settling standby time, and is expressed by equation (1) below.
Oscillation settling standby time = oscillation settling time + standby time
= trc + (8 to 16,384 states)
................. (1)
Therefore, when a transition is made from standby mode, watch mode, or subactive mode, to
active (high-speed/medium-speed) mode, with an oscillator element connected to the system clock
oscillator, careful evaluation must be carried out on the installation circuit before deciding on the
oscillation settling standby time. In particular, since the oscillation settling time is affected by
installation circuit constants, stray capacitance, and so forth, suitable constants should be
determined in consultation with the oscillator element manufacturer.
4.5.2
Notes on Use of Crystal Oscillator Element (Excluding Ceramic Oscillator
Element)
When a microcomputer operates, the internal power supply potential fluctuates slightly in
synchronization with the system clock. Depending on the individual crystal oscillator element
characteristics, the oscillation waveform amplitude may not be sufficiently large immediately after
the oscillation settling standby time, making the oscillation waveform susceptible to influence by
fluctuations in the power supply potential. In this state, the oscillation waveform may be
disrupted, leading to an unstable system clock and erroneous operation of the microcomputer.
If erroneous operation occurs, change the setting of standby timer select bits 2 to 0 (STS2 to
STS0) (bits 6 to 4 in system control register 1 (SYSCR1)) to give a longer standby time.
For example, if erroneous operation occurs with a standby time setting of 16 states, check the
operation with a standby time setting of 1,024 states or more.
If the same kind of erroneous operation occurs after a reset as after a state transition, hold the RES
pin low for a longer period.
92
Section 5 Power-Down Modes
5.1
Overview
The H8/3802 Series has nine modes of operation after a reset. These include eight power-down
modes, in which power dissipation is significantly reduced. Table 5.1 gives a summary of the eight
operating modes.
Table 5.1
Operating Modes
Operating Mode
Description
Active (high-speed) mode
The CPU and all on-chip peripheral functions are operable on
the system clock in high-speed operation
Active (medium-speed) mode
The CPU and all on-chip peripheral functions are operable on
the system clock in low-speed operation
Subactive mode
The CPU is operable on the subclock in low-speed operation
Sleep (high-speed) mode
The CPU halts. On-chip peripheral functions are operable on
the system clock
Sleep (medium-speed) mode
The CPU halts. On-chip peripheral functions operate at a
frequency of 1/64, 1/32, 1/16, or 1/8 of the system clock
frequency
Subsleep mode
The CPU halts. The time-base function of timer A, timer F,
SCI3, AEC and LCD controller/driver are operable on the
subclock
Watch mode
The CPU halts. The time-base function of timer A, timer F,
AEC and LCD controller/driver are operable on the subclock
Standby mode
The CPU and all on-chip peripheral functions halt
Module standby mode
Individual on-chip peripheral functions specified by software
enter standby mode and halt
Of these nine operating modes, all but the active (high-speed) mode are power-down modes. In
this section the two active modes (high-speed and medium speed) will be referred to collectively
as active mode.
93
Figure 5.1 shows the transitions among these operation modes. Table 5.2 indicates the internal
states in each mode.
Program
execution state
Reset state
SLEEP
instruction*a
Active
(high-speed)
mode
P *d
EE n
SL uctio
r
t
ins
Program
halt state
Program
halt state
a
SLEEP
instruction*f
SLEEP
instruction*g
*4
SL
instr EEP
uctio *d
n
*4
*1
*1
SLEEP
instruction*e
Watch
mode
*1
SLEEP
instruction*i
P *e
EE tion
L
c
S ru
st
in
SLEEP
instruction*h
ins SLEE
tru
ctio P
n *e
Active
(medium-speed)
mode
Subactive
mode
P *
EE tion
SL ruc
st
inin SL
st E
ru EP
ct
io
n *b
SLEEP
instruction*b
*3
Sleep
(medium-speed)
mode
ins SLEE
tru P
cti
on *j
S
ins LE
tru EP
ctio
n *i
Standby
mode
Sleep
(high-speed)
mode
*3
SLEEP
instruction*c
*2
Subsleep
mode
Power-down modes
Mode Transition Conditions (1)
Mode Transition Conditions (2)
LSON MSON SSBY TMA3 DTON
Interrupt Sources
a
b
0
0
0
1
0
0
✻
✻
0
0
1
c
d
1
0
✻
✻
0
1
1
0
0
0
2
e
f
g
✻
0
0
✻
0
1
1
0
0
1
✻
✻
0
1
1
3
Timer A, Timer F interrupt, IRQ0 interrupt, WKP7 to
WKP0 interrupts
Timer A, Timer F, SCI3 interrupt, IRQ1 and IRQ0
interrupts, IRQAEC, WKP7 to WKP0 interrupts, AEC
All interrupts
4
IRQ1 or IRQ0 interrupt, WKP7 to WKP0 interrupts
h
i
0
1
1
✻
1
1
1
1
1
1
j
0
0
1
1
1
* : Don’t care
Notes: 1. A transition between different modes cannot be made to occur simply because an interrupt
request is generated. Make sure that interrupt handling is performed after the interrupt is
accepted.
2. Details on the mode transition conditions are given in the explanations of each mode,
in sections 5-2 through 5-8.
Figure 5.1 Mode Transition Diagram
94
Table 5.2
Internal State in Each Operating Mode
Active Mode
Function
HighSpeed
System clock oscillator
Subclock oscillator
CPU
Instructions
operations RAM
MediumSpeed
Sleep Mode
HighSpeed
Subactive
Mode
Subsleep
Mode
Standby
Mode
Functions Functions Functions Functions Halted
Halted
Halted
Halted
Functions Functions Functions Functions Functions
Functions
Functions
Functions
Functions Functions Halted
Functions
Halted
Halted
Retained
Retained
Retained
MediumSpeed
Watch
Mode
Halted
Halted
Retained
Retained
Registers
Retained*1
I/O ports
External
IRQ0
Functions Functions Functions Functions Functions
interrupts
IRQ1
Retained*5
Functions
Functions
Retained*5
IRQAEC
WKP0
Functions
Functions Functions Functions Functions Functions
Functions
Functions
Functions
Functions*4
Retained
Functions
Functions
Functions*6
WKP1
WKP2
WKP3
WKP4
WKP5
WKP6
WKP7
Peripheral
Timer A
functions
Notes:
1.
2.
3.
4.
5.
6.
7.
Functions Functions Functions Functions Functions*4 Functions*4
*6
Asynchronous
counter
Functions
Timer F
Functions/
Retained*7
Functions/
Retained*7
Functions/
Retained*7
Retained
SCI3
Reset
Functions/
Retained*2
Functions/
Retained*2
Reset
PWM
Retained
Retained
Retained
Retained
A/D converter
Retained
Retained
Retained
Retained
LCD
Functions/
Retained*3
Functions/
Retained*3
Functions/
Retained*3
Retained
Register contents are retained, but output is high-impedance state.
Functions if øW /2 is selected as the internal clock; otherwise halted and retained.
Functions if øW , øW/2 or øW/4 is selected as the operating clock; otherwise halted and retained.
Functions if the timekeeping time-base function is selected.
External interrupt requests are ignored. Interrupt request register contents are not altered.
Incrementing is possible, but interrupt generation is not.
Functions if the ø W /4 internal clock is selected; otherwise halted and retained.
95
5.1.1
System Control Registers
The operation mode is selected using the system control registers described in table 5.3.
Table 5.3
System Control Registers
Name
Abbreviation
R/W
Initial Value
Address
System control register 1
SYSCR1
R/W
H'07
H'FFF0
System control register 2
SYSCR2
R/W
H'F0
H'FFF1
1. System control register 1 (SYSCR1)
Bit
7
6
5
4
3
2
1
0
SSBY
STS2
STS1
STS0
LSON
—
MA1
MA0
Initial value
0
0
0
0
0
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
—
R/W
R/W
SYSCR1 is an 8-bit read/write register for control of the power-down modes.
Upon reset, SYSCR1 is initialized to H'07.
Bit 7: Software standby (SSBY)
This bit designates transition to standby mode or watch mode.
Bit 7
SSBY
Description
0
•
When a SLEEP instruction is executed in active mode,
a transition is made to sleep mode
•
When a SLEEP instruction is executed in subactive mode, a transition is made to
subsleep mode
•
When a SLEEP instruction is executed in active mode, a transition is made to
standby mode or watch mode
•
When a SLEEP instruction is executed in subactive mode, a transition is made to
watch mode
1
96
(initial value)
Bits 6 to 4: Standby timer select 2 to 0 (STS2 to STS0)
These bits designate the time the CPU and peripheral modules wait for stable clock operation after
exiting from standby mode or watch mode to active mode due to an interrupt. The designation
should be made according to the operating frequency so that the waiting time is at least equal to
the oscillation settling time.
Bit 6
STS2
Bit 5
STS1
Bit 4
STS0
Description
0
0
0
Wait time = 8,192 states
0
0
1
Wait time = 16,384 states
0
1
0
Wait time = 1,024 states
0
1
1
Wait time = 2,048 states
1
0
0
Wait time = 4,096 states
1
0
1
Wait time = 2 states
1
1
0
Wait time = 8 states
1
1
1
Wait time = 16 states
(initial value)
(External clock mode)
Note: In the case that external clock is input, set up the “Standby timer select” selection to
External clock mode before Mode Transition. Also, do not set up to external clock mode, in
the case that it does not use external clock.
Bit 3: Low speed on flag (LSON)
This bit chooses the system clock (ø) or subclock (øSUB ) as the CPU operating clock when watch
mode is cleared. The resulting operation mode depends on the combination of other control bits
and interrupt input.
Bit 3
LSON
Description
0
The CPU operates on the system clock (ø)
1
The CPU operates on the subclock (øSUB)
(initial value)
Bits 2: Reserved bit
Bit 2 is reserved: it is always read as 1 and cannot be modified.
97
Bits 1 and 0: Active (medium-speed) mode clock select (MA1, MA0)
Bits 1 and 0 choose øosc /128, øosc /64, øosc /32, or ø osc /16 as the operating clock in active (mediumspeed) mode and sleep (medium-speed) mode. MA1 and MA0 should be written in active (highspeed) mode or subactive mode.
Bit 1
MA1
Bit 0
MA0
Description
0
0
øosc/16
0
1
øosc/32
1
0
øosc/64
1
1
øosc/128
(initial value)
2. System control register 2 (SYSCR2)
Bit
7
6
5
4
3
2
1
0
—
—
—
NESEL
DTON
MSON
SA1
SA0
Initial value
1
1
1
1
0
0
0
0
Read/Write
—
—
—
R/W
R/W
R/W
R/W
R/W
SYSCR2 is an 8-bit read/write register for power-down mode control.
Bits 7 to 5: Reserved bits
These bits are reserved; they are always read as 1, and cannot be modified.
Bit 4: Noise elimination sampling frequency select (NESEL)
This bit selects the frequency at which the watch clock signal (øW) generated by the subclock
pulse generator is sampled, in relation to the oscillator clock (øOSC ) generated by the system clock
pulse generator. When øOSC = 2 to 16 MHz, clear NESEL to 0.
Bit 4
NESEL
Description
0
Sampling rate is ø OSC/16
1
Sampling rate is ø OSC/4
98
(initial value)
Bit 3: Direct transfer on flag (DTON)
This bit designates whether or not to make direct transitions among active (high-speed), active
(medium-speed) and subactive mode when a SLEEP instruction is executed. The mode to which
the transition is made after the SLEEP instruction is executed depends on a combination of this
and other control bits.
Bit 3
DTON
Description
0
•
When a SLEEP instruction is executed in active mode,
a transition is made to standby mode, watch mode, or sleep mode
•
When a SLEEP instruction is executed in subactive mode, a transition is made to
watch mode or subsleep mode
•
When a SLEEP instruction is executed in active (high-speed) mode, a direct
transition is made to active (medium-speed) mode if SSBY = 0, MSON = 1, and
LSON = 0, or to subactive mode if SSBY = 1, TMA3 = 1, and LSON = 1
•
When a SLEEP instruction is executed in active (medium-speed) mode, a direct
transition is made to active (high-speed) mode if SSBY = 0, MSON = 0, and
LSON = 0, or to subactive mode if SSBY = 1, TMA3 = 1, and LSON = 1
•
When a SLEEP instruction is executed in subactive mode, a direct transition is
made to active (high-speed) mode if SSBY = 1, TMA3 = 1, LSON = 0, and MSON
= 0, or to active (medium-speed) mode if SSBY = 1, TMA3 = 1, LSON = 0, and
MSON = 1
1
(initial value)
Bit 2: Medium speed on flag (MSON)
After standby, watch, or sleep mode is cleared, this bit selects active (high-speed) or active
(medium-speed) mode.
Bit 2
MSON
Description
0
Operation in active (high-speed) mode
1
Operation in active (medium-speed) mode
(initial value)
99
Bits 1 and 0: Subactive mode clock select (SA1 and SA0)
These bits select the CPU clock rate (øW/2, øW /4, or ø W /8) in subactive mode. SA1 and SA0
cannot be modified in subactive mode.
Bit 1
SA1
Bit 0
SA0
Description
0
0
øW/8
0
1
øW/4
1
*
øW/2
(initial value)
* : Don’t care
100
5.2
Sleep Mode
5.2.1
Transition to Sleep Mode
1. Transition to sleep (high-speed) mode
The system goes from active mode to sleep (high-speed) mode when a SLEEP instruction is
executed while the SSBY and LSON bits in SYSCR1 are cleared to 0, the MSON and DTON bits
in SYSCR2 are cleared to 0. In sleep mode CPU operation is halted but the on-chip peripheral
functions. CPU register contents are retained.
2. Transition to sleep (medium-speed) mode
The system goes from active mode to sleep (medium-speed) mode when a SLEEP instruction is
executed while the SSBY and LSON bits in SYSCR1 are cleared to 0, the MSON bit in SYSCR2
is set to 1, and the DTON bit in SYSCR2 is cleared to 0. In sleep (medium-speed) mode, as in
sleep (high-speed) mode, CPU operation is halted but the on-chip peripheral functions are
operational. The clock frequency in sleep (medium-speed) mode is determined by the MA1 and
MA0 bits in SYSCR1. CPU register contents are retained.
Furthermore, it sometimes acts with half state early timing at the time of transition to sleep
(medium-speed) mode.
5.2.2
Clearing Sleep Mode
Sleep mode is cleared by any interrupt (timer A, timer F, asynchronous counter, IRQAEC, IRQ 1,
IRQ0, WKP7 to WKP0, SCI3, A/D converter), or by input at the RES pin.
• Clearing by interrupt
When an interrupt is requested, sleep mode is cleared and interrupt exception handling starts. A
transition is made from sleep (high-speed) mode to active (high-speed) mode, or from sleep
(medium-speed) mode to active (medium-speed) mode. Sleep mode is not cleared if the I bit of the
condition code register (CCR) is set to 1 or the particular interrupt is disabled in the interrupt
enable register.
Interrupt signal and system clock are mutually asynchronous. Synchronization error time in a
maximum is 2/ø (s).
• Clearing by RES input
When the RES pin goes low, the CPU goes into the reset state and sleep mode is cleared.
101
5.2.3
Clock Frequency in Sleep (Medium-Speed) Mode
Operation in sleep (medium-speed) mode is clocked at the frequency designated by the MA1 and
MA0 bits in SYSCR1.
5.3
Standby Mode
5.3.1
Transition to Standby Mode
The system goes from active mode to standby mode when a SLEEP instruction is executed while
the SSBY bit in SYSCR1 is set to 1, the LSON bit in SYSCR1 is cleared to 0, and bit TMA3 in
TMA is cleared to 0. In standby mode the clock pulse generator stops, so the CPU and on-chip
peripheral modules stop functioning, but as long as the rated voltage is supplied, the contents of
CPU registers, on-chip RAM, and some on-chip peripheral module registers are retained. On-chip
RAM contents will be further retained down to a minimum RAM data retention voltage. The I/O
ports go to the high-impedance state.
5.3.2
Clearing Standby Mode
Standby mode is cleared by an interrupt (IRQ1 or IRQ0), WKP 7 to WKP0 or by input at the RES
pin.
• Clearing by interrupt
When an interrupt is requested, the system clock pulse generator starts. After the time set in bits
STS2 to STS0 in SYSCR1 has elapsed, a stable system clock signal is supplied to the entire chip,
standby mode is cleared, and interrupt exception handling starts. Operation resumes in active
(high-speed) mode if MSON = 0 in SYSCR2, or active (medium-speed) mode if MSON = 1.
Standby mode is not cleared if the I bit of CCR is set to 1 or the particular interrupt is disabled in
the interrupt enable register.
• Clearing by RES input
When the RES pin goes low, the system clock pulse generator starts. After the pulse generator
output has stabilized, if the RES pin is driven high, the CPU starts reset exception handling. Since
system clock signals are supplied to the entire chip as soon as the system clock pulse generator
starts functioning, the RES pin should be kept at the low level until the pulse generator output
stabilizes.
102
5.3.3
Oscillator Settling Time after Standby Mode is Cleared
Bits STS2 to STS0 in SYSCR1 should be set as follows.
• When a crystal oscillator is used
The table below gives settings for various operating frequencies. Set bits STS2 to STS0 for a
waiting time at least as long as the oscillation settling time.
Table 5.4
Clock Frequency and Settling Time (times are in ms)
STS2
STS1
STS0
Waiting Time
5 MHz
2 MHz
0
0
0
8,192 states
1.638
4.1
0
0
1
16,384 states
3.277
8.2
0
1
0
1,024 states
0.205
0.512
0
1
1
2,048 states
0.410
1.024
1
0
0
4,096 states
0.819
2.048
1
0
1
2 states
(Use prohibited)
0.0004
0.001
1
1
0
8 states
0.0002
0.004
1
1
1
16 states
0.003
0.008
• When an external clock is used
STS2 = 1, STS1 = 0, and STS0 = 1 should be set. Other values possible use, but CPU sometimes
will start operation before waiting time completion.
103
5.3.4
Standby Mode Transition and Pin States
When a SLEEP instruction is executed in active (high-speed) mode or active (medium-speed)
mode while bit SSBY is set to 1 and bit LSON is cleared to 0 in SYSCR1, and bit TMA3 is
cleared to 0 in TMA, a transition is made to standby mode. At the same time, pins go to the highimpedance state (except pins for which the pull-up MOS is designated as on). Figure 5.2 shows
the timing in this case.
ø
Internal data bus
SLEEP instruction fetch
Fetch of next instruction
SLEEP instruction execution
Pins
Internal processing
Port output
Active (high-speed) mode or active (medium-speed) mode
Figure 5.2 Standby Mode Transition and Pin States
104
High-impedance
Standby mode
5.3.5
Notes on External Input Signal Changes before/after Standby Mode
1. When external input signal changes before/after standby mode or watch mode
When an external input signal such as IRQ, WKP, or IRQAEC is input, both the high- and
low-level widths of the signal must be at least two cycles of system clock ø or subclock øSUB
(referred to together in this section as the internal clock). As the internal clock stops in
standby mode and watch mode, the width of external input signals requires careful attention
when a transition is made via these operating modes. Ensure that external input signals
conform to the conditions stated in 3, Recommended timing of external input signals, below
2. When external input signals cannot be captured because internal clock stops
The case of falling edge capture is illustrated in figure 5.3
As shown in the case marked "Capture not possible," when an external input signal falls
immediately after a transition to active (high-speed or medium-speed) mode or subactive
mode, after oscillation is started by an interrupt via a different signal, the external input signal
cannot be captured if the high-level width at that point is less than 2 t cyc or 2 tsubcyc .
3. Recommended timing of external input signals
To ensure dependable capture of an external input signal, high- and low-level signal widths of
at least 2 tcyc or 2 tsubcyc are necessary before a transition is made to standby mode or watch
mode, as shown in "Capture possible: case 1."
External input signal capture is also possible with the timing shown in "Capture possible: case
2" and "Capture possible: case 3," in which a 2 tcyc or 2 tsubcyc level width is secured.
105
Operating
mode
Active (high-speed,
medium-speed) mode
or subactive mode
tcyc
tsubcyc
tcyc
tsubcyc
Wait for Active (high-speed,
Standby mode oscillation medium-speed) mode
or watch mode to settle or subactive mode
tcyc
tsubcyc
tcyc
tsubcyc
ø or øSUB
External input signal
Capture possible:
case 1
Capture possible:
case 2
Capture possible:
case 3
Capture not
possible
Interrupt by different
signall
Figure 5.3 External Input Signal Capture when Signal Changes before/after
Standby Mode or Watch Mode
4. Input pins to which these notes apply:
IRQ1 to IRQ0, WKP7 to WKP0, IRQAEC
106
5.4
Watch Mode
5.4.1
Transition to Watch Mode
The system goes from active or subactive mode to watch mode when a SLEEP instruction is
executed while the SSBY bit in SYSCR1 is set to 1 and bit TMA3 in TMA is set to 1.
In watch mode, operation of on-chip peripheral modules is halted except for timer A, timer F,
AEC and the LCD controller/driver (for which operation or halting can be set) is halted. As long
as a minimum required voltage is applied, the contents of CPU registers, the on-chip RAM and
some registers of the on-chip peripheral modules, are retained. I/O ports keep the same states as
before the transition.
5.4.2
Clearing Watch Mode
Watch mode is cleared by an interrupt (timer A, timer F, IRQ0, or WKP7 to WKP0) or by input at
the RES pin.
• Clearing by interrupt
When watch mode is cleared by interrupt, the mode to which a transition is made depends on the
settings of LSON in SYSCR1 and MSON in SYSCR2. If both LSON and MSON are cleared to 0,
transition is to active (high-speed) mode; if LSON = 0 and MSON = 1, transition is to active
(medium-speed) mode; if LSON = 1, transition is to subactive mode. When the transition is to
active mode, after the time set in SYSCR1 bits STS2 to STS0 has elapsed, a stable clock signal is
supplied to the entire chip, watch mode is cleared, and interrupt exception handling starts. Watch
mode is not cleared if the I bit of CCR is set to 1 or the particular interrupt is disabled in the
interrupt enable register.
• Clearing by RES input
Clearing by RES pin is the same as for standby mode; see 2. Clearing by RES pin in 5.3.2,
Clearing Standby Mode.
5.4.3
Oscillator Settling Time after Watch Mode is Cleared
The waiting time is the same as for standby mode; see 5.3.3, Oscillator Settling Time after
Standby Mode is Cleared.
5.4.4
Notes on External Input Signal Changes before/after Watch Mode
See 5.3.5, Notes on External Input Signal Changes before/after Standby Mode.
107
5.5
Subsleep Mode
5.5.1
Transition to Subsleep Mode
The system goes from subactive mode to subsleep mode when a SLEEP instruction is executed
while the SSBY bit in SYSCR1 is cleared to 0, LSON bit in SYSCR1 is set to 1, and TMA3 bit in
TMA is set to 1. In subsleep mode, operation of on-chip peripheral modules other than the A/D
converter, and PWM is halted. As long as a minimum required voltage is applied, the contents of
CPU registers, the on-chip RAM and some registers of the on-chip peripheral modules are
retained. I/O ports keep the same states as before the transition.
5.5.2
Clearing Subsleep Mode
Subsleep mode is cleared by an interrupt (timer A, timer F, asynchronous counter, SCI3,
IRQAEC, IRQ1, IRQ0, WKP7 to WKP0) or by a low input at the RES pin.
• Clearing by interrupt
When an interrupt is requested, subsleep mode is cleared and interrupt exception handling starts.
Subsleep mode is not cleared if the I bit of CCR is set to 1 or the particular interrupt is disabled in
the interrupt enable register.
Interrupt signal and system clock are mutually asynchronous. Synchronization error time in a
maximum is 2/øSUB (s).
• Clearing by RES input
Clearing by RES pin is the same as for standby mode; see Clearing by RES pin in 5.3.2, Clearing
Standby Mode.
108
5.6
Subactive Mode
5.6.1
Transition to Subactive Mode
Subactive mode is entered from watch mode if a timer A, timer F, IRQ 0, or WKP7 to WKP0
interrupt is requested while the LSON bit in SYSCR1 is set to 1. From subsleep mode, subactive
mode is entered if a timer A, timer F, asynchronous event counter, SCI3, IRQAEC, IRQ1, IRQ0,
or WKP7 to WKP0 interrupt is requested. A transition to subactive mode does not take place if the
I bit of CCR is set to 1 or the particular interrupt is disabled in the interrupt enable register.
5.6.2
Clearing Subactive Mode
Subactive mode is cleared by a SLEEP instruction or by a low input at the RES pin.
• Clearing by SLEEP instruction
If a SLEEP instruction is executed while the SSBY bit in SYSCR1 is set to 1 and TMA3 bit in
TMA is set to 1, subactive mode is cleared and watch mode is entered. If a SLEEP instruction is
executed while SSBY = 0 and LSON = 1 in SYSCR1 and TMA3 = 1 in TMA, subsleep mode is
entered. Direct transfer to active mode is also possible; see 5.8, Direct Transfer, below.
• Clearing by RES pin
Clearing by RES pin is the same as for standby mode; see Clearing by RES pin in 5.3.2, Clearing
Standby Mode.
5.6.3
Operating Frequency in Subactive Mode
The operating frequency in subactive mode is set in bits SA1 and SA0 in SYSCR2. The choices
are øW /2, øW /4, and øW /8.
109
5.7
Active (Medium-Speed) Mode
5.7.1
Transition to Active (Medium-Speed) Mode
If the RES pin is driven low, active (medium-speed) mode is entered. If the LSON bit in SYSCR2
is set to 1 while the LSON bit in SYSCR1 is cleared to 0, a transition to active (medium-speed)
mode results from IRQ0, IRQ1 or WKP7 to WKP0 interrupts in standby mode, timer A, timer F,
IRQ0, or WKP7 to WKP0 interrupts in watch mode, or any interrupt in sleep mode. A transition
to active (medium-speed) mode does not take place if the I bit of CCR is set to 1 or the particular
interrupt is disabled in the interrupt enable register.
Furthermore, it sometimes acts with half state early timing at the time of transition to active
(medium-speed) mode.
5.7.2
Clearing Active (Medium-Speed) Mode
Active (medium-speed) mode is cleared by a SLEEP instruction.
• Clearing by SLEEP instruction
A transition to standby mode takes place if the SLEEP instruction is executed while the SSBY bit
in SYSCR1 is set to 1, the LSON bit in SYSCR1 is cleared to 0, and the TMA3 bit in TMA is
cleared to 0. The system goes to watch mode if the SSBY bit in SYSCR1 is set to 1 and bit TMA3
in TMA is set to 1 when a SLEEP instruction is executed.
When both SSBY and LSON are cleared to 0 in SYSCR1 and a SLEEP instruction is executed,
sleep mode is entered. Direct transfer to active (high-speed) mode or to subactive mode is also
possible. See 5.8, Direct Transfer, below for details.
• Clearing by RES pin
When the RES pin is driven low, a transition is made to the reset state and active (medium-speed)
mode is cleared.
5.7.3
Operating Frequency in Active (Medium-Speed) Mode
Operation in active (medium-speed) mode is clocked at the frequency designated by the MA1 and
MA0 bits in SYSCR1.
110
5.8
Direct Transfer
5.8.1
Overview of Direct Transfer
The CPU can execute programs in three modes: active (high-speed) mode, active (medium-speed)
mode, and subactive mode. A direct transfer is a transition among these three modes without the
stopping of program execution. A direct transfer can be made by executing a SLEEP instruction
while the DTON bit in SYSCR2 is set to 1. After the mode transition, direct transfer interrupt
exception handling starts.
If the direct transfer interrupt is disabled in interrupt enable register 2, a transition is made instead
to sleep mode or watch mode. Note that if a direct transition is attempted while the I bit in CCR is
set to 1, sleep mode or watch mode will be entered, and it will be impossible to clear the resulting
mode by means of an interrupt.
• Direct transfer from active (high-speed) mode to active (medium-speed) mode
When a SLEEP instruction is executed in active (high-speed) mode while the SSBY and LSON
bits in SYSCR1 are cleared to 0, the MSON bit in SYSCR2 is set to 1, and the DTON bit in
SYSCR2 is set to 1, a transition is made to active (medium-speed) mode via sleep mode.
• Direct transfer from active (medium-speed) mode to active (high-speed) mode
When a SLEEP instruction is executed in active (medium-speed) mode while the SSBY and
LSON bits in SYSCR1 are cleared to 0, the MSON bit in SYSCR2 is cleared to 0, and the DTON
bit in SYSCR2 is set to 1, a transition is made to active (high-speed) mode via sleep mode.
• Direct transfer from active (high-speed) mode to subactive mode
When a SLEEP instruction is executed in active (high-speed) mode while the SSBY and LSON
bits in SYSCR1 are set to 1, the DTON bit in SYSCR2 is set to 1, and the TMA3 bit in TMA is set
to 1, a transition is made to subactive mode via watch mode.
• Direct transfer from subactive mode to active (high-speed) mode
When a SLEEP instruction is executed in subactive mode while the SSBY bit in SYSCR1 is set to
1, the LSON bit in SYSCR1 is cleared to 0, the MSON bit in SYSCR2 is cleared to 0, the DTON
bit in SYSCR2 is set to 1, and the TMA3 bit in TMA is set to 1, a transition is made directly to
active (high-speed) mode via watch mode after the waiting time set in SYSCR1 bits STS2 to STS0
has elapsed.
111
• Direct transfer from active (medium-speed) mode to subactive mode
When a SLEEP instruction is executed in active (medium-speed) while the SSBY and LSON bits
in SYSCR1 are set to 1, the DTON bit in SYSCR2 is set to 1, and the TMA3 bit in TMA is set to
1, a transition is made to subactive mode via watch mode.
• Direct transfer from subactive mode to active (medium-speed) mode
When a SLEEP instruction is executed in subactive mode while the SSBY bit in SYSCR1 is set to
1, the LSON bit in SYSCR1 is cleared to 0, the MSON bit in SYSCR2 is set to 1, the DTON bit in
SYSCR2 is set to 1, and the TMA3 bit in TMA is set to 1, a transition is made directly to active
(medium-speed) mode via watch mode after the waiting time set in SYSCR1 bits STS2 to STS0
has elapsed.
5.8.2
Direct Transition Times
1. Time for direct transition from active (high-speed) mode to active (medium-speed) mode
A direct transition from active (high-speed) mode to active (medium-speed) mode is performed by
executing a SLEEP instruction in active (high-speed) mode while bits SSBY and LSON are both
cleared to 0 in SYSCR1, and bits MSON and DTON are both set to 1 in SYSCR2. The time from
execution of the SLEEP instruction to the end of interrupt exception handling (the direct transition
time) is given by equation (1) below.
Direct transition time = { (Number of SLEEP instruction execution states) + (number of internal
processing states) } × (tcyc before transition) + (number of interrupt
exception handling execution states) × (tcyc after transition)
.................................. (1)
Example: Direct transition time = (2 + 1) × 2tosc + 14 × 16tosc = 230tosc (when ø/8 is selected
as the CPU operating clock)
Notation:
tosc: OSC clock cycle time
tcyc: System clock (ø) cycle time
112
2. Time for direct transition from active (medium-speed) mode to active (high-speed) mode
A direct transition from active (medium-speed) mode to active (high-speed) mode is performed by
executing a SLEEP instruction in active (medium-speed) mode while bits SSBY and LSON are
both cleared to 0 in SYSCR1, and bit MSON is cleared to 0 and bit DTON is set to 1 in SYSCR2.
The time from execution of the SLEEP instruction to the end of interrupt exception handling (the
direct transition time) is given by equation (2) below.
Direct transition time = { (Number of SLEEP instruction execution states) + (number of internal
processing states) } × (tcyc before transition) + (number of interrupt
exception handling execution states) × (tcyc after transition)
.................................. (2)
Example: Direct transition time = (2 + 1) × 16tosc + 14 × 2tosc = 76tosc (when ø/8 is selected as
the CPU operating clock)
Notation:
tosc: OSC clock cycle time
tcyc: System clock (ø) cycle time
3. Time for direct transition from subactive mode to active (high-speed) mode
A direct transition from subactive mode to active (high-speed) mode is performed by executing a
SLEEP instruction in subactive mode while bit SSBY is set to 1 and bit LSON is cleared to 0 in
SYSCR1, bit MSON is cleared to 0 and bit DTON is set to 1 in SYSCR2, and bit TMA3 is set to 1
in TMA. The time from execution of the SLEEP instruction to the end of interrupt exception
handling (the direct transition time) is given by equation (3) below.
Direct transition time = { (Number of SLEEP instruction execution states) + (number of internal
processing states) } × (tsubcyc before transition) + { (wait time set in
STS2 to STS0) + (number of interrupt exception handling execution
states) } × (tcyc after transition)
........................ (3)
Example: Direct transition time = (2 + 1) × 8tw + (8192 + 14) × 2tosc = 24tw + 16412tosc (when
øw/8 is selected as the CPU operating clock, and wait time = 8192 states)
Notation:
tosc:
tw:
tcyc:
tsubcyc:
OSC clock cycle time
Watch clock cycle time
System clock (ø) cycle time
Subclock (øSUB) cycle time
113
4. Time for direct transition from subactive mode to active (medium-speed) mode
A direct transition from subactive mode to active (medium-speed) mode is performed by
executing a SLEEP instruction in subactive mode while bit SSBY is set to 1 and bit LSON is
cleared to 0 in SYSCR1, bits MSON and DTON are both set to 1 in SYSCR2, and bit TMA3 is set
to 1 in TMA. The time from execution of the SLEEP instruction to the end of interrupt exception
handling (the direct transition time) is given by equation (4) below.
Direct transition time = { (Number of SLEEP instruction execution states) + (number of internal
processing states) } × (tsubcyc before transition) + { (wait time set in
STS2 to STS0) + (number of interrupt exception handling execution
states) } × (tcyc after transition)
........................ (4)
Example: Direct transition time = (2 + 1) × 8tw + (8192 + 14) × 16tosc = 24tw + 131296tosc
(when øw/8 or ø8 is selected as the CPU operating clock, and wait time = 8192 states)
Notation:
tosc:
tw:
tcyc:
tsubcyc:
OSC clock cycle time
Watch clock cycle time
System clock (ø) cycle time
Subclock (øSUB) cycle time
5.8.3
Notes on External Input Signal Changes before/after Direct Transition
1. Direct transition from active (high-speed) mode to subactive mode
Since the mode transition is performed via watch mode, see 5.3.5, Notes on External Input
Signal Changes before/after Standby Mode.
2. Direct transition from active (medium-speed) mode to subactive mode
Since the mode transition is performed via watch mode, see 5.3.5, Notes on External Input
Signal Changes before/after Standby Mode.
3. Direct transition from subactive mode to active (high-speed) mode
Since the mode transition is performed via watch mode, see 5.3.5, Notes on External Input
Signal Changes before/after Standby Mode.
4. Direct transition from subactive mode to active (medium-speed) mode
Since the mode transition is performed via watch mode, see 5.3.5, Notes on External Input
Signal Changes before/after Standby Mode.
114
5.9
Module Standby Mode
5.9.1
Setting Module Standby Mode
Module standby mode is set for individual peripheral functions. All the on-chip peripheral
modules can be placed in module standby mode. When a module enters module standby mode,
the system clock supply to the module is stopped and operation of the module halts. This state is
identical to standby mode.
Module standby mode is set for a particular module by setting the corresponding bit to 0 in clock
stop register 1 (CKSTPR1) or clock stop register 2 (CKSTPR2). (See table 5.5.)
5.9.2
Clearing Module Standby Mode
Module standby mode is cleared for a particular module by setting the corresponding bit to 1 in
clock stop register 1 (CKSTPR1) or clock stop register 2 (CKSTPR2). (See table 5.5.)
Following a reset, clock stop register 1 (CKSTPR1) and clock stop register 2 (CKSTPR2) are both
initialized to H'FF.
Table 5.5
Register Name
Bit Name
CKSTPR1
TACKSTP
TFCKSTP
ADCKSTP
S32CKSTP
Operation
1
Timer A module standby mode is cleared
0
Timer A is set to module standby mode
1
Timer F module standby mode is cleared
0
Timer F is set to module standby mode
1
A/D converter module standby mode is cleared
0
A/D converter is set to module standby mode
1
SCI3 module standby mode is cleared
0
SCI3 is set to module standby mode
115
Register Name
Bit Name
CKSTPR2
LDCKSTP
PW1CKSTP
AECKSTP
PW2CKSTP
Operation
1
LCD module standby mode is cleared
0
LCD is set to module standby mode
1
PWM1 module standby mode is cleared
0
PWM1 is set to module standby mode
1
Asynchronous event counter module standby mode
is cleared
0
Asynchronous event counter is set to module standby
mode
1
PWM2 module standby mode is cleared
0
PWM2 is set to module standby mode
Note: For details of module operation, see the sections on the individual modules.
116
Section 6 ROM
6.1
Overview
The H8/3802 has 16 kbytes of on-chip mask ROM, the H8/3801 has 12 kbytes, and the H8/3800
has 8 kbytes. The ROM is connected to the CPU by a 16-bit data bus, allowing high-speed twostate access for both byte data and word data. The H8/3802 has a ZTAT™ version with 16-kbyte
PROM.
6.1.1
Block Diagram
Figure 6.1 shows a block diagram of the on-chip ROM.
Internal data bus (upper 8 bits)
Internal data bus (lower 8 bits)
H'0000
H'0000
H'0001
H'0002
H'0002
H'0003
On-chip ROM
H'3FFE
H'3FFE
H'3FFF
Even-numbered
address
Odd-numbered
address
Figure 6.1 ROM Block Diagram (H8/3802)
117
6.2
H8/3802 PROM Mode
6.2.1
Setting to PROM Mode
If the on-chip ROM is PROM, setting the chip to PROM mode stops operation as a
microcontroller and allows the PROM to be programmed in the same way as the standard
HN27C101 EPROM. However, page programming is not supported. Table 6.1 shows how to set
the chip to PROM mode.
Table 6.1
Setting to PROM Mode
Pin Name
Setting
TEST
High level
PB0/AN0
Low level
PB1/AN1
PB2/AN2
6.2.2
High level
Socket Adapter Pin Arrangement and Memory Map
A standard PROM programmer can be used to program the PROM. A socket adapter is required
for conversion to 32 pins.
Figure 6.2 shows the pin-to-pin wiring of the socket adapter. Figure 6.3 shows a memory map.
118
H8/3802
FP-64A, FP-64E
EPROM socket
DP-64S
Pin
Pin
8
16
RES
VPP
1
40
48
P60
EO0
13
39
47
P61
EO1
14
38
46
P62
EO2
15
37
45
P63
EO3
17
36
44
P64
EO4
18
35
43
P65
EO5
19
34
42
P66
EO6
20
33
41
P67
EO7
21
57
1
P40
EA0
12
58
2
P41
EA1
11
10
18
P32
EA2
10
11
19
P33
EA3
9
12
20
P34
EA4
8
13
21
P35
EA5
7
14
22
P36
EA6
6
15
23
P37
EA7
5
32
40
P70
EA8
27
60
4
P43
EA9
26
30
38
P72
EA10
23
29
37
P73
EA11
25
28
36
P74
EA12
4
27
35
P75
EA13
28
26
34
P76
EA14
29
52
60
P93
EA15
3
53
61
P94
EA16
25
33
P77
CE
22
31
39
P71
OE
24
51
59
P92
PGM
31
16
24
VCC
VCC
32
61
5
AVCC
7
15
TEST
2
10
X1
64
8
PB2
49
57
P90
50
58
P91
54
62
P95
55
63
VSS
VSS
16
4
12
AVSS
62
6
PB0
63
7
PB1
HN27C101 (32-pin)
2
Note: Pins not indicated in the figure should be left open.
Figure 6.2 Socket Adapter Pin Correspondence (with HN27C101)
119
Address in
MCU mode
Address in
PROM mode
H'0000
H'0000
On-chip PROM
H'3FFF
H'3FFF
Uninstalled area*
H'1FFFF
Note: * The output data is not guaranteed if this address area is read in PROM mode. Therefore, when programming with a PROM programmer, be sure to specify addresses
from H'0000 to H'3FFF. If programming is inadvertently performed from H'4000 onward, it may not be possible to continue PROM programming and verification.
When programming, H'FF should be set as the data in this address area (H'4000 to
H'1FFFF).
Figure 6.3 H8/3802 Memory Map in PROM Mode
120
6.3
H8/3802 Programming
The write, verify, and other modes are selected as shown in table 6.2 in H8/3802 PROM mode.
Table 6.2
Mode Selection in PROM Mode (H8/3802)
Pins
Mode
CE
OE
PGM
VPP
VCC
EO7 to EO0
EA 16 to EA0
Write
L
H
L
VPP
VCC
Data input
Address input
Verify
L
L
H
VPP
VCC
Data output
Address input
Programming
L
L
L
VPP
VCC
High impedance
Address input
disabled
L
H
H
H
L
L
H
H
H
Notation
L:
Low level
H:
High level
VPP: VPP level
VCC: VCC level
The specifications for writing and reading are identical to those for the standard HN27C101
EPROM. However, page programming is not supported, and so page programming mode must not
be set. A PROM programmer that only supports page programming mode cannot be used. When
selecting a PROM programmer, ensure that it supports high-speed, high-reliability byte-by-byte
programming. Also, be sure to specify addresses from H'0000 to H'3FFF.
6.3.1
Writing and Verifying
An efficient, high-speed, high-reliability method is available for writing and verifying the PROM
data. This method achieves high speed without voltage stress on the device and without lowering
the reliability of written data. The basic flow of this high-speed, high-reliability programming
method is shown in figure 6.4.
121
Start
Set write/verify mode
VCC = 6.0 V ± 0.25 V, VPP = 12.5 V ± 0.3 V
Address = 0
n=0
n+1 →n
No
Yes
n < 25
Write time t PW = 0.2 ms ± 5%
No Go
Address + 1 → address
Verify
Go
Write time tOPW = 0.2n ms
Last address?
No
Yes
Set read mode
VCC = 5.0 V ± 0.25 V, V PP = VCC
No Go
Error
Read all
addresses?
Go
End
Figure 6.4 High-Speed, High-Reliability Programming Flow Chart
122
Table 6.3 and table 6.4 give the electrical characteristics in programming mode.
Table 6.3
DC Characteristics
(Conditions: VCC = 6.0 V ±0.25 V, VPP = 12.5 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C)
Item
Symbol Min
Typ
Max
Unit
Test
Condition
Input highlevel voltage
EO7 to EO 0, EA16 to EA 0 VIH
OE, CE, PGM
2.4
—
VCC + 0.3 V
Input lowlevel voltage
EO7 to EO 0, EA16 to EA 0 VIL
OE, CE, PGM
–0.3
—
0.8
V
Output highlevel voltage
EO7 to EO 0
VOH
2.4
—
—
V
I OH = –200 µA
Output lowlevel voltage
EO7 to EO 0
VOL
—
—
0.45
V
I OL = 0.8 mA
Input leakage EO7 to EO 0, EA16 to EA 0 |ILI|
current
OE, CE, PGM
—
—
2
µA
Vin = 5.25 V/
0.5 V
VCC current
I CC
—
—
40
mA
VPP current
I PP
—
—
40
mA
123
Table 6.4
AC Characteristics
(Conditions: VCC = 6.0 V ±0.25 V, VPP = 12.5 V ±0.3 V, Ta = 25°C ±5°C)
Item
Symbol
Min
Typ
Max
Unit
Test Condition
Address setup time
t AS
2
—
—
µs
Figure 6.5 *1
OE setup time
t OES
2
—
—
µs
Data setup time
t DS
2
—
—
µs
Address hold time
t AH
0
—
—
µs
Data hold time
t DH
2
—
—
µs
—
—
130
ns
2
—
—
µs
0.19
0.20
0.21
ms
0.19
—
5.25
ms
*2
Data output disable time
t DF
VPP setup time
t VPS
Programming pulse width
t PW
PGM pulse width for overwrite
programming
t OPW
CE setup time
t CES
2
—
—
µs
VCC setup time
t VCS
2
—
—
µs
Data output delay time
t OE
0
—
200
ns
*3
Notes: 1. Input pulse level: 0.45 V to 2.2 V
Input rise time/fall time ≤ 20 ns
Timing reference levels Input: 0.8 V, 2.0 V
Output: 0.8 V, 2.0 V
2. t DF is defined at the point at which the output is floating and the output level cannot be
read.
3. t OPW is defined by the value given in figure 6.4, High-Speed, High-Reliability
Programming Flow Chart.
124
Figure 6.5 shows a PROM write/verify timing diagram.
Write
Verify
Address
tAS
Data
tAH
Input data
tDS
VPP
tDH
tDF
VPP
VCC
VCC
Output data
tVPS
VCC+1
VCC
tVCS
CE
tCES
PGM
tPW
tOES
tOE
OE
tOPW*
Note: * tOPW is defined by the value shown in figure 6.4, High-Speed, High-Reliability Programming Flowchart.
Figure 6.5 PROM Write/Verify Timing
125
6.3.2
Programming Precautions
• Use the specified programming voltage and timing.
The programming voltage in PROM mode (VPP) is 12.5 V. Use of a higher voltage can
permanently damage the chip. Be especially careful with respect to PROM programmer
overshoot.
Setting the PROM programmer to Hitachi specifications for the HN27C101 will result in
correct VPP of 12.5 V.
• Make sure the index marks on the PROM programmer socket, socket adapter, and chip are
properly aligned. If they are not, the chip may be destroyed by excessive current flow. Before
programming, be sure that the chip is properly mounted in the PROM programmer.
• Avoid touching the socket adapter or chip while programming, since this may cause contact
faults and write errors.
• Take care when setting the programming mode, as page programming is not supported.
• When programming with a PROM programmer, be sure to specify addresses from H'0000 to
H'3FFF. If programming is inadvertently performed from H'4000 onward, it may not be
possible to continue PROM programming and verification. When programming, H'FF should
be set as the data in address area H'4000 to H'1FFFF.
126
6.4
Reliability of Programmed Data
A highly effective way to improve data retention characteristics is to bake the programmed chips
at 150°C, then screen them for data errors. This procedure quickly eliminates chips with PROM
memory cells prone to early failure.
Figure 6.6 Shows the recommended screening procedure.
Program chip and verify
programmed data
Bake chip for 24 to 48 hours at
125°C to 150°C with power off
Read and check program
Install
Figure 6.6 Recommended Screening Procedure
If a series of programming errors occurs while the same PROM programmer is in use, stop
programming and check the PROM programmer and socket adapter for defects. Please inform
Hitachi of any abnormal conditions noted during or after programming or in screening of program
data after high-temperature baking.
127
128
Section 7 RAM
7.1
Overview
The H8/3802 has 1 kbyte of high-speed static RAM on-chip, and the H8/3801 and H8/3800 have
512 bytes. The RAM is connected to the CPU by a 16-bit data bus, allowing high-speed 2-state
access for both byte data and word data.
7.1.1
Block Diagram
Figure 7.1 shows a block diagram of the on-chip RAM.
Internal data bus (upper 8 bits)
Internal data bus (lower 8 bits)
H'FB80
H'FB80
H'FB81
H'FB82
H'FB82
H'FB83
On-chip RAM
H'FF7E
H'FF7E
H'FF7F
Even-numbered
address
Odd-numbered
address
Figure 7.1 RAM Block Diagram (H8/3802)
129
130
Section 8 I/O Ports
8.1
Overview
The H8/3802 Series is provided with three 8-bit I/O ports, one 7-bit I/O port, one 4-bit I/O port,
one 3-bit I/O port, one 1-bit I/O port, one 4-bit input-only port, one 1-bit input-only port, and one
6-bit output-only port. Table 8.1 indicates the functions of each port.
Each port has of a port control register (PCR) that controls input and output, and a port data
register (PDR) for storing output data. Input or output can be assigned to individual bits.
See 2.9.2, Notes on Bit Manipulation, for information on executing bit-manipulation instructions
to write data in PCR or PDR.
Ports 5, 6, 7, 8, and A are also used as liquid crystal display segment and common pins, selectable
in 4-bit units.
Block diagrams of each port are given in Appendix C, I/O Port Block Diagrams.
Table 8.1
Port Functions
Function
Switching
Registers
Port
Description
Pins
Other Functions
Port 3
•
7-bit I/O port
•
MOS input pull-up
option
P37/AEVL
P36/AEVH
P35, P3 4, P3 3
Asynchronous event counter PMR3
event inputs AEVL, AEVH
•
Large-current port
P32, TMOFH
P31, TMOFL
Timer F output compare
output
PMR3
Port 4
Port 5
•
1-bit input port
P43/IRQ0
External interrupt 0
PMR2
•
3-bit I/O port
P42/TXD32
P41/RXD32
P40/SCK32
SCI3 data output (TXD32),
data input (RXD32), clock
input/output (SCK32)
SCR3
SMR
•
8-bit I/O port
•
MOS input pull-up
option
P57 to P5 0/
WKP 7 to WKP 0/
SEG8 to SEG 1
Wakeup input (WKP 7 to
WKP 0), segment output
(SEG8 to SEG 1)
PMR5
LPCR
131
Function
Switching
Registers
Port
Description
Pins
Other Functions
Port 6
•
8-bit I/O port
MOS input pull-up
option
Segment output (SEG16 to
SEG9)
LPCR
•
P67 to P6 0/
SEG16 to SEG 9
Port 7
•
8-bit I/O port
P77 to P7 0/
SEG24 to SEG 17
Segment output (SEG24 to
SEG17)
LPCR
Port 8
•
1-bit I/O port
P80/SEG 25,
Segment output
LPCR
Port 9
•
6-bit output port
P95 to P9 2
None
•
High-voltage, large- P91, P90/
PWM2, PWM1
current port
•
High-voltage port
10-bit PWM output
IRQAEC
None
PMR9
Port A
4-bit I/O port
PA3 to PA 0/
COM4 to COM1
Common output (COM4 to
COM1)
LPCR
Port B
4-bit input port
PB3 to PB 0/
AN 3 to AN0
A/D converter analog input
AMR
132
8.2
Port 3
8.2.1
Overview
Port 3 is a 7-bit I/O port, configured as shown in figure 8.1.
P3 7 /AEVL
P3 6 /AEVH
P3 5
P3 4
Port 3
P3 3
P3 2 /TMOFH
P3 1 /TMOFL
Figure 8.1 Port 3 Pin Configuration
8.2.2
Register Configuration and Description
Table 8.2 shows the port 3 register configuration.
Table 8.2
Port 3 Registers
Name
Abbrev.
R/W
Initial Value
Address
Port data register 3
PDR3
R/W
—
H'FFD6
Port control register 3
PCR3
W
—
H'FFE6
Port pull-up control register 3
PUCR3
R/W
—
H'FFE1
Port mode register 3
PMR3
R/W
—
H'FFCA
Port mode register 2
PMR2
R/W
—
H'FFC9
133
1. Port data register 3 (PDR3)
Bit
7
6
5
4
3
2
1
0
P3 7
P36
P35
P34
P3 3
P32
P31
—
Initial value
0
0
0
0
0
0
0
—
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
PDR3 is an 8-bit register that stores data for port 3 pins P37 to P31. If port 3 is read while PCR3
bits are set to 1, the values stored in PDR3 are read, regardless of the actual pin states. If port 3 is
read while PCR3 bits are cleared to 0, the pin states are read.
2. Port control register 3 (PCR3)
Bit
7
6
5
4
3
2
1
0
PCR3 7
PCR3 6
PCR3 5
PCR34
PCR3 3
PCR3 2
PCR31
—
Initial value
0
0
0
0
0
0
0
—
Read/Write
W
W
W
W
W
W
W
W
PCR3 is an 8-bit register for controlling whether each of the port 3 pins P37 to P31 functions as an
input pin or output pin. Setting a PCR3 bit to 1 makes the corresponding pin an output pin, while
clearing the bit to 0 makes the pin an input pin. The settings in PCR3 and in PDR3 are valid only
when the corresponding pin is designated in PMR3 as a general I/O pin.
PCR3 is a write-only register. Bits 7 to 1 are always read as 1. Bit 0 is reserved; only 0 can be
written to this bit.
3. Port pull-up control register 3 (PUCR3)
Bit
7
6
5
4
3
2
1
PUCR37 PUCR36 PUCR3 5 PUCR34 PUCR3 3 PUCR3 2 PUCR31
0
—
Initial value
0
0
0
0
0
0
0
—
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
PUCR3 controls whether the MOS pull-up of each of the port 3 pins P37 to P31 is on or off. When
a PCR3 bit is cleared to 0, setting the corresponding PUCR3 bit to 1 turns on the MOS pull-up for
the corresponding pin, while clearing the bit to 0 turns off the MOS pull-up.
Bit 0 is reserved; only 0 can be written to this bit.
134
4. Port mode register 3 (PMR3)
Bit
7
6
5
4
3
2
1
0
AEVL
AEVH
—
—
—
TMOFH
TMOFL
—
Initial value
0
0
—
—
—
0
0
—
Read/Write
R/W
R/W
W
W
W
R/W
R/W
W
PMR3 is an 8-bit read/write register, controlling the selection of pin functions for port 3 pins.
Bit 7: P37/AEVL pin function switch (AEVL)
This bit selects whether pin P37/AEVL is used as P37 or as AEVL.
Bit 7
AEVL
Description
0
Functions as P3 7 I/O pin
1
Functions as AEVL input pin
(initial value)
Bit 6: P36/AEVH pin function switch (AEVH)
This bit selects whether pin P36/AEVH is used as P36 or as AEVH.
Bit 6
AEVH
Description
0
Functions as P3 6 I/O pin
1
Functions as AEVH input pin
(initial value)
Bits 5 to 3: Reserved bits
Bits 5 to 3 are reserved; only 0 can be written to these bits.
Bit 2: P32/TMOFH pin function switch (TMOFH)
This bit selects whether pin P32/TMOFH is used as P32 or as TMOFH.
Bit 2
TMOFH
Description
0
Functions as P3 2 I/O pin
1
Functions as TMOFH output pin
(initial value)
135
Bit 1: P31/TMOFL pin function switch (TMOFL)
This bit selects whether pin P31/TMOFL is used as P3 1 or as TMOFL.
Bit 1
TMOFL
Description
0
Functions as P3 1 I/O pin
1
Functions as TMOFL output pin
(initial value)
Bit 0: Reserved bit
Bit 0 is reserved; only 0 can be written to this bit.
5. Port mode register 2 (PMR2)
Bit
7
6
5
4
3
2
1
0
—
—
POF1
—
—
—
—
IRQ0
Initial value
1
1
0
1
1
—
—
0
Read/Write
—
—
R/W
—
—
W
W
R/W
PMR2 is an 8-bit read/write register controlling the PMOS on/off state for the P3 5 pin.
Bit 5: P3 5 pin PMOS control (POF1)
This bit controls the on/off state of the P3 5 pin output buffer PMOS.
Bit 5
POF1
Description
0
CMOS output
1
NMOS open-drain output
136
(initial value)
8.2.3
Pin Functions
Table 8.3 shows the port 3 pin functions.
Table 8.3
Port 3 Pin Functions
Pin
Pin Functions and Selection Method
P37/AEVL
The pin function depends on bit AEVL in PMR3 and bit PCR32 in PCR3.
AEVL
P36/AEVH
0
PCR37
0
1
*
Pin function
P37 input pin
P37 output pin
AEVL input pin
The pin function depends on bit AEVH in PMR3 and bit PCR3 6 in PCR3.
AEVH
P35 to P3 3
1
0
1
PCR36
0
1
*
Pin function
P36 input pin
P36 output pin
AEVH input pin
The pin function depends on the corresponding bit in PCR3.
PCR3n
0
1
Pin function
P3n input pin
P3n output pin
(n = 5 to 3)
P32/TMOFH
The pin function depends on bit TMOFH in PMR3 and bit PCR32 in PCR3.
TMOFH
P31/TMOFL
0
1
PCR32
0
1
*
Pin function
P32 input pin
P32 output pin
TMOFH output pin
The pin function depends on bit TMOFL in PMR3 and bit PCR3 1 in PCR3.
TMOFL
0
1
PCR31
0
1
*
Pin function
P31 input pin
P31 output pin
THOFL output pin
*: Don’t care
137
8.2.4
Pin States
Table 8.4 shows the port 3 pin states in each operating mode.
Table 8.4
Port 3 Pin States
Pins
Reset
Sleep
Subsleep Standby
P37/AEVL
P36/AEVH
P35
P34
P33
P32/TMOFH
P31/TMOFL
Highimpedance
Retains Retains
previous previous
state
state
Watch
Subactive Active
HighRetains Functional Functional
impedance* previous
state
Note: * A high-level signal is output when the MOS pull-up is in the on state.
8.2.5
MOS Input Pull-Up
Port 3 has a built-in MOS input pull-up function that can be controlled by software. When a
PCR3 bit is cleared to 0, setting the corresponding PUCR3 bit to 1 turns on the MOS pull-up for
that pin. The MOS pull-up function is in the off state after a reset.
PCR3n
0
0
1
PUCR3n
0
1
*
MOS input pull-up
Off
On
Off
(n = 7 to 1)
*: Don’t care
138
8.3
Port 4
8.3.1
Overview
Port 4 is a 3-bit I/O port and 1-bit input port, configured as shown in figure 8.2.
P4 3 /IRQ0
P4 2 /TXD32
Port 4
P4 1 /RXD32
P4 0 /SCK32
Figure 8.2 Port 4 Pin Configuration
8.3.2
Register Configuration and Description
Table 8.5 shows the port 4 register configuration.
Table 8.5
Port 4 Registers
Name
Abbrev.
R/W
Initial Value
Address
Port data register 4
PDR4
R/W
H'F8
H'FFD7
Port control register 4
PCR4
W
H'F8
H'FFE7
Port mode register 2
PMR2
R/W
—
H'FFC9
1. Port data register 4 (PDR4)
Bit
7
6
5
4
3
2
1
0
—
—
—
—
P43
P4 2
P4 1
P4
Initial value
1
1
1
1
1
0
0
0
Read/Write
—
—
—
—
R
R/W
R/W
R/W
0
PDR4 is an 8-bit register that stores data for port 4 pins P42 to P40. If port 4 is read while PCR4
bits are set to 1, the values stored in PDR4 are read, regardless of the actual pin states. If port 4 is
read while PCR4 bits are cleared to 0, the pin states are read.
Upon reset, PDR4 is initialized to H'F8.
139
2. Port control register 4 (PCR4)
Bit
7
6
5
4
3
2
1
0
—
—
—
—
—
PCR42
PCR4 1
PCR4 0
Initial value
1
1
1
1
1
0
0
0
Read/Write
—
—
—
—
—
W
W
W
PCR4 is an 8-bit register for controlling whether each of port 4 pins P42 to P40 functions as an
input pin or output pin. Setting a PCR4 bit to 1 makes the corresponding pin an output pin, while
clearing the bit to 0 makes the pin an input pin. PCR4 and PDR4 settings are valid when the
corresponding pins are designated for general-purpose input/output by SCR3-2.
Upon reset, PCR4 is initialized to H'F8.
PCR4 is a write-only register, which is always read as all 1s.
3. Port mode register 2 (PMR2)
Bit
7
6
5
4
3
2
1
0
—
—
POF1
—
—
—
—
IRQ0
Initial value
1
1
0
1
1
—
—
0
Read/Write
—
—
R/W
—
—
W
W
R/W
PMR2 is an 8-bit read/write register controlling the selection of the P43/IRQ0 pin function and the
PMOS on/off state for the P35 pin. Upon reset, PMR2 is initialized to H'DE.
Bits 7, 6, 4, and 3: Reserved bits
Bits 7, 6, and 4 to 1 are reserved; they are always read as 1 and cannot be modified.
Bit 5: P3 5 pin PMOS control (POF1)
This bit controls the on/off state of the P3 5 pin output buffer PMOS.
Bit 5
POF1
Description
0
CMOS output
1
NMOS open-drain output
Bits 2 and 1: Reserved bits
Bits 2 and 1 are reserved; only 0 can be written to these bits.
140
(initial value)
Bit 0: P43/IRQ0 pin function switch (IRQ0)
This bit selects whether pin P43/IRQ0 is used as P43 or as IRQ0.
Bit 0
IRQ0
Description
0
Functions as P4 3 input pin
1
Functions as IRQ0 input pin
8.3.3
(initial value)
Pin Functions
Table 8.6 shows the port 4 pin functions.
Table 8.6
Port 4 Pin Functions
Pin
Pin Functions and Selection Method
P43/IRQ0
The pin function depends on bit IRQ0 in PMR2.
P42/TXD32
P41/RXD32
IRQ0
0
1
Pin function
P43 input pin
IRQ0 input pin
The pin function depends on bit TE in SCR3, bit SPC32 in SPCR, and bit PCR4 2
in PCR4.
SPC32
0
1
TE
0
1
PCR42
0
1
*
Pin function
P42 input pin
P42 output pin
TXD32 output pin
The pin function depends on bit RE in SCR3 and bit PCR4 1 in PCR4.
RE
0
1
PCR41
0
1
*
Pin function
P41 input pin
P41 output pin
RXD32 input pin
141
Pin
Pin Functions and Selection Method
P40/SCK32
The pin function depends on bit CKE1 and CKE0 in SCR3, bit COM in SMR, and
bit PCR40 in PCR4.
CKE1
0
CKE0
1
0
COM
0
PCR40
Pin function
0
1
1
*
1
*
*
*
*
P40 input pin P40 output pin SCK 32 output SCK 32 input
pin
pin
*: Don’t care
8.3.4
Pin States
Table 8.7 shows the port 4 pin states in each operating mode.
Table 8.7
Port 4 Pin States
Pins
Reset
P43/IRQ0
P42/TXD32
P41/RXD32
P40/SCK32
HighRetains Retains
impedance previous previous
state
state
142
Sleep
Subsleep Standby
Watch
Subactive Active
HighRetains Functional Functional
impedance previous
state
8.4
Port 5
8.4.1
Overview
Port 5 is an 8-bit I/O port, configured as shown in figure 8.3.
P57/WKP7/SEG8
P56/WKP6/SEG7
P55/WKP5/SEG6
P54/WKP4/SEG5
Port 5
P53/WKP3/SEG4
P52/WKP2/SEG3
P51/WKP1/SEG2
P50/WKP0/SEG1
Figure 8.3 Port 5 Pin Configuration
8.4.2
Register Configuration and Description
Table 8.8 shows the port 5 register configuration.
Table 8.8
Port 5 Registers
Name
Abbrev.
R/W
Initial Value
Address
Port data register 5
PDR5
R/W
H'00
H'FFD8
Port control register 5
PCR5
W
H'00
H'FFE8
Port pull-up control register 5
PUCR5
R/W
H'00
H'FFE2
Port mode register 5
PMR5
R/W
H'00
H'FFCC
143
1. Port data register 5 (PDR5)
Bit
7
6
5
4
3
2
1
0
P5 7
P5 6
P55
P5 4
P53
P52
P51
P5 0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PDR5 is an 8-bit register that stores data for port 5 pins P57 to P50. If port 5 is read while PCR5
bits are set to 1, the values stored in PDR5 are read, regardless of the actual pin states. If port 5 is
read while PCR5 bits are cleared to 0, the pin states are read.
Upon reset, PDR5 is initialized to H'00.
2. Port control register 5 (PCR5)
Bit
7
6
5
4
3
2
1
0
PCR57
PCR56
PCR55
PCR54
PCR53
PCR52
PCR51
PCR50
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
PCR5 is an 8-bit register for controlling whether each of the port 5 pins P57 to P50 functions as an
input pin or output pin. Setting a PCR5 bit to 1 makes the corresponding pin an output pin, while
clearing the bit to 0 makes the pin an input pin. PCR5 and PDR5 settings are valid when the
corresponding pins are designated for general-purpose input/output by PMR5 and bits SGS3 to
SGS0 in LPCR.
Upon reset, PCR5 is initialized to H'00.
PCR5 is a write-only register, which is always read as all 1s.
3. Port pull-up control register 5 (PUCR5)
Bit
7
6
5
4
3
2
1
0
PUCR57 PUCR56 PUCR55 PUCR54 PUCR53 PUCR52 PUCR51 PUCR50
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PUCR5 controls whether the MOS pull-up of each of port 5 pins P5 7 to P50 is on or off. When a
PCR5 bit is cleared to 0, setting the corresponding PUCR5 bit to 1 turns on the MOS pull-up for
the corresponding pin, while clearing the bit to 0 turns off the MOS pull-up.
Upon reset, PUCR5 is initialized to H'00.
144
4. Port mode register 5 (PMR5)
Bit
7
6
5
4
3
2
1
0
WKP7
WKP6
WKP5
WKP4
WKP3
WKP2
WKP1
WKP0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PMR5 is an 8-bit read/write register, controlling the selection of pin functions for port 5 pins.
Upon reset, PMR5 is initialized to H'00.
Bit n: P5n/WKPn/SEGn+1 pin function switch (WKPn)
When pin P5n/WKPn/SEGn+1 is not used as SEGn+1 , these bits select whether the pin is used as
P5n or WKPn.
Bit n
WKPn
Description
0
Functions as P5n I/O pin
1
Functions as WKP n input pin
(initial value)
(n = 7 to 0)
Note: For use as SEGn+1, see 13.2.1, LCD Port Control Register (LPCR).
145
8.4.3
Pin Functions
Table 8.9 shows the port 5 pin functions.
Table 8.9
Port 5 Pin Functions
Pin
Pin Functions and Selection Method
P57/WKP 7/
SEG8 to
The pin function depends on bit WKP n in PMR5, bit PCR5n in PCR5, and bits
SGS3 to SGS0 in LPCR.
P50/WKP 0/
SEG1
P57 to P5 4
SGS3 to SGS0
(n = 7 to 4)
Other than 0010, 0011, 0100, 0101, 0110,
0111, 1000, 1001
WKP n
PCR5n
Pin function
0
0
1
P5n input pin P5n output pin
1
*
*
*
WKPn input
pin
SEGn+1
output pin
P53 to P5 0
SGS3 to SGS0
0010, 0011,
0100, 0101,
0110, 0111,
1000, 1001
(m= 3 to 0)
Other than 0001, 0010, 0011, 0100, 0101,
0110, 0111, 1000
WKP m
0
0001, 0010,
0011, 0100,
0101, 0110,
0111, 1000
1
*
PCR5m
0
1
*
*
Pin function
P5m input pin
P5m output
pin
WKPm output
pin
SEGm+1
output pin
*: Don’t care
146
8.4.4
Pin States
Table 8.10 shows the port 5 pin states in each operating mode.
Table 8.10 Port 5 Pin States
Pins
Reset
Sleep
Subsleep Standby
P57/WKP 7/
SEG8 to P5 0/
WKP 0/SEG 1
HighRetains Retains
impedance previous previous
state
state
Watch
Subactive Active
HighRetains Functional Functional
impedance* previous
state
Note: * A high-level signal is output when the MOS pull-up is in the on state.
8.4.5
MOS Input Pull-Up
Port 5 has a built-in MOS input pull-up function that can be controlled by software. When a
PCR5 bit is cleared to 0, setting the corresponding PUCR5 bit to 1 turns on the MOS pull-up for
that pin. The MOS pull-up function is in the off state after a reset.
PCR5n
0
0
1
PUCR5n
0
1
*
MOS input pull-up
Off
On
Off
(n = 7 to 0)
*: Don’t care
147
8.5
Port 6
8.5.1
Overview
Port 6 is an 8-bit I/O port. The port 6 pin configuration is shown in figure 8.4.
P67/SEG16
P66/SEG15
P65/SEG14
P64/SEG13
Port 6
P63/SEG12
P62/SEG11
P61/SEG10
P60/SEG9
Figure 8.4 Port 6 Pin Configuration
8.5.2
Register Configuration and Description
Table 8.11 shows the port 6 register configuration.
Table 8.11 Port 6 Registers
Name
Abbrev.
R/W
Initial Value
Address
Port data register 6
PDR6
R/W
H'00
H'FFD9
Port control register 6
PCR6
W
H'00
H'FFE9
Port pull-up control register 6
PUCR6
R/W
H'00
H'FFE3
148
1. Port data register 6 (PDR6)
Bit
7
6
5
4
3
2
1
0
P6 7
P66
P65
P64
P6 3
P62
P61
P6 0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PDR6 is an 8-bit register that stores data for port 6 pins P67 to P60.
If port 6 is read while PCR6 bits are set to 1, the values stored in PDR6 are read, regardless of the
actual pin states. If port 6 is read while PCR6 bits are cleared to 0, the pin states are read.
Upon reset, PDR6 is initialized to H'00.
2. Port control register 6 (PCR6)
Bit
7
6
5
4
3
2
1
0
PCR67
PCR66
PCR65
PCR64
PCR63
PCR62
PCR61
PCR60
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
PCR6 is an 8-bit register for controlling whether each of the port 6 pins P67 to P60 functions as an
input pin or output pin.
Setting a PCR6 bit to 1 makes the corresponding pin (P6 7 to P60) an output pin, while clearing the
bit to 0 makes the pin an input pin. PCR6 and PDR6 settings are valid when the corresponding
pins are designated for general-purpose input/output by bits SGS3 to SGS0 in LPCR.
Upon reset, PCR6 is initialized to H'00.
PCR6 is a write-only register, which is always read as all 1s.
149
3. Port pull-up control register 6 (PUCR6)
Bit
7
6
5
4
3
2
0
1
PUCR67 PUCR66 PUCR6 5 PUCR64 PUCR6 3 PUCR6 2 PUCR61 PUCR60
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PUCR6 controls whether the MOS pull-up of each of the port 6 pins P67 to P60 is on or off. When
a PCR6 bit is cleared to 0, setting the corresponding PUCR6 bit to 1 turns on the MOS pull-up for
the corresponding pin, while clearing the bit to 0 turns off the MOS pull-up.
Upon reset, PUCR6 is initialized to H'00.
8.5.3
Pin Functions
Table 8.12 shows the port 6 pin functions.
Table 8.12 Port 6 Pin Functions
Pin
Pin Functions and Selection Method
P67/SEG 16 to
P60/SEG 9
The pin function depends on bit PCR6n in PCR6 and bits SGS3 to SGS0 in
LPCR.
P67 to P6 4
SEG3 to SEGS0
(n = 7 to 4)
Other than 0100, 0101, 0110, 0111,
1000, 1001, 1010, 1011
0100, 0101, 0110,
0111, 1000, 1001,
1010, 1011
PCR6n
0
1
*
Pin function
P6n input pin
P6n output pin
SEGn+9 output pin
P63 to P6 0
SEG3 to SEGS0
(m = 3 to 0)
Other than 0011, 0100, 0101, 0110,
0111, 1000, 1001, 1010
0011, 0100, 0101,
0110, 0111, 1000,
1001, 1010
PCR6m
0
1
*
Pin function
P6m input pin
P6m output pin
SEGn+9 output pin
*: Don’t care
150
8.5.4
Pin States
Table 8.13 shows the port 6 pin states in each operating mode.
Table 8.13 Port 6 Pin States
Pin
Reset
Sleep
Subsleep Standby
P67/SEG 16 to
P60/SEG 9
HighRetains Retains
impedance previous previous
state
state
Watch
Subactive Active
HighRetains Functional Functional
impedance* previous
state
Note: * A high-level signal is output when the MOS pull-up is in the on state.
8.5.5
MOS Input Pull-Up
Port 6 has a built-in MOS pull-up function that can be controlled by software. When a PCR6 bit is
cleared to 0, setting the corresponding PUCR6 bit to 1 turns on the MOS pull-up for that pin. The
MOS pull-up function is in the off state after a reset.
PCR6n
0
0
1
PUCR6n
0
1
*
MOS input pull-up
Off
On
Off
(n = 7 to 0)
*: Don’t care
151
8.6
Port 7
8.6.1
Overview
Port 7 is an 8-bit I/O port, configured as shown in figure 8.5.
P77/SEG24
P76/SEG23
P75/SEG22
P74/SEG21
Port 7
P73/SEG20
P72/SEG19
P71/SEG18
P70/SEG17
Figure 8.5 Port 7 Pin Configuration
8.6.2
Register Configuration and Description
Table 8.14 shows the port 7 register configuration.
Table 8.14 Port 7 Registers
Name
Abbrev.
R/W
Initial Value
Address
Port data register 7
PDR7
R/W
H'00
H'FFDA
Port control register 7
PCR7
W
H'00
H'FFEA
152
1. Port data register 7 (PDR7)
Bit
7
6
5
4
3
2
1
0
P7 7
P7 6
P75
P7 4
P73
P72
P71
P70
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PDR7 is an 8-bit register that stores data for port 7 pins P77 to P70. If port 7 is read while PCR7
bits are set to 1, the values stored in PDR7 are read, regardless of the actual pin states. If port 7 is
read while PCR7 bits are cleared to 0, the pin states are read.
Upon reset, PDR7 is initialized to H'00.
2. Port control register 7 (PCR7)
Bit
7
6
5
4
3
2
1
0
PCR77
PCR76
PCR75
PCR74
PCR73
PCR72
PCR71
PCR70
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
PCR7 is an 8-bit register for controlling whether each of the port 7 pins P77 to P70 functions as an
input pin or output pin. Setting a PCR7 bit to 1 makes the corresponding pin an output pin, while
clearing the bit to 0 makes the pin an input pin. PCR7 and PDR7 settings are valid when the
corresponding pins are designated for general-purpose input/output by bits SGS3 to SGS0 in
LPCR.
Upon reset, PCR7 is initialized to H'00.
PCR7 is a write-only register, which is always read as all 1s.
153
8.6.3
Pin Functions
Table 8.15 shows the port 7 pin functions.
Table 8.15 Port 7 Pin Functions
Pin
Pin Functions and Selection Method
P77/SEG 24 to
P70/SEG 17
The pin function depends on bit PCR7n in PCR7 and bits SGS3 to SGS0 in
LPCR.
P77 to P7 4
(n = 7 to 4)
SEGS3 to SEGS0
Other than 0110, 0111, 1000, 1001,
1010, 1011, 1100, 1101
0110, 0111, 1000,
1001, 1010, 1011,
1100, 1101
PCR7n
0
1
*
Pin function
P7n input pin
P7n output pin
SEGn+17 output pin
P73 to P7 0
(m = 3 to 0)
SEGS3 to SEGS0
Other than 0101, 0110, 0111, 1000,
1001, 1010, 1011, 1100
0101, 0110, 0111,
1000, 1001, 1010,
1011, 1100
PCR7m
0
1
*
Pin function
P7m input pin
P7m output pin
SEGm+17 output
pin
*: Don’t care
8.6.4
Pin States
Table 8.16 shows the port 7 pin states in each operating mode.
Table 8.16 Port 7 Pin States
Pins
Reset
P77/SEG 24 to
P70/SEG 17
HighRetains Retains
impedance previous previous
state
state
154
Sleep
Subsleep Standby
Watch
Subactive Active
HighRetains Functional Functional
impedance previous
state
8.7
Port 8
8.7.1
Overview
Port 8 is an 1-bit I/O port configured as shown in figure 8.6.
P80/SEG25
Port 8
Figure 8.6 Port 8 Pin Configuration
8.7.2
Register Configuration and Description
Table 8.17 shows the port 8 register configuration.
Table 8.17 Port 8 Registers
Name
Abbrev.
R/W
Initial Value
Address
Port data register 8
PDR8
R/W
—
H'FFDB
Port control register 8
PCR8
W
—
H'FFEB
155
1. Port data register 8 (PDR8)
Bit
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
P8 0
Initial value
—
—
—
—
—
—
—
0
Read/Write
—
—
—
—
—
—
—
R/W
PDR8 is an 8-bit register that stores data for port 8 pin P80. If port 8 is read while PCR8 bits are
set to 1, the values stored in PDR8 are read, regardless of the actual pin states. If port 8 is read
while PCR8 bits are cleared to 0, the pin states are read.
2. Port control register 8 (PCR8)
Bit
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
PCR8
Initial value
—
—
—
—
—
—
—
0
Read/Write
W
W
W
W
W
W
W
W
PCR8 is an 8-bit register for controlling whether the port 8 pin P80 functions as an input or output
pin. Setting a PCR8 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0
makes the pin an input pin. PCR8 and PDR8 settings are valid when the corresponding pins are
designated for general-purpose input/output by bits SGS3 to SGS0 in LPCR.
PCR8 is a write-only register, which is always read as all 1s.
Bits 7 to 1: Reserved bits
Bits 7 to 1 are reserved; only 0 can be written to these bits.
156
8.7.3
Pin Functions
Table 8.18 shows the port 8 pin functions.
Table 8.18 Port 8 Pin Functions
Pin
Pin Functions and Selection Method
P80/SEG 25
The pin function depends on bit PCR8n in PCR8 and bits SGS3 to SGS0 in LPCR.
SEGS3 to SEGS0 Other than 0111, 1000, 1001, 1010, 1011,
1100, 1101, 1110
0111, 1000, 1001,
1010, 1011, 1100,
1101, 1110
PCR80
0
1
*
Pin function
P80 input pin
P80 output pin
SEG25 output pin
*: Don’t care
8.7.4
Pin States
Table 8.19 shows the port 8 pin states in each operating mode.
Table 8.19 Port 8 Pin States
Pins
Reset
Sleep
Subsleep Standby
P80/SEG 25
HighRetains Retains
impedance previous previous
state
state
Watch
Subactive Active
HighRetains Functional Functional
impedance previous
state
157
8.8
Port 9
8.8.1
Overview
Port 9 is a 6-bit output-only port, configured as shown in figure 8.7.
P95
P94
P93
Port 9
P92
P91/PWM2
P90/PWM1
Figure 8.7 Port 5 Pin Configuration
8.8.2
Register Configuration and Description
Table 8.20 shows the port 9 register configuration.
Table 8.20 Port 9 Registers
Name
Abbrev.
R/W
Initial Value
Address
Port data register 9
PDR9
R/W
H'FF
H'FFDC
Port mode register 9
PMR9
R/W
—
H'FFEC
1. Port data register 9 (PDR9)
Bit
7
6
5
4
3
2
1
0
—
—
P95
P9 4
P93
P92
P91
P9 0
Initial value
1
1
1
1
1
1
1
1
Read/Write
—
—
R/W
R/W
R/W
R/W
R/W
R/W
PDR9 is an 8-bit register that stores data for port 9 pins P95 to P90.
Upon reset, PDR9 is initialized to H'FF.
158
2. Port mode register 9 (PMR9)
Bit
7
6
5
4
3
2
1
0
—
—
—
—
PIOFF
—
PWM2
PWM1
Initial value
1
1
1
1
0
—
0
0
Read/Write
—
—
—
—
R/W
W
R/W
R/W
PMR9 is an 8-bit read/write register controlling the selection of the P90 and P91 pin functions.
Bit 3: P9 2 to P90 step-up circuit control (PIOFF)
Bit 3 turns the P92 to P90 step-up circuit on and off.
Bit 3
PIOFF
Description
0
Large-current port step-up circuit is turned on
1
Large-current port step-up circuit is turned off
(initial value)
Note: When turning the step-up circuit on or off, the register must be rewritten only when the
buffer NMOS is off (port data is 1).
When turning the step-up circuit on, first clear PIOFF to 0, then wait for the elapse of 30
system clock before turning the buffer NMOS on (clearing port data to 0).
Without the elapse of the 30 system clock interval the step-up circuit will not start up, and it
will not be possible for a large current to flow, making operation unstable.
Port 9 Pin Output Low Level Permitted Currents
Pin
Symbol
Test Conditions
P92 to P9 0
I OL
VCC = 1.8 V to 5.5 V* —
P93 to P9 5
Min
—
Typ
Max
PIOFF Bit Value
—
25 mA*
0
10 mA
1
10 mA
—
—
Note: * For details, see section 14.2.2, DC Characteristics.
Bit 2: Reserved bit
Bit 2 is reserved; only 0 can be written to this bit.
159
Bits 1 and 0: P9n/PWM pin function switches
These pins select whether pin P9n/PWMn+1 is used as P9n or as PWMn+1.
Bit n
WKPn+1
Description
0
Functions as P9 n output pin
1
Functions as PWM n+1 output pin
(initial value)
(n = 0 or 1)
8.8.3
Pin Functions
Table 8.21 shows the port 9 pin functions.
Table 8.21 Port 9 Pin Functions
Pin
Pin Functions and Selection Method
P91/PWMn+1 to
P90/PWMn+1
The pin function depends on bit WKP n in PMR5, bit PCR5n in PCR5, and bits
SGS3 to SGS0 in LPCR.
(n = 1 or 0)
PMR9n
0
1
Pin function
P9n output pin
PWMn+1 output pin
*: Don’t care
8.8.4
Pin States
Table 8.22 shows the port 5 pin states in each operating mode.
Table 8.22 Port 5 Pin States
Pins
Reset
Sleep
Subsleep Standby
P95 to P9 2
P9n/PWMn+1 to
P9n/PWMn+1
HighRetains Retains
impedance previous previous
state
state
Watch
Subactive Active
HighRetains Functional Functional
impedance* previous
state
(n = 1 or 0)
160
8.9
Port A
8.9.1
Overview
Port A is a 4-bit I/O port, configured as shown in figure 8.8.
PA3/COM4
PA2/COM3
Port A
PA1/COM2
PA0/COM1
Figure 8.8 Port A Pin Configuration
8.9.2
Register Configuration and Description
Table 8.23 shows the port A register configuration.
Table 8.23 Port A Registers
Name
Abbrev.
R/W
Initial Value
Address
Port data register A
PDRA
R/W
H'F0
H'FFDD
Port control register A
PCRA
W
H'F0
H'FFED
1. Port data register A (PDRA)
Bit
7
6
5
4
3
2
1
0
—
—
—
—
PA 3
PA 2
PA 1
Initial value
1
1
1
1
0
0
0
0
Read/Write
—
—
—
—
R/W
R/W
R/W
R/W
PA 0
PDRA is an 8-bit register that stores data for port A pins PA3 to PA 0. If port A is read while
PCRA bits are set to 1, the values stored in PDRA are read, regardless of the actual pin states. If
port A is read while PCRA bits are cleared to 0, the pin states are read.
Upon reset, PDRA is initialized to H'F0.
161
2. Port control register A (PCRA)
Bit
7
6
5
4
3
2
1
—
—
—
—
PCRA 3
PCRA 2
PCRA 1
Initial value
1
1
1
1
0
0
0
0
Read/Write
—
—
—
—
R/W
R/W
R/W
R/W
0
PCRA 0
PCRA controls whether each of port A pins PA3 to PA 0 functions as an input pin or output pin.
Setting a PCRA bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0
makes the pin an input pin. PCRA and PDRA settings are valid when the corresponding pins are
designated for general-purpose input/output by LPCR.
Upon reset, PCRA is initialized to H'F0.
PCRA is a write-only register, which is always read as all 1s.
162
8.9.3
Pin Functions
Table 8.24 shows the port A pin functions.
Table 8.24 Port A Pin Functions
Pin
Pin Functions and Selection Method
PA3/COM4
The pin function depends on bit PCRA3 in PCRA and bits SGS3 to SGS0.
PA2/COM3
PA1/COM2
PA0/COM1
SEGS3 to SEGS0
0000
0000
Not 0000
PCRA3
0
1
*
Pin function
PA3 input pin
PA3 output pin
COM4 output pin
The pin function depends on bit PCRA2 in PCRA and bits SGS3 to SGS0.
SEGS3 to SEGS0
0000
0000
Not 0000
PCRA2
0
1
*
Pin function
PA2 input pin
PA2 output pin
COM3 output pin
The pin function depends on bit PCRA1 in PCRA and bits SGS3 to SGS0.
SEGS3 to SEGS0
0000
0000
Not 0000
PCRA1
0
1
*
Pin function
PA1 input pin
PA1 output pin
COM2 output pin
The pin function depends on bit PCRA0 in PCRA and bits SGS3 to SGS0.
SEGS3 to SEGS0
0000
Not 0000
PCRA0
0
1
*
Pin function
PA0 input pin
PA0 output pin
COM1 output pin
*: Don’t care
163
8.9.4
Pin States
Table 8.25 shows the port A pin states in each operating mode.
Table 8.25 Port A Pin States
Pins
Reset
PA3/COM4
PA2/COM3
PA1/COM2
PA0/COM1
HighRetains Retains
impedance previous previous
state
state
164
Sleep
Subsleep Standby
Watch
Subactive Active
HighRetains Functional Functional
impedance previous
state
8.10
Port B
8.10.1
Overview
Port B is a 4-bit input-only port, configured as shown in figure 8.9.
PB3/AN3/IRQ1
PB2/AN2
Port B
PB1/AN1
PB0/AN0
Figure 8.9 Port B Pin Configuration
8.10.2
Register Configuration and Description
Table 8.26 shows the port B register configuration.
Table 8.26 Port B Register
Name
Abbrev.
R/W
Initial Value
Address
Port data register B
PDRB
R
—
H'FFDE
Port mode register B
PMRB
R/W
H'F7
H'FFEE
1. Port Data Register B (PDRB)
Bit
Read/Write
7
6
5
4
3
2
1
0
—
—
—
—
PB3
PB2
PB1
PB 0
—
—
—
—
R
R
R
R
Reading PDRB always gives the pin states. However, if a port B pin is selected as an analog input
channel for the A/D converter by AMR bits CH3 to CH0, that pin reads 0 regardless of the input
voltage.
165
2. Port mode register B (PMRB)
Bit
7
6
5
4
3
2
1
0
—
—
—
—
IRQ1
—
—
—
Initial value
1
1
1
1
0
1
1
1
Read/Write
—
—
—
—
R/W
—
—
—
PMRB is an 8-bit read/write register controlling the selection of the PB3 pin function. Upon reset,
PMRB is initialized to H'F7.
Bits 7 to 4 and 2 to 0: Reserved bits
Bits 7 to 4 and 2 to 0 are reserved; they are always read as 1 and cannot be modified.
Bit 3: PB3/AN3/IRQ1 pin function switch (IRQ1)
These bits select whether pin PB3/AN3/IRQ1 is used as PB3/AN3 or as IRQ1.
Bit 3
IRQ1
Description
0
Functions as PB 3/AN3 input pin
1
Functions as IRQ1 input pin
Note: Rising or falling edge sensing can be selected for the IRQ1 pin.
166
(initial value)
8.10.3
Pin Functions
Table 8.27 shows the port B pin functions.
Table 8.27 Port B Pin Functions
Pin
Pin Functions and Selection Method
PB3/AN3/IRQ1
The pin function depends on bits CH3 to CH0 in AMR and bit IRQ1 in PMRB.
IRQ1
PB2/AN2
PB1/AN1
PB0/AN0
0
1
CH3 to CH0
Not 0111
1
*
Pin function
PB3 input pin
AN 3 input pin
IRQ1 input pin
The pin function depends on bits CH3 to CH0 in AMR.
CH3 to CH0
Not 0110
0110
Pin function
PB2 input pin
AN 2 input pin
The pin function depends on bits CH3 to CH0 in AMR.
CH3 to CH0
Not 0101
Not 0000
Pin function
PB1 input pin
AN 1 input pin
The pin function depends on bits CH3 to CH0 in AMR.
CH3 to CH0
Not 0100
0100
Pin function
PB0 input pin
AN 0 input pin
*: Don’t care
167
8.11
Input/Output Data Inversion Function
8.11.1
Overview
With input pin RXD32 and output pin TXD32, the data can be handled in inverted form.
SCINV2
RXD32
P41/RXD32
SCINV3
P42/TXD32
TXD32
Figure 8.10 Input/Output Data Inversion Function
8.11.2
Register Configuration and Descriptions
Table 8.28 shows the registers used by the input/output data inversion function.
Table 8.28 Register Configuration
Name
Abbreviation
R/W
Address
Serial port control register
SPCR
R/W
H'FF91
Serial Port Control Register (SPCR)
Bit
7
6
5
4
—
—
SPC32
—
Initial value
1
1
0
—
0
Read/Write
—
—
R/W
W
R/W
3
1
0
—
—
0
—
—
R/W
W
W
2
SCINV3 SCINV2
SPCR is an 8-bit readable/writable register that performs RXD32 and TXD32 pin input/output data
inversion switching.
Bits 7 and 6: Reserved bits
Bits 7 and 6 are reserved; they are always read as 1 and cannot be modified.
168
Bit 5: P42/TXD32 pin function switch (SPC32)
This bit selects whether pin P42/TXD32 is used as P42 or as TXD32.
Bit 5
SPC32
Description
0
Functions as P4 2 I/O pin
1
Functions as TXD 32 output pin*
(initial value)
Note: * Set the TE bit in SCR3 after setting this bit to 1.
Bit 4: Reserved bit
Bit 4 is reserved; only 0 can be written to this bit.
Bit 3: TXD32 pin output data inversion switch
Bit 3 specifies whether or not TXD32 pin output data is to be inverted.
Bit 3
SCINV3
Description
0
TXD32 output data is not inverted
1
TXD32 output data is inverted
(initial value)
Bit 2: RXD 32 pin input data inversion switch
Bit 2 specifies whether or not RXD 32 pin input data is to be inverted.
Bit 2
SCINV2
Description
0
RXD32 input data is not inverted
1
RXD32 input data is inverted
(initial value)
Bits 1 and 0: Reserved bits
Bits 1 and 0 are reserved; only 0 can be written to these bits.
8.11.3
Note on Modification of Serial Port Control Register
When a serial port control register is modified, the data being input or output up to that point is
inverted immediately after the modification, and an invalid data change is input or output. When
modifying a serial port control register, do so in a state in which data changes are invalidated.
169
8.12
Application Note
8.12.1
How to Handle an Unused Pin
If an I/O pin not used by the user system is floating, pull it up or down.
• If an unused pin is an input pin, handle it in one of the following ways:
 Pull it up to V CC with an on-chip pull-up MOS.
 Pull it up to V CC with an external resistor of approximately 100 kΩ.
 Pull it down to VSS with an external resistor of approximately 100 kΩ.
 For a pin also used by the A/D converter, pull it up to AVCC.
• If an unused pin is an output pin, handle it in one of the following ways:
 Set the output of the unused pin to high and pull it up to VCC with an on-chip pull-up MOS.
 Set the output of the unused pin to high and pull it up to VCC with an external resistor of
approximately 100 kΩ.
 Set the output of the unused pin to low and pull it down to GND with an external resistor of
approximately 100 kΩ.
170
Section 9 Timers
9.1
Overview
The H8/3802 Series provides three timers: timers A, F, and an asynchronous event counter. The
functions of these timers are outlined in table 9.1.
Table 9.1
Timer Functions
Event
Input Pin
Waveform
Output Pin Remarks
—
—
ø/4 to ø/32, øw/4
(4 choices)
—
TMOFL
TMOFH
ø/2 to ø/8
(3 choices)
AEVL
AEVH
IRQAEC
—
Name
Functions
Timer A
•
8-bit interval timer ø/8 to ø/8192
•
Interval function
(8 choices)
•
Time base
øw/128 (choice of 4
overflow periods)
•
16-bit timer
•
Also usable as two
independent8-bit
timers.
•
Output compare
output function
Timer F
Asynchro- •
nous
•
event
counter
16-bit counter
Also usable as two
independent 8-bit
counters
•
Counts events
asynchronous to ø
and øw
•
Can count
asynchronous
events
(rising/falling/both
edges) independently of the MCU's
internal clock
Internal Clock
171
9.2
Timer A
9.2.1
Overview
Timer A is an 8-bit timer with interval timing and real-time clock time-base functions. The clock
time-base function is available when a 32.768 kHz crystal oscillator is connected.
1. Features
Features of timer A are given below.
• Choice of eight internal clock sources (ø/8192, ø/4096, ø/2048, ø/512, ø/256, ø/128, ø/32, ø/8).
• Choice of four overflow periods (1 s, 0.5 s, 0.25 s, 31.25 ms) when timer A is used as a clock
time base (using a 32.768 kHz crystal oscillator).
• An interrupt is requested when the counter overflows.
• Use of module standby mode enables this module to be placed in standby mode independently
when not used.
172
2. Block diagram
Figure 9.1 shows a block diagram of timer A.
øW
TMA
PSW
1/4
Internal data bus
øW/4
øW /128
ø
÷256*
÷128*
÷64*
ø/8192, ø/4096, ø/2048,
ø/512, ø/256, ø/128,
ø/32, ø/8
÷8*
TCA
PSS
IRRTA
Notation:
TMA:
TCA:
IRRTA:
PSW:
PSS:
Timer mode register A
Timer counter A
Timer A overflow interrupt request flag
Prescaler W
Prescaler S
Note: * Can be selected only when the prescaler W output (øW/128) is used as the TCA input clock.
Figure 9.1 Block Diagram of Timer A
173
3. Register configuration
Table 9.2 shows the register configuration of timer A.
Table 9.2
Timer A Registers
Name
Abbrev.
R/W
Initial Value
Address
Timer mode register A
TMA
R/W
—
H'FFB0
Timer counter A
TCA
R
H'00
H'FFB1
Clock stop register 1
CKSTPR1
R/W
H'FF
H'FFFA
9.2.2
Register Descriptions
1. Timer mode register A (TMA)
Bit
7
6
5
4
3
2
1
0
—
—
—
—
TMA3
TMA2
TMA1
TMA0
Initial value
—
—
—
1
0
0
0
0
Read/Write
W
W
W
—
R/W
R/W
R/W
R/W
TMA is an 8-bit read/write register for selecting the prescaler, and input clock.
Bits 7 to 5: Reserved bits
Bits 7 to 5 are reserved; only 0 can be written to these bits.
Bit 4: Reserved bit
Bit 4 is reserved; it is always read as 1, and cannot be modified.
174
Bits 3 to 0: Internal clock select (TMA3 to TMA0)
Bits 3 to 0 select the clock input to TCA. The selection is made as follows.
Description
Bit 3
TMA3
Bit 2
TMA2
Bit 1
TMA1
Bit 0
TMA0
Prescaler and Divider Ratio
or Overflow Period
0
0
0
0
PSS, ø/8192
1
PSS, ø/4096
0
PSS, ø/2048
1
PSS, ø/512
0
PSS, ø/256
1
PSS, ø/128
0
PSS, ø/32
1
PSS, ø/8
0
PSW, 1 s
Clock time
1
PSW, 0.5 s
base
0
PSW, 0.25 s
(when using
1
PSW, 0.03125 s
32.768 kHz)
0
PSW and TCA are reset
1
1
0
1
1
0
0
1
1
0
Function
(initial value) Interval timer
1
1
0
1
175
2. Timer counter A (TCA)
Bit
7
6
5
4
3
2
1
0
TCA7
TCA6
TCA5
TCA4
TCA3
TCA2
TCA1
TCA0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R
R
R
R
TCA is an 8-bit read-only up-counter, which is incremented by internal clock input. The clock
source for input to this counter is selected by bits TMA3 to TMA0 in timer mode register A
(TMA). TCA values can be read by the CPU in active mode, but cannot be read in subactive
mode. When TCA overflows, the IRRTA bit in interrupt request register 1 (IRR1) is set to 1.
TCA is cleared by setting bits TMA3 and TMA2 of TMA to 11.
Upon reset, TCA is initialized to H'00.
3. Clock stop register 1 (CKSTPR1)
Bit:
7
6
—
—
5
4
S32CKSTP ADCKSTP
3
2
1
0
—
TFCKSTP
—
TACKSTP
Initial value:
1
1
1
1
1
1
1
1
Read/Write:
—
—
R/W
R/W
—
R/W
—
R/W
CKSTPR1 is an 8-bit read/write register that performs module standby mode control for peripheral
modules. Only the bit relating to timer A is described here. For details of the other bits, see the
sections on the relevant modules.
Bit 0: Timer A module standby mode control (TACKSTP)
Bit 0 controls setting and clearing of module standby mode for timer A.
TACKSTP
Description
0
Timer A is set to module standby mode
1
Timer A module standby mode is cleared
176
(initial value)
9.2.3
Timer Operation
1. Interval timer operation
When bit TMA3 in timer mode register A (TMA) is cleared to 0, timer A functions as an 8-bit
interval timer.
Upon reset, TCA is cleared to H'00 and bit TMA3 is cleared to 0, so up-counting and interval
timing resume immediately. The clock input to timer A is selected by bits TMA2 to TMA0 in
TMA; any of eight internal clock signals output by prescaler S can be selected.
After the count value in TCA reaches H'FF, the next clock signal input causes timer A to
overflow, setting bit IRRTA to 1 in interrupt request register 1 (IRR1). If IENTA = 1 in interrupt
enable register 1 (IENR1), a CPU interrupt is requested.*
At overflow, TCA returns to H'00 and starts counting up again. In this mode timer A functions as
an interval timer that generates an overflow output at intervals of 256 input clock pulses.
Note: * For details on interrupts, see 3.3, Interrupts.
2. Real-time clock time base operation
When bit TMA3 in TMA is set to 1, timer A functions as a real-time clock time base by counting
clock signals output by prescaler W. The overflow period of timer A is set by bits TMA1 and
TMA0 in TMA. A choice of four periods is available. In time base operation (TMA3 = 1), setting
bit TMA2 to 1 clears both TCA and prescaler W to their initial values of H'00.
9.2.4
Timer A Operation States
Table 9.3 summarizes the timer A operation states.
Table 9.3
Timer A Operation States
Operation Mode
Reset
Active
Watch
Subactive
Subsleep
Standby
Module
Standby
TCA Interval
Reset
Functions Functions Halted
Halted
Halted
Halted
Halted
Functions Functions Functions Functions Functions Halted
Halted
Clock time base Reset
TMA
Reset
Sleep
Functions Retained
Retained Functions Retained
Retained Retained
Note: When the real-time clock time base function is selected as the internal clock of TCA in
active mode or sleep mode, the internal clock is not synchronous with the system clock, so
it is synchronized by a synchronizing circuit. This may result in a maximum error of 1/ø (s) in
the count cycle.
177
9.2.5
Application Note
When bit 0 (TACKSTP) of the clock stop register 1 (CKSTPR1) is cleared to 0, bit 3 (TMA3) of
the timer mode register A (TMA) cannot be rewritten.
Set bit 0 (TACKSTP) of the clock stop register 1 (CKSTPR1) to 1 before rewriting bit 3 (TMA3)
of the timer mode register A (TMA).
9.3
Timer F
9.3.1
Overview
Timer F is a 16-bit timer with a built-in output compare function. Timer F also provides for
counter resetting, interrupt request generation, toggle output, etc., using compare match signals.
Timer F can also be used as two independent 8-bit timers (timer FH and timer FL).
1. Features
Features of timer F are given below.
• Choice of four internal clock sources (ø/32, ø/16, ø/4, øw/4)
• TMOFH pin toggle output provided using a single compare match signal (toggle output initial
value can be set)
• Counter resetting by a compare match signal
• Two interrupt sources: one compare match, one overflow
• Can operate as two independent 8-bit timers (timer FH and timer FL) (in 8-bit mode).
Timer FH 8-Bit Timer*
Timer FL
8-Bit Timer/Event Counter
Internal clock
Choice of 4 (ø/32, ø/16, ø/4, øw/4)
Toggle output
One compare match signal, output to
TMOFH pin(initial value settable)
Counter reset
Counter can be reset by compare match signal
Interrupt sources
One compare match
One overflow
One compare match signal, output to
TMOFL pin (initial value settable)
Note: * When timer F operates as a 16-bit timer, it operates on the timer FL overflow signal.
• Operation in watch mode, subactive mode, and subsleep mode
When øw/4 is selected as the internal clock, timer F can operate in watch mode, subactive
mode, and subsleep mode.
• Use of module standby mode enables this module to be placed in standby mode independently
when not used.
178
2. Block diagram
Figure 9.2 shows a block diagram of timer F.
ø
PSS
IRRTFL
TCRF
øw/4
TCFL
Toggle
circuit
Comparator
Internal data bus
TMOFL
OCRFL
TCFH
TMOFH
Toggle
circuit
Comparator
Match
OCRFH
TCSRF
IRRTFH
Notation:
TCRF:
Timer control register F
TCSRF: Timer control/status register F
TCFH:
8-bit timer counter FH
TCFL:
8-bit timer counter FL
OCRFH: Output compare register FH
OCRFL: Output compare register FL
IRRTFH: Timer FH interrupt request flag
IRRTFL: Timer FL interrupt request flag
PSS:
Prescaler S
Figure 9.2 Block Diagram of Timer F
179
3. Pin configuration
Table 9.4 shows the timer F pin configuration.
Table 9.4
Pin Configuration
Name
Abbrev.
I/O
Function
Timer FH output
TMOFH
Output
Timer FH toggle output pin
Timer FL output
TMOFL
Output
Timer FL toggle output pin
4. Register configuration
Table 9.5 shows the register configuration of timer F.
Table 9.5
Timer F Registers
Name
Abbrev.
R/W
Initial Value
Address
Timer control register F
TCRF
W
H'00
H'FFB6
Timer control/status register F
TCSRF
R/W
H'00
H'FFB7
8-bit timer counter FH
TCFH
R/W
H'00
H'FFB8
8-bit timer counter FL
TCFL
R/W
H'00
H'FFB9
Output compare register FH
OCRFH
R/W
H'FF
H'FFBA
Output compare register FL
OCRFL
R/W
H'FF
H'FFBB
Clock stop register 1
CKSTPR1
R/W
H'FF
H'FFFA
180
9.3.2
Register Descriptions
1. 16-bit timer counter (TCF)
8-bit timer counter (TCFH)
8-bit timer counter (TCFL)
TCF
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Read/Write:
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
TCFH
TCFL
TCF is a 16-bit read/write up-counter configured by cascaded connection of 8-bit timer counters
TCFH and TCFL. In addition to the use of TCF as a 16-bit counter with TCFH as the upper 8 bits
and TCFL as the lower 8 bits, TCFH and TCFL can also be used as independent 8-bit counters.
TCFH and TCFL can be read and written by the CPU, but when they are used in 16-bit mode, data
transfer to and from the CPU is performed via a temporary register (TEMP). For details of TEMP,
see 9.3.3, CPU Interface.
TCFH and TCFL are each initialized to H'00 upon reset.
a. 16-bit mode (TCF)
When CKSH2 is cleared to 0 in TCRF, TCF operates as a 16-bit counter. The TCF input clock
is selected by bits CKSL2 to CKSL0 in TCRF.
TCF can be cleared in the event of a compare match by means of CCLRH in TCSRF.
When TCF overflows from H'FFFF to H'0000, OVFH is set to 1 in TCSRF. If OVIEH in
TCSRF is 1 at this time, IRRTFH is set to 1 in IRR2, and if IENTFH in IENR2 is 1, an
interrupt request is sent to the CPU.
b. 8-bit mode (TCFL/TCFH)
When CKSH2 is set to 1 in TCRF, TCFH and TCFL operate as two independent 8-bit
counters. The TCFH (TCFL) input clock is selected by bits CKSH2 to CKSH0 (CKSL2 to
CKSL0) in TCRF.
TCFH (TCFL) can be cleared in the event of a compare match by means of CCLRH (CCLRL)
in TCSRF.
When TCFH (TCFL) overflows from H'FF to H'00, OVFH (OVFL) is set to 1 in TCSRF. If
OVIEH (OVIEL) in TCSRF is 1 at this time, IRRTFH (IRRTFL) is set to 1 in IRR2, and if
IENTFH (IENTFL) in IENR2 is 1, an interrupt request is sent to the CPU.
181
2. 16-bit output compare register (OCRF)
8-bit output compare register (OCRFH)
8-bit output compare register (OCRFL)
OCRF
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value:
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Read/Write:
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
OCRFH
OCRFL
OCRF is a 16-bit read/write register composed of the two registers OCRFH and OCRFL. In
addition to the use of OCRF as a 16-bit register with OCRFH as the upper 8 bits and OCRFL as
the lower 8 bits, OCRFH and OCRFL can also be used as independent 8-bit registers.
OCRFH and OCRFL can be read and written by the CPU, but when they are used in 16-bit mode,
data transfer to and from the CPU is performed via a temporary register (TEMP). For details of
TEMP, see 9.3.3, CPU Interface.
OCRFH and OCRFL are each initialized to H'FF upon reset.
a. 16-bit mode (OCRF)
When CKSH2 is cleared to 0 in TCRF, OCRF operates as a 16-bit register. OCRF contents are
constantly compared with TCF, and when both values match, CMFH is set to 1 in TCSRF. At
the same time, IRRTFH is set to 1 in IRR2. If IENTFH in IENR2 is 1 at this time, an interrupt
request is sent to the CPU.
Toggle output can be provided from the TMOFH pin by means of compare matches, and the
output level can be set (high or low) by means of TOLH in TCRF.
b. 8-bit mode (OCRFH/OCRFL)
When CKSH2 is set to 1 in TCRF, OCRFH and OCRFL operate as two independent 8-bit
registers. OCRFH contents are compared with TCFH, and OCRFL contents are with TCFL.
When the OCRFH (OCRFL) and TCFH (TCFL) values match, CMFH (CMFL) is set to 1 in
TCSRF. At the same time, IRRTFH (IRRTFL) is set to 1 in IRR2. If IENTFH (IENTFL) in
IENR2 is 1 at this time, an interrupt request is sent to the CPU.
Toggle output can be provided from the TMOFH pin (TMOFL pin) by means of compare
matches, and the output level can be set (high or low) by means of TOLH (TOLL) in TCRF.
182
3. Timer control register F (TCRF)
Bit:
7
6
5
4
3
2
1
0
TOLH
CKSH2
CKSH1
CKSH0
TOLL
CKSL2
CKSL1
CKSL0
Initial value:
0
0
0
0
0
0
0
0
Read/Write:
W
W
W
W
W
W
W
W
TCRF is an 8-bit write-only register that switches between 16-bit mode and 8-bit mode, selects the
input clock from among four internal clock sources and sets the output level of the TMOFH and
TMOFL pins.
TCRF is initialized to H'00 upon reset.
Bit 7: Toggle output level H (TOLH)
Bit 7 sets the TMOFH pin output level. The output level is effective immediately after this bit is
written.
Bit 7
TOLH
Description
0
Low level
1
High level
(initial value)
Bits 6 to 4: Clock select H (CKSH2 to CKSH0)
Bits 6 to 4 select the clock input to TCFH from among four internal clock sources or TCFL
overflow.
Bit 6
CKSH2
Bit 5
CKSH1
Bit 4
CKSH0
Description
0
0
0
16-bit mode, counting on TCFL overflow signal
0
0
1
0
1
0
0
1
1
Use prohibited
1
0
0
Internal clock: counting on ø/32
1
0
1
Internal clock: counting on ø/16
1
1
0
Internal clock: counting on ø/4
1
1
1
Internal clock: counting on øw/4
(initial value)
183
Bit 3: Toggle output level L (TOLL)
Bit 3 sets the TMOFL pin output level. The output level is effective immediately after this bit is
written.
Bit 3
TOLL
Description
0
Low level
1
High level
(initial value)
Bits 2 to 0: Clock select L (CKSL2 to CKSL0)
Bits 2 to 0 select the clock input to TCFL from among four internal clock sources or external event
input.
Bit 2
CKSL2
Bit 1
CKSL1
Bit 0
CKSL0
Description
0
0
0
Non-operational
0
0
1
Use prohibited
0
1
0
0
1
1
1
0
0
Internal clock: counting on ø/32
1
0
1
Internal clock: counting on ø/16
1
1
0
Internal clock: counting on ø/4
1
1
1
Internal clock: counting on øw/4
184
(initial value)
4. Timer control/status register F (TCSRF)
Bit:
7
6
5
4
3
2
1
0
OVFH
CMFH
OVIEH
CCLRH
OVFL
CMFL
OVIEL
CCLRL
Initial value:
0
0
0
0
0
0
0
0
Read/Write:
R/(W)*
R/(W)*
R/W
R/W
R/(W)*
R/(W)*
R/W
R/W
Note: * Bits 7, 6, 3, and 2 can only be written with 0, for flag clearing.
TCSRF is an 16-bit read/write register that performs counter clear selection, overflow flag setting,
and compare match flag setting, and controls enabling of overflow interrupt requests.
TCSRF is initialized to H'00 upon reset.
Bit 7: Timer overflow flag H (OVFH)
Bit 7 is a status flag indicating that TCFH has overflowed from H'FF to H'00. This flag is set by
hardware and cleared by software. It cannot be set by software.
Bit 7
OVFH
Description
0
Clearing conditions:
After reading OVFH = 1, cleared by writing 0 to OVFH
1
Setting conditions:
Set when TCFH overflows from H’FF to H’00
(initial value)
Bit 6: Compare match flag H (CMFH)
Bit 6 is a status flag indicating that TCFH has matched OCRFH. This flag is set by hardware and
cleared by software. It cannot be set by software.
Bit 6
CMFH
Description
0
Clearing conditions:
After reading CMFH = 1, cleared by writing 0 to CMFH
1
Setting conditions:
Set when the TCFH value matches the OCRFH value
(initial value)
185
Bit 5: Timer overflow interrupt enable H (OVIEH)
Bit 5 selects enabling or disabling of interrupt generation when TCFH overflows.
Bit 5
OVIEH
Description
0
TCFH overflow interrupt request is disabled
1
TCFH overflow interrupt request is enabled
(initial value)
Bit 4: Counter clear H (CCLRH)
In 16-bit mode, bit 4 selects whether TCF is cleared when TCF and OCRF match.
In 8-bit mode, bit 4 selects whether TCFH is cleared when TCFH and OCRFH match.
Bit 4
CCLRH
0
1
Description
16-bit mode: TCF clearing by compare match is disabled
8-bit mode: TCFH clearing by compare match is disabled
(initial value)
16-bit mode: TCF clearing by compare match is enabled
8-bit mode: TCFH clearing by compare match is enabled
Bit 3: Timer overflow flag L (OVFL)
Bit 3 is a status flag indicating that TCFL has overflowed from H'FF to H'00. This flag is set by
hardware and cleared by software. It cannot be set by software.
Bit 3
OVFL
Description
0
Clearing conditions:
After reading OVFL = 1, cleared by writing 0 to OVFL
1
Setting conditions:
Set when TCFL overflows from H’FF to H’00
186
(initial value)
Bit 2: Compare match flag L (CMFL)
Bit 2 is a status flag indicating that TCFL has matched OCRFL. This flag is set by hardware and
cleared by software. It cannot be set by software.
Bit 2
CMFL
Description
0
Clearing conditions:
After reading CMFL = 1, cleared by writing 0 to CMFL
1
Setting conditions:
Set when the TCFL value matches the OCRFL value
(initial value)
Bit 1: Timer overflow interrupt enable L (OVIEL)
Bit 1 selects enabling or disabling of interrupt generation when TCFL overflows.
Bit 1
OVIEL
Description
0
TCFL overflow interrupt request is disabled
1
TCFL overflow interrupt request is enabled
(initial value)
Bit 0: Counter clear L (CCLRL)
Bit 0 selects whether TCFL is cleared when TCFL and OCRFL match.
Bit 0
CCLRL
Description
0
TCFL clearing by compare match is disabled
1
TCFL clearing by compare match is enabled
(initial value)
187
5. Clock stop register 1 (CKSTPR1)
7
6
—
—
Initial value:
1
1
1
Read/Write:
—
—
R/W
Bit:
5
4
3
2
1
0
—
TFCKSTP
—
TACKSTP
1
1
1
1
1
R/W
—
R/W
—
R/W
S32CKSTP ADCKSTP
CKSTPR1 is an 8-bit read/write register that performs module standby mode control for peripheral
modules. Only the bit relating to timer F is described here. For details of the other bits, see the
sections on the relevant modules.
Bit 2: Timer F module standby mode control (TFCKSTP)
Bit 2 controls setting and clearing of module standby mode for timer F.
TFCKSTP
Description
0
Timer F is set to module standby mode
1
Timer F module standby mode is cleared
188
(initial value)
9.3.3
CPU Interface
TCF and OCRF are 16-bit read/write registers, but the CPU is connected to the on-chip peripheral
modules by an 8-bit data bus. When the CPU accesses these registers, it therefore uses an 8-bit
temporary register (TEMP).
In 16-bit mode, TCF read/write access and OCRF write access must be performed 16 bits at a time
(using two consecutive byte-size MOV instructions), and the upper byte must be accessed before
the lower byte. Data will not be transferred correctly if only the upper byte or only the lower byte
is accessed.
In 8-bit mode, there are no restrictions on the order of access.
1. Write access
Write access to the upper byte results in transfer of the upper-byte write data to TEMP. Next,
write access to the lower byte results in transfer of the data in TEMP to the upper register byte,
and direct transfer of the lower-byte write data to the lower register byte.
189
Figure 9.3 shows an example in which H'AA55 is written to TCF.
Write to upper byte
CPU
(H'AA)
Module data bus
Bus
interface
TEMP
(H'AA)
TCFH
(
)
TCFL
(
)
Write to lower byte
CPU
(H'55)
Module data bus
Bus
interface
TEMP
(H'AA)
TCFH
(H'AA)
TCFL
(H'55)
Figure 9.3 Write Access to TCR (CPU → TCF)
190
2. Read access
In access to TCF, when the upper byte is read the upper-byte data is transferred directly to the
CPU and the lower-byte data is transferred to TEMP. Next, when the lower byte is read, the
lower-byte data in TEMP is transferred to the CPU.
In access to OCRF, when the upper byte is read the upper-byte data is transferred directly to the
CPU. When the lower byte is read, the lower-byte data is transferred directly to the CPU.
Figure 9.4 shows an example in which TCF is read when it contains H'AAFF.
Read upper byte
CPU
(H'AA)
Module data bus
Bus
interface
TEMP
(H'FF)
TCFH
(H'AA)
TCFL
(H'FF)
Read lower byte
CPU
(H'FF)
Module data bus
Bus
interface
TEMP
(H'FF)
TCFH
(AB)*
TCFL
(00)*
Note: * H'AB00 if counter has been updated once.
Figure 9.4 Read Access to TCF (TCF → CPU)
191
9.3.4
Operation
Timer F is a 16-bit counter that increments on each input clock pulse. The timer F value is
constantly compared with the value set in output compare register F, and the counter can be
cleared, an interrupt requested, or port output toggled, when the two values match. Timer F can
also function as two independent 8-bit timers.
1. Timer F operation
Timer F has two operating modes, 16-bit timer mode and 8-bit timer mode. The operation in each
of these modes is described below.
a. Operation in 16-bit timer mode
When CKSH2 is cleared to 0 in timer control register F (TCRF), timer F operates as a 16-bit
timer.
Following a reset, timer counter F (TCF) is initialized to H'0000, output compare register F
(OCRF) to H'FFFF, and timer control register F (TCRF) and timer control/status register F
(TCSRF) to H'00.
The timer F operating clock can be selected from three internal clocks output by prescaler S by
means of bits CKSL2 to CKSL0 in TCRF.
OCRF contents are constantly compared with TCF, and when both values match, CMFH is set
to 1 in TCSRF. If IENTFH in IENR2 is 1 at this time, an interrupt request is sent to the CPU,
and at the same time, TMOFH pin output is toggled. If CCLRH in TCSRF is 1, TCF is
cleared. TMOFH pin output can also be set by TOLH in TCRF.
When TCF overflows from H'FFFF to H'0000, OVFH is set to 1 in TCSRF. If OVIEH in
TCSRF and IENTFH in IENR2 are both 1, an interrupt request is sent to the CPU.
b. Operation in 8-bit timer mode
When CKSH2 is set to 1 in TCRF, TCF operates as two independent 8-bit timers, TCFH and
TCFL. The TCFH/TCFL input clock is selected by CKSH2 to CKSH0/CKSL2 to CKSL0 in
TCRF.
When the OCRFH/OCRFL and TCFH/TCFL values match, CMFH/CMFL is set to 1 in
TCSRF. If IENTFH/IENTFL in IENR2 is 1, an interrupt request is sent to the CPU, and at the
same time, TMOFH pin/TMOFL pin output is toggled. If CCLRH/CCLRL in TCSRF is 1,
TCFH/TCFL is cleared. TMOFH pin/TMOFL pin output can also be set by TOLH/TOLL in
TCRF.
When TCFH/TCFL overflows from H'FF to H'00, OVFH/OVFL is set to 1 in TCSRF. If
OVIEH/OVIEL in TCSRF and IENTFH/IENTFL in IENR2 are both 1, an interrupt request is
sent to the CPU.
192
2.
TCF increment timing
TCF is incremented by clock input (internal clock input). Bits CKSH2 to CKSH0 or CKSL2 to
CKSL0 in TCRF select one of four internal clock sources (ø/32, ø/16, ø/4, or øw/4) created by
dividing the system clock (ø or øw).
3. TMOFH/TMOFL output timing
In TMOFH/TMOFL output, the value set in TOLH/TOLL in TCRF is output. The output is
toggled by the occurrence of a compare match. Figure 9.5 shows the output timing.
ø
Count input
clock
TCF
OCRF
N
N+1
N
N
N+1
N
Compare match
signal
TMOFH TMOFL
Figure 9.5 TMOFH/TMOFL Output Timing
193
4. TCF clear timing
TCF can be cleared by a compare match with OCRF.
5. Timer overflow flag (OVF) set timing
OVF is set to 1 when TCF overflows from H'FFFF to H'0000.
6. Compare match flag set timing
The compare match flag (CMFH or CMFL) is set to 1 when the TCF and OCRF values match.
The compare match signal is generated in the last state during which the values match (when TCF
is updated from the matching value to a new value). When TCF matches OCRF, the compare
match signal is not generated until the next counter clock.
7. Timer F operation modes
Timer F operation modes are shown in table 9.6.
Table 9.6
Timer F Operation Modes
Sleep
Watch
Subactive
Subsleep
Standby
Module
Standby
Operation Mode
Reset
Active
TCF
Reset
Functions Functions Functions/ Functions/ Functions/ Halted
Halted*
Halted*
Halted*
Halted
OCRF
Reset
Functions Held
Held
Functions Held
Held
Held
TCRF
Reset
Functions Held
Held
Functions Held
Held
Held
TCSRF
Reset
Functions Held
Held
Functions Held
Held
Held
Note: * When ø w/4 is selected as the TCF internal clock in active mode or sleep mode, since the
system clock and internal clock are mutually asynchronous, synchronization is maintained
by a synchronization circuit. This results in a maximum count cycle error of 1/ø (s). When
the counter is operated in subactive mode, watch mode, or subsleep mode, ø w/4 must be
selected as the internal clock. The counter will not operate if any other internal clock is
selected.
194
9.3.5
Application Notes
The following types of contention and operation can occur when timer F is used.
1. 16-bit timer mode
In toggle output, TMOFH pin output is toggled when all 16 bits match and a compare match
signal is generated. If a TCRF write by a MOV instruction and generation of the compare match
signal occur simultaneously, TOLH data is output to the TMOFH pin as a result of the TCRF
write. TMOFL pin output is unstable in 16-bit mode, and should not be used; the TMOFL pin
should be used as a port pin.
If an OCRFL write and compare match signal generation occur simultaneously, the compare
match signal is invalid. However, if the written data and the counter value match, a compare
match signal will be generated at that point. As the compare match signal is output in
synchronization with the TCFL clock, a compare match will not result in compare match signal
generation if the clock is stopped.
Compare match flag CMFH is set when all 16 bits match and a compare match signal is generated.
Compare match flag CMFL is set if the setting conditions for the lower 8 bits are satisfied.
When TCF overflows, OVFH is set. OVFL is set if the setting conditions are satisfied when the
lower 8 bits overflow. If a TCFL write and overflow signal output occur simultaneously, the
overflow signal is not output.
2. 8-bit timer mode
a. TCFH, OCRFH
In toggle output, TMOFH pin output is toggled when a compare match occurs. If a TCRF
write by a MOV instruction and generation of the compare match signal occur simultaneously,
TOLH data is output to the TMOFH pin as a result of the TCRF write.
If an OCRFH write and compare match signal generation occur simultaneously, the compare
match signal is invalid. However, if the written data and the counter value match, a compare
match signal will be generated at that point. The compare match signal is output in
synchronization with the TCFH clock.
If a TCFH write and overflow signal output occur simultaneously, the overflow signal is not
output.
b. TCFL, OCRFL
In toggle output, TMOFL pin output is toggled when a compare match occurs. If a TCRF
write by a MOV instruction and generation of the compare match signal occur simultaneously,
TOLL data is output to the TMOFL pin as a result of the TCRF write.
195
If an OCRFL write and compare match signal generation occur simultaneously, the compare
match signal is invalid. However, if the written data and the counter value match, a compare
match signal will be generated at that point. As the compare match signal is output in
synchronization with the TCFL clock, a compare match will not result in compare match signal
generation if the clock is stopped.
If a TCFL write and overflow signal output occur simultaneously, the overflow signal is not
output.
3. Clear timer FH, timer FL interrupt request flags (IRRTFH, IRRTFL), timer overflow flags H,
L (OVFH, OVFL) and compare match flags H, L (CMFH, CMFL)
When øw/4 is selected as the internal clock, “Interrupt factor generation signal” will be operated
with øw and the signal will be outputted with øw width. And, “Overflow signal” and “Compare
match signal” are controlled with 2 cycles of øw signals. Those signals are outputted with 2 cycles
width of øw (figure 9.6)
In active (high-speed, medium-speed) mode, even if you cleared interrupt request flag during the
term of validity of “Interrupt factor generation signal”, same interrupt request flag is set. (figure
9.6 1) And, you cannot be cleared timer overflow flag and compare match flag during the term of
validity of “Overflow signal” and “Compare match signal”.
For interrupt request flag is set right after interrupt request is cleared, interrupt process to one time
timer FH, timer FL interrupt might be repeated. (figure 9.6 2) Therefore, to definitely clear
interrupt request flag in active (high-speed, medium-speed) mode, clear should be processed after
the time that calculated with below (1) formula. And, to definitely clear timer overflow flag and
compare match flag, clear should be processed after read timer control status register F (TCSRF)
after the time that calculated with below (1) formula. For ST of (1) formula, please substitute the
longest number of execution states in used instruction. (10 states of RTE instruction when
MULXU, DIVXU instruction is not used, 14 states when MULXU, DIVXU instruction is used) In
subactive mode, there are not limitation for interrupt request flag, timer overflow flag, and
compare match flag clear.
The term of validity of “Interrupt factor generation signal”
= 1 cycle of øw + waiting time for completion of executing instruction
+ interrupt time synchronized with ø = 1/øw + ST × (1/ø) + (2/ø) (second).....(1)
ST: Executing number of execution states
Method 1 is recommended to operate for time efficiency.
Method 1
1. Prohibit interrupt in interrupt handling routine (set IENFH, IENFL to 0).
2. After program process returned normal handling, clear interrupt request flags (IRRTFH,
IRRTFL) after more than that calculated with (1) formula.
196
3. After read timer control status register F (TCSRF), clear timer overflow flags (OVFH,
OVFL) and compare match flags (CMFH, CMFL).
4. Operate interrupt permission (set IENFH, IENFL to 1).
Method 2
1. Set interrupt handling routine time to more than time that calculated with (1) formula.
2. Clear interrupt request flags (IRRTFH, IRRTFL) at the end of interrupt handling routine.
3. After read timer control status register F (TCSRF), clear timer overflow flags (OVFH,
OVFL) and compare match flags (CMFH, CMFL).
All above attentions are also applied in 16-bit mode and 8-bit mode.
Interrupt request
flag clear
Interrupt request
flag clear
2
Program process
Interrupt
Interrupt
Normal
øw
Interrupt factor
generation signal
(Internal signal,
nega-active)
Overflow signal,
Compare match signal
(Internal signal,
nega-active)
Interrupt request flag
(IRRTFH, IRRTFL)
1
Figure 9.6 Clear Interrupt Request Flag when Interrupt Factor Generation Signal is Valid
4. Timer counter (TCF) read/write
When øw/4 is selected as the internal clock in active (high-speed, medium-speed) mode, write on
TCF is impossible. And, when read TCF, as the system clock and internal clock are mutually
asynchronous, TCF synchronizes with synchronization circuit. This results in a maximum TCF
read value error of ±1.
When read/write TCF in active (high-speed, medium-speed) mode is needed, please select internal
clock except for øw/4 before read/write.
In subactive mode, even øw/4 is selected as the internal clock, normal read/write TCF is possible.
197
9.4
Asynchronous Event Counter (AEC)
9.4.1
Overview
The asynchronous event counter is incremented by external event clock or internal clock input.
1. Features
Features of the asynchronous event counter are given below.
• Can count asynchronous events
Can count external events input asynchronously without regard to the operation of base clocks ø
and øSUB .
The counter has a 16-bit configuration, enabling it to count up to 65536 (216) events.
• Can also be used as two independent 8-bit event counter channels.
• Can be used as single-channel independent 16-bit event counter.
• Event/clock input is enabled only when IRQAEC is high or event counter PWM output
(IECPWM) is high.
• Both edge sensing can be used for IRQAEC or event counter PWM output (IECPWM)
interrupts. When the asynchronous counter is not used, independent interrupt function use is
possible.
• When an event counter PWM is used, event clock input enabling/disabling can be performed
automatically in a fixed cycle.
• External event input or a prescaler output clock can be selected by software for the ECH and
ECL clock sources. ø/2, ø/4, or ø/8 can be selected as the prescaler output clock.
• Both edge counting is possible for AEVL and AEVH.
• Counter resetting and halting of the count-up function controllable by software
• Automatic interrupt generation on detection of event counter overflow
• Use of module standby mode enables this module to be placed in standby mode independently
when not used.
198
2. Block diagram
Figure 9.7 shows a block diagram of the asynchronous event counter.
IRREC
ø
ECCR
PSS
ECCSR
ø/2
ø/4, ø/8
OVH
OVL
AEVL
CK
ECL
(8 bit)
CK
Edge sensing
circuit
Edge sensing
circuit
Edge sensing
circuit
IECPWM
IRQAEC
To CPU interrupt
(IRREC2)
Internal data bus
AEVH
ECH
(8 bit)
ECPWCRL
ECPWCRH
PWM waveform generator
ø/2, ø/4,
ø/8, ø/16,
ø/32, ø/64
ECPWDRL
ECPWDRH
AEGSR
Notation
ECPWCRH:
ECPWDRH:
AEGSR:
ECCSR:
ECH:
ECL:
Event counter PWM compare register H
Event counter PWM data register H
Input pin edge selection register
Event counter control/status register
Event counter H
Event counter L
ECPWCRL:
ECPWDRL:
ECCR:
Event counter PWM compare register L
Event counter PWM data register L
Event counter control register
Figure 9.7 Block Diagram of Asynchronous Event Counter
199
3. Pin configuration
Table 9.7 shows the asynchronous event counter pin configuration.
Table 9.7
Pin Configuration
Name
Abbrev.
I/O
Function
Asynchronous event input H
AEVH
Input
Event input pin for input to event counter H
Asynchronous event input L
AEVL
Input
Event input pin for input to event counter L
Input
Input pin for interrupt enabling event input
Event input enable interrupt input IRQAEC
4. Register configuration
Table 9.8 shows the register configuration of the asynchronous event counter.
Table 9.8
Asynchronous Event Counter Registers
Name
R/W
Initial Value
Address
Event counter PWM compare register H ECPWCRH
R/W
H'FF
H'FF8C
Event counter PWM compare register L ECPWCRL
R/W
H'FF
H'FF8D
Event counter PWM data register H
ECPWDRH
W
H'00
H'FF8E
Event counter PWM data register L
ECPWDRL
W
H'00
H'FF8F
Input pin edge selection register
AEGSR
R/W
H'00
H'FF92
Event counter control register
ECCR
R/W
H'00
H'FF94
Event counter control/status register
ECCSR
R/W
H'00
H'FF95
Event counter H
ECH
R
H'00
H'FF96
Event counter L
ECL
R
H'00
H'FF97
Clock stop register 2
CKSTP2
R/W
H'FF
H'FFFB
200
Abbrev.
9.4.2
Register Configurations
1. Event counter PWM compare register H (ECPWCRH)
Bit
7
6
5
4
3
2
1
0
ECPWCRH7 ECPWCRH6 ECPWCRH5 ECPWCRH4 ECPWCRH3 ECPWCRH2 ECPWCRH1 ECPWCRH0
Initial value
1
1
1
1
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Note: When ECPWME in AEGSR is 1, event counter PWM is operating and therefore ECPWCRH
should not be modified.
When changing the conversion period, event counter PWM must be halted by clearing
ECPWME to 0 in AEGSR before modifying ECPWCRH.
ECPWCRH is an 8-bit read/write register that sets the event counter PWM waveform conversion
period.
2. Event counter PWM compare register L (ECPWCRL)
Bit
7
6
5
4
3
2
1
0
ECPWCRL7 ECPWCRL6 ECPWCRL5 ECPWCRL4 ECPWCRL3 ECPWCRL2 ECPWCRL1 ECPWCRL0
Initial value
1
1
1
1
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Note: When ECPWME in AEGSR is 1, event counter PWM is operating and therefore ECPWCRL
should not be modified.
When changing the conversion period, event counter PWM must be halted by clearing
ECPWME to 0 in AEGSR before modifying ECPWCRL.
ECPWCRL is an 8-bit read/write register that sets the event counter PWM waveform conversion
period.
201
3. Event counter PWM data register H (ECPWDRH)
Bit
7
6
5
4
3
2
1
0
ECPWDRH7 ECPWDRH6 ECPWDRH5 ECPWDRH4 ECPWDRH3 ECPWDRH2 ECPWDRH1 ECPWDRH0
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
Note: When ECPWME in AEGSR is 1, event counter PWM is operating and therefore ECPWDRH
should not be modified.
When changing the data, event counter PWM must be halted by clearing ECPWME to 0 in
AEGSR before modifying ECPWDRH.
ECPWDRH is an 8-bit write-only register that controls event counter PWM waveform generator
data.
4. Event counter PWM data register L (ECPWDRL)
Bit
7
6
5
4
3
2
1
0
ECPWDRL7 ECPWDRL6 ECPWDRL5 ECPWDRL4 ECPWDRL3 ECPWDRL2 ECPWDRL1 ECPWDRL0
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
Note: When ECPWME in AEGSR is 1, event counter PWM is operating and therefore ECPWDRL
should not be modified.
When changing the data, event counter PWM must be halted by clearing ECPWME to 0 in
AEGSR before modifying ECPWDRL.
ECPWDRL is an 8-bit write-only register that controls event counter PWM waveform generator
data.
5. Input pin edge selection register (AEGSR)
Bit
7
6
5
4
3
2
1
AHEGS1 AHEGS0 ALEGS1 ALEGS0 AIEGS1 AIEGS0 ECPWME
0
—
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
AEGSR is an 8-bit read/write register that selects rising, falling, or both edge sensing for the
AEVH, AEVL, and IRQAEC pins.
202
Bits 7 and 6: AEC edge select H
Bits 7 and 6 select rising, falling, or both edge sensing for the AEVH pin.
Bit 7
AHEGS1
Bit 6
AHEGS0
Description
0
0
Falling edge on AEVH pin is sensed
1
Rising edge on AEVH pin is sensed
0
Both edges on AEVH pin are sensed
1
Use prohibited
1
(initial value)
Bits 5 and 4: AEC edge select L
Bits 5 and 4 select rising, falling, or both edge sensing for the AEVL pin.
Bit 5
ALEGS1
Bit 4
ALEGS0
Description
0
0
Falling edge on AEVL pin is sensed
1
Rising edge on AEVL pin is sensed
0
Both edges on AEVL pin are sensed
1
Use prohibited
1
(initial value)
Bits 3 and 2: IRQAEC edge select
Bits 3 and 2 select rising, falling, or both edge sensing for the IRQAEC pin.
Bit 3
AIEGS1
Bit 2
AIEGS0
Description
0
0
Falling edge on IRQAEC pin is sensed
1
Rising edge on IRQAEC pin is sensed
0
Both edges on IRQAEC pin are sensed
1
Use prohibited
1
(initial value)
203
Bit 1: Event counter PWM enable
Bit 1 controls enabling/disabling of event counter PWM and selection/deselection of IRQAEC.
Bit 1
ECPWME
Description
0
AEC PWM halted, IRQAEC selected
1
AEC PWM operation enabled, IRQAEC deselected
(initial value)
Bit 0: Reserved bit
Bit 0 is a readable/writable reserved bit. It is initialized to 0 by a reset.
Note: Do not set this bit to 1.
6. Event counter control register (ECCR)
Bit
7
6
5
4
3
2
1
0
ACKH1
ACKH0
ACKL1
ACKL0
PWCK0
—
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PWCK2 PWCK1
ECCR performs counter input clock and IRQAEC/IECPWM control.
Bits 7 and 6: AEC clock select H (ACKH1, ACKH0)
Bits 7 and 6 select the clock used by ECH.
Bit 7
ACKH1
Bit 6
ACKH0
Description
0
0
AEVH pin input
1
ø/2
0
ø/4
1
ø/8
1
204
(initial value)
Bits 5 and 4: AEC clock select L (ACKL1, ACKL0)
Bits 5 and 4 select the clock used by ECL.
Bit 5
ACKL1
Bit 4
ACKL0
Description
0
0
AEVL pin input
1
ø/2
0
ø/4
1
ø/8
1
(initial value)
Bits 3 to 1: Event counter PWM clock select (PWCK2, PWCK1, PWCK0)
Bits 3 to 1 select the event counter PWM clock.
Bit 3
PWCK2
Bit 2
PWCK1
Bit 1
PWCK0
Description
0
0
0
ø/2
1
ø/4
0
ø/8
1
ø/16
0
ø/32
1
ø/64
1
1
*
(initial value)
*: Don’t care
Bit 0: Reserved bit
Bit 0 is a readable/writable reserved bit. It is initialized to 0 by a reset.
Note: Do not set this bit to 1.
7. Event counter control/status register (ECCSR)
Bit
7
6
5
4
3
2
1
0
OVH
OVL
—
CH2
CUEH
CUEL
CRCH
CRCL
Initial Value
0
0
0
0
0
0
0
0
Read/Write
R/W*
R/W*
R/W
R/W
R/W
R/W
R/W
R/W
Note: * Bits 7 and 6 can only be written with 0, for flag clearing.
205
ECCSR is an 8-bit read/write register that controls counter overflow detection, counter resetting,
and halting of the count-up function.
ECCSR is initialized to H'00 upon reset.
Bit 7: Counter overflow flag H (OVH)
Bit 7 is a status flag indicating that ECH has overflowed from H'FF to H'00. This flag is set when
ECH overflows. It is cleared by software but cannot be set by software. OVH is cleared by
reading it when set to 1, then writing 0.
When ECH and ECL are used as a 16-bit event counter with CH2 cleared to 0, OVH functions as a
status flag indicating that the 16-bit event counter has overflowed from H'FFFF to H'0000.
Bit 7
OVH
Description
0
ECH has not overflowed
Clearing conditions:
After reading OVH = 1, cleared by writing 0 to OVH
1
ECH has overflowed
Setting conditions:
Set when ECH overflows from H’FF to H’00
(initial value)
Bit 6: Counter overflow flag L (OVL)
Bit 6 is a status flag indicating that ECL has overflowed from H'FF to H'00. This flag is set when
ECL overflows. It is cleared by software but cannot be set by software. OVL is cleared by
reading it when set to 1, then writing 0.
Bit 6
OVL
Description
0
ECL has not overflowed
Clearing conditions:
After reading OVL = 1, cleared by writing 0 to OVL
1
ECL has overflowed
Setting conditions:
Set when ECL overflows from H'FF to H'00 while CH2 is set to 1
Bit 5: Reserved bit
Bit 5 is reserved; it can be read and written, and is initialized to 0 upon reset.
206
(initial value)
Bit 4: Channel select (CH2)
Bit 4 selects whether ECH and ECL are used as a single-channel 16-bit event counter or as two
independent 8-bit event counter channels. When CH2 is cleared to 0, ECH and ECL function as a
16-bit event counter which is incremented each time an event clock is input to the AEVL pin. In
this case, the overflow signal from ECL is selected as the ECH input clock. When CH2 is set to 1,
ECH and ECL function as independent 8-bit event counters which are incremented each time an
event clock is input to the AEVH or AEVL pin, respectively.
Bit 4
CH2
Description
0
ECH and ECL are used together as a single-channel 16-bit event counter
(initial value)
1
ECH and ECL are used as two independent 8-bit event counter channels
Bit 3: Count-up enable H (CUEH)
Bit 3 enables event clock input to ECH. When 1 is written to this bit, event clock input is enabled
and increments the counter. When 0 is written to this bit, event clock input is disabled and the
ECH value is held. The AEVH pin or the ECL overflow signal can be selected as the event clock
source by bit CH2.
Bit 3
CUEH
Description
0
ECH event clock input is disabled
ECH value is held
1
ECH event clock input is enabled
(initial value)
Bit 2: Count-up enable L (CUEL)
Bit 3 enables event clock input to ECL. When 1 is written to this bit, event clock input is enabled
and increments the counter. When 0 is written to this bit, event clock input is disabled and the
ECL value is held.
Bit 2
CUEL
Description
0
ECL event clock input is disabled
ECL value is held
1
ECL event clock input is enabled
(initial value)
207
Bit 1: Counter reset control H (CRCH)
Bit 1 controls resetting of ECH. When this bit is cleared to 0, ECH is reset. When 1 is written to
this bit, the counter reset is cleared and the ECH count-up function is enabled.
Bit 1
CRCH
Description
0
ECH is reset
1
ECH reset is cleared and count-up function is enabled
(initial value)
Bit 0: Counter reset control L (CRCL)
Bit 0 controls resetting of ECL. When this bit is cleared to 0, ECL is reset. When 1 is written to
this bit, the counter reset is cleared and the ECL count-up function is enabled.
Bit 0
CRCL
Description
0
ECL is reset
1
ECL reset is cleared and count-up function is enabled
(initial value)
8. Event counter H (ECH)
Bit
7
6
5
4
3
2
1
0
ECH7
ECH6
ECH5
ECH4
ECH3
ECH2
ECH1
ECH0
Initial Value
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R
R
R
R
ECH is an 8-bit read-only up-counter that operates either as an independent 8-bit event counter or
as the upper 8-bit up-counter of a 16-bit event counter configured in combination with ECL.
Either the external asynchronous event AEVH pin or the overflow signal from lower 8-bit counter
ECL can be selected as the input clock source. ECH can be cleared to H'00 by software, and is
also initialized to H'00 upon reset.
208
9. Event counter L (ECL)
ECL is an 8-bit read-only up-counter that operates either as an independent 8-bit event counter or
as the lower 8-bit up-counter of a 16-bit event counter configured in combination with ECH. The
event clock from the external asynchronous event AEVL pin, or ø/2, ø/4, or ø/8, is used as the
input clock source. ECL can be cleared to H'00 by software, and is also initialized to H'00 upon
reset.
Bit
7
6
5
4
3
2
1
0
ECL7
ECL6
ECL5
ECL4
ECL3
ECL2
ECL1
ECL0
Initial Value
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R
R
R
R
1
0
10. Clock stop register 2 (CKSTPR2)
Bit
7
6
5
—
—
—
4
3
Initial value
1
1
1
1
1
1
1
1
Read/Write
—
—
—
R/W
R/W
—
R/W
R/W
PW2CKSTP AECKSTP
2
—
PW1CKSTP LDCKSTP
CKSTPR2 is an 8-bit read/write register that performs module standby mode control for peripheral
modules. Only the bit relating to the asynchronous event counter is described here. For details of
the other bits, see the sections on the relevant modules.
Bit 3: Asynchronous event counter module standby mode control (AECKSTP)
Bit 3 controls setting and clearing of module standby mode for the asynchronous event counter.
AECKSTP
Description
0
Asynchronous event counter is set to module standby mode
1
Asynchronous event counter module standby mode is cleared
(initial value)
209
9.4.3
Operation
1. 16-bit event counter operation
When bit CH2 is cleared to 0 in ECCSR, ECH and ECL operate as a 16-bit event counter.
Any of four input clock sources—ø/2, ø/4, ø/8, or AEVL pin input—can be selected by means of
bits ACKL1 and ACKL0 in ECCR.
When AEVL pin input is selected, input sensing is selected with bits ALEGS1 and ALEGS0.
The input clock is enabled only when IRQAEC is high or IECPWM is high. When IRQAEC is
low or IECPWM is low, the input clock is not input to the counter, which therefore does not
operate. Figure 9.8 shows an example of the software processing when ECH and ECL are used as
a 16-bit event counter.
Start
Clear CH2 to 0
Set ACKL1—0 and ALEGS1—0
Clear CUEH, CUEL, CRCH, and CRCL to 0
Clear OVH and OVL to 0
Set CUEH, CUEL, CRCH, and CRCL to 1
End
Figure 9.8 Example of Software Processing when Using ECH and ECL as 16-Bit Event
Counter
As CH2 is cleared to 0 by a reset, ECH and ECL operate as a 16-bit event counter after a reset,
and as ACKL1 and ACKL0 are cleared to 00, the operating clock is asynchronous event input
from the AEVL pin (using falling edge sensing). When the next clock is input after the count
value reaches H'FF in both ECH and ECL, ECH and ECL overflow from H'FFFF to H'0000, the
OVH flag is set to 1 in ECCSR, the ECH and ECL count values each return to H'00, and counting
up is restarted. When overflow occurs, the IRREC bit is set to 1 in IRR2. If the IENEC bit in
IENR2 is 1 at this time, an interrupt request is sent to the CPU.
210
2. 8-bit event counter operation
When bit CH2 is set to 1 in ECCSR, ECH and ECL operate as independent 8-bit event counters.
ø/2, ø/4, ø/8, or AEVH pin input can be selected as the input clock source for ECH by means of
bits ACKH1 and ACKH0 in ECCR, and ø/2, ø/4, ø/8, or AEVL pin input can be selected as the
input clock source for ECL by means of bits ACKL1 and ACKL0 in ECCR.
Input sensing is selected with bits AHEGS1 and AHEGS0 when AEVH pin input is selected, and
with bits ALEGS1 and ALEGS0 when AEVL pin input is selected.
The input clock is enabled only when IRQAEC is high or IECPWM is high. When IRQAEC is
low or IECPWM is low, the input clock is not input to the counter, which therefore does not
operate. Figure 9.9 shows an example of the software processing when ECH and ECL are used as
8-bit event counters.
Start
Set CH2 to 1
Set ACKH1—0, ACKL1—0, AHEGS1—0, ALEGS1—0
Clear CUEH, CUEL, CRCH, and CRCL to 0
Clear OVH to 0
Set CUEH, CUEL, CRCH, and CRCL to 1
End
Figure 9.9 Example of Software Processing when Using ECH and ECL as 8-Bit Event
Counters
ECH and ECL can be used as 8-bit event counters by carrying out the software processing shown
in the example in figure 9.9. When the next clock is input after the ECH count value reaches
H'FF, ECH overflows, the OVH flag is set to 1 in ECCSR, the ECH count value returns to H'00,
and counting up is restarted. Similarly, when the next clock is input after the ECL count value
reaches H'FF, ECL overflows, the OVL flag is set to 1 in ECCSR, the ECL count value returns to
H'00, and counting up is restarted. When overflow occurs, the IRREC bit is set to 1 in IRR2. If
the IENEC bit in IENR2 is 1 at this time, an interrupt request is sent to the CPU.
211
3. IRQAEC operation
When ECPWME in AEGSR is 0, the ECH and ECL input clocks are enabled only when IRQAEC
is high. When IRQAEC is low, the input clocks are not input to the counters, and so ECH and
ECL do not count. ECH and ECL count operations can therefore be controlled from outside by
controlling IRQAEC. In this case, ECH and ECL cannot be controlled individually.
IRQAEC can also operate as an interrupt source. In this case the vector number is 6 and the vector
addresses are H'000C and H'000D.
Interrupt enabling is controlled by IENEC2 in IENR1. When an IRQAEC interrupt is generated,
IRR1 interrupt request flag IRREC2 is set to 1. If IENEC2 in IENR1 is set to 1 at this time, an
interrupt request is sent to the CPU.
Rising, falling, or both edge sensing can be selected for the IRQAEC input pin with bits AIAGS1
and AIAGS0 in AEGSR.
4. Event counter PWM operation
When ECPWME in AEGSR is 1, the ECH and ECL input clocks are enabled only when event
counter PWM output (IECPWM) is high. When IECPWM is low, the input clocks are not input to
the counters, and so ECH and ECL do not count. ECH and ECL count operations can therefore be
controlled cyclically from outside by controlling event counter PWM. In this case, ECH and ECL
cannot be controlled individually.
IECPWM can also operate as an interrupt source. In this case the vector number is 6 and the
vector addresses are H'000C and H'000D.
Interrupt enabling is controlled by IENEC2 in IENR1. When an IECPWM interrupt is generated,
IRR1 interrupt request flag IRREC2 is set to 1. If IENEC2 in IENR1 is set to 1 at this time, an
interrupt request is sent to the CPU.
Rising, falling, or both edge detection can be selected for IECPWM interrupt sensing with bits
AIAGS1 and AIAGS0 in AEGSR.
Figure 9.10 and table 9.9 show examples of event counter PWM operation.
212
toff = T × (Ndr +1)
Ton :
Toff :
Tcm :
T:
Ndr :
Clock input enabled time
Clock input disabled time
One conversion period
ECPWM input clock cycle
Value of ECPWDRH and ECPWDRL
Fixed high when Ndr = H'FFFF
Ncm : Value of ECPWCRH and ECPWCRL
ton
tcm = T × (Ncm +1)
Figure 9.10 Event Counter Operation Waveform
Note: Ndr and N cm above must be set so that Ndr < Ncm. If the settings do not satisfy this
condition, do not set ECPWME to 1 in AEGSR.
Table 9.9
Examples of Event Counter PWM Operation
Conditions: fosc = 4 MHz, fø = 2 MHz, high-speed active mode, ECPWCR value (Ncm) = H'7A11,
ECPWDR value (Ndr) = H'16E3
Clock Source Clock Source ECPWMCR ECPWMDR toff = T ×
Selection
Cycle (T)*
Value (Ncm) Value (Ndr) (Ndr + 1)
tcm = T ×
(Ncm + 1)
ton = tcm – toff
ø/2
1 µs
5.86 ms
31.25 ms
25.39 ms
ø/4
2 µs
11.72 ms
62.5 ms
50.78 ms
ø/8
4 µs
23.44 ms
125.0 ms
101.56 ms
ø/16
8 µs
46.88 ms
250.0 ms
203.12 ms
ø/32
16 µs
93.76 ms
500.0 ms
406.24 ms
ø/64
32 µs
187.52 ms 1000.0 ms 812.48 ms
H'7A11
D'31249
H'16E3
D'5859
Note: * t off minimum width
5. Clock Input Enable/Disable Function Operation
The clock input to the event counter can be controlled by the IRQAEC pin when ECPWME in
AEGSR is 0, and by event counter PWM output IECPWM when ECPWME in AEGSR is 1. As
this function forcibly terminates the clock input by each signal, a maximum error of one count will
occur depending the IRQAEC or IECPWM timing.
Figure 9.11 shows an example of the operation of this function.
213
Input event
IRQAEC or IECPWM
Edge generated by clock return
Actually counted clock source
Counter value
N
N+1
N+2
N+3
N+4
N+5
N+6
Clock stopped
Figure 9.11 Example of Clock Control Operation
9.4.4
Asynchronous Event Counter Operation Modes
Asynchronous event counter operation modes are shown in table 9.10.
Table 9.10 Asynchronous Event Counter Operation Modes
Operation
Mode
Reset Active
AEGSR
Reset
ECCR
ECCSR
ECH
Reset
Reset
Reset
Watch
Subactive
Subsleep
Standby
Module
Standby
Functions Functions
Held*1
Functions
Functions
Held*1
Held
Functions Functions
1
Functions
1
Held
Sleep
Functions Functions
Functions Functions
Held*
Functions
1
Held*
Functions
Held*
1
Functions
1 2
2
1 2
2
Functions* * Functions*
Held*
Held
2
Functions* * Halted
2
Functions*
1 2
ECL
Reset
Functions Functions
Functions* * Functions*
Functions*
Functions*1*2 Halted
IEQAEC
Reset
Functions Functions
Held*3
Functions
Functions
Held*3
Held*4
Event
counter
PWM
Reset
Functions Functions
Held
Held
Held
Held
Held
Notes: 1. When an asynchronous external event is input, the counter increments but the counter
overflow H/L flags are not affected.
2. Operates when asynchronous mode external events are selected; halted and retained
otherwise.
3. Clock control by IRQAEC operates, but interrupts do not.
4. As the clock is stopped in module standby mode, IRQAEC has no effect.
214
9.4.5
Application Notes
1. When reading the values in ECH and ECL, first clear bits CUEH and CUEL to 0 in ECCSR to
prevent asynchronous event input to the counter. The correct value will not be returned if the
event counter increments while being read.
2. Use a clock with a frequency of up to 16 MHz for input to the AEVH and AEVL pins, and
ensure that the high and low widths of the clock are at least 30 ns. The duty cycle is
immaterial.
Mode
Maximum AEVH/AEVL Pin Input
Clock Frequency
Active (high-speed), sleep (high-speed)
16 MHz
Active (medium-speed), sleep (medium-speed) (ø/16)
2 · fOSC
(ø/32)
f OSC
(ø/64)
1/2 · f OSC
f OSC = 1 MHz to 4 MHz
(ø/128)
1/4 · f OSC
Watch, subactive, subsleep, standby
(øw/2)
1000 kHz
(øw/4)
500 kHz
øw = 32.768 kHz or 38.4 kHz
(øw/8)
250 kHz
3. When AEC uses with 16-bit mode, set CUEH in ECCSR to “1” first, set CRCH in ECCSR to
“1” second, or set both CUEH and CRCH to “1” at same time before clock entry. While AEC
is operating on 16-bit mode, do not change CUEH. Otherwise, ECH will be miscounted up.
4. When ECPWME in AEGSR is 1, event counter PWM is operating and therefore ECPWCRH,
ECPWCRL, ECPWDRH, and ECPWDRL should not be modified.
When changing the data, event counter PWM must be halted by clearing ECPWME to 0 in
AEGSR before modifying these registers.
5. The event counter PWM data register and event counter PWM compare register must be set so
that event counter PWM data register < event counter PWM compare register. If the settings
do not satisfy this condition, do not set ECPWME to 1 in AEGSR.
6. As synchronization is established internally when an IRQAEC interrupt is generated, a
maximum error of 1 tcyc will occur between clock halting and interrupt acceptance.
215
216
Section 10 Serial Communication Interface
10.1
Overview
The H8/3802 Series is provided with one serial communication interface, SCI3.
Serial communication interface 3 (SCI3) can carry out serial data communication in either
asynchronous or synchronous mode. It is also provided with a multiprocessor communication
function that enables serial data to be transferred among processors.
10.1.1
Features
Features of SCI3 are listed below.
• Choice of asynchronous or synchronous mode for serial data communication
 Asynchronous mode
Serial data communication is performed asynchronously, with synchronization provided
character by character. In this mode, serial data can be exchanged with standard
asynchronous communication LSIs such as a Universal Asynchronous
Receiver/Transmitter (UART) or Asynchronous Communication Interface Adapter
(ACIA). A multiprocessor communication function is also provided, enabling serial data
communication among processors.
There is a choice of 16 data transfer formats.
Data length
7, 8, 5 bits
Stop bit length
1 or 2 bits
Parity
Even, odd, or none
Multiprocessor bit
1 or 0
Receive error detection
Parity, overrun, and framing errors
Break detection
Break detected by reading the RXD 32 pin level directly when a
framing error occurs
217
 Synchronous mode
Serial data communication is synchronized with a clock. In his mode, serial data can be
exchanged with another LSI that has a synchronous communication function.
Data length
8 bits
Receive error detection
Overrun errors
• Full-duplex communication
Separate transmission and reception units are provided, enabling transmission and reception to
be carried out simultaneously. The transmission and reception units are both double-buffered,
allowing continuous transmission and reception.
• On-chip baud rate generator, allowing any desired bit rate to be selected
• Choice of an internal or external clock as the transmit/receive clock source
• Six interrupt sources: transmit end, transmit data empty, receive data full, overrun error,
framing error, and parity error
218
10.1.2
Block diagram
Figure 10.1 shows a block diagram of SCI3.
SCK32
External
clock
Internal clock (ø/64, ø/16, øw/2, ø)
Baud rate generator
BRC
BRR
SMR
Transmit/receive
control circuit
SCR3
SSR
TXD
TSR
TDR
RSR
RDR
Internal data bus
Clock
SPCR
RXD
Interrupt request
(TEI, TXI, RXI, ERI)
Notation:
RSR:
Receive shift register
RDR: Receive data register
TSR:
Transmit shift register
TDR:
Transmit data register
SMR: Serial mode register
SCR3: Serial control register 3
SSR:
Serial status register
BRR:
Bit rate register
BRC:
Bit rate counter
SPCR: Serial port control register
Figure 10.1 SCI3 Block Diagram
219
10.1.3
Pin configuration
Table 10.1 shows the SCI3 pin configuration.
Table 10.1 Pin Configuration
Name
Abbrev.
I/O
Function
SCI3 clock
SCK 32
I/O
SCI3 clock input/output
SCI3 receive data input
RXD32
Input
SCI3 receive data input
SCI3 transmit data output
TXD32
Output
SCI3 transmit data output
10.1.4
Register configuration
Table 10.2 shows the SCI3 register configuration.
Table 10.2 Registers
Name
Abbrev.
R/W
Initial Value
Address
Serial mode register
SMR
R/W
H'00
H'FFA8
Bit rate register
BRR
R/W
H'FF
H'FFA9
Serial control register 3
SCR3
R/W
H'00
H'FFAA
Transmit data register
TDR
R/W
H'FF
H'FFAB
Serial data register
SSR
R/W
H'84
H'FFAC
Receive data register
RDR
R
H'00
H'FFAD
Transmit shift register
TSR
Protected —
—
Receive shift register
RSR
Protected —
—
Bit rate counter
BRC
Protected —
—
Clock stop register 1
CKSTPR1
R/W
H'FF
H'FFFA
Serial port control register
SPCR
R/W
—
H'FF91
220
10.2
Register Descriptions
10.2.1
Receive shift register (RSR)
Bit
7
6
5
4
3
2
1
0
Read/Write
—
—
—
—
—
—
—
—
RSR is a register used to receive serial data. Serial data input to RSR from the RXD32 pin is set in
the order in which it is received, starting from the LSB (bit 0), and converted to parallel data.
When one byte of data is received, it is transferred to RDR automatically.
RSR cannot be read or written directly by the CPU.
10.2.2
Receive data register (RDR)
Bit
7
6
5
4
3
2
1
0
RDR7
RDR6
RDR5
RDR4
RDR3
RDR2
RDR1
RDR0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R
R
R
R
RDR is an 8-bit register that stores received serial data.
When reception of one byte of data is finished, the received data is transferred from RSR to RDR,
and the receive operation is completed. RSR is then able to receive data. RSR and RDR are
double-buffered, allowing consecutive receive operations.
RDR is a read-only register, and cannot be written by the CPU.
RDR is initialized to H'00 upon reset, and in standby, module standby or watch mode.
221
10.2.3
Transmit shift register (TSR)
Bit
7
6
5
4
3
2
1
0
Read/Write
—
—
—
—
—
—
—
—
TSR is a register used to transmit serial data. Transmit data is first transferred from TDR to TSR,
and serial data transmission is carried out by sending the data to the TXD 32 pin in order, starting
from the LSB (bit 0). When one byte of data is transmitted, the next byte of transmit data is
transferred to TDR, and transmission started, automatically. Data transfer from TDR to TSR is
not performed if no data has been written to TDR (if bit TDRE is set to 1 in the serial status
register (SSR)).
TSR cannot be read or written directly by the CPU.
10.2.4
Transmit data register (TDR)
Bit
7
6
5
4
3
2
1
0
TDR7
TDR6
TDR5
TDR4
TDR3
TDR2
TDR1
TDR0
Initial value
1
1
1
1
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TDR is an 8-bit register that stores transmit data. When TSR is found to be empty, the transmit
data written in TDR is transferred to TSR, and serial data transmission is started. Continuous
transmission is possible by writing the next transmit data to TDR during TSR serial data
transmission.
TDR can be read or written by the CPU at any time.
TDR is initialized to H'FF upon reset, and in standby, module standby, or watch mode.
222
10.2.5
Serial mode register (SMR)
Bit
7
6
5
4
3
2
1
0
COM
CHR
PE
PM
STOP
MP
CKS1
CKS0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
SMR is an 8-bit register used to set the serial data transfer format and to select the clock source for
the baud rate generator.
SMR can be read or written by the CPU at any time.
SMR is initialized to H'00 upon reset, and in standby, module standby, or watch mode.
Bit 7: Communication mode (COM)
Bit 7 selects whether SCI3 operates in asynchronous mode or synchronous mode.
Bit 7
COM
Description
0
Asynchronous mode
1
Synchronous mode
(initial value)
Bit 6: Character length (CHR)
Bit 6 selects either 7 or 8 bits as the data length to be used in asynchronous mode. In synchronous
mode the data length is always 8 bits, irrespective of the bit 6 setting.
Bit 6
CHR
Description
0
8-bit data/5-bit data *2
1
*1
(initial value)
*2
7-bit data /5-bit data
Notes: 1. When 7-bit data is selected, the MSB (bit 7) of TDR is not transmitted.
2. When 5-bit data is selected, set both PE and MP to 1. The three most significant bits
(bits 7, 6, and 5) of TDR are not transmitted.
223
Bit 5: Parity enable (PE)
Bit 5 selects whether a parity bit is to be added during transmission and checked during reception
in asynchronous mode. In synchronous mode parity bit addition and checking is not performed,
irrespective of the bit 5 setting.
Bit 5
PE
Description
0
Parity bit addition and checking disabled *2
1
Parity bit addition and checking enabled
(initial value)
*1/*2
Notes: 1. When PE is set to 1, even or odd parity, as designated by bit PM, is added to transmit
data before it is sent, and the received parity bit is checked against the parity
designated by bit PM.
2. For the case where 5-bit data is selected, see table 10.11.
Bit 4: Parity mode (PM)
Bit 4 selects whether even or odd parity is to be used for parity addition and checking. The PM bit
setting is only valid in asynchronous mode when bit PE is set to 1, enabling parity bit addition and
checking. The PM bit setting is invalid in synchronous mode, and in asynchronous mode if parity
bit addition and checking is disabled.
Bit 4
PM
Description
0
Even parity*1
1
Odd parity
(initial value)
*2
Notes: 1. When even parity is selected, a parity bit is added in transmission so that the total
number of 1 bits in the transmit data plus the parity bit is an even number; in reception,
a check is carried out to confirm that the number of 1 bits in the receive data plus the
parity bit is an even number.
2. When odd parity is selected, a parity bit is added in transmission so that the total
number of 1 bits in the transmit data plus the parity bit is an odd number; in reception, a
check is carried out to confirm that the number of 1 bits in the receive data plus the
parity bit is an odd number.
224
Bit 3: Stop bit length (STOP)
Bit 3 selects 1 bit or 2 bits as the stop bit length in asynchronous mode. The STOP bit setting is
only valid in asynchronous mode. When synchronous mode is selected the STOP bit setting is
invalid since stop bits are not added.
Bit 3
STOP
Description
0
1 stop bit *1
1
2 stop bits
(initial value)
*2
Notes: 1. In transmission, a single 1 bit (stop bit) is added at the end of a transmit character.
2. In transmission, two 1 bits (stop bits) are added at the end of a transmit character.
In reception, only the first of the received stop bits is checked, irrespective of the STOP bit setting.
If the second stop bit is 1 it is treated as a stop bit, but if 0, it is treated as the start bit of the next
transmit character.
Bit 2: Multiprocessor mode (MP)
Bit 2 enables or disables the multiprocessor communication function. When the multiprocessor
communication function is enabled, the parity settings in the PE and PM bits are invalid. The MP
bit setting is only valid in asynchronous mode. When synchronous mode is selected the MP bit
should be set to 0. For details on the multiprocessor communication function, see 10.3.4,
Multiprocessor Communication Function.
Bit 2
MP
Description
0
Multiprocessor communication function disabled*
1
Multiprocessor communication function enabled*
(initial value)
Note: * For the case where 5-bit data is selected, see table 10.11.
225
Bits 1 and 0: Clock select 1, 0 (CKS1, CKS0)
Bits 1 and 0 choose ø/64, ø/16, øw/2, or ø as the clock source for the baud rate generator.
For the relation between the clock source, bit rate register setting, and baud rate, see 8, Bit rate
register (BRR).
Bit 1
CKS1
Bit 0
CKS0
Description
0
0
ø clock
(initial value)
*1
*2
0
1
ø w/2 clock /ø w clock
1
0
ø/16 clock
1
1
ø/64 clock
Notes: 1. ø w/2 clock in active (medium-speed/high-speed) mode and sleep mode
2. ø w clock in subactive mode and subsleep mode
3. In subactive or subsleep mode, SCI3 can be operated when CPU clock is øw/2 only.
10.2.6
Serial control register 3 (SCR3)
Bit
7
6
5
4
3
2
1
0
TIE
RIE
TE
RE
MPIE
TEIE
CKE1
CKE0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
SCR3 is an 8-bit register for selecting transmit or receive operation, the asynchronous mode clock
output, interrupt request enabling or disabling, and the transmit/receive clock source.
SCR3 can be read or written by the CPU at any time.
SCR3 is initialized to H'00 upon reset, and in standby, module standby or watch mode.
226
Bit 7: Transmit interrupt enable (TIE)
Bit 7 selects enabling or disabling of the transmit data empty interrupt request (TXI) when
transmit data is transferred from the transmit data register (TDR) to the transmit shift register
(TSR), and bit TDRE in the serial status register (SSR) is set to 1.
TXI can be released by clearing bit TDRE or bit TIE to 0.
Bit 7
TIE
Description
0
Transmit data empty interrupt request (TXI) disabled
1
Transmit data empty interrupt request (TXI) enabled
(initial value)
Bit 6: Receive interrupt enable (RIE)
Bit 6 selects enabling or disabling of the receive data full interrupt request (RXI) and the receive
error interrupt request (ERI) when receive data is transferred from the receive shift register (RSR)
to the receive data register (RDR), and bit RDRF in the serial status register (SSR) is set to 1.
There are three kinds of receive error: overrun, framing, and parity.
RXI and ERI can be released by clearing bit RDRF or the FER, PER, or OER error flag to 0, or by
clearing bit RIE to 0.
Bit 6
RIE
Description
0
Receive data full interrupt request (RXI) and receive error interrupt
request (ERI) disabled
1
Receive data full interrupt request (RXI) and receive error interrupt
request (ERI) enabled
(initial value)
Bit 5: Transmit enable (TE)
Bit 5 selects enabling or disabling of the start of transmit operation.
Bit 5
TE
Description
0
Transmit operation disabled*1 (TXD32 pin is transmit data pin)
1
(initial value)
*2
Transmit operation enabled (TXD32 pin is transmit data pin)
Notes: 1. Bit TDRE in SSR is fixed at 1.
2. When transmit data is written to TDR in this state, bit TDR in SSR is cleared to 0 and
serial data transmission is started. Be sure to carry out serial mode register (SMR)
settings, and setting of bit SPC32 in SPCR, to decide the transmission format before
setting bit TE to 1.
227
Bit 4: Receive enable (RE)
Bit 4 selects enabling or disabling of the start of receive operation.
Bit 4
RE
Description
0
Receive operation disabled *1 (RXD pin is I/O port)
1
(initial value)
*2
Receive operation enabled (RXD pin is receive data pin)
Notes: 1. Note that the RDRF, FER, PER, and OER flags in SSR are not affected when bit RE is
cleared to 0, and retain their previous state.
2. In this state, serial data reception is started when a start bit is detected in asynchronous
mode or serial clock input is detected in synchronous mode. Be sure to carry out serial
mode register (SMR) settings to decide the reception format before setting bit RE to 1.
Bit 3: Multiprocessor interrupt enable (MPIE)
Bit 3 selects enabling or disabling of the multiprocessor interrupt request. The MPIE bit setting is
only valid when asynchronous mode is selected and reception is carried out with bit MP in SMR
set to 1. The MPIE bit setting is invalid when bit COM is set to 1 or bit MP is cleared to 0.
Bit 3
MPIE
Description
0
Multiprocessor interrupt request disabled (normal receive operation)
Clearing conditions:
When data is received in which the multiprocessor bit is set to 1
1
Multiprocessor interrupt request enabled*
(initial value)
Note: * Receive data transfer from RSR to RDR, receive error detection, and setting of the RDRF,
FER, and OER status flags in SSR is not performed. RXI, ERI, and setting of the RDRF,
FER, and OER flags in SSR, are disabled until data with the multiprocessor bit set to 1 is
received. When a receive character with the multiprocessor bit set to 1 is received, bit
MPBR in SSR is set to 1, bit MPIE is automatically cleared to 0, and RXI and ERI requests
(when bits TIE and RIE in serial control register 3 (SCR3) are set to 1) and setting of the
RDRF, FER, and OER flags are enabled.
228
Bit 2: Transmit end interrupt enable (TEIE)
Bit 2 selects enabling or disabling of the transmit end interrupt request (TEI) if there is no valid
transmit data in TDR when MSB data is to be sent.
Bit 2
TEIE
Description
0
Transmit end interrupt request (TEI) disabled
1
Transmit end interrupt request (TEI) enabled*
(initial value)
Note: * TEI can be released by clearing bit TDRE to 0 and clearing bit TEND to 0 in SSR, or by
clearing bit TEIE to 0.
Bits 1 and 0: Clock enable 1 and 0 (CKE1, CKE0)
Bits 1 and 0 select the clock source and enabling or disabling of clock output from the SCK32 pin.
The combination of CKE1 and CKE0 determines whether the SCK 32 pin functions as an I/O port,
a clock output pin, or a clock input pin.
The CKE0 bit setting is only valid in case of internal clock operation (CKE1 = 0) in asynchronous
mode. In synchronous mode, or when external clock operation is used (CKE1 = 1), bit CKE0
should be cleared to 0.
After setting bits CKE1 and CKE0, set the operating mode in the serial mode register (SMR).
For details on clock source selection, see table 10.9 in 10.3.1.
Bit 1
Bit 0
CKE1
CKE0
Communication Mode
Clock Source
SCK32 Pin Function
0
0
Asynchronous
Internal clock
I/O port*1
Synchronous
Internal clock
Serial clock output *1
Asynchronous
Internal clock
Clock output*2
Synchronous
Reserved
Asynchronous
External clock
Clock input *3
Synchronous
External clock
Serial clock input
Asynchronous
Reserved
Synchronous
Reserved
0
1
1
1
0
1
Description
Notes: 1. Initial value
2. A clock with the same frequency as the bit rate is output.
3. Input a clock with a frequency 16 times the bit rate.
229
10.2.7
Serial status register (SSR)
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
TDRE
RDRF
OER
FER
PER
TEND
MPBR
MPBT
1
R/(W) *
0
0
0
0
1
0
0
R/(W)*
R/(W) *
R/(W)*
R/(W) *
R
R
R/W
Note: * Only a write of 0 for flag clearing is possible.
SSR is an 8-bit register containing status flags that indicate the operational status of SCI3, and
multiprocessor bits.
SSR can be read or written to by the CPU at any time, but 1 cannot be written to bits TDRE,
RDRF, OER, PER, and FER.
Bits TEND and MPBR are read-only bits, and cannot be modified.
SSR is initialized to H'84 upon reset, and in standby, module standby, or watch mode.
Bit 7: Transmit data register empty (TDRE)
Bit 7 indicates that transmit data has been transferred from TDR to TSR.
Bit 7
TDRE
Description
0
Transmit data written in TDR has not been transferred to TSR
Clearing conditions:
After reading TDRE = 1, cleared by writing 0 to TDRE
When data is written to TDR by an instruction
1
Transmit data has not been written to TDR, or transmit data written in
TDR has been transferred to TSR
Setting conditions:
When bit TE in SCR3 is cleared to 0
When data is transferred from TDR to TSR
230
(initial value)
Bit 6: Receive data register full (RDRF)
Bit 6 indicates that received data is stored in RDR.
Bit 6
RDRF
Description
0
There is no receive data in RDR
Clearing conditions:
After reading RDRF = 1, cleared by writing 0 to RDRF
When RDR data is read by an instruction
(initial value)
1
There is receive data in RDR
Setting conditions:
When reception ends normally and receive data is transferred from RSR to RDR
Note: If an error is detected in the receive data, or if the RE bit in SCR3 has been cleared to 0,
RDR and bit RDRF are not affected and retain their previous state.
Note that if data reception is completed while bit RDRF is still set to 1, an overrun error
(OER) will result and the receive data will be lost.
Bit 5: Overrun error (OER)
Bit 5 indicates that an overrun error has occurred during reception.
Bit 5
OER
Description
0
Reception in progress or completed*1
Clearing conditions:
After reading OER = 1, cleared by writing 0 to OER
1
An overrun error has occurred during reception*2
Setting conditions:
When reception is completed with RDRF set to 1
(initial value)
Notes: 1. When bit RE in SCR3 is cleared to 0, bit OER is not affected and retains its previous
state.
2. RDR retains the receive data it held before the overrun error occurred, and data
received after the error is lost. Reception cannot be continued with bit OER set to 1,
and in synchronous mode, transmission cannot be continued either.
231
Bit 4: Framing error (FER)
Bit 4 indicates that a framing error has occurred during reception in asynchronous mode.
Bit 4
FER
Description
0
Reception in progress or completed*1
Clearing conditions:
After reading FER = 1, cleared by writing 0 to FER
1
A framing error has occurred during reception
Setting conditions:
When the stop bit at the end of the receive data is checked for a value
of 1 at the end of reception, and the stop bit is 0*2
(initial value)
Notes: 1. When bit RE in SCR3 is cleared to 0, bit FER is not affected and retains its previous
state.
2. Note that, in 2-stop-bit mode, only the first stop bit is checked for a value of 1, and the
second stop bit is not checked. When a framing error occurs the receive data is
transferred to RDR but bit RDRF is not set. Reception cannot be continued with bit
FER set to 1. In synchronous mode, neither transmission nor reception is possible
when bit FER is set to 1.
Bit 3: Parity error (PER)
Bit 3 indicates that a parity error has occurred during reception with parity added in asynchronous
mode.
Bit 3
PER
Description
0
Reception in progress or completed*1
Clearing conditions:
After reading PER = 1, cleared by writing 0 to PER
1
A parity error has occurred during reception *2
Setting conditions:
When the number of 1 bits in the receive data plus parity bit does not
match the parity designated by bit PM in the serial mode register (SMR)
(initial value)
Notes: 1. When bit RE in SCR3 is cleared to 0, bit PER is not affected and retains its previous
state.
2. Receive data in which it a parity error has occurred is still transferred to RDR, but bit
RDRF is not set. Reception cannot be continued with bit PER set to 1. In synchronous
mode, neither transmission nor reception is possible when bit FER is set to 1.
232
Bit 2: Transmit end (TEND)
Bit 2 indicates that bit TDRE is set to 1 when the last bit of a transmit character is sent.
Bit 2 is a read-only bit and cannot be modified.
Bit 2
TEND
Description
0
Transmission in progress
Clearing conditions:
After reading TDRE = 1, cleared by writing 0 to TDRE
When data is written to TDR by an instruction
1
Transmission ended
(initial value)
Setting conditions:
When bit TE in SCR3 is cleared to 0
When bit TDRE is set to 1 when the last bit of a transmit character is sent
Bit 1: Multiprocessor bit receive (MPBR)
Bit 1 stores the multiprocessor bit in a receive character during multiprocessor format reception in
asynchronous mode.
Bit 1 is a read-only bit and cannot be modified.
Bit 1
MPBR
Description
0
Data in which the multiprocessor bit is 0 has been received*
1
Data in which the multiprocessor bit is 1 has been received
(initial value)
Note: * When bit RE is cleared to 0 in SCR3 with the multiprocessor format, bit MPBR is not
affected and retains its previous state.
Bit 0: Multiprocessor bit transfer (MPBT)
Bit 0 stores the multiprocessor bit added to transmit data when transmitting in asynchronous
mode. The bit MPBT setting is invalid when synchronous mode is selected, when the
multiprocessor communication function is disabled, and when not transmitting.
Bit 0
MPBT
Description
0
A 0 multiprocessor bit is transmitted
1
A 1 multiprocessor bit is transmitted
(initial value)
233
10.2.8
Bit rate register (BRR)
Bit
7
6
5
4
3
2
1
0
BRR7
BRR6
BRR5
BRR4
BRR3
BRR2
BRR1
BRR0
Initial value
1
1
1
1
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
BRR is an 8-bit register that designates the transmit/receive bit rate in accordance with the baud
rate generator operating clock selected by bits CKS1 and CKS0 of the serial mode register (SMR).
BRR can be read or written by the CPU at any time.
BRR is initialized to H'FF upon reset, and in standby, module standby, or watch mode.
Table 10.3 shows examples of BRR settings in asynchronous mode. The values shown are for
active (high-speed) mode.
Table 10.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (1)
OSC
32.8 kHz
B Bit Rate
(bit/s)
n
N
38.4 kHz
Error
(%) n
2 MHz
2.4576 MHz
4 MHz
N
Error
(%) n
N
Error
(%) n
N
Error
(%) n
N
Error
(%)
110
Cannot be used, —
—
—
—
—
—
2
21
–0.83 —
—
—
150
as error
0
3
0
2
12
0.16
3
3
0
2
25
0.16
200
exceeds 3%
0
2
0
0
155 0.16
3
2
0
—
—
—
250
—
—
—
0
124 0
0
153 –0.26 0
249 0
300
0
1
0
0
103 0.16
3
1
0
2
12
600
0
0
0
0
51
0.16
3
0
0
0
103 0.16
1200
—
—
—
0
25
0.16
2
1
0
0
51
0.16
2400
—
—
—
0
12
0.16
2
0
0
0
25
0.16
4800
—
—
—
—
—
—
0
7
0
0
12
0.16
9600
—
—
—
—
—
—
0
3
0
—
—
—
19200
—
—
—
—
—
—
0
1
0
—
—
—
31250
—
—
—
0
0
0
—
—
—
0
1
0
38400
—
—
—
—
—
—
0
0
0
—
—
—
234
0.16
Table 10.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (2)
OSC
10 MHz
16 MHz
B Bit Rate
(bit/s)
n
N
Error
(%) n
N
110
2
88
–0.25 2
141 –0.02
150
2
64
0.16
103 0.16
200
2
48
–0.35 2
77
0.16
250
2
38
0.16
2
62
–0.79
300
—
—
—
2
51
0.16
600
—
—
—
2
25
0.16
1200
0
129 0.16
0
207 0.16
2400
0
64
0.16
0
103 0.16
4800
—
—
—
0
51
0.16
9600
—
—
—
0
25
0.16
19200
—
—
—
0
12
0.16
31250
0
4
0
0
7
0
38400
—
—
—
—
—
—
2
Error
(%)
Notes: 1. The setting should be made so that the error is not more than 1%.
2. The value set in BRR is given by the following equation:
N=
OSC
(64 × 2 2n × B)
—1
where
B:
Bit rate (bit/s)
N:
Baud rate generator BRR setting (0 ≤ N ≤ 255)
OSC: Value of øOSC (Hz)
n:
Baud rate generator input clock number (n = 0, 2, or 3)
(The relation between n and the clock is shown in table 10.4.)
3. The error in table 10.3 is the value obtained from the following equation, rounded to two
decimal places.
Error (%) =
B (rate obtained from n, N, OSC) — R(bit rate in left-hand column in table 10.3.)
R (bit rate in left-hand column in table 10.3.)
× 100
235
Table 10.4 Relation between n and Clock
SMR Setting
n
Clock
0
ø
*1
*2
CKS1
CKS0
0
0
0
øw/2 /øw
0
1
2
ø/16
1
0
3
ø/64
1
1
Notes: 1. ø w/2 clock in active (medium-speed/high-speed) mode and sleep mode
2. ø w clock in subactive mode and subsleep mode
In subactive or subsleep mode, SCI3 can be operated when CPU clock is øw/2 only.
Table 10.5 shows the maximum bit rate for each frequency. The values shown are for active
(high-speed) mode.
Table 10.5 Maximum Bit Rate for Each Frequency (Asynchronous Mode)
Maximum Bit Rate
Setting
OSC (MHz)
(bit/s)
n
N
0.0384*
600
0
0
2
31250
0
0
2.4576
38400
0
0
4
62500
0
0
10
156250
0
0
16
250000
0
0
Note: * When SMR is set up to CKS1 = 0, CKS0 = 1.
236
Table 10.6 shows examples of BRR settings in synchronous mode. The values shown are for
active (high-speed) mode.
Table 10.6 Examples of BRR Settings for Various Bit Rates (Synchronous Mode) (1)
OSC
B Bit Rate
38.4 kHz
2 MHz
4 MHz
(bit/s)
n
N
Error
n
N
Error
n
N
Error
200
0
23
0
—
—
—
—
—
—
250
—
—
—
—
—
—
2
124
0
300
2
0
0
—
—
—
—
—
—
500
—
—
—
—
—
—
1k
0
249
0
—
—
—
2.5k
0
99
0
0
199
0
5k
0
49
0
0
99
0
10k
0
24
0
0
49
0
25k
0
9
0
0
19
0
50k
0
4
0
0
9
0
100k
—
—
—
0
4
0
250k
0
0
0
0
1
0
0
0
0
500k
1M
237
Table 10.6 Examples of BRR Settings for Various Bit Rates (Synchronous Mode) (2)
OSC
B Bit Rate
10 MHz
16 MHz
(bit/s)
n
N
Error
n
N
Error
200
—
—
—
—
—
—
250
—
—
—
3
124
0
300
—
—
—
—
—
—
500
—
—
—
2
249
0
1k
—
—
—
2
124
0
2.5k
—
—
—
2
49
0
5k
0
249
0
2
24
0
10k
0
124
0
0
199
0
25k
0
49
0
0
79
0
50k
0
24
0
0
39
0
100k
—
—
—
0
19
0
250k
0
4
0
0
7
0
500k
—
—
—
0
3
0
1M
—
—
—
0
1
0
Blank: Cannot be set.
— : A setting can be made, but an error will result.
Notes: The value set in BRR is given by the following equation:
N=
OSC
(8 × 2 2n × B)
—1
where
B:
Bit rate (bit/s)
N:
Baud rate generator BRR setting (0 ≤ N ≤ 255)
OSC: Value of øOSC (Hz)
n:
Baud rate generator input clock number (n = 0, 2, or 3)
(The relation between n and the clock is shown in table 10.7.)
238
Table 10.7 Relation between n and Clock
SMR Setting
n
Clock
0
ø
*1
*2
CKS1
CKS0
0
0
0
øw/2 /øw
0
1
2
ø/16
1
0
3
ø/64
1
1
Notes: 1. ø w/2 clock in active (medium-speed/high-speed) mode and sleep mode
2. ø w clock in subactive mode and subsleep mode
In subactive or subsleep mode, SCI3 can be operated when CPU clock is øw/2 only.
10.2.9
Clock stop register 1 (CKSTPR1)
Bit
7
6
5
4
—
—
Initial value
1
1
1
1
Read/Write
—
—
R/W
R/W
S32CKSTP ADCKSTP
3
2
1
0
—
TFCKSTP
—
TACKSTP
1
1
1
1
—
R/W
—
R/W
CKSTPR1 is an 8-bit read/write register that performs module standby mode control for peripheral
modules. Only the bits relating to SCI3 are described here. For details of the other bits, see the
sections on the relevant modules.
Bit 5: SCI3 module standby mode control (S32CKSTP)
Bit 5 controls setting and clearing of module standby mode for SCI3.
S32CKSTP
Description
0
SCI3 is set to module standby mode
1
SCI3 module standby mode is cleared
(initial value)
Note: All SCI3 register is initialized in module standby mode.
239
10.2.10
Serial Port Control Register (SPCR)
Bit
7
6
5
4
—
—
SPC32
—
3
2
SCINV3 SCINV2
1
0
—
—
Initial value
1
1
0
—
0
0
—
—
Read/Write
—
—
R/W
W
R/W
R/W
W
W
SPCR is an 8-bit readable/writable register that performs RXD32 and TXD32 pin input/output data
inversion switching.
Bits 7 and 6: Reserved bits
Bits 7 and 6 are reserved; they are always read as 1 and cannot be modified.
Bit 5: P42/TXD32 pin function switch (SPC32)
This bit selects whether pin P42/TXD32 is used as P42 or as TXD32.
Bit 5
SPC32
Description
0
Functions as P4 2 I/O pin
1
Functions as TXD 32 output pin*
(initial value)
Note: * Set the TE bit in SCR3 after setting this bit to 1.
Bits 4, 1, and 0: Reserved bits
Bits 4, 1, and 0 are reserved; only 0 can be written to these bits.
Bit 3 specifies whether or not TXD32 pin output data is to be inverted.
Bit 3
SCINV3
Description
0
TXD32 output data is not inverted
1
TXD32 output data is inverted
Bit 2: RXD 32 pin input data inversion switch
Bit 2 specifies whether or not RXD 32 pin input data is to be inverted.
240
(initial value)
Bit 2
SCINV2
Description
0
RXD32 input data is not inverted
1
RXD32 input data is inverted
10.3
Operation
10.3.1
Overview
(initial value)
SCI3 can perform serial communication in two modes: asynchronous mode in which
synchronization is provided character by character, and synchronous mode in which
synchronization is provided by clock pulses. The serial mode register (SMR) is used to select
asynchronous or synchronous mode and the data transfer format, as shown in table 10.8.
The clock source for SCI3 is determined by bit COM in SMR and bits CKE1 and CKE0 in SCR3,
as shown in table 10.9.
1. Asynchronous mode
• Choice of 5-, 7-, or 8-bit data length
• Choice of parity addition, multiprocessor bit addition, and addition of 1 or 2 stop bits. (The
combination of these parameters determines the data transfer format and the character length.)
• Framing error (FER), parity error (PER), overrun error (OER), and break detection during
reception
• Choice of internal or external clock as the clock source
When internal clock is selected: SCI3 operates on the baud rate generator clock, and a clock
with the same frequency as the bit rate can be output.
When external clock is selected: A clock with a frequency 16 times the bit rate must be input.
(The on-chip baud rate generator is not used.)
2. Synchronous mode
• Data transfer format: Fixed 8-bit data length
• Overrun error (OER) detection during reception
• Choice of internal or external clock as the clock source
When internal clock is selected: SCI3 operates on the baud rate generator clock, and a serial
clock is output.
When external clock is selected: The on-chip baud rate generator is not used, and SCI3
operates on the input serial clock.
241
Table 10.8 SMR Settings and Corresponding Data Transfer Formats
SMR
Data Transfer Format
bit 7
COM
bit 6
CHR
bit 2
MP
bit 5
PE
bit 3
STOP Mode
0
0
0
0
0
Asynchronous 8-bit data No
1
mode
1
Data
Length
Multiprocessor Parity Stop Bit
Bit
Bit
Length
No
2 bits
0
Yes
1
1
0
0
7-bit data
No
1
0
0
Yes
0
8-bit data Yes
No
0
0
5-bit data No
1 bit
2 bits
0
7-bit data Yes
1 bit
1
1
2 bits
0
5-bit data No
Yes
1
1
*
0
*
*
1 bit
2 bits
1
1
1 bit
2 bits
1
1
1 bit
2 bits
1
0
1 bit
2 bits
1
1
1 bit
1 bit
2 bits
Synchronous
mode
8-bit data No
No
No
*: Don’t care
242
Table 10.9 SMR and SCR3 Settings and Clock Source Selection
SMR
SCR3
bit 7 bit 1
bit 0
Transmit/Receive Clock
COM CKE1 CKE0 Mode
0
0
Clock Source SCK32 Pin Function
0
Asynchronous Internal
I/O port (SCK32 pin not used)
1
mode
Outputs clock with same frequency as bit rate
1
0
External
Inputs clock with frequency 16 times bit rate
0
0
Synchronous
Internal
Outputs serial clock
1
0
mode
External
Inputs serial clock
0
1
1
Reserved (Do not specify these combinations)
1
0
1
1
1
1
1
3. Interrupts and continuous transmission/reception
SCI3 can carry out continuous reception using RXI and continuous transmission using TXI.
These interrupts are shown in table 10.10.
Table 10.10 Transmit/Receive Interrupts
Interrupt
Flags
Interrupt Request Conditions
Notes
RXI
RDRF
RIE
When serial reception is performed
normally and receive data is transferred
from RSR to RDR, bit RDRF is set to 1,
and if bit RIE is set to 1 at this time, RXI
is enabled and an interrupt is requested.
(See figure 10.2 (a).)
The RXI interrupt routine reads the
receive data transferred to RDR and
clears bit RDRF to 0. Continuous
reception can be performed by
repeating the above operations until
reception of the next RSR data is
completed.
TXI
TDRE
TIE
When TSR is found to be empty (on
completion of the previous transmission)
and the transmit data placed in TDR is
transferred to TSR, bit TDRE is set to 1.
If bit TIE is set to 1 at this time, TXI is
enabled and an interrupt is requested.
(See figure 10.2 (b).)
The TXI interrupt routine writes the
next transmit data to TDR and clears
bit TDRE to 0. Continuous
transmission can be performed by
repeating the above operations until
the data transferred to TSR has
been transmitted.
TEI
TEND
TEIE
When the last bit of the character in
TSR is transmitted, if bit TDRE is set to
1, bit TEND is set to 1. If bit TEIE is set
to 1 at this time, TEI is enabled and an
interrupt is requested. (See figure 10.2
(c).)
TEI indicates that the next transmit
data has not been written to TDR
when the last bit of the transmit
character in TSR is sent.
243
RDR
RDR
RSR (reception in progress)
RSR↑ (reception completed, transfer)
RXD32 pin
RXD32 pin
RDRF ← 1
(RXI request when RIE = 1)
RDRF = 0
Figure 10.2 (a) RDRF Setting and RXI Interrupt
TDR (next transmit data)
TDR
TSR (transmission in progress)
TXD32 pin
TSR↓ (transmission completed, transfer)
TXD32 pin
TDRE ← 1
(TXI request when TIE = 1)
TDRE = 0
Figure 10.2 (b) TDRE Setting and TXI Interrupt
TDR
TDR
TSR (transmission in progress)
TSR (reception completed)
TXD32 pin
TXD32 pin
TEND = 0
TEND ← 1
(TEI request when TEIE = 1)
Figure 10.2 (c) TEND Setting and TEI Interrupt
244
10.3.2
Operation in Asynchronous Mode
In asynchronous mode, serial communication is performed with synchronization provided
character by character. A start bit indicating the start of communication and one or two stop bits
indicating the end of communication are added to each character before it is sent.
SCI3 has separate transmission and reception units, allowing full-duplex communication. As the
transmission and reception units are both double-buffered, data can be written during transmission
and read during reception, making possible continuous transmission and reception.
1. Data transfer format
The general data transfer format in asynchronous communication is shown in figure 10.3.
(LSB)
Serial
data
(MSB)
Start
bit
Transmit/receive data
1 bit
5, 7 or 8 bits
1
Parity
bit
1 bit
or none
Stop
bit(s)
Mark
state
1 or 2 bits
One transfer data unit (character or frame)
Figure 10.3 Data Format in Asynchronous Communication
In asynchronous communication, the communication line is normally in the mark state (high
level). SCI3 monitors the communication line and when it detects a space (low level), identifies
this as a start bit and begins serial data communication.
One transfer data character consists of a start bit (low level), followed by transmit/receive data
(LSB-first format, starting from the least significant bit), a parity bit (high or low level), and
finally one or two stop bits (high level).
In asynchronous mode, synchronization is performed by the falling edge of the start bit during
reception. The data is sampled on the 8th pulse of a clock with a frequency 16 times the bit
period, so that the transfer data is latched at the center of each bit.
245
Table 10.11 shows the 16 data transfer formats that can be set in asynchronous mode. The format
is selected by the settings in the serial mode register (SMR).
Table 10.11 Data Transfer Formats (Asynchronous Mode)
SMR
CHR PE
Serial Data Transfer Format and Frame Length
MP
STOP
1
2
3
4
5
6
7
8
9
10 11 12
0
0
0
0
S
8-bit data
STOP
0
0
0
1
S
8-bit data
STOP STOP
0
0
1
0
S
8-bit data
MPB STOP
S
8-bit data
MPB STOP STOP
S
8-bit data
P
STOP
S
8-bit data
P
STOP STOP
S
5-bit data
STOP
S
5-bit data
STOP STOP
S
7-bit data
STOP
S
7-bit data
STOP STOP
S
7-bit data
MPB STOP
S
7-bit data
MPB STOP STOP
S
7-bit data
P
STOP
P
STOP STOP
0
0
1
1
0
1
0
0
0
0
0
1
1
1
1
1
0
0
0
1
1
0
0
1
0
1
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
S
7-bit data
1
1
1
0
S
5-bit data
P
STOP
1
1
1
1
S
5-bit data
P
STOP STOP
Notation:
S:
Start bit
STOP: Stop bit
P:
Parity bit
MPB: Multiprocessor bit
246
2. Clock
Either an internal clock generated by the baud rate generator or an external clock input at the
SCK32 pin can be selected as the SCI3 transmit/receive clock. The selection is made by means of
bit COM in SMR and bits SCE1 and CKE0 in SCR3. See table 10.9 for details on clock source
selection.
When an external clock is input at the SCK32 pin, the clock frequency should be 16 times the bit
rate.
When SCI3 operates on an internal clock, the clock can be output at the SCK 32 pin. In this case
the frequency of the output clock is the same as the bit rate, and the phase is such that the clock
rises at the center of each bit of transmit/receive data, as shown in figure 10.4.
Clock
Serial
data
0
D0
D1
D2
D3
D4
D5
D6
D7
0/1
1
1
1 character (1 frame)
Figure 10.4 Phase Relationship between Output Clock and Transfer Data
(Asynchronous Mode) (8-bit data, parity, 2 stop bits)
3. Data transfer operations
• SCI3 initialization
Before data is transferred on SCI3, bits TE and RE in SCR3 must first be cleared to 0, and then
SCI3 must be initialized as follows.
Note: If the operation mode or data transfer format is changed, bits TE and RE must first be
cleared to 0.
When bit TE is cleared to 0, bit TDRE is set to 1.
Note that the RDRF, PER, FER, and OER flags and the contents of RDR are retained
when RE is cleared to 0.
When an external clock is used in asynchronous mode, the clock should not be stopped
during operation, including initialization. When an external clock is used in synchronous
mode, the clock should not be supplied during operation, including initialization.
247
Figure 10.5 shows an example of a flowchart for initializing SCI3.
Start
Clear bits TE and
RE to 0 in SCR3
1
Set bits CKE1
and CKE0
2
Set data transfer
format in SMR
3
Set value in BRR
1. Set clock selection in SCR3. Be sure to
clear the other bits to 0. If clock output
is selected in asynchronous mode, the
clock is output immediately after setting
bits CKE1 and CKE0. If clock output is
selected for reception in synchronous
mode, the clock is output immediately
after bits CKE1, CKE0, and RE are
set to 1.
2. Set the data transfer format in the serial
mode register (SMR).
Wait
Has 1-bit period
elapsed?
Yes
Set bit SPC32 to
1 in SPCR
4
Set bits TIE, RIE,
MPIE, and TEIE in
SCR3, and set bits
RE and TE to 1
in SCR3
No
3. Write the value corresponding to the
transfer rate in BRR. This operation is
not necessary when an external clock
is selected.
4. Wait for at least one bit period, then set
bits TIE, RIE, MPIE, and TEIE in SCR3,
and set bits RE and TE to 1 in PMR7.
Setting bits TE and RE enables the TXD32
and RXD32 pins to be used. In asynchronous
mode the mark state is established when
transmitting, and the idle state waiting for
a start bit when receiving.
End
Figure 10.5 Example of SCI3 Initialization Flowchart
248
• Transmitting
Figure 10.6 shows an example of a flowchart for data transmission. This procedure should be
followed for data transmission after initializing SCI3.
Start
Sets bit SPC32 to
1 in SPCR
1
Read bit TDRE
in SSR
No
TDRE = 1?
Yes
Write transmit
data to TDR
2
Continue data
transmission?
Yes
2. When continuing data transmission,
be sure to read TDRE = 1 to confirm that
a write can be performed before writing
data to TDR. When data is written to
TDR, bit TDRE is cleared to 0
automatically.
3. If a break is to be output when data
transmission ends, set the port PCR to 1
and clear the port PDR to 0, then clear bit
TE in SCR3 to 0.
No
Read bit TEND
in SSR
TEND = 1?
1. Read the serial status register (SSR)
and check that bit TDRE is set to 1,
then write transmit data to the transmit
data register (TDR). When data is
written to TDR, bit TDRE is cleared to 0
automatically.
(After the TE bit is set to 1, one frame of
1s is output, then transmission is possible.)
No
Yes
3
Break output?
No
Yes
Set PDR = 0,
PCR = 1
Clear bit TE to 0
in SCR3
End
Figure 10.6 Example of Data Transmission Flowchart (Asynchronous Mode)
249
SCI3 operates as follows when transmitting data.
SCI3 monitors bit TDRE in SSR, and when it is cleared to 0, recognizes that data has been written
to TDR and transfers data from TDR to TSR. It then sets bit TDRE to 1 and starts transmitting. If
bit TIE in SCR3 is set to 1 at this time, a TXI request is made.
Serial data is transmitted from the TXD32 pin using the relevant data transfer format in table 10.11.
When the stop bit is sent, SCI3 checks bit TDRE. If bit TDRE is cleared to 0, SCI3 transfers data
from TDR to TSR, and when the stop bit has been sent, starts transmission of the next frame. If
bit TDRE is set to 1, bit TEND in SSR bit is set to 1the mark state, in which 1s are transmitted, is
established after the stop bit has been sent. If bit TEIE in SCR3 is set to 1 at this time, a TEI
request is made.
Figure 10.7 shows an example of the operation when transmitting in asynchronous mode.
Start
bit
Serial
data
1
0
Transmit
data
D0
D1
D7
Parity Stop Start
bit
bit bit
0/1
1
0
1 frame
Transmit
data
D0
D1
D7
Parity Stop
bit
bit
0/1
1
1 frame
TDRE
TEND
LSI
TXI request
operation
TDRE
cleared to 0
User
processing
Data written
to TDR
TXI request
TEI request
Figure 10.7 Example of Operation when Transmitting in Asynchronous Mode
(8-bit data, parity, 1 stop bit)
250
Mark
state
1
• Receiving
Figure 10.8 shows an example of a flowchart for data reception. This procedure should be
followed for data reception after initializing SCI3.
Start
1
Read bits OER,
PER, FER in SSR
OER + PER
+ FER = 1?
1. Read bits OER, PER, and FER in the
serial status register (SSR) to determine
if there is an error. If a receive error has
occurred, execute receive error
processing.
Yes
2. Read SSR and check that bit RDRF is
set to 1. If it is, read the receive data
in RDR. When the RDR data is read,
bit RDRF is cleared to 0 automatically.
No
2
Read bit RDRF
in SSR
RDRF = 1?
3.
No
When continuing data reception, finish
reading of bit RDRF and RDR before
receiving the stop bit of the current
frame. When the data in RDR is read,
bit RDRF is cleared to 0 automatically.
Yes
Read receive
data in RDR
4
3
Continue data
reception?
Receive error
processing
Yes
No
(A)
Clear bit RE to
0 in SCR3
End
Figure 10.8 Example of Data Reception Flowchart (Asynchronous Mode)
251
Start receive
error processing
4
Overrun error
processing
OER = 1?
Yes
No
FER = 1?
Break?
Yes
No
No
PER = 1?
Yes
4. If a receive error has
occurred, read bits OER,
PER, and FER in SSR to
identify the error, and after
carrying out the necessary
error processing, ensure
that bits OER, PER, and
FER are all cleared to 0.
Yes
Reception cannot be
resumed if any of these
bits is set to 1. In the case
of a framing error, a break
can be detected by reading
the value of the RXD32 pin.
Framing error
processing
No
Clear bits OER, PER,
FER to 0 in SSR
Parity error
processing
(A)
End of receive
error processing
Figure 10.8 Example of Data Reception Flowchart (Asynchronous Mode) (cont)
252
SCI3 operates as follows when receiving data.
SCI3 monitors the communication line, and when it detects a 0 start bit, performs internal
synchronization and begins reception. Reception is carried out in accordance with the relevant
data transfer format in table 10.11. The received data is first placed in RSR in LSB-to-MSB order,
and then the parity bit and stop bit(s) are received. SCI3 then carries out the following checks.
• Parity check
SCI3 checks that the number of 1 bits in the receive data conforms to the parity (odd or even)
set in bit PM in the serial mode register (SMR).
• Stop bit check
SCI3 checks that the stop bit is 1. If two stop bits are used, only the first is checked.
• Status check
SCI3 checks that bit RDRF is set to 0, indicating that the receive data can be transferred from
RSR to RDR.
If no receive error is found in the above checks, bit RDRF is set to 1, and the receive data is stored
in RDR. If bit RIE is set to 1 in SCR3, an RXI interrupt is requested. If the error checks identify a
receive error, bit OER, PER, or FER is set to 1 depending on the kind of error. Bit RDRF retains
its state prior to receiving the data. If bit RIE is set to 1 in SCR3, an ERI interrupt is requested.
Table 10.12 shows the conditions for detecting a receive error, and receive data processing.
Note: No further receive operations are possible while a receive error flag is set. Bits OER,
FER, PER, and RDRF must therefore be cleared to 0 before resuming reception.
Table 10.12 Receive Error Detection Conditions and Receive Data Processing
Receive Error Abbreviation Detection Conditions
Receive Data Processing
Overrun error
OER
When the next date receive
operation is completed while bit
RDRF is still set to 1 in SSR
Receive data is not transferred
from RSR to RDR
Framing error
FER
When the stop bit is 0
Receive data is transferred
from RSR to RDR
Parity error
PER
When the parity (odd or even) set Receive data is transferred
in SMR is different from that of
from RSR to RDR
the received data
253
Figure 10.9 shows an example of the operation when receiving in asynchronous mode.
Start
bit
Serial
data
1
0
Receive
data
D0
D1
D7
Parity Stop Start
bit
bit bit
0/1
1
0
1 frame
Receive
data
D0
D1
Parity Stop
bit
bit
D7
0/1
0
Mark state
(idle state)
1
1 frame
RDRF
FER
LSI
operation
RXI request
RDRF
cleared to 0
RDR data read
User
processing
0 start bit
detected
ERI request in
response to
framing error
Framing error
processing
Figure 10.9 Example of Operation when Receiving in Asynchronous Mode
(8-bit data, parity, 1 stop bit)
10.3.3
Operation in Synchronous Mode
In synchronous mode, SCI3 transmits and receives data in synchronization with clock pulses. This
mode is suitable for high-speed serial communication.
SCI3 has separate transmission and reception units, allowing full-duplex communication with a
shared clock.
As the transmission and reception units are both double-buffered, data can be written during
transmission and read during reception, making possible continuous transmission and reception.
254
1. Data transfer format
The general data transfer format in asynchronous communication is shown in figure 10.10.
*
*
Serial
clock
LSB
Serial
data
Bit 0
Don't
care
MSB
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
8 bits
Bit 7
Don't
care
One transfer data unit (character or frame)
Note: * High level except in continuous transmission/reception
Figure 10.10 Data Format in Synchronous Communication
In synchronous communication, data on the communication line is output from one falling edge of
the serial clock until the next falling edge. Data confirmation is guaranteed at the rising edge of
the serial clock.
One transfer data character begins with the LSB and ends with the MSB. After output of the
MSB, the communication line retains the MSB state.
When receiving in synchronous mode, SCI3 latches receive data at the rising edge of the serial
clock.
The data transfer format uses a fixed 8-bit data length.
Parity and multiprocessor bits cannot be added.
2. Clock
Either an internal clock generated by the baud rate generator or an external clock input at the
SCK32 pin can be selected as the SCI3 serial clock. The selection is made by means of bit COM
in SMR and bits CKE1 and CKE0 in SCR3. See table 10.9 for details on clock source selection.
When SCI3 operates on an internal clock, the serial clock is output at the SCK 32 pin. Eight pulses
of the serial clock are output in transmission or reception of one character, and when SCI3 is not
transmitting or receiving, the clock is fixed at the high level.
255
3. Data transfer operations
• SCI3 initialization
Data transfer on SCI3 first of all requires that SCI3 be initialized as described in 10.3.2 3. SCI3
initialization, and shown in figure 10.5.
• Transmitting
Figure 10.11 shows an example of a flowchart for data transmission. This procedure should be
followed for data transmission after initializing SCI3.
Start
Sets bit SPC32 to
1 in SPCR
1
Read bit TDRE
in SSR
No
TDRE = 1?
Yes
2. When continuing data transmission, be
sure to read TDRE = 1 to confirm that
a write can be performed before writing
data to TDR. When data is written to
TDR, bit TDRE is cleared to 0 automatically.
Write transmit
data to TDR
2
Continue data
transmission?
1. Read the serial status register (SSR) and
check that bit TDRE is set to 1, then write
transmit data to the transmit data register
(TDR). When data is written to TDR, bit
TDRE is cleared to 0 automatically, the
clock is output, and data transmission is
started. When clock output is selected,
the clock is output and data transmission
started when data is written to TDR.
Yes
No
Read bit TEND
in SSR
TEND = 1?
No
Yes
Clear bit TE to 0
in SCR3
End
Figure 10.11 Example of Data Transmission Flowchart (Synchronous Mode)
256
SCI3 operates as follows when transmitting data.
SCI3 monitors bit TDRE in SSR, and when it is cleared to 0, recognizes that data has been written
to TDR and transfers data from TDR to TSR. It then sets bit TDRE to 1 and starts transmitting. If
bit TIE in SCR3 is set to 1 at this time, a TXI request is made.
When clock output mode is selected, SCI3 outputs 8 serial clock pulses. When an external clock
is selected, data is output in synchronization with the input clock.
Serial data is transmitted from the TXD32 pin in order from the LSB (bit 0) to the MSB (bit 7).
When the MSB (bit 7) is sent, checks bit TDRE. If bit TDRE is cleared to 0, SCI3 transfers data
from TDR to TSR, and starts transmission of the next frame. If bit TDRE is set to 1, SCI3 sets bit
TEND to 1 in SSR, and after sending the MSB (bit 7), retains the MSB state. If bit TEIE in SCR3
is set to 1 at this time, a TEI request is made.
After transmission ends, the SCK pin is fixed at the high level.
Note: Transmission is not possible if an error flag (OER, FER, or PER) that indicates the data
reception status is set to 1. Check that these error flags are all cleared to 0 before a
transmit operation.
Figure 10.12 shows an example of the operation when transmitting in synchronous mode.
Serial
clock
Serial
data
Bit 0
Bit 1
Bit 7
1 frame
Bit 0
Bit 1
Bit 6
Bit 7
1 frame
TDRE
TEND
TXI request
LSI
operation
TDRE cleared
to 0
User
processing
Data written
to TDR
TXI request
TEI request
Figure 10.12 Example of Operation when Transmitting in Synchronous Mode
257
• Receiving
Figure 10.13 shows an example of a flowchart for data reception. This procedure should be
followed for data reception after initializing SCI3.
Start
1
Read bit OER
in SSR
1. Read bit OER in the serial status register
(SSR) to determine if there is an error.
If an overrun error has occurred, execute
overrun error processing.
Yes
OER = 1?
2. Read SSR and check that bit RDRF is
set to 1. If it is, read the receive data in
RDR. When the RDR data is read, bit
RDRF is cleared to 0 automatically.
No
2
Read bit RDRF
in SSR
RDRF = 1?
3. When continuing data reception, finish
reading of bit RDRF and RDR before
receiving the MSB (bit 7) of the current
frame. When the data in RDR is read,
bit RDRF is cleared to 0 automatically.
No
4. If an overrun error has occurred, read bit
OER in SSR, and after carrying out the
necessary error processing, clear bit OER
to 0. Reception cannot be resumed if bit
OER is set to 1.
Yes
Read receive
data in RDR
4
3
Continue data
reception?
Overrun error
processing
Yes
No
Clear bit RE to
0 in SCR3
End
4
Start overrun
error processing
Overrun error
processing
Clear bit OER to
0 in SSR
End of overrun
error processing
Figure 10.13 Example of Data Reception Flowchart (Synchronous Mode)
258
SCI3 operates as follows when receiving data.
SCI3 performs internal synchronization and begins reception in synchronization with the serial
clock input or output.
The received data is placed in RSR in LSB-to-MSB order.
After the data has been received, SCI3 checks that bit RDRF is set to 0, indicating that the receive
data can be transferred from RSR to RDR.
If this check shows that there is no overrun error, bit RDRF is set to 1, and the receive data is
stored in RDR. If bit RIE is set to 1 in SCR3, an RXI interrupt is requested. If the check
identifies an overrun error, bit OER is set to 1.
Bit RDRF remains set to 1. If bit RIE is set to 1 in SCR3, an ERI interrupt is requested.
See table 10.12 for the conditions for detecting a receive error, and receive data processing.
Note: No further receive operations are possible while a receive error flag is set. Bits OER,
FER, PER, and RDRF must therefore be cleared to 0 before resuming reception.
Figure 10.14 shows an example of the operation when receiving in synchronous mode.
Serial
clock
Serial
data
Bit 7
Bit 0
Bit 7
Bit 0
1 frame
Bit 1
Bit 6
Bit 7
1 frame
RDRF
OER
LSI
operation
User
processing
RXI request
RDRE cleared
to 0
RDR data read
RXI request
ERI request in
response to
overrun error
RDR data has
not been read
(RDRF = 1)
Overrun error
processing
Figure 10.14 Example of Operation when Receiving in Synchronous Mode
259
• Simultaneous transmit/receive
Figure 10.15 shows an example of a flowchart for a simultaneous transmit/receive operation. This
procedure should be followed for simultaneous transmission/reception after initializing SCI3.
Start
Sets bit SPC32 to
1 in SPCR
1
1. Read the serial status register (SSR) and
check that bit TDRE is set to 1, then write
transmit data to the transmit data register
(TDR). When data is written to TDR, bit
TDRE is cleared to 0 automatically.
Read bit TDRE
in SSR
No
TDRE = 1?
2. Read SSR and check that bit RDRF is set
to 1. If it is, read the receive data in RDR.
When the RDR data is read, bit RDRF is
cleared to 0 automatically.
Yes
Write transmit
data to TDR
3. When continuing data transmission/reception,
finish reading of bit RDRF and RDR before
receiving the MSB (bit 7) of the current frame.
Before receiving the MSB (bit 7) of the current
frame, also read TDRE = 1 to confirm that a
write can be performed, then write data to TDR.
When data is written to TDR, bit TDRE is cleared
to 0 automatically, and when the data in RDR is
read, bit RDRF is cleared to 0 automatically.
Read bit OER
in SSR
Yes
OER = 1?
4. If an overrun error has occurred, read bit OER
in SSR, and after carrying out the necessary
error processing, clear bit OER to 0. Transmission and reception cannot be resumed if bit
OER is set to 1.
See figure 10-13 for details on overrun error
processing.
No
2
Read bit RDRF
in SSR
No
RDRF = 1?
Yes
Read receive data
in RDR
4
3
Continue data
transmission/reception?
Overrun error
processing
Yes
No
Clear bits TE and
RE to 0 in SCR3
End
Figure 10.15 Example of Simultaneous Data Transmission/Reception Flowchart
(Synchronous Mode)
260
Notes: 1. When switching from transmission to simultaneous transmission/reception, check that
SCI3 has finished transmitting and that bits TDRE and TEND are set to 1, clear bit TE
to 0, and then set bits TE and RE to 1 simultaneously.
2. When switching from reception to simultaneous transmission/reception, check that
SCI3 has finished receiving, clear bit RE to 0, then check that bit RDRF and the error
flags (OER, FER, and PER) are cleared to 0, and finally set bits TE and RE to 1
simultaneously.
10.3.4
Multiprocessor Communication Function
The multiprocessor communication function enables data to be exchanged among a number of
processors on a shared communication line. Serial data communication is performed in
asynchronous mode using the multiprocessor format (in which a multiprocessor bit is added to the
transfer data).
In multiprocessor communication, each receiver is assigned its own ID code. The serial
communication cycle consists of two cycles, an ID transmission cycle in which the receiver is
specified, and a data transmission cycle in which the transfer data is sent to the specified receiver.
These two cycles are differentiated by means of the multiprocessor bit, 1 indicating an ID
transmission cycle, and 0, a data transmission cycle.
The sender first sends transfer data with a 1 multiprocessor bit added to the ID code of the receiver
it wants to communicate with, and then sends transfer data with a 0 multiprocessor bit added to the
transmit data. When a receiver receives transfer data with the multiprocessor bit set to 1, it
compares the ID code with its own ID code, and if they are the same, receives the transfer data
sent next. If the ID codes do not match, it skips the transfer data until data with the multiprocessor
bit set to 1 is sent again.
In this way, a number of processors can exchange data among themselves.
Figure 10.16 shows an example of communication between processors using the multiprocessor
format.
261
Sender
Communication line
Serial
data
Receiver A
Receiver B
Receiver C
Receiver D
(ID = 01)
(ID = 02)
(ID = 03)
(ID = 04)
H'01
(MPB = 1)
ID transmission cycle
(specifying the receiver)
H'AA
(MPB = 0)
Data transmission cycle
(sending data to the receiver
specified by the ID)
MPB: Multiprocessor bit
Figure 10.16 Example of Inter-Processor Communication Using Multiprocessor Format
(Sending data H'AA to receiver A)
There is a choice of four data transfer formats. If a multiprocessor format is specified, the parity
bit specification is invalid. See table 10.11 for details.
For details on the clock used in multiprocessor communication, see 10.3.2, Operation in
Synchronous Mode.
• Multiprocessor transmitting
Figure 10.17 shows an example of a flowchart for multiprocessor data transmission. This
procedure should be followed for multiprocessor data transmission after initializing SCI3.
262
Start
Sets bit SPC32 to
1 in SPCR
1
Read bit TDRE
in SSR
TDRE = 1?
No
2. When continuing data transmission, be
sure to read TDRE = 1 to confirm that a
write can be performed before writing data
to TDR. When data is written to TDR, bit
TDRE is cleared to 0 automatically.
Yes
Set bit MPDT
in SSR
3. If a break is to be output when data
transmission ends, set the port PCR to 1
and clear the port PDR to 0, then clear bit
TE in SCR3 to 0.
Write transmit
data to TDR
2
Continue data
transmission?
1. Read the serial status register (SSR)
and check that bit TDRE is set to 1,
then set bit MPBT in SSR to 0 or 1 and
write transmit data to the transmit data
register (TDR). When data is written to
TDR, bit TDRE is cleared to 0 automatically.
Yes
No
Read bit TEND
in SSR
TEND = 1?
No
Yes
3
Break output?
No
Yes
Set PDR = 0,
PCR = 1
Clear bit TE to
0 in SCR3
End
Figure 10.17 Example of Multiprocessor Data Transmission Flowchart
263
SCI3 operates as follows when transmitting data.
SCI3 monitors bit TDRE in SSR, and when it is cleared to 0, recognizes that data has been written
to TDR and transfers data from TDR to TSR. It then sets bit TDRE to 1 and starts transmitting. If
bit TIE in SCR3 is set to 1 at this time, a TXI request is made.
Serial data is transmitted from the TXD pin using the relevant data transfer format in table 10.11.
When the stop bit is sent, SCI3 checks bit TDRE. If bit TDRE is cleared to 0, SCI3 transfers data
from TDR to TSR, and when the stop bit has been sent, starts transmission of the next frame. If
bit TDRE is set to 1 bit TEND in SSR bit is set to 1, the mark state, in which 1s are transmitted, is
established after the stop bit has been sent. If bit TEIE in SCR3 is set to 1 at this time, a TEI
request is made.
Figure 10.18 shows an example of the operation when transmitting using the multiprocessor
format.
Start
bit
Serial
data
1
0
Transmit
data
D0
D1
D7
MPB
0/1
Stop Start
bit bit
1
0
Transmit
data
D0
D1
MPB
D7
0/1
Stop
bit
Mark
state
1
1
1 frame
1 frame
TDRE
TEND
LSI
TXI request
operation
TDRE
cleared to 0
User
processing
Data written
to TDR
TXI request
TEI request
Figure 10.18 Example of Operation when Transmitting using Multiprocessor Format
(8-bit data, multiprocessor bit, 1 stop bit)
• Multiprocessor receiving
Figure 10.19 shows an example of a flowchart for multiprocessor data reception. This procedure
should be followed for multiprocessor data reception after initializing SCI3.
264
Start
1
2
1. Set bit MPIE to 1 in SCR3.
Set bit MPIE to 1
in SCR3
2. Read bits OER and FER in the serial
status register (SSR) to determine if
there is an error. If a receive error has
occurred, execute receive error processing.
Read bits OER
and FER in SSR
OER + FER = 1?
3. Read SSR and check that bit RDRF is
set to 1. If it is, read the receive data in
RDR and compare it with this receiver's
own ID. If the ID is not this receiver's,
set bit MPIE to 1 again. When the RDR
data is read, bit RDRF is cleared to 0
automatically.
Yes
No
3
Read bit RDRF
in SSR
RDRF = 1?
4. Read SSR and check that bit RDRF is
set to 1, then read the data in RDR.
No
5. If a receive error has occurred, read bits
OER and FER in SSR to identify the error,
and after carrying out the necessary error
processing, ensure that bits OER and FER
are both cleared to 0. Reception cannot be
resumed if either of these bits is set to 1.
In the case of a framing error, a break can
be detected by reading the value of the
RXD32 pin.
Yes
Read receive
data in RDR
Own ID?
No
Yes
Read bits OER
and FER in SSR
OER + FER = 1?
Yes
No
4
Read bit RDRF
in SSR
RDRF = 1?
No
Yes
Read receive
data in RDR4
Continue data
reception?
No
5
Receive error
processing
Yes
(A)
Clear bit RE to
0 in SCR3
End
Figure 10.19 Example of Multiprocessor Data Reception Flowchart
265
Start receive
error processing
Overrun error
processing
OER = 1?
Yes
Yes
No
FER = 1?
No
Break?
Yes
No
Framing error
processing
Clear bits OER and
FER to 0 in SSR
End of receive
error processing
(A)
Figure 10.19 Example of Multiprocessor Data Reception Flowchart (cont)
Figure 10.20 shows an example of the operation when receiving using the multiprocessor format.
266
Start
bit
Serial
data
1
0
Receive
data (ID1)
D0
D1
D7
MPB
1
Stop Start
bit bit
1
0
Receive data
(Data1)
D0
1 frame
D1
D7
MPB
Stop
bit
Mark state
(idle state)
0
1
1
1 frame
MPIE
RDRF
RDR
value
ID1
RXI request
MPIE cleared
to 0
LSI
operation
RDRF cleared
to 0
User
processing
No RXI request
RDR retains
previous state
RDR data read
When data is not
this receiver's ID,
bit MPIE is set to
1 again
(a) When data does not match this receiver's ID
Start
bit
Serial
data
1
0
Receive
data (ID2)
D0
D1
D7
MPB
1
Stop Start
bit bit
1
0
Receive data
(Data2)
D0
D1
D7
MPB
Stop
bit
Mark state
(idle state)
0
1
1
1 frame
1 frame
MPIE
RDRF
RDR
value
ID1
LSI
operation
User
processing
ID2
RXI request
MPIE cleared
to 0
RDRF cleared
to 0
RDR data read
Data2
RXI request
When data is
this receiver's
ID, reception
is continued
RDRF cleared
to 0
RDR data read
Bit MPIE set to
1 again
(b) When data matches this receiver's ID
Figure 10.20 Example of Operation when Receiving using Multiprocessor Format
(8-bit data, multiprocessor bit, 1 stop bit)
267
10.4
Interrupts
SCI3 can generate six kinds of interrupts: transmit end, transmit data empty, receive data full, and
three receive error interrupts (overrun error, framing error, and parity error). These interrupts have
the same vector address.
The various interrupt requests are shown in table 10.13.
Table 10.13 SCI3 Interrupt Requests
Interrupt
Abbreviation
Interrupt Request
Vector
Address
RXI
Interrupt request initiated by receive data full flag (RDRF)
H'0024
TXI
Interrupt request initiated by transmit data empty flag (TDRE)
TEI
Interrupt request initiated by transmit end flag (TEND)
ERI
Interrupt request initiated by receive error flag (OER, FER, PER)
Each interrupt request can be enabled or disabled by means of bits TIE and RIE in SCR3.
When bit TDRE is set to 1 in SSR, a TXI interrupt is requested. When bit TEND is set to 1 in
SSR, a TEI interrupt is requested. These two interrupts are generated during transmission.
The initial value of bit TDRE in SSR is 1. Therefore, if the transmit data empty interrupt request
(TXI) is enabled by setting bit TIE to 1 in SCR3 before transmit data is transferred to TDR, a TXI
interrupt will be requested even if the transmit data is not ready.
Also, the initial value of bit TEND in SSR is 1. Therefore, if the transmit end interrupt request
(TEI) is enabled by setting bit TEIE to 1 in SCR3 before transmit data is transferred to TDR, a TEI
interrupt will be requested even if the transmit data has not been sent.
Effective use of these interrupt requests can be made by having processing that transfers transmit
data to TDR carried out in the interrupt service routine.
To prevent the generation of these interrupt requests (TXI and TEI), on the other hand, the enable
bits for these interrupt requests (bits TIE and TEIE) should be set to 1 after transmit data has been
transferred to TDR.
When bit RDRF is set to 1 in SSR, an RXI interrupt is requested, and if any of bits OER, PER, and
FER is set to 1, an ERI interrupt is requested. These two interrupt requests are generated during
reception.
For further details, see 3.3, Interrupts.
268
10.5
Application Notes
The following points should be noted when using SCI3.
1. Relation between writes to TDR and bit TDRE
Bit TDRE in the serial status register (SSR) is a status flag that indicates that data for serial
transmission has not been prepared in TDR. When data is written to TDR, bit TDRE is cleared to
0 automatically. When SCI3 transfers data from TDR to TSR, bit TDRE is set to 1.
Data can be written to TDR irrespective of the state of bit TDRE, but if new data is written to
TDR while bit TDRE is cleared to 0, the data previously stored in TDR will be lost of it has not
yet been transferred to TSR. Accordingly, to ensure that serial transmission is performed
dependably, you should first check that bit TDRE is set to 1, then write the transmit data to TDR
once only (not two or more times).
2. Operation when a number of receive errors occur simultaneously
If a number of receive errors are detected simultaneously, the status flags in SSR will be set to the
states shown in table 10.14. If an overrun error is detected, data transfer from RSR to RDR will
not be performed, and the receive data will be lost.
Table 10.14 SSR Status Flag States and Receive Data Transfer
SSR Status Flags
Receive Data Transfer
RDRF* OER
FER
PER
RSR → RDR
Receive Error Status
1
1
0
0
X
Overrun error
0
0
1
0
O
Framing error
0
0
0
1
O
Parity error
1
1
1
0
X
Overrun error + framing error
1
1
0
1
X
Overrun error + parity error
0
0
1
1
O
Framing error + parity error
1
1
1
1
X
Overrun error + framing error + parity error
O : Receive data is transferred from RSR to RDR.
X : Receive data is not transferred from RSR to RDR.
Note: * Bit RDRF retains its state prior to data reception. However, note that if RDR is read after an
overrun error has occurred in a frame because reading of the receive data in the previous
frame was delayed, RDRF will be cleared to 0.
269
3. Break detection and processing
When a framing error is detected, a break can be detected by reading the value of the RXD32 pin
directly. In a break, the input from the RXD 32 pin becomes all 0s, with the result that bit FER is
set and bit PER may also be set.
SCI3 continues the receive operation even after receiving a break. Note, therefore, that even
though bit FER is cleared to 0 it will be set to 1 again.
4. Mark state and break detection
When bit TE is cleared to 0, the TXD32 pin functions as an I/O port whose input/output direction
and level are determined by PDR and PCR. This fact can be used to set the TXD32 pin to the
mark state, or to detect a break during transmission.
To keep the communication line in the mark state (1 state) until bit TE is set to 1, set PCR = 1 and
PDR = 1. Since bit TE is cleared to 0 at this time, the TXD32 pin functions as an I/O port and 1 is
output.
To detect a break, clear bit TE to 0 after setting PCR = 1 and PDR = 0.
When bit TE is cleared to 0, the transmission unit is initialized regardless of the current
transmission state, the TXD 32 pin functions as an I/O port, and 0 is output from the TXD32 pin.
5. Receive error flags and transmit operation (synchronous mode only)
When a receive error flag (OER, PER, or FER) is set to 1, transmission cannot be started even if
bit TDRE is cleared to 0. The receive error flags must be cleared to 0 before starting transmission.
Note also that receive error flags cannot be cleared to 0 even if bit RE is cleared to 0.
6. Receive data sampling timing and receive margin in asynchronous mode
In asynchronous mode, SCI3 operates on a basic clock with a frequency 16 times the transfer rate.
When receiving, SCI3 performs internal synchronization by sampling the falling edge of the start
bit with the basic clock. Receive data is latched internally at the 8th rising edge of the basic clock.
This is illustrated in figure 10.21.
270
16 clock pulses
8 clock pulses
0
7
15 0
7
15 0
Internal
basic clock
Receive data
(RXD32)
Start bit
D0
D1
Synchronization
sampling timing
Data sampling
timing
Figure 10.21 Receive Data Sampling Timing in Asynchronous Mode
Consequently, the receive margin in asynchronous mode can be expressed as shown in equation
(1).
M ={(0.5 –
1
D – 0.5
)–
– (L – 0.5) F} × 100 [%]
2N
N
..... Equation (1)
where
M: Receive margin (%)
N: Ratio of bit rate to clock (N = 16)
D: Clock duty (D = 0.5 to 1.0)
L: Frame length (L = 9 to 12)
F: Absolute value of clock frequency deviation
Substituting 0 for F (absolute value of clock frequency deviation) and 0.5 for D (clock duty) in
equation (1), a receive margin of 46.875% is given by equation (2).
When D = 0.5 and F = 0,
M = {0.5 — 1/(2 × 16)} × 100 [%]
= 46.875%
..... Equation (2)
However, this is only a computed value, and a margin of 20% to 30% should be allowed when
carrying out system design.
271
7. Relation between RDR reads and bit RDRF
In a receive operation, SCI3 continually checks the RDRF flag. If bit RDRF is cleared to 0 when
reception of one frame ends, normal data reception is completed. If bit RDRF is set to 1, this
indicates that an overrun error has occurred.
When the contents of RDR are read, bit RDRF is cleared to 0 automatically. Therefore, if bit
RDR is read more than once, the second and subsequent read operations will be performed while
bit RDRF is cleared to 0. Note that, when an RDR read is performed while bit RDRF is cleared to
0, if the read operation coincides with completion of reception of a frame, the next frame of data
may be read. This is illustrated in figure 10.22.
Communication
line
Frame 1
Frame 2
Frame 3
Data 1
Data 2
Data 3
Data 1
Data 2
RDRF
RDR
(A)
RDR read
(B)
RDR read
Data 1 is read at point (A)
Data 2 is read at point (B)
Figure 10.22 Relation between RDR Read Timing and Data
In this case, only a single RDR read operation (not two or more) should be performed after first
checking that bit RDRF is set to 1. If two or more reads are performed, the data read the first time
should be transferred to RAM, etc., and the RAM contents used. Also, ensure that there is
sufficient margin in an RDR read operation before reception of the next frame is completed. To
be precise in terms of timing, the RDR read should be completed before bit 7 is transferred in
synchronous mode, or before the STOP bit is transferred in asynchronous mode.
8. Transmit and receive operations when making a state transition
Make sure that transmit and receive operations have completely finished before carrying out state
transition processing.
272
9. Switching SCK 32 function
If pin SCK32 is used as a clock output pin by SCI3 in synchronous mode and is then switched to a
general input/output pin (a pin with a different function), the pin outputs a low level signal for half
a system clock (ø) cycle immediately after it is switched.
This can be prevented by either of the following methods according to the situation.
a. When an SCK32 function is switched from clock output to non clock-output
When stopping data transfer, issue one instruction to clear bits TE and RE to 0 and to set bits
CKE1 and CKE0 in SCR3 to 1 and 0, respectively. In this case, bit COM in SMR should be left 1.
The above prevents SCK32 from being used as a general input/output pin. To avoid an
intermediate level of voltage from being applied to SCK32, the line connected to SCK32 should be
pulled up to the VCC level via a resistor, or supplied with output from an external device.
b. When an SCK32 function is switched from clock output to general input/output
When stopping data transfer,
(i) Issue one instruction to clear bits TE and RE to 0 and to set bits CKE1 and CKE0 in SCR3 to
1 and 0, respectively.
(ii) Clear bit COM in SMR to 0
(iii) Clear bits CKE1 and CKE0 in SCR3 to 0
Note that special care is also needed here to avoid an intermediate level of voltage from being
applied to SCK 32.
10. Set up at subactive or subsleep mode
At subactive or subsleep mode, SCI3 becomes possible use only at CPU clock is øw/2.
273
274
Section 11 10-Bit PWM
11.1
Overview
The H8/3802 Series is provided with two on-chip 10-bit PWMs (pulse width modulators),
designated PWM1 and PWM2, with identical functions. The PWMs can be used as D/A
converters by connecting a low-pass filter. In this section the suffix m (m = 1 or 2) is used with
register names, etc., as in PWDRLm, which denotes the PWDRL registers for each PWM.
11.1.1
Features
Features of the 10-bit PWMs are as follows.
• Choice of four conversion periods
Any of the following conversion periods can be chosen:
4,096/ø, with a minimum modulation width of 4/ø
2,048/ø, with a minimum modulation width of 2/ø
1,024/ø, with a minimum modulation width of 1/ø
512/ø, with a minimum modulation width of 1/2 ø
• Pulse division method for less ripple
• Use of module standby mode enables this module to be placed in standby mode independently
when not used.
275
11.1.2
Block Diagram
Figure 11.1 shows a block diagram of the 10-bit PWM.
PWDRLm
ø/2
ø/4
ø/8
ø
Internal data bus
PWDRUm
PWM
waveform
generator
PWCRm
PWMm
Notation:
PWDRLm: PWM data register L
PWDRUm: PWM data register U
PWCRm: PWM control register
m= 1 or 2
Figure 11.1 Block Diagram of the 10 bit PWM
11.1.3
Pin Configuration
Table 11.1 shows the output pin assigned to the 10-bit PWM.
Table 11.1 Pin Configuration
Name
Abbrev.
I/O
Function
PWM1 output pin
PWM1
Output
Pulse-division PWM waveform output
(PWM1)
PWM2 output pin
PWM2
Output
Pulse-division PWM waveform output
(PWM2)
276
11.1.4
Register Configuration
Table 11.2 shows the register configuration of the 10-bit PWM.
Table 11.2 Register Configuration
Name
Abbrev.
R/W
Initial Value
Address
PWM1 control register
PWCR1
W
H'FC
H'FFD0
PWM1 data register U
PWDRU1
W
H'FC
H'FFD1
PWM1 data register L
PWDRL1
W
H'00
H'FFD2
PWM2 control register
PWCR2
W
H'FC
H'FFCD
PWM2 data register U
PWDRU2
W
H'FC
H'FFCE
PWM2 data register L
PWDRL2
W
H'00
H'FFCF
Clock stop register 2
CKSTPR2
R/W
H'FF
H'FFFB
277
11.2
Register Descriptions
11.2.1
PWM Control Register (PWCRm)
Bit
7
6
5
4
3
2
—
—
—
—
—
—
Initial value
1
1
1
1
1
1
0
0
Read/Write
—
—
—
—
—
—
W
W
1
0
PWCRm1 PWCRm0
PWCRm is an 8-bit write-only register for input clock selection.
Upon reset, PWCRm is initialized to H'FC.
Bits 7 to 2: Reserved bits
Bits 7 to 2 are reserved; they are always read as 1, and cannot be modified.
Bits 1 and 0: Clock select 1 and 0 (PWCRm1, PWCRm0)
Bits 1 and 0 select the clock supplied to the 10-bit PWM. These bits are write-only bits; they are
always read as 1.
Bit 1
Bit 0
PWCRm1 PWCRm0 Description
0
0
The input clock is ø (tø* = 1/ø)
The conversion period is 512/ø, with a minimum modulation
width of 1/2ø
0
1
The input clock is ø/2 (tø* = 2/ø)
The conversion period is 1,024/ø, with a minimum
modulation width of 1/ø
1
0
The input clock is ø/4 (tø* = 4/ø)
The conversion period is 2,048/ø, with a minimum
modulation width of 2/ø
1
1
The input clock is ø/8 (tø* = 8/ø)
The conversion period is 4,096/ø, with a minimum
modulation width of 4/ø
Note: * Period of PWM input clock.
278
(initial value)
11.2.2
PWM Data Registers U and L (PWDRUm, PWDRLm)
PWDRUm
Bit
7
6
5
4
3
2
—
—
—
—
—
—
Initial value
1
1
1
1
1
1
0
0
Read/Write
—
—
—
—
—
—
W
W
7
6
5
4
3
2
1
0
1
0
PWDRUm1 PWDRUm0
PWDRLm
Bit
PWDRLm7 PWDRLm6 PWDRLm5 PWDRLm4 PWDRLm3 PWDRLm2 PWDRLm1 PWDRLm0
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
PWDRUm and PWDRLm form a 10-bit write-only register, with the upper 2 bits assigned to
PWDRUm and the lower 8 bits to PWDRLm. The value written to PWDRUm and PWDRLm
gives the total high-level width of one PWM waveform cycle.
When 10-bit data is written to PWDRUm and PWDRLm, the register contents are latched in the
PWM waveform generator, updating the PWM waveform generation data. The 10-bit data should
always be written in the following sequence:
1. Write the lower 8 bits to PWDRLm.
2. Write the upper 2 bits to PWDRUm for the same channel.
PWDRUm and PWDRLm are write-only registers. If they are read, all bits are read as 1.
Upon reset, PWDRUm is initialized to H'FC, and PWDRLm to H'00.
11.2.3
Clock Stop Register 2 (CKSTPR2)
Bit
7
6
5
—
—
—
4
3
PW2CKSTP AECKSTP
2
—
1
0
PW1CKSTP LDCKSTP
Initial value
1
1
1
1
1
1
1
1
Read/Write
—
—
—
R/W
R/W
—
R/W
R/W
CKSTPR2 is an 8-bit read/write register that performs module standby mode control for peripheral
modules. Only the bit relating to the PWM is described here. For details of the other bits, see the
sections on the relevant modules.
279
Bits 4 and 1: PWM module standby mode control (PWmCKSTP)
Bits 4 and 1 control setting and clearing of module standby mode for the PWMm.
PWmCKSTP Description
0
PWMm is set to module standby mode
1
PWMm module standby mode is cleared
280
(initial value)
11.3
Operation
11.3.1
Operation
When using the 10-bit PWM, set the registers in the following sequence.
1. Set PWM1 or PWM2 in PMR9 to 1 for the PWM channel to be used, so that pin P90/PWM1 or
P9 1/PWM2 is designated as the PWM output pin.
2. Set bits PWCRm1 and PWCRm0 in the PWM control register (PWCRm) to select a
conversion period of 4,096/ø (PWCRm1 = 1, PWCRm0 = 1), 2,048/ø (PWCRm1 = 1,
PWCRm0 = 0), 1,024/ø (PWCRm1 = 0, PWCRm0 = 1), or 512/ø (PWCRm1 = 0, PWCRm0 =
0).
3. Set the output waveform data in PWDRUm and PWDRLm. Be sure to write in the correct
sequence, first PWDRLm then PWDRUm for the same channel. When data is written to
PWDRUm, the data will be latched in the PWM waveform generator, updating the PWM
waveform generation in synchronization with internal signals.
One conversion period consists of 4 pulses, as shown in figure 11.2. The total of the high-level
pulse widths during this period (TH) corresponds to the data in PWDRUm and PWDRLm.
This relation can be represented as follows.
TH = (data value in PWDRUm and PWDRLm + 4) × tø/2
where tø is the PWM input clock period: 1/ø (PWCRm = H'0), 2/ø (PWCRm = H'1), 4/ø (PWCRm
= H'2), or 8/ø (PWCRm = H'3).
Example: Settings in order to obtain a conversion period of 1,024 µs:
When PWCRm1 = 0 and PWCRm0 = 0, the conversion period is 512/ø, so ø must be
0.5 MHz. In this case, tfn = 256 µs, with 1/2ø (resolution) = 1.0 µs.
When PWCRm1 = 0 and PWCRm0 = 1, the conversion period is 1,024/ø, so ø must be
1 MHz. In this case, tfn = 256 µs, with 1/ø (resolution) = 1.0 µs.
When PWCRm1 = 1 and PWCRm0 = 0, the conversion period is 2,048/ø , so ø must be
2 MHz. In this case, tfn = 256 µs, with 2/ø (resolution) = 1.0 µs.
When PWCRm1 = 1 and PWCRm0 = 1, the conversion period is 4,096/ø, so ø must be
4 MHz.
In this case, tfn = 256 µs, with 4/ø (resolution) = 1.0 µs
Accordingly, for a conversion period of 1,024 µs, the system clock frequency (ø) must
be 0.5 MHz, 1 MHz, 2 Mhz, or 4MHz.
281
1 conversion period
tf2
tf3
tf1
tH1
tH2
tH3
tf4
tH4
TH = tH1+tH2+tH3+tH4
tf1 = tf2 = tf3 =tf4
Figure 11.2 PWM Output Waveform
11.3.2
PWM Operation Modes
PWM operation modes are shown in table 11.3.
Table 11.3 PWM Operation Modes
Operation
Mode
Reset
Active
Subactive Subsleep Standby
Module
Standby
PWCRm
Reset
Functions Functions Held
Held
Held
Held
Held
PWDRUm Reset
Functions Functions Held
Held
Held
Held
Held
PWDRLm Reset
Functions Functions Held
Held
Held
Held
Held
282
Sleep
Watch
Section 12 A/D Converter
12.1
Overview
The H8/3802 Series includes on-chip a resistance-ladder-based successive-approximation analogto-digital converter, and can convert up to 4 channels of analog input.
12.1.1
Features
The A/D converter has the following features.
•
•
•
•
•
•
10-bit resolution
Four input channels
Conversion time: approx. 12.4 µs per channel (at 5 MHz operation)
Built-in sample-and-hold function
Interrupt requested on completion of A/D conversion
Use of module standby mode enables this module to be placed in standby mode independently
when not used.
283
12.1.2
Block Diagram
Figure 12.1 shows a block diagram of the A/D converter.
AMR
AN 0
AN 1
AN 3
Multiplexer
ADSR
AVCC
+
Comparator
–
AVCC
Reference
voltage
Control logic
AVSS
AVSS
ADRRH
ADRRL
Notation:
AMR: A/D mode register
ADSR: A/D start register
ADRR: A/D result register
IRRAD: A/D conversion end interrupt request flag
Figure 12.1 Block Diagram of the A/D Converter
284
Internal data bus
AN 2
IRRAD
12.1.3
Pin Configuration
Table 12.1 shows the A/D converter pin configuration.
Table 12.1 Pin Configuration
Name
Abbrev.
I/O
Function
Analog power supply
AVCC
Input
Power supply and reference voltage of analog part
Analog ground
AVSS
Input
Ground and reference voltage of analog part
Analog input 0
AN 0
Input
Analog input channel 0
Analog input 1
AN 1
Input
Analog input channel 1
Analog input 2
AN 2
Input
Analog input channel 2
Analog input 3
AN 3
Input
Analog input channel 3
12.1.4
Register Configuration
Table 12.2 shows the A/D converter register configuration.
Table 12.2 Register Configuration
Name
Abbrev.
R/W
Initial Value
Address
A/D mode register
AMR
R/W
H'30
H'FFC6
A/D start register
ADSR
R/W
H'7F
H'FFC7
A/D result register H
ADRRH
R
Not fixed
H'FFC4
A/D result register L
ADRRL
R
Not fixed
H'FFC5
Clock stop register 1
CKSTPR1
R/W
H'FF
H'FFFA
285
12.2
Register Descriptions
12.2.1
A/D Result Registers (ADRRH, ADRRL)
Bit
7
Initial value
Read/Write
5
4
3
2
1
0
ADR9 ADR8 ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0
—
—
—
—
—
—
Not
fixed
R
—
—
—
—
—
—
—
—
—
—
—
—
Not
fixed
R
6
5
Not
Not
fixed fixed
R
R
4
3
2
Not
Not
Not
fixed fixed fixed
R
R
R
1
0
Not Not
fixed fixed
R
R
7
Not
fixed
R
6
ADRRH
ADRRL
ADRRH and ADRRL together comprise a 16-bit read-only register for holding the results of
analog-to-digital conversion. The upper 8 bits of the data are held in ADRRH, and the lower 2
bits in ADRRL.
ADRRH and ADRRL can be read by the CPU at any time, but the ADRRH and ADRRL values
during A/D conversion are not fixed. After A/D conversion is complete, the conversion result is
stored as 10-bit data, and this data is held until the next conversion operation starts.
ADRRH and ADRRL are not cleared on reset.
12.2.2
A/D Mode Register (AMR)
Bit
7
6
5
4
3
2
1
0
CKS
—
—
—
CH3
CH2
CH1
CH0
Initial value
0
0
1
1
0
0
0
0
Read/Write
R/W
R/W
—
—
R/W
R/W
R/W
R/W
AMR is an 8-bit read/write register for specifying the A/D conversion speed, external trigger
option, and the analog input pins.
Upon reset, AMR is initialized to H'30.
286
Bit 7: Clock select (CKS)
Bit 7 sets the A/D conversion speed.
Bit 7
Conversion Time
CKS
Conversion Period
ø = 1 MHz
ø = 5 MHz
0
62/ø (initial value)
62 µs
12.4 µs
1
31/ø
31 µs
—*
Note: * Operation is not guaranteed if the conversion time is less than 12.4 µs. Set bit 7 for a value
of at least 12.4 µs.
Bit 6: Reserved bit
Bit 6 is reserved; only 0 can be written to this bit.
Bits 5 and 4: Reserved bits
Bits 5 and 4 are reserved; they are always read as 1, and cannot be modified.
Bits 3 to 0: Channel select (CH3 to CH0)
Bits 3 to 0 select the analog input channel.
The channel selection should be made while bit ADSF is cleared to 0.
Bit 3
CH3
Bit 2
CH2
Bit 1
CH1
Bit 0
CH0
Analog Input Channel
0
0
*
*
No channel selected
0
1
0
0
AN 0
0
1
0
1
AN 1
0
1
1
0
AN 2
0
1
1
1
AN 3
1
0
0
0
Setting prohibited
1
0
0
1
1
0
1
0
1
0
1
1
(initial value)
*: Don’t care
287
12.2.3
A/D Start Register (ADSR)
Bit
7
6
5
4
3
2
1
0
ADSF
—
—
—
—
—
—
—
Initial value
0
1
1
1
1
1
1
1
Read/Write
R/W
—
—
—
—
—
—
—
The A/D start register (ADSR) is an 8-bit read/write register for starting and stopping A/D
conversion.
A/D conversion is started by writing 1 to the A/D start flag (ADSF), which also sets ADSF to 1.
When conversion is complete, the converted data is set in ADRRH and ADRRL, and at the same
time ADSF is cleared to 0.
Bit 7: A/D start flag (ADSF)
Bit 7 controls and indicates the start and end of A/D conversion.
Bit 7
ADSF
Description
0
Read: Indicates the completion of A/D conversion
Write: Stops A/D conversion
1
Read: Indicates A/D conversion in progress
Write: Starts A/D conversion
Bits 6 to 0: Reserved bits
Bits 6 to 0 are reserved; they are always read as 1, and cannot be modified.
288
(initial value)
12.2.4
Clock Stop Register 1 (CKSTPR1)
Bit
7
6
—
—
5
Initial value
1
1
1
Read/Write
—
—
R/W
4
3
2
1
0
—
TFCKSTP
—
TACKSTP
1
1
1
1
1
R/W
—
R/W
—
R/W
S32CKSTP ADCKSTP
CKSTPR1 is an 8-bit read/write register that performs module standby mode control for peripheral
modules. Only the bit relating to the A/D converter is described here. For details of the other bits,
see the sections on the relevant modules.
Bit 4: A/D converter module standby mode control (ADCKSTP)
Bit 4 controls setting and clearing of module standby mode for the A/D converter.
ADCKSTP
Description
0
A/D converter is set to module standby mode
1
A/D converter module standby mode is cleared
(initial value)
289
12.3
Operation
12.3.1
A/D Conversion Operation
The A/D converter operates by successive approximations, and yields its conversion result as 10bit data.
A/D conversion begins when software sets the A/D start flag (bit ADSF) to 1. Bit ADSF keeps a
value of 1 during A/D conversion, and is cleared to 0 automatically when conversion is complete.
The completion of conversion also sets bit IRRAD in interrupt request register 2 (IRR2) to 1. An
A/D conversion end interrupt is requested if bit IENAD in interrupt enable register 2 (IENR2) is
set to 1.
If the conversion time or input channel needs to be changed in the A/D mode register (AMR)
during A/D conversion, bit ADSF should first be cleared to 0, stopping the conversion operation,
in order to avoid malfunction.
12.3.2
A/D Converter Operation Modes
A/D converter operation modes are shown in table 12.3.
Table 12.3 A/D Converter Operation Modes
Operation
Mode
Reset
Active
Subactive Subsleep Standby
Module
Standby
AMR
Reset
Functions Functions Held
Held
Held
Held
Held
ADSR
Reset
Functions Functions Held
Held
Held
Held
Held
ADRRH
Held*
Functions Functions Held
Held
Held
Held
Held
ADRRL
Held*
Functions Functions Held
Held
Held
Held
Held
Sleep
Note: * Undefined in a power-on reset.
290
Watch
12.4
Interrupts
When A/D conversion ends (ADSF changes from 1 to 0), bit IRRAD in interrupt request register 2
(IRR2) is set to 1.
A/D conversion end interrupts can be enabled or disabled by means of bit IENAD in interrupt
enable register 2 (IENR2).
For further details see 3.3, Interrupts.
12.5
Typical Use
An example of how the A/D converter can be used is given below, using channel 1 (pin AN1) as
the analog input channel. Figure 12.2 shows the operation timing.
1. Bits CH3 to CH0 of the A/D mode register (AMR) are set to 0101, making pin AN1 the analog
input channel. A/D interrupts are enabled by setting bit IENAD to 1, and A/D conversion is
started by setting bit ADSF to 1.
2. When A/D conversion is complete, bit IRRAD is set to 1, and the A/D conversion result is
stored is stored in ADRRH and ADRRL. At the same time ADSF is cleared to 0, and the A/D
converter goes to the idle state.
3. Bit IENAD = 1, so an A/D conversion end interrupt is requested.
4. The A/D interrupt handling routine starts.
5. The A/D conversion result is read and processed.
6. The A/D interrupt handling routine ends.
If ADSF is set to 1 again afterward, A/D conversion starts and steps 2 through 6 take place.
Figures 12.3 and 12.4 show flow charts of procedures for using the A/D converter.
291
Figure 12.2 Typical A/D Converter Operation Timing
292
Idle
A/D conversion starts
A/D conversion (1)
Set *
Set *
Note: * ( ) indicates instruction execution by software.
ADRRH
ADRRL
Channel 1 (AN1)
operation state
ADSF
IENAD
Interrupt
(IRRAD)
A/D conversion (2)
A/D conversion result (1)
Read conversion result
Idle
Set *
A/D conversion result (2)
Read conversion result
Idle
Start
Set A/D conversion speed
and input channel
Disable A/D conversion
end interrupt
Start A/D conversion
Read ADSR
No
ADSF = 0?
Yes
Read ADRRH/ADRRL data
Yes
Perform A/D
conversion?
No
End
Figure 12.3 Flow Chart of Procedure for Using A/D Converter (Polling by Software)
293
Start
Set A/D conversion speed
and input channels
Enable A/D conversion
end interrupt
Start A/D conversion
A/D conversion
end interrupt?
No
Yes
Clear bit IRRAD to
0 in IRR2
Read ADRRH/ADRRL data
Yes
Perform A/D
conversion?
No
End
Figure 12.4 Flow Chart of Procedure for Using A/D Converter (Interrupts Used)
12.6
Application Notes
• Data in ADRRH and ADRRL should be read only when the A/D start flag (ADSF) in the A/D
start register (ADSR) is cleared to 0.
• Changing the digital input signal at an adjacent pin during A/D conversion may adversely
affect conversion accuracy.
• When A/D conversion is started after clearing module standby mode, wait for 10 ø clock
cycles before starting.
• In active mode and sleep mode, the analog power supply current (AISTOP1) flows in the ladder
resistance even when the A/D converter is on standby. Therefore, if the A/D converter is not
used, it is recommended that AV CC be connected to the system power supply and the
ADCKSTP (A/D converter module standby mode control) bit be cleared to 0 in clock stop
register 1 (CKSTPR1).
294
Section 13 LCD Controller/Driver
13.1
Overview
The H8/3802 Series has an on-chip segment type LCD control circuit, LCD driver, and power
supply circuit, enabling it to directly drive an LCD panel.
13.1.1
Features
1. Features
Features of the LCD controller/driver are given below.
• Display capacity
Duty Cycle
Internal Driver
Static
25 seg
1/2
25 seg
1/3
25 seg
1/4
25 seg
• LCD RAM capacity
8 bits × 13 bytes (104 bits)
• Word access to LCD RAM
• All four segment output pins can be used individually as port pins.
• Common output pins not used because of the duty cycle can be used for common doublebuffering (parallel connection).
• Display possible in operating modes other than standby mode
• Choice of 11 frame frequencies
• Built-in power supply split-resistance, supplying LCD drive power
• Use of module standby mode enables this module to be placed in standby mode independently
when not used.
• A or B waveform selectable by software
295
13.1.2
Block Diagram
Figure 13.1 shows a block diagram of the LCD controller/driver.
LCD drive power supply
VCC
V1
V2
V3
VSS
ø/2 to ø/256
Common
data latch
Internal data bus
øw
Common
driver
LPCR
LCR
LCR2
COM1
COM4
SEG25
25-bit shift
register
Display timing generator
Segment
driver
LCD RAM
(13 bytes)
SEG1
SEGn
Notation:
LPCR: LCD port control register
LCR: LCD control register
LCR2: LCD control register 2
Figure 13.1 Block Diagram of LCD Controller/Driver
296
13.1.3
Pin Configuration
Table 13.1 shows the LCD controller/driver pin configuration.
Table 13.1 Pin Configuration
Name
Abbrev.
I/O
Function
Segment output pins
SEG25 to SEG 1
Output
LCD segment drive pins
All pins are multiplexed as port pins
(setting programmable)
Common output pins
COM4 to COM1
Output
LCD common drive pins
Pins can be used in parallel with static or
1/2 duty
LCD power supply pins
V1, V2, V3
—
Used when a bypass capacitor is
connected externally, and when an
external power supply circuit is used
13.1.4
Register Configuration
Table 13.2 shows the register configuration of the LCD controller/driver.
Table 13.2 LCD Controller/Driver Registers
Name
Abbrev.
R/W
Initial Value
Address
LCD port control register
LPCR
R/W
—
H'FFC0
LCD control register
LCR
R/W
H'80
H'FFC1
LCD control register 2
LCR2
R/W
—
H'FFC2
LCD RAM
—
R/W
Undefined
H'F740 to H'F74C
Clock stop register 2
CKSTPR2
R/W
H'FF
H'FFFB
297
13.2
Register Descriptions
13.2.1
LCD Port Control Register (LPCR)
Bit
7
6
5
4
3
2
1
0
DTS1
DTS0
CMX
—
SGS3
SGS2
SGS1
SGS0
Initial value
0
0
0
—
0
0
0
0
Read/Write
R/W
R/W
R/W
W
R/W
R/W
R/W
R/W
LPCR is an 8-bit read/write register which selects the duty cycle and LCD driver pin functions.
Bits 7 to 5: Duty cycle select 1 and 0 (DTS1, DTS0), common function select (CMX)
The combination of DTS1 and DTS0 selects static, 1/2, 1/3, or 1/4 duty. CMX specifies whether
or not the same waveform is to be output from multiple pins to increase the common drive power
when not all common pins are used because of the duty setting.
Bit 7
DTS1
Bit 6
DTS0
Bit 5
CMX
Duty Cycle
Common Drivers
0
0
0
Static
COM1 (initial value) Do not use COM4, COM3, and
COM2.
1
0
1
0
1/2 duty
1
1
0
0
1/3 duty
1
1
1
0
1/4 duty
COM4 to COM1
COM4, COM3, and COM 2 output
the same waveform as COM1.
COM2 to COM1
Do not use COM4 and COM3.
COM4 to COM1
COM4 outputs the same waveform
as COM3, and COM 2 outputs the
same waveform as COM1.
COM3 to COM1
Do not use COM4.
COM4 to COM1
Do not use COM4.
COM4 to COM1
—
1
Bit 4: Reserved bit
Bit 4 is reserved; only 0 can be written to this bit.
Bits 3 to 0: Segment driver select 3 to 0 (SGS3 to SGS0)
Bits 3 to 0 select the segment drivers to be used.
298
Notes
Function of Pins SEG 25 to SEG1
Bit 3
Bit 2
Bit 1
Bit 0
SEG 24 to
SEG 20 to
SEG 16 to
SEG 12 to
SEG 8 to
SEG 4 to
SGS3
SGS2
SGS1
SGS0
SEG 25
SEG 21
SEG 17
SEG 13
SEG 9
SEG 5
SEG 1
Notes
0
0
0
0
Port
Port
Port
Port
Port
Port
Port
(Initial value)
1
Port
Port
Port
Port
Port
Port
SEG
0
Port
Port
Port
Port
Port
SEG
SEG
1
Port
Port
Port
Port
SEG
SEG
SEG
0
Port
Port
Port
SEG
SEG
SEG
SEG
1
Port
Port
SEG
SEG
SEG
SEG
SEG
0
Port
SEG
SEG
SEG
SEG
SEG
SEG
1
SEG
SEG
SEG
SEG
SEG
SEG
SEG
0
SEG
SEG
SEG
SEG
SEG
SEG
SEG
1
SEG
SEG
SEG
SEG
SEG
SEG
Port
0
SEG
SEG
SEG
SEG
SEG
Port
Port
1
SEG
SEG
SEG
SEG
Port
Port
Port
0
SEG
SEG
SEG
Port
Port
Port
Port
1
SEG
SEG
Port
Port
Port
Port
Port
0
SEG
Port
Port
Port
Port
Port
Port
1
Port
Port
Port
Port
Port
Port
Port
1
1
0
1
1
0
0
1
1
0
1
299
13.2.2
LCD Control Register (LCR)
Bit
7
6
5
4
3
2
1
0
—
PSW
ACT
DISP
CKS3
CKS2
CKS1
CKS0
Initial value
1
0
0
0
0
0
0
0
Read/Write
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LCR is an 8-bit read/write register which performs LCD drive power supply on/off control and
display data control, and selects the frame frequency.
LCR is initialized to H'80 upon reset.
Bit 7: Reserved bit
Bit 7 is reserved; it is always read as 1 and cannot be modified.
Bit 6: LCD drive power supply on/off control (PSW)
Bit 6 can be used to turn the LCD drive power supply off when LCD display is not required in a
power-down mode, or when an external power supply is used. When the ACT bit is cleared to 0,
or in standby mode, the LCD drive power supply is turned off regardless of the setting of this bit.
Bit 6
PSW
Description
0
LCD drive power supply off
1
LCD drive power supply on
(initial value)
Bit 5: Display function activate (ACT)
Bit 5 specifies whether or not the LCD controller/driver is used. Clearing this bit to 0 halts
operation of the LCD controller/driver. The LCD drive power supply is also turned off, regardless
of the setting of the PSW bit. However, register contents are retained.
Bit 5
ACT
Description
0
LCD controller/driver operation halted
1
LCD controller/driver operates
300
(initial value)
Bit 4: Display data control (DISP)
Bit 4 specifies whether the LCD RAM contents are displayed or blank data is displayed regardless
of the LCD RAM contents.
Bit 4
DISP
Description
0
Blank data is displayed
1
LCD RAM data is display
(initial value)
Bits 3 to 0: Frame frequency select 3 to 0 (CKS3 to CKS0)
Bits 3 to 0 select the operating clock and the frame frequency. In subactive mode, watch mode,
and subsleep mode, the system clock (ø) is halted, and therefore display operations are not
performed if one of the clocks from ø/2 to ø/256 is selected. If LCD display is required in these
modes, øw, øw/2, or øw/4 must be selected as the operating clock.
Frame Frequency*2
Bit 3
Bit 2
Bit 1
Bit 0
CKS3
CKS2
CKS1
CKS0
Operating Clock
ø = 2 MHz
0
*
0
0
øw
128 Hz *3 (initial value)
0
*
0
1
øw/2
64 Hz *3
0
*
1
*
øw/4
32 Hz *3
1
0
0
0
ø/2
—
244 Hz
1
0
0
1
ø/4
977 Hz
122 Hz
1
0
1
0
ø/8
488 Hz
61 Hz
1
0
1
1
ø/16
244 Hz
30.5 Hz
1
1
0
0
ø/32
122 Hz
—
1
1
0
1
ø/64
61 Hz
—
1
1
1
0
ø/128
30.5 Hz
—
1
1
1
1
ø/256
—
—
ø = 250 kHz*1
*: Don’t care
Notes: 1. This is the frame frequency in active (medium-speed, øosc/16) mode when ø = 2 MHz.
2. When 1/3 duty is selected, the frame frequency is 4/3 times the value shown.
3. This is the frame frequency when øw = 32.768 kHz.
301
13.2.3
LCD Control Register 2 (LCR2)
Bit
7
6
5
4
3
2
1
0
LCDAB
—
—
—
—
—
—
—
Initial value
0
1
1
—
—
—
—
—
Read/Write
R/W
—
—
W
W
W
W
W
LCR2 is an 8-bit read/write register which controls switching between the A waveform and B
waveform.
Bit 7: A waveform/B waveform switching control (LCDAB)
Bit 7 specifies whether the A waveform or B waveform is used as the LCD drive waveform.
Bit 7
LCDAB
Description
0
Drive using A waveform
1
Drive using B waveform
Bits 6 and 5: Reserved bits
Bits 6 and 5 are reserved; they are always read as 1 and cannot be modified.
Bits 4 to 0: Reserved bits
Bits 4 to 0 are reserved; only 0 can be written to these bits.
302
(initial value)
13.2.4
Clock Stop Register 2 (CKSTPR2)
Bit
7
6
5
—
—
—
Initial value
1
1
1
1
1
1
1
1
Read/Write
—
—
—
R/W
R/W
—
R/W
R/W
4
3
PW2CKSTP AECKSTP
2
—
1
0
PW1CKSTP LDCKSTP
CKSTPR2 is an 8-bit read/write register that performs module standby mode control for peripheral
modules. Only the bit relating to the LCD controller/driver is described here. For details of the
other bits, see the sections on the relevant modules.
Bit 0: LCD controller/driver module standby mode control (LDCKSTP)
Bit 0 controls setting and clearing of module standby mode for the LCD controller/driver.
Bit 0
LDCKSTP
Description
0
LCD controller/driver is set to module standby mode
1
LCD controller/driver module standby mode is cleared
(initial value)
303
13.3
Operation
13.3.1
Settings up to LCD Display
To perform LCD display, the hardware and software related items described below must first be
determined.
1. Hardware settings
a. Using 1/2 duty
When 1/2 duty is used, interconnect pins V2 and V 3 as shown in figure 13.2.
VCC
V1
V2
V3
VSS
Figure 13.2 Handling of LCD Drive Power Supply when Using 1/2 Duty
b. Large-panel display
As the impedance of the built-in power supply split-resistance is large, it may not be
suitable for driving a large panel. If the display lacks sharpness when using a large panel,
refer to section 13.3.4, Boosting the LCD Drive Power Supply. When static or 1/2 duty is
selected, the common output drive capability can be increased. Set CMX to 1 when
selecting the duty cycle. In this mode, with a static duty cycle pins COM4 to COM1 output
the same waveform, and with 1/2 duty the COM 1 waveform is output from pins COM 2 and
COM1, and the COM2 waveform is output from pins COM4 and COM3.
304
2. Software settings
a. Duty selection
Any of four duty cycles—static, 1/2 duty, 1/3 duty, or 1/4 duty—can be selected with bits
DTS1 and DTS0.
b. Segment selection
The segment drivers to be used can be selected with bits SGS3 to SGS0.
c. Frame frequency selection
The frame frequency can be selected by setting bits CKS3 to CKS0. The frame frequency
should be selected in accordance with the LCD panel specification. For the clock selection
method in watch mode, subactive mode, and subsleep mode, see 13.3.3, Operation in
Power-Down Modes.
d. A or B waveform selection
Either the A or B waveform can be selected as the LCD waveform to be used by means of
LCDAB.
305
13.3.2
Relationship between LCD RAM and Display
The relationship between the LCD RAM and the display segments differs according to the duty
cycle. LCD RAM maps for the different duty cycles are shown in figures 13.3 to 13.6.
After setting the registers required for display, data is written to the part corresponding to the duty
using the same kind of instruction as for ordinary RAM, and display is started automatically when
turned on. Word- or byte-access instructions can be used for RAM setting.
H'F740
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
SEG2
SEG2
SEG2
SEG2
SEG1
SEG1
SEG1
SEG1
SEG25
SEG25
SEG25
SEG25
COM4
COM3
COM2
COM1
H'F74C
COM4
COM3
COM2
COM1
Figure 13.3 LCD RAM Map (1/4 Duty)
306
bit7
H'F740
bit6
bit5
bit4
SEG2
SEG2
SEG2
H'F74C
COM3
COM2
COM1
bit3
bit2
bit1
bit0
SEG1
SEG1
SEG1
SEG25
SEG25
SEG25
COM3
COM2
COM1
Space not used for display
Figure 13.4 LCD RAM Map (1/3 Duty)
307
H'F740
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
SEG4
SEG4
SEG3
SEG3
SEG2
SEG2
SEG1
SEG1
Display space
SEG25
SEG25
H'F746
Space not used for display
H'F74C
COM2
COM1
COM2
COM1
COM2
COM1
COM2
COM1
Figure 13.5 LCD RAM Map (1/2 Duty)
H'F740
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
Display
space
SEG25
H'F743
Space not
used for
display
H'F74C
COM1
COM1
COM1
COM1
COM1
COM1
COM1
Figure 13.6 LCD RAM Map (Static Mode)
308
COM1
1 frame
1 frame
M
M
Data
Data
V1
V2
V3
VSS
COM1
V1
V2
V3
VSS
V1
V2
V3
VSS
COM2
COM3
V1
V2
V3
VSS
V1
V2
V3
VSS
COM4
SEGn
V1
V2
V3
VSS
COM1
V1
V2
V3
VSS
V1
V2
V3
VSS
COM2
COM3
V1
V2
V3
VSS
SEGn
(a) Waveform with 1/4 duty
(b) Waveform with 1/3 duty
1 frame
1 frame
M
M
Data
Data
COM1
V1
V2, V3
VSS
COM1
COM2
V1
V2, V3
VSS
SEGn
V1
V2, V3
VSS
SEGn
(c) Waveform with 1/2 duty
V1
VSS
V1
VSS
(d) Waveform with static output
M: LCD alternation signal
Figure 13.7 Output Waveforms for Each Duty Cycle (A Waveform)
309
1 frame
1 frame
1 frame
1 frame
1 frame
M
M
Data
Data
V1
V2
V3
VSS
V1
V2
V3
VSS
V1
V2
V3
VSS
V1
V2
V3
VSS
COM1
COM2
COM3
COM4
V1
V2
V3
VSS
SEGn
1 frame
1 frame
1 frame
1 frame
V1
V2
V3
VSS
V1
V2
V3
VSS
V1
V2
V3
VSS
COM1
COM2
COM3
V1
V2
V3
VSS
SEGn
(a) Waveform with 1/4 duty
1 frame
1 frame
(b) Waveform with 1/3 duty
1 frame
1 frame
1 frame
1 frame
1 frame
M
M
Data
Data
V1
COM1
V1
V2, V3
VSS
COM1
COM2
V1
V2, V3
VSS
SEGn
SEGn
V1
V2, V3
VSS
(c) Waveform with 1/2 duty
VSS
V1
VSS
(d) Waveform with static output
M: LCD alternation signal
Figure 13.8 Output Waveforms for Each Duty Cycle (B Waveform)
310
Table 13.3 Output Levels
Data
0
0
1
1
M
0
1
0
1
Common output
V1
VSS
V1
VSS
Segment output
V1
VSS
VSS
V1
Common output
V2, V3
V2, V3
V1
VSS
Segment output
V1
VSS
VSS
V1
Common output
V3
V2
V1
VSS
Segment output
V2
V3
VSS
V1
Common output
V3
V2
V1
VSS
Segment output
V2
V3
VSS
V1
Static
1/2 duty
1/3 duty
1/4 duty
M: LCD alternation signal
13.3.3
Operation in Power-Down Modes
In the H8/3802 Series, the LCD controller/driver can be operated even in the power-down modes.
The operating state of the LCD controller/driver in the power-down modes is summarized in table
13.4.
In subactive mode, watch mode, and subsleep mode, the system clock oscillator stops, and
therefore, unless øw, øw/2, or øw/4 has been selected by bits CKS3 to CKS0, the clock will not be
supplied and display will halt. Since there is a possibility that a direct current will be applied to
the LCD panel in this case, it is essential to ensure that øw, øw/2, or øw/4 is selected. In active
(medium-speed) mode, the system clock is switched, and therefore CKS3 to CKS0 must be
modified to ensure that the frame frequency does not change.
311
Table 13.4 Power-Down Modes and Display Operation
Reset Active
Sleep
Watch
Subactive
Subsleep
Module
Standby Standby
ø
Runs
Runs
Runs
Stops
Stops
Stops
Stops
Stops*4
øw
Runs
Runs
Runs
Runs
Runs
Runs
Stops*1
Stops*4
ACT = 0
Stops
Stops
Stops
Stops
Stops
Stops
Stops*2
Stops
*2
Stops
Mode
Clock
Display
operation ACT = 1
Stops
Functions Functions Functions
*3
Functions
*3
Functions
*3
Stops
Notes: 1. The subclock oscillator does not stop, but clock supply is halted.
2. The LCD drive power supply is turned off regardless of the setting of the PSW bit.
3. Display operation is performed only if øw, øw/2, or øw/4 is selected as the operating
clock.
4. The clock supplied to the LCD stops.
13.3.4
Boosting the LCD Drive Power Supply
When a large panel is driven, the on-chip power supply capacity may be insufficient. If the power
supply capacity is insufficient when V CC is used as the power supply, the power supply
impedance must be reduced. This can be done by connecting bypass capacitors of around 0.1 to
0.3 µF to pins V1 to V3, as shown in figure 13.9, or by adding a split-resistance externally.
R
VCC
V1
R
H8/3802 Series
R = several kΩ to
several MΩ
V2
R
C= 0.1 to 0.3µF
V3
R
VSS
Figure 13.9 Connection of External Split-Resistance
312
Section 14 Electrical Characteristics
14.1
H8/3802 Series Absolute Maximum Ratings
Table 14.1 lists the absolute maximum ratings.
Table 14.1 Absolute Maximum Ratings
Item
Symbol
Value
Unit
Power supply voltage
VCC
–0.3 to +7.0
V
Analog power supply voltage
AVCC
–0.3 to +7.0
V
Programming voltage
VPP
–0.3 to +13.0
V
Input voltage
Ports other than Port B,
IRQAEC
Vin
–0.3 to VCC +0.3
V
Port B
AVin
–0.3 to AVCC +0.3
V
IRQAEC
HV in
–0.3 to +7.3
V
Operating temperature
Topr
–20 to +75
°C
Storage temperature
Tstg
–55 to +125
°C
Note: Permanent damage may occur to the chip if maximum ratings are exceeded. Normal
operation should be under the conditions specified in Electrical Characteristics. Exceeding
these values can result in incorrect operation and reduced reliability.
313
14.2
H8/3802 Series Electrical Characteristics
14.2.1
Power Supply Voltage and Operating Range
The power supply voltage and operating range are indicated by the shaded region in the figures.
1. Power supply voltage and oscillator frequency range
38.4
fW (kHz)
fosc (MHz)
16.0
10.0
32.768
4.0
2.0
1.8
2.7
4.5
5.5
VCC (V)
3.0
5.5
4.5
VCC (V)
• Active (high-speed) mode
• All operating
• Sleep (high-speed) mode
• Note 2: When an oscillator is used for the subclock,
hold VCC at 2.2 V to 5.5 V from power-on
until the oscillation settling time has elapsed.
• Note 1: The fosc values are those when an oscillator
is used; when an external clock is used the
minimum value of fosc is 1 MHz.
314
1.8
2. Power supply voltage and operating frequency range
8.0
5.0
16.384
2.0
1.0
(0.5)
9.6
1.8
2.7
4.5
5.5
VCC (V)
• Active (high-speed) mode
øSUB (kHz)
ø (MHz)
19.2
• Sleep (high-speed) mode (except CPU)
8.192
4.8
4.096
Note 1. The figure in parentheses is the minimum operating
frequency when an external clock is input. When
using an oscillator, the minimum operating frequency
(ø) is 1 MHz.
1.8
3.6
5.5
VCC (V)
1000
• Subactive mode
ø (kHz)
• Subsleep mode (except CPU)
• Watch mode (except CPU)
625
250
15.625
(7.8125)
1.8
2.7
4.5
5.5
VCC (V)
• Active (medium-speed) mode
• Sleep (medium-speed) mode
(except A/D converter)
Note 2. The figure in parentheses is the minimum operating
frequency when an external clock is input. When
using an oscillator, the minimum operating frequency
(ø) is 15.625 kHz.
3. Analog power supply voltage and A/D converter operating range
1000
ø (kHz)
ø (MHz)
5.0
1.0
625
500
(0.5)
1.8
Note 3:
2.7
4.5
5.5
AVCC (V)
1.8
2.7
• Active (high-speed) mode
• Active (medium-speed) mode
• Sleep (high-speed) mode
• Sleep (medium-speed) mode
4.5
5.5
AVCC (V)
When AVCC = 1.8 V to 2.7 V, the operating range is limited to ø = 1.0 MHz when using an oscillator,
and is ø = 0.5 MHz to 1.0 MHz when using an external clock.
315
14.2.2
DC Characteristics
Table 14.2 lists the DC characteristics of the H8/3802.
Table 14.2 DC Characteristics
VCC = 1.8 V to 5.5 V, AVCC = 1.8 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = –20°C to +75°C
(including subactive mode) unless otherwise indicated.
Values
Item
Symbol Applicable Pins Min
Input high
VIH
voltage
Max
Unit Test Condition
V
RES,
0.8 V CC
—
VCC + 0.3
WKP0 to WKP7,
IRQ0, IRQ1,
AEVL, AEVH,
SCK32
0.9 V CC
—
VCC + 0.3
RXD32
0.7 V CC
—
VCC + 0.3
0.8 V CC
—
VCC + 0.3
0.8 V CC
—
VCC + 0.3
0.9 V CC
—
VCC + 0.3
X1
0.9 V CC
—
VCC + 0.3
V
VCC = 1.8 V to 5.5 V
P31 to P37,
P40 to P43,
P50 to P57,
P60 to P67,
P70 to P77,
P80,
PA 0 to PA3
0.7 V CC
—
VCC + 0.3
V
VCC = 4.0 V to 5.5 V
0.8 V CC
—
VCC + 0.3
Except the above
PB 0 to PB3
0.7 V CC
—
AV CC + 0.3
VCC = 4.0 V to 5.5 V
0.8 V CC
—
AV CC + 0.3
Except the above
0.8 V CC
—
7.3
0.9 V CC
—
7.3
OSC1
IRQAEC
Note: Connect the TEST pin to VSS.
316
Typ
VCC = 4.0 V to 5.5 V
Except the above
V
VCC = 4.0 V to 5.5 V
Except the above
V
VCC = 4.0 V to 5.5 V
Except the above
V
VCC = 4.0 V to 5.5 V
Except the above
Notes
Values
Item
Symbol Applicable Pins Min
Input low
VIL
voltage
Output low
voltage
VOL
Max
Unit Test Condition
V
RES,
–0.3
—
0.2 V CC
WKP0 to WKP7,
IRQ0, IRQ1,
IRQAEC, AEVL,
AEVH, SCK 32
–0.3
—
0.1 V CC
RXD32 ,
–0.3
—
0.3 V CC
–0.3
—
0.2 V CC
–0.3
—
0.2 V CC
–0.3
—
0.1 V CC
X1
–0.3
—
0.1 V CC
V
VCC = 1.8 V to 5.5 V
P31 to P37,
P40 to P43,
P50 to P57,
P60 to P67,
P70 to P77,
P80,
PA 0 to PA3,
PB 0 to PB3
–0.3
—
0.3 V CC
V
VCC = 4.0 V to 5.5 V
–0.3
—
0.2 V CC
P31 to P37,
P40 to P42,
P50 to P57,
P60 to P67,
P70 to P77,
P80,
PA 0 to PA3
VCC – 1.0 —
—
VCC – 0.5 —
—
VCC = 4.0 V to 5.5 V
–I OH = 0.5 mA
VCC – 0.3 —
—
–I OH = 0.1 mA
P40 to P42
—
—
0.6
—
—
0.5
IOL = 0.4 mA
P50 to P57, P60
to P6 7, P70 to
P77, P80,
PA 0 to PA3
—
—
0.5
IOL = 0.4 mA
P31 to P37
—
—
1.5
VCC = 4.0 V to 5.5 V
IOL = 10 mA
—
—
0.6
VCC = 4.0 V to 5.5 V
IOL = 1.6 mA
—
—
0.5
IOL = 0.4 mA
OSC1
Output high VOH
voltage
Typ
Notes
VCC = 4.0 V to 5.5 V
Except the above
V
VCC = 4.0 V to 5.5 V
Except the above
V
VCC = 4.0 V to 5.5 V
Except the above
Except the above
V
V
VCC = 4.0 V to 5.5 V
–I OH = 1.0 mA
VCC = 4.0 V to 5.5 V
IOL = 1.6 mA
317
Values
Item
Symbol Applicable Pins Min
Typ
Max
Unit Test Condition
Output low
voltage
VOL
—
0.5
V
P90 to P92
—
Notes
VCC = 2.2 V to 5.5 V,
IOL = 25 mA
IOL = 15 mA
IOL = 10 mA
*6
P93 to P95
—
—
0.5
RES, P43
—
—
20.0
—
—
1.0
OSC1, X1,
P31 to P37,
P40 to P42,
P50 to P57,
P60 to P67,
P70 to P77,
P80, IRQAEC,
P90 to P95,
PA 0 to PA3
—
—
1.0
PB 0 to PB3
—
—
1.0
P31 to P37,
P50 to P57,
50.0
—
300.0
current
P60 to P67
—
35.0
—
Input
CIN
capacitance
All input pins
except power
supply, RES,
IRQAEC, P43,
PB 0 to PB3
—
—
15.0
IRQAEC
—
—
30.0
RES
—
—
80.0
*2
—
—
15.0
*1
—
—
50.0
*2
—
—
15.0
*1
—
—
15.0
Input/output | I IL |
leakage
current
Pull-up
MOS
–I p
P43
PB 0 to PB3
318
IOL = 10 mA
µA
µA
VIN = 0.5 V to
*2
VCC – 0.5 V
*1
VIN = 0.5 V to
VCC – 0.5 V
VIN = 0.5 V to
AV CC – 0.5 V
µA
VCC = 5 V,
VIN = 0 V
VCC = 2.7 V,
VIN = 0 V
pF
Reference
value
f = 1 MHz,
VIN =0 V,
Ta = 25°C
Values
Item
Symbol Applicable Pins Min
Typ
Max
Unit Test Condition
Notes
Active
mode
current
dissipation
IOPE1
7.0
10.0
mA
Active (high-speed)
mode V CC = 5 V,
fOSC = 10 MHz
*3
Active (mediumspeed) mode
VCC = 5 V,
fOSC = 10 MHz
øosc/128
*3
VCC=5 V,
fOSC= 10 MHz
*3
VCC = 2.7 V,
LCD on 32 kHz
crystal oscillator
(ø SUB=øw/2)
*3
VCC = 2.7 V,
LCD on 32 kHz
crystal oscillator
(ø SUB=øw/8)
*3
VCC = 2.7 V,
LCD on 32 kHz
crystal oscillator
(ø SUB=øw/2)
*3
VCC = 2.7 V 3
2 kHz crystal
oscillator
LCD not used
*2
IOPE2
VCC
VCC
Sleep mode ISLEEP
current
dissipation
VCC
Subactive
mode
current
dissipation
VCC
ISUB
—
—
—
—
—
Subsleep
mode
current
dissipation
ISUBSP
Watch
mode
current
dissipation
IWATCH
VCC
VCC
—
—
2.2
3.8
15.0
8.0
7.5
3.8
3.0
5.0
30.0
—
16.0
6.0
mA
mA
µA
µA
µA
µA
*4
*4
*4
*4
*4
Reference
value
*4
*3
*4
*1
2.8
*3
*4
Standby
mode
current
dissipation
ISTBY
RAM data
retaining
voltage
VRAM
VCC
VCC
—
1.5
1.0
—
5.0
—
µA
32 kHz crystal
oscillator not used
*3
*4
V
319
Values
Item
Symbol Applicable Pins Min
Typ
Max
Unit Test Condition
Allowable
output low
current
(per pin)
IOL
mA
Allowable
output low
current
(per pin)
Allowable
output low
current
(total)
IOL
∑ IOL
Allowable
output high
current
(per pin)
–I OH
Allowable
output high
∑ – IOH
Output pins
except port 3
and 9
—
—
2.0
Port 3
—
—
10.0
Output pins
except port 9
—
—
0.5
P90 to P92
—
—
25.0
—
—
15.0
—
—
10.0
P93 to P95
—
—
10.0
Output pins
except ports 3
and 9
—
—
40.0
Port 3
—
—
80.0
Output pins
except port 9
—
—
20.0
Port 9
—
—
80.0
All output pins
—
—
2.0
—
—
0.2
—
—
15.0
—
—
10.0
All output pins
Notes: 1. Applies to the Mask ROM products.
2. Applies to the HD6473802.
320
Notes
VCC = 4.0 V to 5.5 V
VCC = 4.0 V to 5.5 V
mA
VCC = 2.2 V to 5.5 V
mA
VCC = 4.0 V to 5.5 V
VCC = 4.0 V to 5.5 V
mA
VCC = 4.0 V to 5.5 V
Except the above
mA
VCC = 4.0 V to 5.5 V
Except the above
*5
3. Pin states during current measurement.
Mode
Active (high-speed)
mode (IOPE1)
RES
Pin
Internal State
Other
Pins
LCD Power
Supply
VCC
Operates
VCC
Halted
Active (mediumspeed) mode (IOPE2)
Oscillator Pins
System clock oscillator:
crystal
Subclock oscillator:
Pin X1 = GND
Sleep mode
VCC
Only timers operate
VCC
Halted
Subactive mode
VCC
Operates
VCC
Halted
System clock oscillator:
Subsleep mode
VCC
Only timers operate,
CPU stops
VCC
Halted
crystal
Subclock oscillator:
Watch mode
VCC
Only time base
operates, CPU stops
VCC
Halted
crystal
Standby mode
VCC
CPU and timers both
stop
VCC
Halted
System clock oscillator:
crystal
Subclock oscillator:
Pin X1 = GND
4. Excludes current in pull-up MOS transistors and output buffers.
5. When the PIOFF bit in the port mode register 9 is 0.
6. When the PIOFF bit in the port mode register 9 is 1.
321
14.2.3
AC Characteristics
Table 14.3 lists the control signal timing, and tables 14.4 lists the serial interface timing of the
H8/3802.
Table 14.3 Control Signal Timing
VCC = 1.8 V to 5.5 V, AVCC = 1.8 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = –20°C to +75°C
(including subactive mode) unless otherwise indicated.
Applicable
Values
Reference
Item
Symbol Pins
Min
Typ
Max
Unit
Test Condition
System clock
fOSC
2.0
—
16.0
MHz
VCC = 4.5 V to 5.5 V
oscillation
2.0
—
10.0
VCC = 2.7 V to 5.5 V
frequency
2.0
—
4.0
Except the above
62.5
—
500
ns
(1000)
VCC = 4.5 V to 5.5 V Figure 14.1
100
—
500
(1000)
VCC = 2.7 V to 5.5 V
250
—
500
(1000)
Except the above
2
—
128
tOSC
—
—
128
µs
OSC clock (ø OSC)
cycle time
System clock (ø)
tOSC
OSC1, OSC2
OSC1, OSC2
tcyc
cycle time
Figure
*2
Subclock oscillation fW
frequency
X1, X2
—
32.768 —
or 38.4
kHz
Watch clock (øW )
cycle time
tW
X1, X2
—
30.5 or —
26.0
µs
Figure 14.1
Subclock (øSUB)
cycle time
tsubcyc
2
—
8
tW
*1
2
—
—
tcyc
tsubcyc
—
20
45
µs
Figure 14.7
Figure 14.7
VCC = 2.2 V to 5.5 V
—
—
50
ms
Except the above
Instruction cycle
time
Oscillation
stabilization time
322
trc
OSC1, OSC2
Figure 14.7
Applicable
Values
Reference
Item
Symbol Pins
Min
Typ
Max
Unit
Test Condition
Figure
Oscillation
stabilization time
trc
—
—
2.0
s
VCC = 2.7 V to 5.5 V
*3
—
—
10.0
25
—
—
40
—
—
VCC = 2.7 V to 5.5 V
100
—
—
Except the above
X1
—
15.26
or
13.02
—
µs
OSC1
25
—
—
ns
40
—
—
VCC = 2.7 V to 5.5 V
100
—
—
Except the above
X1
—
15.26
or
13.02
—
µs
OSC1
—
—
6
ns
—
—
10
VCC = 2.7 V to 5.5 V
—
—
25
Except the above
X1
—
—
55.0
ns
OSC1
—
—
6
ns
—
—
10
VCC = 2.7 V to 5.5 V
—
—
25
Except the above
X1
—
—
55.0
ns
RES
10
—
—
tcyc
Figure 14.2
IRQ0, IRQ1,
2
IRQAEC,
WKP0 to WKP7
—
—
tcyc
tsubcyc
Figure 14.3
AEVL, AEVH
—
—
tOSC
IRQ0 to IRQ1,
2
IRQAEC,
WKP0 to WKP7
—
—
tcyc
tsubcyc
AEVL, AEVH
—
—
tOSC
External clock high
tCPH
X1, X2
OSC1
width
External clock low
tCPL
width
External clock rise
tCPr
time
External clock fall
tCPf
time
Pin RES low width
tREL
Input pin high width tIH
Input pin low width
tIL
0.5
0.5
VCC = 2.7 V to 5.5 V
ns
VCC = 4.5 V to 5.5 V Figure 14.1
Figure 14.1
VCC = 4.5 V to 5.5 V Figure 14.1
Figure 14.1
VCC = 4.5 V to 5.5 V Figure 14.1
Figure 14.1
VCC = 4.5 V to 5.5 V Figure 14.1
Figure 14.1
Figure 14.3
Notes: 1. Selected with SA1 and SA0 of system clock control register 2 (SYSCR2).
2. The figure in parentheses applies when an external clock is used.
3. After powering on, hold VCC at 2.2 V to 5.5 V until the chip's oscillation settling time has
elapsed.
323
Table 14.4 Serial Interface (SCI3) Timing
VCC = 1.8 V to 5.5 V, AVCC = 1.8 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = –20°C to +75°C
(including subactive mode) unless otherwise indicated.
Values
Item
Input clock
Asynchronous
cycle
Synchronous
Reference
Symbol
Min
Typ
Max
Unit
tscyc
4
—
—
tcyc or
6
—
—
tsubcyc
Test Conditions
Figure
Figure 14.4
Input clock pulse width
tSCKW
0.4
—
0.6
tscyc
Transmit data delay time
tTXD
—
—
1
tcyc or
VCC = 4.0 V to 5.5 V Figure 14.5
—
—
1
tsubcyc
Except the above
200.0
—
—
ns
VCC = 4.0 V to 5.5 V Figure 14.5
400.0
—
—
200.0
—
—
400.0
—
—
(synchronous)
Receive data setup time
tRXS
(synchronous)
Receive data hold time
(synchronous)
324
tRXH
Figure 14.4
Except the above
ns
Figure 14.5
VCC = 4.0 V to 5.5 V Figure 14.5
Except the above
Figure 14.5
14.2.4
A/D Converter Characteristics
Table 14.5 shows the A/D converter characteristics of the H8/3802.
Table 14.5 A/D Converter Characteristics
VCC = 1.8 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = –20°C to +75°C unless otherwise indicated.
Applicable
Item
Symbol Pins
Values
Reference
Min
Typ
Max
Unit
Analog power AV CC
supply voltage
AV CC
1.8
—
5.5
V
Analog input
voltage
AV IN
AN0 to AN3
– 0.3
—
AV CC + 0.3
V
Analog power
AI OPE
AV CC
—
—
1.5
mA
AV CC
—
600
—
µA
supply current AI STOP1
Test Condition
Figure
*1
AV CC = 5 V
*2
Reference
value
*3
AI STOP2
AV CC
—
—
5
µA
Analog input
capacitance
CAIN
AN0 to AN3
—
—
15.0
pF
Allowable
signal source
impedance
RAIN
—
—
10.0
kΩ
Resolution
(data length)
—
—
10
bit
Nonlinearity
error
—
—
±2.5
LSB
—
—
±5.5
AV CC = 2.0 V to 5.5 V
VCC = 2.0 V to 5.5 V
—
—
±7.5
Except the above
—
—
±0.5
Quantization
error
AV CC = 2.7 V to 5.5 V
VCC = 2.7 V to 5.5 V
*4
LSB
325
Applicable
Item
Absolute
accuracy
Conversion
time
Symbol Pins
Values
Reference
Min
Typ
Max
Unit
Test Condition
—
—
±3.0
LSB
AV CC = 2.7 V to 5.5 V
VCC = 2.7 V to 5.5 V
—
—
±6.0
AV CC = 2.0 V to 5.5 V
VCC = 2.0 V to 5.5 V
—
—
±8.0
Except the above
12.4
—
124
62
—
124
µs
Figure
*4
AV CC = 2.7 V to 5.5 V
VCC = 2.7 V to 5.5 V
Except the above
Notes: 1. Set AVCC = VCC when the A/D converter is not used.
2. AI STOP1 is the current in active and sleep modes while the A/D converter is idle.
3. AI STOP2 is the current at reset and in standby, watch, subactive, and subsleep modes
while the A/D converter is idle.
4. Conversion time 62 µs
326
14.2.5
LCD Characteristics
Table 14.6 shows the LCD characteristics.
Table 14.6 LCD Characteristics
VCC = 1.8 V to 5.5 V, AVCC = 1.8 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = –20°C to +75°C
(including subactive mode) unless otherwise specified.
Applicable Test
Values
Reference
Item
Symbol Pins
Conditions
Segment driver
drop voltage
VDS
SEG1 to
SEG25
I D = 2 µA
—
V1 = 2.7 V to 5.5 V
—
0.6
V
*1
Common driver
drop voltage
VDC
COM1 to
COM4
I D = 2 µA
—
V1 = 2.7 V to 5.5 V
—
0.3
V
*1
Between V 1 and
VSS
0.5
3.0
9.0
MΩ
2.2
—
5.5
V
LCD power supply RLCD
split-resistance
Liquid crystal
display voltage
VLCD
V1
Min Typ Max Unit Figure
*2
Notes: 1. The voltage drop from power supply pins V1, V2, V3, and VSS to each segment pin or
common pin.
2. When the liquid crystal display voltage is supplied from an external power source,
ensure that the following relationship is maintained: V CC ≥ V1 ≥ V2 ≥ V3 ≥ VSS.
327
14.3
Operation Timing
Figures 14.1 to 14.5 show timing diagrams.
t OSC , tw
VIH
OSC1
x1
VIL
t CPH
t CPL
t CPr
t CPf
Figure 14.1 Clock Input Timing
RES
VIL
tREL
Figure 14.2 RES Low Width
IRQ0, IRQ1,
WKP0 to WKP7,
IRQAEC,
AEVL, AEVH
VIH
VIL
t IL
t IH
Figure 14.3 Input Timing
328
t SCKW
SCK 32
t scyc
Figure 14.4 SCK3 Input Clock Timing
t scyc
VIH or VOH *
SCK 32 VIL or VOL *
t TXD
*
VOH
TXD32
(transmit data)
VOL *
t RXS
t RXH
RXD32
(receive data)
Note: * Output timing reference levels
Output high
VOH = 1/2Vcc + 0.2 V
Output low
VOL = 0.8 V
Load conditions are shown in figure 14.6.
Figure 14.5 SCI3 Synchronous Mode Input/Output Timing
329
14.4
Output Load Circuit
VCC
2.4 kΩ
Output pin
12 k Ω
30 pF
Figure 14.6 Output Load Condition
14.5
Resonator Equivalent Circuit
LS
CS
RS
OSC1
OSC2
CO
Crystal Resonator Parameter
Ceramic Resonator Parameters
Frequency
(MHz)
4.193
Frequency
(MHz)
4
RS (max)
100 Ω
RS (max)
8.8 Ω
CO (max)
16 pF
CO (max)
36 pF
Figure 14.7 Resonator Equivalent Circuit
330
14.6
Usage Note
The ZTAT and mask ROM versions both satisfy the electrical characteristics shown in this
manual, but actual electrical characteristic values, operating margins, noise margins, and other
properties may vary due to differences in manufacturing process, on-chip ROM, layout patterns,
and so on.
When system evaluation testing is carried out using the ZTAT version, the same evaluation testing
should also be conducted for the mask ROM version when changing over to that version.
331
332
Appendix A CPU Instruction Set
A.1
Instructions
Operation Notation
Rd8/16
General register (destination) (8 or 16 bits)
Rs8/16
General register (source) (8 or 16 bits)
Rn8/16
General register (8 or 16 bits)
CCR
Condition code register
N
N (negative) flag in CCR
Z
Z (zero) flag in CCR
V
V (overflow) flag in CCR
C
C (carry) flag in CCR
PC
Program counter
SP
Stack pointer
#xx: 3/8/16
Immediate data (3, 8, or 16 bits)
d: 8/16
Displacement (8 or 16 bits)
@aa: 8/16
Absolute address (8 or 16 bits)
+
Addition
–
Subtraction
×
Multiplication
÷
Division
∧
Logical AND
∨
Logical OR
⊕
Exclusive logical OR
→
Move
—
Logical complement
Condition Code Notation
↔
Symbol
Modified according to the instruction result
*
Not fixed (value not guaranteed)
0
Always cleared to 0
—
Not affected by the instruction execution result
333
Table A.1 lists the H8/300L CPU instruction set.
Table A.1
Instruction Set
MOV.B @aa:8, Rd
B @aa:8 → Rd8
MOV.B @aa:16, Rd
B @aa:16 → Rd8
MOV.B Rs, @Rd
B Rs8 → @Rd16
MOV.B Rs, @(d:16, Rd)
B Rs8 → @(d:16, Rd16)
MOV.B Rs, @–Rd
B Rd16–1 → Rd16
Rs8 → @Rd16
MOV.B Rs, @aa:8
B Rs8 → @aa:8
MOV.B Rs, @aa:16
B Rs8 → @aa:16
MOV.W #xx:16, Rd
W #xx:16 → Rd
MOV.W Rs, Rd
W Rs16 → Rd16
MOV.W @Rs, Rd
W @Rs16 → Rd16
MOV.W @aa:16, Rd
W @aa:16 → Rd16
W Rs16 → @Rd16
4
— —
2
4
2
— —
— —
— —
4
— —
2
— —
2
4
4
— —
— —
— —
2
— —
2
— —
4
— —
2
— —
4
2
— —
— —
— —
0 — 2
0 — 4
0 — 6
0 — 6
0 — 4
0 — 6
0 — 4
0 — 6
0 — 6
0 — 4
0 — 6
0 — 4
0 — 2
0 — 4
0 — 6
0 — 6
0 — 6
0 — 4
0 — 6
MOV.W Rs, @–Rd
W Rd16–2 → Rd16
Rs16 → @Rd16
MOV.W Rs, @aa:16
W Rs16 → @aa:16
POP Rd
W @SP → Rd16
SP+2 → SP
2
— —
↔ ↔
↔ ↔
4
No. of States
Implied
— —
2
0 — 2
0 — 6
PUSH Rs
W SP–2 → SP
Rs16 → @SP
2
— —
↔
↔
MOV.W Rs, @(d:16, Rd) W Rs16 → @(d:16, Rd16)
@@aa
— —
W @Rs16 → Rd16
Rs16+2 → Rs16
MOV.W Rs, @Rd
@(d:8, PC)
— —
2
MOV.W @(d:16, Rs), Rd W @(d:16, Rs16) → Rd16
MOV.W @Rs+, Rd
@aa: 8/16
2
↔ ↔ ↔ ↔ ↔
↔ ↔ ↔ ↔ ↔
B @(d:16, Rs16)→ Rd8
B @Rs16 → Rd8
Rs16+1 → Rs16
H N Z V C
↔ ↔ ↔ ↔ ↔
↔ ↔ ↔ ↔ ↔
MOV.B @(d:16, Rs), Rd
MOV.B @Rs+, Rd
I
— —
↔ ↔ ↔ ↔ ↔ ↔ ↔
↔ ↔ ↔ ↔ ↔ ↔ ↔
B Rs8 → Rd8
B @Rs16 → Rd8
Condition Code
↔ ↔ ↔ ↔
↔ ↔ ↔ ↔
MOV.B Rs, Rd
MOV.B @Rs, Rd
@–Rn/@Rn+
2
@(d:16, Rn)
#xx: 8/16
B #xx:8 → Rd8
@Rn
Operation
MOV.B #xx:8, Rd
Rn
Mnemonic
Operand Size
Addressing Mode/
Instruction Length (bytes)
0 — 6
334
2
— —
4
— —
0 — 6
0 — 6
W Rd16+Rs16 → Rd16
ADDX.B #xx:8, Rd
B Rd8+#xx:8 +C → Rd8
ADDX.B Rs, Rd
B Rd8+Rs8 +C → Rd8
2
2
—
— (1)
—
2
No. of States
Implied
@@aa
@(d:8, PC)
@aa: 8/16
@–Rn/@Rn+
@(d:16, Rn)
@Rn
—
2
—
(2)
(2)
↔ ↔ ↔ ↔ ↔
ADD.W Rs, Rd
2
I H N Z V C
↔ ↔ ↔
↔ ↔ ↔ ↔ ↔
B Rd8+#xx:8 → Rd8
B Rd8+Rs8 → Rd8
Condition Code
↔ ↔
↔ ↔
↔ ↔ ↔ ↔ ↔
ADD.B #xx:8, Rd
ADD.B Rs, Rd
Rn
Operation
#xx: 8/16
Mnemonic
Operand Size
Addressing Mode/
Instruction Length (bytes)
2
2
2
2
2
2
— — — — — — 2
2
— — — — — — 2
INC.B Rd
B Rd8+1 → Rd8
2
— —
DAA.B Rd
B Rd8 decimal adjust → Rd8
2
— *
B Rd8–Rs8 → Rd8
2
—
W Rd16–Rs16 → Rd16
2
— (1)
2
—
SUBX.B #xx:8, Rd
B Rd8–#xx:8 –C → Rd8
SUBX.B Rs, Rd
B Rd8–Rs8 –C → Rd8
2
—
— 2
* (3) 2
(2)
(2)
↔ ↔ ↔ ↔
SUB.B Rs, Rd
SUB.W Rs, Rd
↔ ↔ ↔ ↔
↔
↔ ↔ ↔ ↔
W Rd16+1 → Rd16
W Rd16+2 → Rd16
↔
↔ ↔
↔ ↔ ↔ ↔ ↔ ↔
ADDS.W #1, Rd
ADDS.W #2, Rd
2
2
2
2
2
— — — — — — 2
2
— — — — — — 2
DEC.B Rd
B Rd8–1 → Rd8
2
— —
— 2
DAS.B Rd
B Rd8 decimal adjust → Rd8
2
— *
* — 2
2
—
NEG.B Rd
B 0–Rd → Rd
CMP.B #xx:8, Rd
B Rd8–#xx:8
2
—
CMP.B Rs, Rd
B Rd8–Rs8
2
—
CMP.W Rs, Rd
W Rd16–Rs16
2
— (1)
↔ ↔ ↔ ↔
W Rd16–1 → Rd16
W Rd16–2 → Rd16
↔ ↔ ↔
↔ ↔ ↔ ↔ ↔ ↔
↔ ↔ ↔ ↔ ↔ ↔
↔
↔ ↔ ↔ ↔
SUBS.W #1, Rd
SUBS.W #2, Rd
2
2
2
2
335
↔
2
0
↔
2
0
↔
2
0
↔
2
0
↔
2
0
↔
2
0 — 2
0 — 2
0 — 2
0 — 2
0 — 2
Implied
XOR.B Rs, Rd
B Rd8⊕Rs8 → Rd8
2
— —
NOT.B Rd
B Rd → Rd
2
— —
SHAL.B Rd
B
2
— —
2
— —
2
— —
2
— — 0
2
— —
2
— —
C
0
b7
SHAR.B Rd
B
B
C
SHLR.B Rd
B
0
B
b0
0
C
b7
ROTXL.B Rd
b0
C
b7
b0
C
b7
ROTXR.B Rd
336
b0
B
b7
0 — 2
0 — 2
b0
b7
SHLL.B Rd
No. of States
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔
↔
— —
— —
↔
↔
2
2
↔
↔
B Rd8∨Rs8 → Rd8
B Rd8⊕#xx:8 → Rd8
— —
— —
↔
2
OR.B Rs, Rd
H N Z V C
— —
2
XOR.B #xx:8, Rd
I
↔
↔
B Rd8∧Rs8 → Rd8
B Rd8∨#xx:8 → Rd8
Condition Code
↔
↔
AND.B Rs, Rd
OR.B #xx:8, Rd
2
@@aa
B Rd8∧#xx:8 → Rd8
@(d:8, PC)
AND.B #xx:8, Rd
@aa: 8/16
— — (5) (6) — — 14
@–Rn/@Rn+
— — — — — — 14
2
@(d:16, Rn)
2
B Rd16÷Rs8 → Rd16
(RdH: remainder,
RdL: quotient)
@Rn
B Rd8 × Rs8 → Rd16
DIVXU.B Rs, Rd
Operation
Rn
MULXU.B Rs, Rd
#xx: 8/16
Mnemonic
Operand Size
Addressing Mode/
Instruction Length (bytes)
b0
C
BSET #xx:3, Rd
No. of States
↔
Implied
@@aa
@(d:8, PC)
@aa: 8/16
@–Rn/@Rn+
@(d:16, Rn)
— —
0
2
— —
0
2
2
— — — — — — 2
b0
B
C
b7
2
↔
ROTR.B Rd
H N Z V C
2
↔
↔
b7
Condition Code
I
↔
↔
C
@Rn
B
Operation
Rn
ROTL.B Rd
#xx: 8/16
Mnemonic
Operand Size
Addressing Mode/
Instruction Length (bytes)
b0
B (#xx:3 of Rd8) ← 1
BSET #xx:3, @Rd
B (#xx:3 of @Rd16) ← 1
BSET #xx:3, @aa:8
B (#xx:3 of @aa:8) ← 1
BSET Rn, Rd
B (Rn8 of Rd8) ← 1
BSET Rn, @Rd
B (Rn8 of @Rd16) ← 1
BSET Rn, @aa:8
B (Rn8 of @aa:8) ← 1
BCLR #xx:3, Rd
B (#xx:3 of Rd8) ← 0
BCLR #xx:3, @Rd
B (#xx:3 of @Rd16) ← 0
BCLR #xx:3, @aa:8
B (#xx:3 of @aa:8) ← 0
BCLR Rn, Rd
B (Rn8 of Rd8) ← 0
BCLR Rn, @Rd
B (Rn8 of @Rd16) ← 0
BCLR Rn, @aa:8
B (Rn8 of @aa:8) ← 0
BNOT #xx:3, Rd
B (#xx:3 of Rd8) ←
(#xx:3 of Rd8)
BNOT #xx:3, @Rd
B (#xx:3 of @Rd16) ←
(#xx:3 of @Rd16)
BNOT #xx:3, @aa:8
B (#xx:3 of @aa:8) ←
(#xx:3 of @aa:8)
BNOT Rn, Rd
B (Rn8 of Rd8) ←
(Rn8 of Rd8)
BNOT Rn, @Rd
B (Rn8 of @Rd16) ←
(Rn8 of @Rd16)
BNOT Rn, @aa:8
B (Rn8 of @aa:8) ←
(Rn8 of @aa:8)
4
— — — — — — 8
4
2
— — — — — — 8
— — — — — — 2
4
— — — — — — 8
4
2
— — — — — — 8
— — — — — — 2
4
— — — — — — 8
4
2
— — — — — — 8
— — — — — — 2
4
— — — — — — 8
4
2
— — — — — — 8
— — — — — — 2
4
— — — — — — 8
4
2
— — — — — — 8
— — — — — — 2
4
— — — — — — 8
4
— — — — — — 8
337
B (Rn8 of Rd8) → Z
B (Rn8 of @Rd16) → Z
BTST Rn, @aa:8
B (Rn8 of @aa:8) → Z
BLD #xx:3, Rd
B (#xx:3 of Rd8) → C
BLD #xx:3, @Rd
B (#xx:3 of @Rd16) → C
BLD #xx:3, @aa:8
B (#xx:3 of @aa:8) → C
BILD #xx:3, Rd
B (#xx:3 of Rd8) → C
BILD #xx:3, @Rd
B (#xx:3 of @Rd16) → C
BILD #xx:3, @aa:8
B (#xx:3 of @aa:8) → C
BST #xx:3, Rd
B C → (#xx:3 of Rd8)
BST #xx:3, @Rd
B C → (#xx:3 of @Rd16)
BST #xx:3, @aa:8
B C → (#xx:3 of @aa:8)
BIST #xx:3, Rd
B C → (#xx:3 of Rd8)
BIST #xx:3, @Rd
B C → (#xx:3 of @Rd16)
BIST #xx:3, @aa:8
B C → (#xx:3 of @aa:8)
BAND #xx:3, Rd
B C∧(#xx:3 of Rd8) → C
BAND #xx:3, @Rd
B C∧(#xx:3 of @Rd16) → C
BAND #xx:3, @aa:8
B C∧(#xx:3 of @aa:8) → C
BIAND #xx:3, Rd
B C∧(#xx:3 of Rd8) → C
BIAND #xx:3, @Rd
B C∧(#xx:3 of @Rd16) → C
BIAND #xx:3, @aa:8
B C∧(#xx:3 of @aa:8) → C
BOR #xx:3, Rd
B C∨(#xx:3 of Rd8) → C
BOR #xx:3, @Rd
B C∨(#xx:3 of @Rd16) → C
BOR #xx:3, @aa:8
B C∨(#xx:3 of @aa:8) → C
BIOR #xx:3, Rd
B C∨(#xx:3 of Rd8) → C
BIOR #xx:3, @Rd
B C∨(#xx:3 of @Rd16) → C
338
4
— — —
4
2
— — —
— — —
4
— — —
4
2
— — —
— — 2
— — 6
— — 6
— — 2
— — 6
— — 6
— — — — —
4
— — — — —
4
2
— — — — —
— — — — —
4
— — — — —
4
2
No. of States
Implied
@@aa
@(d:8, PC)
@aa: 8/16
@–Rn/@Rn+
H N Z V C
— — — — —
↔ ↔ ↔ ↔ ↔ ↔
BTST Rn, Rd
BTST Rn, @Rd
I
— — —
2
6
6
2
6
6
— — — — — — 2
4
— — — — — — 8
4
2
— — — — — — 8
— — — — — — 2
4
— — — — — — 8
4
2
— — — — — — 8
— — — — —
4
— — — — —
4
2
— — — — —
— — — — —
4
— — — — —
4
2
— — — — —
— — — — —
4
— — — — —
4
2
— — — — —
— — — — —
4
— — — — —
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔
B (#xx:3 of @Rd16) → Z
B (#xx:3 of @aa:8) → Z
2
Condition Code
↔ ↔ ↔ ↔ ↔ ↔
BTST #xx:3, @Rd
BTST #xx:3, @aa:8
@(d:16, Rn)
Operation
@Rn
B (#xx:3 of Rd8) → Z
Rn
BTST #xx:3, Rd
#xx: 8/16
Mnemonic
Operand Size
Addressing Mode/
Instruction Length (bytes)
2
6
6
2
6
6
2
6
6
2
6
B C∨(#xx:3 of @aa:8) → C
B C⊕(#xx:3 of Rd8) → C
BXOR #xx:3, @Rd
B C⊕(#xx:3 of @Rd16) → C
BXOR #xx:3, @aa:8
B C⊕(#xx:3 of @aa:8) → C
BIXOR #xx:3, Rd
B C⊕(#xx:3 of Rd8) → C
BIXOR #xx:3, @Rd
B C⊕(#xx:3 of @Rd16) → C
BIXOR #xx:3, @aa:8
B C⊕(#xx:3 of @aa:8) → C
H N Z V C
— — — — —
2
— — — — —
4
— — — — —
4
— — — — —
2
— — — — —
4
— — — — —
4
No. of States
Implied
@@aa
@(d:8, PC)
@aa: 8/16
@–Rn/@Rn+
@(d:16, Rn)
@Rn
4
Condition Code
I
— — — — —
↔ ↔ ↔ ↔ ↔ ↔ ↔
BIOR #xx:3, @aa:8
BXOR #xx:3, Rd
Rn
Branching
Condition
Operation
#xx: 8/16
Mnemonic
Operand Size
Addressing Mode/
Instruction Length (bytes)
6
2
6
6
2
6
6
BRA d:8 (BT d:8)
— PC ← PC+d:8
2
— — — — — — 4
BRN d:8 (BF d:8)
— PC ← PC+2
2
— — — — — — 4
BHI d:8
— If
condition
is true
— then
— PC ←
PC+d:8
— else next;
—
BLS d:8
BCC d:8 (BHS d:8)
BCS d:8 (BLO d:8)
BNE d:8
BEQ d:8
—
C∨Z=0
2
— — — — — — 4
C∨Z=1
2
— — — — — — 4
C=0
2
— — — — — — 4
C=1
2
— — — — — — 4
Z=0
2
— — — — — — 4
Z=1
2
— — — — — — 4
BVC d:8
—
V=0
2
— — — — — — 4
BVS d:8
—
V=1
2
— — — — — — 4
BPL d:8
—
N=0
2
— — — — — — 4
BMI d:8
—
N=1
2
— — — — — — 4
BGE d:8
—
N⊕V = 0
2
— — — — — — 4
BLT d:8
—
N⊕V = 1
2
— — — — — — 4
BGT d:8
—
Z ∨ (N⊕V) = 0
2
— — — — — — 4
BLE d:8
—
Z ∨ (N⊕V) = 1
2
— — — — — — 4
JMP @Rn
— PC ← Rn16
JMP @aa:16
— PC ← aa:16
JMP @@aa:8
— PC ← @aa:8
BSR d:8
— SP–2 → SP
PC → @SP
PC ← PC+d:8
2
— — — — — — 4
4
— — — — — — 6
2
2
— — — — — — 8
— — — — — — 6
339
Condition Code
I
H N Z V C
No. of States
Implied
@@aa
@(d:8, PC)
@aa: 8/16
@–Rn/@Rn+
@(d:16, Rn)
@Rn
Rn
Operation
#xx: 8/16
Mnemonic
Operand Size
Addressing Mode/
Instruction Length (bytes)
JSR @Rn
— SP–2 → SP
PC → @SP
PC ← Rn16
JSR @aa:16
— SP–2 → SP
PC → @SP
PC ← aa:16
JSR @@aa:8
— SP–2 → SP
PC → @SP
PC ← @aa:8
RTS
— PC ← @SP
SP+2 → SP
2 — — — — — — 8
RTE
— CCR ← @SP
SP+2 → SP
PC ← @SP
SP+2 → SP
2
SLEEP
— Transit to sleep mode.
2 — — — — — — 2
LDC #xx:8, CCR
B #xx:8 → CCR
LDC Rs, CCR
B Rs8 → CCR
2
— — — — — — 6
4
— — — — — — 8
10
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
— — — — — — 8
2
2
↔
↔
↔
↔
↔
↔
2
2
2
— — — — — — 2
STC CCR, Rd
B CCR → Rd8
ANDC #xx:8, CCR
B CCR∧#xx:8 → CCR
2
↔
↔
↔
↔
↔
↔
2
ORC #xx:8, CCR
B CCR∨#xx:8 → CCR
2
↔
↔
↔
↔
↔
↔
2
XORC #xx:8, CCR
B CCR⊕#xx:8 → CCR
2
↔
↔
↔
↔
↔
↔
2
2
NOP
— PC ← PC+2
2 — — — — — — 2
EEPMOV
— if R4L≠0
Repeat @R5 → @R6
R5+1 → R5
R6+1 → R6
R4L–1 → R4L
Until R4L=0
else next;
4 — — — — — — (4)
Notes: (1) Set to 1 when there is a carry or borrow from bit 11; otherwise cleared to 0.
(2) If the result is zero, the previous value of the flag is retained; otherwise the flag is cleared to 0.
(3) Set to 1 if decimal adjustment produces a carry; otherwise retains value prior to arithmetic operation.
(4) The number of states required for execution is 4n + 9 (n = value of R4L).
(5) Set to 1 if the divisor is negative; otherwise cleared to 0.
(6) Set to 1 if the divisor is zero; otherwise cleared to 0.
340
A.2
Operation Code Map
Table A.2 is an operation code map. It shows the operation codes contained in the first byte of the
instruction code (bits 15 to 8 of the first instruction word).
Instruction when first bit of byte 2 (bit 7 of first instruction word) is 0.
Instruction when first bit of byte 2 (bit 7 of first instruction word) is 1.
341
XOR
AND
MOV
D
E
F
Note: * The PUSH and POP instructions are identical in machine language to MOV instructions.
OR
C
BILD
8
BVC
SUBX
BIAND
BAND
BIST
BLD
BST
BEQ
MOV
NEG
NOT
LDC
7
B
BIXOR
BXOR
RTE
BNE
AND
ANDC
6
CMP
BIOR
BOR
BSR
BCS
XOR
XORC
5
A
BTST
RTS
BCC
OR
ORC
4
ADDX
BCLR
BLS
ROTR
ROTXR
LDC
3
9
BNOT
BHI
ROTL
ROTXL
STC
2
ADD
BSET
DIVXU
BRN
SHAR
SHLR
SLEEP
1
8
7
6
MULXU
5
SHAL
SHLL
NOP
0
BRA
Low
4
3
2
1
0
High
Table A.2 Operation Code Map
SUB
ADD
MOV
BVS
9
JMP
BPL
DEC
INC
A
C
CMP
MOV
BLT
D
JSR
BGT
SUBX
ADDX
E
Bit-manipulation instructions
BGE
MOV *
EEPMOV
BMI
SUBS
ADDS
B
;;;;
342
BLE
DAS
DAA
F
A.3
Number of Execution States
The tables here can be used to calculate the number of states required for instruction execution.
Table A.4 indicates the number of states required for each cycle (instruction fetch, read/write,
etc.), and table A.3 indicates the number of cycles of each type occurring in each instruction. The
total number of states required for execution of an instruction can be calculated from these two
tables as follows:
Execution states = I × SI + J × SJ + K × SK + L × SL + M × SM + N × SN
Examples: When instruction is fetched from on-chip ROM, and an on-chip RAM is accessed.
BSET #0, @FF00
From table A.4:
I = L = 2, J = K = M = N= 0
From table A.3:
S I = 2, SL = 2
Number of states required for execution = 2 × 2 + 2 × 2 = 8
When instruction is fetched from on-chip ROM, branch address is read from on-chip ROM, and
on-chip RAM is used for stack area.
JSR @@ 30
From table A.4:
I = 2, J = K = 1, L = M = N = 0
From table A.3:
S I = SJ = SK = 2
Number of states required for execution = 2 × 2 + 1 × 2+ 1 × 2 = 8
343
Table A.3
Number of Cycles in Each Instruction
Execution Status
Access Location
(instruction cycle)
On-Chip Memory
On-Chip Peripheral Module
2
—
Instruction fetch
SI
Branch address read
SJ
Stack operation
SK
Byte data access
SL
2 or 3*
Word data access
SM
—
Internal operation
SN
1
Note: * Depends on which on-chip module is accessed. See 2.9.1, Notes on Data Access for
details.
344
Table A.4
Instruction
ADD
ADDS
ADDX
AND
ANDC
BAND
Bcc
BCLR
BIAND
Number of Cycles in Each Instruction
Mnemonic
Instruction
Fetch
I
ADD.B #xx:8, Rd
1
ADD.B Rs, Rd
1
ADD.W Rs, Rd
1
ADDS.W #1, Rd
1
ADDS.W #2, Rd
1
ADDX.B #xx:8, Rd
1
ADDX.B Rs, Rd
1
AND.B #xx:8, Rd
1
AND.B Rs, Rd
1
ANDC #xx:8, CCR
1
Branch
Stack
Addr. Read Operation
J
K
Byte Data
Access
L
BAND #xx:3, Rd
1
BAND #xx:3, @Rd
2
1
BAND #xx:3, @aa:8
2
1
BRA d:8 (BT d:8)
2
BRN d:8 (BF d:8)
2
BHI d:8
2
BLS d:8
2
BCC d:8 (BHS d:8)
2
BCS d:8 (BLO d:8)
2
BNE d:8
2
BEQ d:8
2
BVC d:8
2
BVS d:8
2
BPL d:8
2
BMI d:8
2
BGE d:8
2
BLT d:8
2
BGT d:8
2
BLE d:8
2
BCLR #xx:3, Rd
1
BCLR #xx:3, @Rd
2
2
BCLR #xx:3, @aa:8
2
2
BCLR Rn, Rd
1
BCLR Rn, @Rd
2
2
BCLR Rn, @aa:8
2
2
BIAND #xx:3, Rd
1
BIAND #xx:3, @Rd
2
1
BIAND #xx:3, @aa:8
2
1
Word Data
Access
M
Internal
Operation
N
345
Instruction
Fetch
I
Branch
Stack
Addr. Read Operation
J
K
Byte Data
Access
L
Instruction
Mnemonic
BILD
BILD #xx:3, Rd
1
BILD #xx:3, @Rd
2
1
BILD #xx:3, @aa:8
2
1
BIOR #xx:3, Rd
1
BIOR #xx:3, @Rd
2
1
BIOR #xx:3, @aa:8
2
1
BIST #xx:3, Rd
1
BIST #xx:3, @Rd
2
2
BIST #xx:3, @aa:8
2
2
BIXOR #xx:3, Rd
1
BIOR
BIST
BIXOR
BLD
BNOT
BOR
BSET
BIXOR #xx:3, @Rd
2
1
BIXOR #xx:3, @aa:8
2
1
BLD #xx:3, Rd
1
BLD #xx:3, @Rd
2
1
BLD #xx:3, @aa:8
2
1
BNOT #xx:3, Rd
1
BNOT #xx:3, @Rd
2
2
BNOT #xx:3, @aa:8
2
2
BNOT Rn, Rd
1
BNOT Rn, @Rd
2
2
BNOT Rn, @aa:8
2
2
BOR #xx:3, Rd
1
BOR #xx:3, @Rd
2
1
BOR #xx:3, @aa:8
2
1
BSET #xx:3, Rd
1
BSET #xx:3, @Rd
2
2
BSET #xx:3, @aa:8
2
2
BSET Rn, Rd
1
BSET Rn, @Rd
2
2
BSET Rn, @aa:8
2
2
BSR
BSR d:8
2
BST
BST #xx:3, Rd
1
BST #xx:3, @Rd
2
2
BST #xx:3, @aa:8
2
2
BTST #xx:3, Rd
1
BTST
346
1
BTST #xx:3, @Rd
2
1
BTST #xx:3, @aa:8
2
1
BTST Rn, Rd
1
BTST Rn, @Rd
2
1
Word Data
Access
M
Internal
Operation
N
Instruction
Mnemonic
Instruction
Fetch
I
BTST
BTST Rn, @aa:8
2
BXOR
BXOR #xx:3, Rd
1
Branch
Stack
Addr. Read Operation
J
K
Byte Data
Access
L
2
1
BXOR #xx:3, @aa:8
2
1
CMP. B #xx:8, Rd
1
CMP. B Rs, Rd
1
CMP.W Rs, Rd
1
DAA
DAA.B Rd
1
DAS
DAS.B Rd
1
DEC
DEC.B Rd
1
DIVXU
DIVXU.B Rs, Rd
1
EEPMOV
EEPMOV
2
INC
INC.B Rd
1
JMP
JSR
LDC
MOV
JMP @Rn
2
JMP @aa:16
2
JMP @@aa:8
2
JSR @Rn
2
JSR @aa:16
2
JSR @@aa:8
2
LDC #xx:8, CCR
1
LDC Rs, CCR
1
MOV.B #xx:8, Rd
1
MOV.B Rs, Rd
1
Internal
Operation
N
1
BXOR #xx:3, @Rd
CMP
Word Data
Access
M
12
2n+2*
1
2
1
2
1
1
1
2
1
MOV.B @Rs, Rd
1
1
MOV.B @(d:16, Rs), Rd
2
1
MOV.B @Rs+, Rd
1
1
MOV.B @aa:8, Rd
1
1
MOV.B @aa:16, Rd
2
1
MOV.B Rs, @Rd
1
1
MOV.B Rs, @(d:16, Rd)
2
1
MOV.B Rs, @–Rd
1
1
MOV.B Rs, @aa:8
1
1
MOV.B Rs, @aa:16
2
1
MOV.W #xx:16, Rd
2
2
2
MOV.W Rs, Rd
1
MOV.W @Rs, Rd
1
1
MOV.W @(d:16, Rs), Rd
2
1
MOV.W @Rs+, Rd
1
1
MOV.W @aa:16, Rd
2
1
2
Note: * n: Initial value in R4L. The source and destination operands are accessed n + 1 times each.
347
Instruction
Fetch
I
Branch
Stack
Addr. Read Operation
J
K
Byte Data
Access
L
Word Data
Access
M
Internal
Operation
N
Instruction
Mnemonic
MOV
MOV.W Rs, @Rd
1
1
MOV.W Rs, @(d:16, Rd)
2
1
MOV.W Rs, @–Rd
1
1
MOV.W Rs, @aa:16
2
1
MULXU
MULXU.B Rs, Rd
1
NEG
NEG.B Rd
1
NOP
NOP
1
NOT
NOT.B Rd
1
OR
OR.B #xx:8, Rd
1
OR.B Rs, Rd
1
ORC
ORC #xx:8, CCR
1
ROTL
ROTL.B Rd
1
ROTR
ROTR.B Rd
1
ROTXL
ROTXL.B Rd
1
ROTXR
ROTXR.B Rd
1
RTE
RTE
2
2
2
RTS
RTS
2
1
2
SHAL
SHAL.B Rd
1
SHAR
SHAR.B Rd
1
SHLL
SHLL.B Rd
1
SHLR
SHLR.B Rd
1
SLEEP
SLEEP
1
STC
STC CCR, Rd
1
SUB
SUBS
SUB.B Rs, Rd
1
SUB.W Rs, Rd
1
SUBS.W #1, Rd
1
2
12
SUBS.W #2, Rd
1
POP
POP Rd
1
1
2
PUSH
PUSH Rs
1
1
2
SUBX
XOR
XORC
348
SUBX.B #xx:8, Rd
1
SUBX.B Rs, Rd
1
XOR.B #xx:8, Rd
1
XOR.B Rs, Rd
1
XORC #xx:8, CCR
1
Appendix B Internal I/O Registers
B.1
Addresses
Lower
Register
Address Name
Bit Names
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
Name
H'80
H'81
H'82
H'83
H'84
H'85
H'86
H'87
H'88
H'89
H'8A
H'8B
H'8C
H'8D
ECPWCRH ECPWCRH7 ECPWCRH6 ECPWCRH5 ECPWCRH4 ECPWCRH3 ECPWCRH2 ECPWCRH1 ECPWCRH0 Asynchronous
event counter
ECPWCRL ECPWCRL7 ECPWCRL6 ECPWCRL5 ECPWCRL4 ECPWCRL3 ECPWCRL2 ECPWCRL1 ECPWCRL0
H'8E
ECPWDRH ECPWDRH7 ECPWDRH6 ECPWDRH5 ECPWDRH4 ECPWDRH3 ECPWDRH2 ECPWDRH1 ECPWDRH0
H'8F
ECPWDRL
ECPWDRL7 ECPWDRL6 ECPWDRL5 ECPWDRL4 ECPWDRL3 ECPWDRL2 ECPWDRL1 ECPWDRL0
H'90
WEGR
WKEGS7
WKEGS6
WKEGS5
WKEGS4
WKEGS3
WKEGS2
WKEGS1
WKEGS0
System control
H'91
SPCR
—
—
SPC32
—
SCINV3
SCINV2
—
—
SCI
H'92
AEGSR
AHEGS1
AHEGS0
ALEGS1
ALEGS0
AIEGS1
AIEGS0
ECPWME
—
Asynchronous
event counter
H'94
ECCR
ACKH1
ACKH0
ACKL1
ACKL0
PWCK2
PWCK1
PWCK0
—
H'95
ECCSR
OVH
OVL
—
CH2
CUEH
CUEL
CRCH
CRCL
H'96
ECH
ECH7
ECH6
ECH5
ECH4
ECH3
ECH2
ECH1
ECH0
H'97
ECL
ECL7
ECL6
ECL5
ECL4
ECL3
ECL2
ECL1
ECL0
H'93
H'98
H'99
H'9A
H'9B
H'9C
H'9D
H'9E
H'9F
H'A0
H'A1
349
Lower
Register
Address Name
Bit Names
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
Name
SCI
H'A2
H'A3
H'A4
H'A5
H'A6
H'A7
H'A8
SMR
COM
CHR
PE
PM
STOP
MP
CKS1
CKS0
H'A9
BRR
BRR7
BRR6
BRR5
BRR4
BRR3
BRR2
BRR1
BRR0
H'AA
SCR3
TIE
RIE
TE
RE
MPIE
TEIE
CKE1
CKE0
H'AB
TDR
TDR7
TDR6
TDR5
TDR4
TDR3
TDR2
TDR1
TDR0
H'AC
SSR
TDRE
RDRF
OER
FER
PER
TEND
MPBR
MPBT
H''AD
RDR
RDR7
RDR6
RDR5
RDR4
RDR3
RDR2
RDR1
RDR0
H'B0
TMA
—
—
—
—
TMA3
TMA2
TMA1
TMA0
H'B1
TCA
TCA7
TCA6
TCA5
TCA4
TCA3
TCA2
TCA1
TCA0
H'B6
TCRF
TOLH
CKSH2
CKSH1
CKSH0
TOLL
CKSL2
CKSL1
CKSL0
H'B7
TCSRF
OVFH
CMFH
OVIEH
CCLRH
OVFL
CMFL
OVIEL
CCLRL
H'B8
TCFH
TCFH7
TCFH6
TCFH5
TCFH4
TCFH3
TCFH2
TCFH1
TCFH0
H'B9
TCFL
TCFL7
TCFL6
TCFL5
TCFL4
TCFL3
TCFL2
TCFL1
TCFL0
H'BA
OCRFH
OCRFH7
OCRFH6
OCRFH5
OCRFH4
OCRFH3
OCRFH2
OCRFH1
OCRFH0
H'BB
OCRFL
OCRFL7
OCRFL6
OCRFL5
OCRFL4
OCRFL3
OCRFL2
OCRFL1
OCRFL0
H'C0
LPCR
DTS1
DTS0
CMX
—
SGS3
SGS2
SGS1
SGS0
H'C1
LCR
—
PSW
ACT
DISP
CKS3
CKS2
CKS1
CKS0
H'C2
LCR2
LCDAB
—
—
—
—
—
—
—
H'C4
ADRRH
ADR9
ADR8
ADR7
ADR6
ADR5
ADR4
ADR3
ADR2
H'C5
ADRRL
ADR1
ADR0
—
—
—
—
—
—
H'C6
AMR
CKS
—
—
—
CH3
CH2
CH1
CH0
H'C7
ADSR
ADSF
—
—
—
—
—
—
—
PMR2
—
—
POF1
—
—
—
—
IRQ0
H'AE
H'AF
Timer A
H'B2
H'B3
H'B4
H'B5
Timer F
H'BC
H'BD
H'BE
H'BF
LCD controller/
driver
H'C3
H'C8
H'C9
350
A/D converter
I/O port
Bit Names
Lower
Register
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
Name
H'CA
PMR3
AEVL
AEVH
—
—
—
TMOFH
TMOFL
—
I/O port
H'CC
PMR5
WKP7
WKP6
WKP5
WKP4
WKP3
WKP2
WKP1
WKP0
H'CD
PWCR2
—
—
—
—
—
—
PWCR21
PWCR20
H'CE
PWDRU2
—
—
—
—
—
—
PWDRU21
PWDRU20
H'CF
PWDRL2
PWDRL27
PWDRL26
PWDRL25
PWDRL24
PWDRL23
PWDRL22
PWDRL21
PWDRL20
H'D0
PWCR1
—
—
—
—
—
—
PWCR11
PWCR10
H'D1
PWDRU1
—
—
—
—
—
—
PWDRU11
PWDRU10
H'D2
PWDRL1
PWDRL17
PWDRL16
PWDRL15
PWDRL14
PWDRL13
PWDRL12
PWDRL11
PWDRL10
H'CB
H'D3
10 bit PWM2
10 bit PWM1
I/O port
H'D4
H'D5
H'D6
PDR3
P37
P36
P35
P34
P33
P32
P31
—
H'D7
PDR4
—
—
—
—
P43
P42
P41
P40
H'D8
PDR5
P57
P56
P55
P54
P53
P52
P51
P50
H'D9
PDR6
P67
P66
P65
P64
P63
P62
P61
P60
H'DA
PDR7
P77
P76
P75
P74
P73
P72
P71
P70
H'DB
PDR8
—
—
—
—
—
—
—
P80
H'DC
PDR9
—
—
P95
P94
P93
P92
P91
P90
H'DD
PDRA
—
—
—
—
PA3
PA2
PA1
PA0
H'DE
PDRB
—
—
—
—
PB3
PB2
PB1
PB0
H'E1
PUCR3
PUCR37
PUCR36
PUCR35
PUCR34
PUCR33
PUCR32
PUCR31
—
H'E2
PUCR5
PUCR57
PUCR56
PUCR55
PUCR54
PUCR53
PUCR52
PUCR51
PUCR50
H'E3
PUCR6
PUCR67
PUCR66
PUCR65
PUCR64
PUCR63
PUCR62
PUCR61
PUCR60
H'E6
PCR3
PCR37
PCR36
PCR35
PCR34
PCR33
PCR32
PCR31
—
H'E7
PCR4
—
—
—
—
—
PCR42
PCR41
PCR40
H'E8
PCR5
PCR57
PCR56
PCR55
PCR54
PCR53
PCR52
PCR51
PCR50
H'E9
PCR6
PCR67
PCR66
PCR65
PCR64
PCR63
PCR62
PCR61
PCR60
H'EA
PCR7
PCR77
PCR76
PCR75
PCR74
PCR73
PCR72
PCR71
PCR70
H'EB
PCR8
—
—
—
—
—
—
—
PCR80
H'EC
PMR9
—
—
—
—
PIOFF
—
PWM2
PWM1
H'ED
PCRA
—
—
—
—
PCRA3
PCRA2
PCRA1
PCRA0
H'EE
PMRB
—
—
—
—
IRQ1
—
—
—
H'DF
H'E0
H'E4
H'E5
H'EF
H'F0
SYSCR1
SSBY
STS2
STS1
STS0
LSON
—
MA1
MA0
H'F1
SYSCR2
—
—
—
NESEL
DTON
MSON
SA1
SA0
System control
351
Bit Names
Lower
Register
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
Name
H'F2
IEGR
—
—
—
—
—
—
IEG1
IEG0
System control
H'F3
IENR1
IENTA
—
IENWP
—
—
IENEC2
IEN1
IEN0
H'F4
IENR2
IENDT
IENAD
—
—
IENTFH
IENTFL
—
IENEC
H'F6
IRR1
IRRTA
—
—
—
—
IRREC2
IRRI1
IRRI0
H'F7
IRR2
IRRDT
IRRAD
—
—
IRRTFH
IRRTFL
—
IRREC
H'F9
IWPR
IWPF7
IWPF6
IWPF5
IWPF4
IWPF3
IWPF2
IWPF1
IWPF0
H'FA
CKSTPR1
—
—
S32CKSTP ADCKSTP
—
TFCKSTP
—
TACKSTP
H'FB
CKSTPR2
—
—
—
—
PW1CKSTP LDCKSTP
H'F5
H'F8
H'FC
H'FD
H'FE
H'FF
Legend
SCI: Serial Communication Interface
352
PW2CKSTP AECKSTP
System control
B.2
Functions
Register name
Address to which the
register is mapped
Register acronym
Name of on-chip
supporting module
Timer F
H'B6
TCRF—Timer Control Register F
Bit numbers
Bit
Initial bit values
Dashes (—) indicate
undefined bits.
7
6
TOLH
Initial value 0
R/W
W
5
4
3
CKSH2 CKSH1 CKSH0
0
W
0
W
TOLL
0
W
2
1
0
CKSL2 CKSL1 CKSL0
0
W
0
W
0
W
0
W
Names of the bits.
Dashes (—) indicate
reserved bits.
Possible types of access
R
Read only
W
Write only
Clock select L
R/W Read and write
—
See relevant register
description
0
*
*
Counts on external event (TMIF) rising/
falling edge
1
1
1
1
0
0
1
1
0
1
0
1
Internal clock: ø/32
Internal clock: ø/16
Internal clock: ø/4
Internal clock: øw/4
Toggle output level L
0
1
Clock select H
*
*
0
0
0
1
1
0
1
0
1
1
1
1
1
Full name of bit
Descriptions of bit
settings
Set to low level
Set to high level
16-bit mode, counts on TCFL overflow signal
Internal clock: ø/32
Internal clock: ø/16
Internal clock: ø/4
Internal clock: øw/4
* Don’t care
Toggle output level H
0
1
Set to low level
Set to high level
353
ECPWCRH—Event Counter PWM Compare Register H H'8C
Bit
7
6
5
4
3
2
AEC
1
0
ECPWCRH7 ECPWCRH6 ECPWCRH5 ECPWCRH4 ECPWCRH3 ECPWCRH2 ECPWCRH1 ECPWCRH0
Initial value
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
Sets event counter PWM waveform conversion period
ECPWCRL—Event Counter PWM Compare Register L
Bit
7
6
5
4
H'8D
3
2
AEC
1
0
ECPWCRL7 ECPWCRL6 ECPWCRL5 ECPWCRL4 ECPWCRL3 ECPWCRL2 ECPWCRL1 ECPWCRL0
Initial value
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
Sets event counter PWM waveform conversion period
ECPWDRH—Event Counter PWM Data Register H
Bit
7
6
5
4
H'8E
3
2
AEC
1
0
ECPWDRH7 ECPWDRH6 ECPWDRH5 ECPWDRH4 ECPWDRH3 ECPWDRH2 ECPWDRH1 ECPWDRH0
Initial value
R/W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
Controls event counter PWM waveform generator data
ECPWDRL—Event Counter PWM Data Register L
Bit
7
6
5
4
H'8F
3
AEC
2
1
0
ECPWDRL7 ECPWDRL6 ECPWDRL5 ECPWDRL4 ECPWDRL3 ECPWDRL2 ECPWDRL1 ECPWDRL0
Initial value
R/W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
Controls event counter PWM waveform generator data
354
0
W
WEGR—Wakeup Edge Select Register
Bit
7
6
5
H'90
4
3
System control
2
1
0
WKEGS7 WKEGS6 WKEGS5 WKEGS4 WKEGS3 WKEGS2 WKEGS1 WKEGS0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
WKPn edge selected
0
1
WKPn pin falling edge detected
WKPn pin rising edge detected
(n = 7 to 0)
355
SPCR—Serial Port Control Register
Bit
H'91
7
6
5
4
—
—
SPC32
—
3
Initial value
1
1
0
—
0
Read/Write
—
—
R/W
W
R/W
1
0
—
—
0
—
—
R/W
W
W
2
SCINV3 SCINV2
RXD32 pin input data inversion switch
0
1
RXD32 input data is not inverted
RXD32 input data is inverted
TXD32 pin output data inversion switch
0
1
TXD32 output data is not inverted
TXD32 output data is inverted
P42/TXD32pin function switch
0
1
356
Function as P42 I/O pin
Function as TXD32 output pin
SCI
AEGSR—Input Pin Edge Selection Register
Bit
7
6
5
H'92
4
3
2
AEC
1
0
AHEGS1 AHEGS0 ALEGS1 ALEGS0 AIEGS1 AIEGS0 ECPWME
Initial value
Read/Write
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
—
0
R/W
Reserved bit
Event counter PWM enable/disable,
IRQAEC select/deselect
0
1
AEC PWM halted, IRQAEC selected
AEC PWM operation enabled, IRQAEC deselected
IRQAEC edge select
Description
Bit 3
Bit 2
AIEGS1 AIEGS0
Falling edge on IRQAEC pin is sensed
0
0
Rising edge on IRQAEC pin is sensed
0
1
Both edges on IRQAEC pin are sensed
1
0
Use prohibited
1
1
AEC edge select L
Bit 5
Bit 4
ALEGS1 ALEGS0
0
0
0
1
1
0
1
1
Description
Falling edge on AEVL pin is sensed
Rising edge on AEVL pin is sensed
Both edges on AEVL pin are sensed
Use prohibited
AEC edge select H
Bit 7
Bit 6
AHEGS1 AHEGS0
0
0
0
1
1
0
1
1
Description
Falling edge on AEVH pin is sensed
Rising edge on AEVH pin is sensed
Both edges on AEVH pin are sensed
Use prohibited
357
ECCR—Event Counter Control Register
Bit
7
6
5
H'94
4
3
AEC
2
1
0
ACKH1 ACKH0 ACKL1 ACKL0 PWCK2 PWCK1 PWCK0
Initial value
Read/Write
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
—
0
R/W
Reserved bit
Event counter PWM clock select
Bit 3
Bit 2
Bit 1
PWCK2 PWCK1 PWCK0
ø/2
0
0
0
ø/4
0
0
1
ø/8
0
1
0
ø/16
0
1
1
ø/32
0
*
0
ø/64
0
*
1
AEC clock select L
Description
Bit 5
Bit 4
ACKL1 ACKL0
AEVL pin input
0
0
ø/2
0
1
ø/4
1
0
ø/8
1
1
AEC clock select H
Description
Bit 7
Bit 6
ACKH1 ACKH0
AEVH pin input
0
0
ø/2
0
1
ø/4
1
0
ø/8
1
1
358
Description
ECCSR—Event counter control/status register
Bit
H'95
AEC
7
6
5
4
3
2
1
0
OVH
OVL
—
CH2
CUEH
CUEL
CRCH
CRCL
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Counter reset control L
0 ECL is reset
1 ECL reset is cleared
and count-up function
is enabled
Counter reset control H
0 ECH is reset
1 ECH reset is cleared and
count-up function is enabled
Count-up enable L
0 ECL event clock input is disabled.
ECL value is held
1 ECL event clock input is enabled
Count-up enable H
0 ECH event clock input is disabled.
ECH value is held
1 ECH event clock input is enabled
Channel select
0 ECH and ECL are used together as a singlechannel 16-bit event counter
1
ECH and ECL are used as two independent
8-bit event counter channels
Counter overflow L
0 ECL has not overflowed
1 ECL has overflowed
Counter overflow H
0 ECH has not overflowed
1 ECH has overflowed
359
ECH—Event counter H
Bit
H'96
AEC
7
6
5
4
3
2
1
0
ECH7
ECH6
ECH5
ECH4
ECH3
ECH2
ECH1
ECH0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R
R
R
R
ECL—Event counter L
Bit
H'97
AEC
7
6
5
4
3
2
1
0
ECL7
ECL6
ECL5
ECL4
ECL3
ECL2
ECL1
ECL0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R
R
R
R
360
SMR—Serial mode register
Bit
H'A8
SCI3
7
6
5
4
3
2
1
0
COM
CHR
PE
PM
STOP
MP
CKS1
CKS0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Clock select
0 0 ø clock
0 1 øw/2 clock
1 0 ø/16 clock
1 1 ø/64 clock
Multiprocessor mode
0 Multiprocessor communication
function disabled
1 Multiprocessor communication
function enabled
Stop bit length
0 1 stop bit
1 2 stop bits
Parity mode
0 Even parity
1 Odd parity
Parity enable
0 Parity bit addition and checking disabled
1 Parity bit addition and checking enabled
Character length
0 8-bit data/5-bit data
1 7-bit data/5-bit data
Communication mode
0 Asynchronous mode
1 Synchronous mode
361
BRR—Bit rate register
Bit
H'A9
SCI3
7
6
5
4
3
2
1
0
BRR7
BRR6
BRR5
BRR4
BRR3
BRR2
BRR1
BRR0
Initial value
1
1
1
1
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
362
SCR3—Serial control register3
Bit
H'AA
SCI3
7
6
5
4
3
2
1
0
TIE
RIE
TE
RE
MPIE
TEIE
CKE1
CKE0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Clock enable
Bit 1
CKE1
0
Bit 0
CKE0
0
0
1
1
0
1
1
Communication Mode
Asynchronous
Synchronous
Asynchronous
Synchronous
Asynchronous
Synchronous
Asynchronous
Synchronous
Description
Clock Source
SCK Pin Function
I/O port
Internal clock
Serial clock output
Internal clock
Clock output
Internal clock
Reserved (Do not specify this combination)
Clock input
External clock
Serial clock input
External clock
Reserved (Do not specify this combination)
Reserved (Do not specify this combination)
Transmit end interrupt enable
0
1
Transmit end interrupt request (TEI) disabled
Transmit end interrupt request (TEI) enabled
Multiprocessor interrupt enable
0
Multiprocessor interrupt request disabled (normal receive operation)
[Clearing conditions]
When data is received in which the multiprocessor bit is set to 1
1
Multiprocessor interrupt request enabled
The receive interrupt request (RXI), receive error interrupt request (ERI), and setting of the
RDRF, FER, and OER flags in the serial status register (SSR), are disabled until data with
the multiprocessor bit set to 1 is received.
Receive enable
0
Receive operation disabled (RXD pin is I/O port)
1
Receive operation enabled (RXD pin is receive data pin)
Transmit enable
0
Transmit operation disabled (TXD pin is transmit data pin)
1
Transmit operation enabled (TXD pin is transmit data pin)
Receive interrupt enable
0
Receive data full interrupt request (RXI) and receive error interrupt request (ERI) disabled
1
Receive data full interrupt request (RXI) and receive error interrupt request (ERI) enabled
Transmit interrupt enable
0
Transmit data empty interrupt request (TXI) disabled
1
Transmit data empty interrupt request (TXI) enabled
363
TDR—Transmit data register
Bit
H'AB
SCI3
7
6
5
4
3
2
1
0
TDR7
TDR6
TDR5
TDR4
TDR3
TDR2
TDR1
TDR0
Initial value
1
1
1
1
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Data for transfer to TSR
364
SSR—Serial status register
Bit
H'AC
SCI3
7
6
5
4
3
2
1
0
TDRE
RDRF
OER
FER
PER
TEND
MPBR
MPBT
Initial value
1
0
0
0
0
1
0
0
Read/Write
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R
R
R/W
Multiprocessor bit transfer
0
A 0 multiprocessor bit is transmitted
1
A 1 multiprocessor bit is transmitted
Multiprocessor bit receive
0
Data in which the multiprocessor bit is 0 has been received
1
Data in which the multiprocessor bit is 1 has been received
Transmit end
0
Transmission in progress
[Clearing conditions] • After reading TDRE = 1, cleared by writing 0 to TDRE
• When data is written to TDR by an instruction
1
Transmission ended
[Setting conditions]
• When bit TE in serial control register3 (SCR3) is cleared to 0
• When bit TDRE is set to 1 when the last bit of a transmit character is sent
Parity error
0
Reception in progress or completed normally
[Clearing conditions] After reading PER = 1, cleared by writing 0 to PER
1
A parity error has occurred during reception
[Setting conditions] When the number of 1 bits in the receive data plus parity bit does not match the parity
designated by the parity mode bit (PM) in the serial mode register (SMR)
Framing error
0
Reception in progress or completed normally
[Clearing conditions] After reading FER = 1, cleared by writing 0 to FER
1
A framing error has occurred during reception
[Setting conditions] When the stop bit at the end of the receive data is checked for a value of 1 at completion of
reception, and the stop bit is 0
Overrun error
0
Reception in progress or completed
[Clearing conditions] After reading OER = 1, cleared by writing 0 to OER
1
An overrun error has occurred during reception
[Setting conditions] When the next serial reception is completed with RDRF set to 1
Receive data register full
0
There is no receive data in RDR
[Clearing conditions] • After reading RDRF = 1, cleared by writing 0 to RDRF
• When RDR data is read by an instruction
1
There is receive data in RDR
[Setting conditions] When reception ends normally and receive data is transferred from RSR to RDR
Transmit data register empty
0
Transmit data written in TDR has not been transferred to TSR
[Clearing conditions] • After reading TDRE = 1, cleared by writing 0 to TDRE
• When data is written to TDR by an instruction
1
Transmit data has not been written to TDR, or transmit data written in TDR has been transferred to TSR
[Setting conditions] • When bit TE in serial control register3 (SCR3) is cleared to 0
• When data is transferred from TDR to TSR
Note: * Only a write of 0 for flag clearing is possible.
365
RDR—Receive data register
Bit
H'AD
SCI3
7
6
5
4
3
2
1
0
RDR7
RDR6
RDR5
RDR4
RDR3
RDR2
RDR1
RDR0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R
R
R
R
TMA—Timer mode register A
Bit
H'B0
Timer A
7
6
5
4
3
2
1
0
—
—
—
—
TMA3
TMA2
TMA1
TMA0
Initial value
—
—
—
1
0
0
0
0
Read/Write
W
W
W
—
R/W
R/W
R/W
R/W
Internal clock select
Prescaler and Divider Ratio
TMA3 TMA2 TMA1 TMA0 or Overflow Period
0
0
0
ø/8192
0
PSS
1
ø/4096
PSS
ø/2048
PSS
1
0
ø/512
PSS
1
1
0
0
ø/256
PSS
1
ø/128
PSS
ø/32
1
0
PSS
ø/8
1
PSS
0
0
0
1s
1
PSW
1
0.5 s
PSW
0.25 s
1
0
PSW
0.03125 s
1
PSW
1
0
0
PSW and TCA are reset
1
1
0
1
366
Function
Interval
timer
Time
base
(when
using
32.768 kHz)
TCA—Timer counter A
Bit
H'B1
Timer A
7
6
5
4
3
2
1
0
TCA7
TCA6
TCA5
TCA4
TCA3
TCA2
TCA1
TCA0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R
R
R
R
Count value
367
TCRF—Timer control register F
Bit
H'B6
Timer F
7
6
5
4
3
2
1
0
TOLH
CKSH2
CKSH1
CKSH0
TOLL
CKSL2
CKSL1
CKSL0
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
Clock select L
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
Toggle output level L
0
1
Low level
High level
Clock select H
0
0
0
0
1
1
1
1
Toggle output level H
0
1
368
Low level
High level
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
16-bit mode, counting on TCFL
overflow signal
Use prohibited
Internal clock ø/32
Internal clock ø/16
Internal clock ø/4
Internal clock øw/4
0
1
0
1
0
1
0
1
Non-operationl
Use prohibited
Use prohibited
Use prohibited
Internal clock ø/32
Internal clock ø/16
Internal clock ø/4
Internal clock øw/4
TCSRF—Timer control/status register F
Bit
Timer F
7
6
5
4
3
2
1
0
OVFH
CMFH
OVIEH
CCLRH
OVFL
CMFL
OVIEL
CCLRL
0
0
0
0
0
0
0
0
R/W
R/W
Initial value
*
Read/Write
H'B7
*
R/(W)
R/(W)
R/W
R/W
*
R/(W)
R/W
*
Counter clear L
0
TCFL clearing by compare match is disabled
1
TCFL clearing by compare match is enabled
Timer overflow interrupt enable L
0
TCFL overflow interrupt request is disabled
1
TCFL overflow interrupt request is enabled
Compare match flag L
0
Clearing conditions:
After reading CMFL = 1, cleared by writing 0 to CMFL
1
Setting conditions:
Set when the TCFL value matches the OCRFL value
Timer overflow flag L
0
Clearing conditions:
After reading OVFL = 1, cleared by writing 0 to OVFL
1
Setting conditions:
Set when TCFL overflows from H'FF to H'00
Counter clear H
0
16-bit mode: TCF clearing by compare match is disabled
8-bit mode: TCFH clearing by compare match is disabled
1
16-bit mode: TCF clearing by compare match is enabled
8-bit mode: TCFH clearing by compare match is enabled
Timer overflow interrupt enable H
0
TCFH overflow interrupt request is disabled
1
TCFH overflow interrupt request is enabled
Compare match flag H
0
Clearing conditions:
After reading CMFH = 1, cleared by writing 0 to CMFH
1
Setting conditions:
Set when the TCFH value matches the OCRFH value
Timer overflow flag H
0
Clearing conditions:
After reading OVFH = 1, cleared by writing 0 to OVFH
1
Setting conditions:
Set when TCFH overflows from H'FF to H'00
Note: * Bits 7, 6, 3, and 2 can only be written with 0, for flag clearing.
369
TCFH—8-bit timer counter FH
Bit
H'B8
Timer F
7
6
5
4
3
2
1
0
TCFH7
TCFH6
TCFH5
TCFH4
TCFH3
TCFH2
TCFH1
TCFH0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Count value
TCFL—8-bit timer counter FL
Bit
H'B9
Timer F
7
6
5
4
3
2
1
0
TCFL7
TCFL6
TCFL5
TCFL4
TCFL3
TCFL2
TCFL1
TCFL0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Count value
OCRFH—Output compare register FH
Bit
7
6
5
H'BA
4
3
Timer F
2
1
0
OCRFH7 OCRFH6 OCRFH5 OCRFH4 OCRFH3 OCRFH2 OCRFH1 OCRFH0
Initial value
1
1
1
1
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
OCRFL—Output compare register FL
Bit
7
6
5
H'BB
4
3
Timer F
2
1
0
OCRFL7 OCRFL6 OCRFL5 OCRFL4 OCRFL3 OCRFL2 OCRFL1 OCRFL0
Initial value
1
1
1
1
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
370
LPCR—LCD port control register
Bit
H'C0
LCD controller/driver
7
6
5
4
3
2
1
0
DTS1
DTS0
CMX
—
SGS3
SGS2
SGS1
SGS0
Initial value
0
0
0
—
0
0
0
0
Read/Write
R/W
R/W
R/W
W
R/W
R/W
R/W
R/W
Clock enable
Bit 3
Bit 2
Bit 1
Bit 0
SGS3
SGS2
SGS1
SGS0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Function of Pins SEG25 to SEG1
SEG25 SEG24 to SEG20 to SEG16 to SEG12 to SEG8 to
SEG21 SEG17 SEG13 SEG9 SEG5
Port
Port
Port
Port
Port
Port
Port
Port
Port
Port
Port
Port
Port
Port
Port
Port
Port SEG
Port
Port
Port
Port SEG SEG
Port
Port
Port SEG SEG SEG
Port
Port SEG SEG SEG SEG
Port SEG SEG SEG SEG SEG
SEG SEG SEG SEG SEG SEG
SEG SEG SEG SEG SEG SEG
SEG SEG SEG SEG SEG SEG
SEG SEG SEG SEG SEG Port
SEG SEG SEG SEG Port
Port
SEG SEG SEG Port
Port
Port
SEG SEG Port
Port
Port
Port
SEG Port
Port
Port
Port
Port
Port
Port
Port
Port
Port
Port
Notes
SEG4 to
SEG1
Port (Initial value)
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
Port
Port
Port
Port
Port
Port
Port
Duty select, common function select
Bit 7 Bit 6 Bit 5
Duty Cycle Common Drivers
DTS1 DTS0 CMX
0
0
0
COM1
Static
1
COM4 to COM1
1
0
0
COM2 to COM1
1/2 duty
1
COM4 to COM1
0
0
1
COM3 to COM1
1/3 duty
1
COM4 to COM1
1
0
1
COM4 to COM1
1/4 duty
1
Notes
COM4 to COM2 output the same waveform as COM1
COM4 outputs the same waveform as COM3 and COM2 outputs the same waveform as COM1
COM4 outputs a non-selected waveform
—
371
LCR—LCD control register
Bit
H'C1
LCD controller/driver
7
6
5
4
3
2
1
0
—
PSW
ACT
DISP
CKS3
CKS2
CKS1
CKS0
Initial value
1
0
0
0
0
0
0
0
Read/Write
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Frame frequency select
Bit 3 Bit 2 Bit 1 Bit 1
CKS3 CKS2 CKS1 CKS0
0
0
0
1
1
1
1
1
1
1
1
*
*
*
0
0
0
0
1
1
1
1
0
0
1
0
0
1
1
0
0
1
1
Display data control
0 Blank data is displayed
1 LCD RAM data is displayed
Display function activate
0 LCD controller/driver operation halted
1 LCD controller/driver operates
LCD drive power supply on/off control
0 LCD drive power supply off
1 LCD drive power supply on
372
0
1
*
0
1
0
1
0
1
0
1
Operating Clock
øw
øw/2
øw/4
ø/2
ø/4
ø/8
ø/16
ø/32
ø/64
ø/128
ø/256
* : Don’t care
LCR2—LCD control register 2
Bit
H'C2
LCD controller/driver
7
6
5
4
3
2
1
0
LCDAB
—
—
—
—
—
—
—
Initial value
0
1
1
—
—
—
—
—
Read/Write
R/W
—
—
W
W
W
W
W
A waveform/B waveform switching control
0 Drive using A waveform
1 Drive using B waveform
373
AMR—A/D mode register
Bit
H'C6
A/D converter
7
6
5
4
3
2
1
0
CKS
—
—
—
CH3
CH2
CH1
CH0
Initial value
0
0
1
1
0
0
0
0
Read/Write
R/W
R/W
—
—
R/W
R/W
R/W
R/W
Channel select
Bit 3 Bit 2 Bit 1
CH3 CH2 CH1
0
0
*
1
0
1
1
0
0
1
Bit 0
CH0
*
0
1
0
1
0
1
0
1
Analog Input Channel
No channel selected
AN 0
AN 1
AN 2
AN 3
Use prohibited
*: Don’t care
Clock select
Bit 7
CKS Conversion Period
0
62/ø
1
31/ø
Conversion Time
ø = 1 MHz ø = 5 MHz
62 µs
31 µs
12.4 µs
*
*: Operation is not guaranteed with a conversion time
of less than 12.4 µs.
Select a setting that gives a conversion time of at
least 12.4 µs.
374
ADRRH—A/D result register H
ADRRL—A/D result register L
H'C4
H'C5
A/D converter
ADRRH
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
ADR9
ADR8
ADR7
ADR6
ADR5
ADR4
ADR3
ADR2
Not fixed Not fixed Not fixed Not fixed Not fixed Not fixed Not fixed Not fixed
R
R
R
R
R
R
R
R
A/D conversion result
ADRRL
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
ADR1
ADR0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Not fixed Not fixed
R
R
A/D conversion result
ADSR—A/D start register
Bit
H'C7
A/D converter
7
6
5
4
3
2
1
0
ADSF
—
—
—
—
—
—
—
Initial value
0
1
1
1
1
1
1
1
Read/Write
R/W
—
—
—
—
—
—
—
A/D status flag
0 Read Indicates completion of A/D conversion
Write Stops A/D conversion
1 Read Indicates A/D conversion in progress
Write Starts A/D conversion
375
PMR2—Port Mode Register 2
Bit
Initial value
Read/Write
H'C9
I/O port
7
6
5
4
3
2
1
0
—
—
POF1
—
—
—
—
IRQ0
1
—
1
—
0
R/W
1
—
1
—
—
W
—
W
0
R/W
P43/IRQ0 pin function switch
0 Functions as P43 I/O pin
1 Functions as IRQ0 input pin
P35 pin output buffer PMOS on/off control
0 CMOS output
1 NMOS open-drain output
376
PMR3—Port mode register 3
Bit
H'CA
I/O port
7
6
5
4
3
2
1
0
AEVL
AEVH
—
—
—
TMOFH
TMOFL
—
Initial value
0
0
—
—
—
0
0
—
Read/Write
R/W
R/W
W
W
W
R/W
R/W
W
P31/TMOFL pin function switch
0 Functions as P31 I/O pin
1 Functions as TMOFL output pin
P32/TMOFH pin function switch
0 Functions as P32 I/O pin
1 Functions as TMOFH output pin
P36/AEVH pin function switch
0 Functions as P36 I/O pin
1 Functions as AEVH input pin
P37/AEVL pin function switch
0 Functions as P37 I/O pin
1 Functions as AEVL input pin
377
PMR5—Port mode register 5
Bit
H'CC
I/O port
7
6
5
4
3
2
1
0
WKP7
WKP6
WKP5
WKP4
WKP3
WKP2
WKP1
WKP0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
P5n/WKPn/SEGn+1 pin function switch
0 Functions as P5n I/O pin
1 Functions as WKPn input pin
PWCR2—PWM2 Control Register
Bit
Initial value
Read/Write
H'CD
7
6
5
4
3
2
—
—
—
—
—
—
1
—
1
—
1
—
1
—
1
—
1
—
1
10-bit PWM
0
PWCR21 PWCR20
0
W
0
W
Cloxk select
0
1
0
1
0
1
The input clock is ø (tø* = 1/ø) The conversion period is 512/ø, with a minimum modulation width of 1/2 ø
The input clock is ø/2 (tø* = 2/ø) The conversion period is 1,024/ø, with a minimum modulation width of 1/ø
The input clock is ø/4 (tø* = 4/ø) The conversion period is 2,048/ø, with a minimum modulation width of 2/ø
The input clock is ø/8 (tø* = 8/ø) The conversion period is 4,096/ø, with a minimum modulation width of 4/ø
Note: * tø: Period of PWM2 input clock
PWDRU2—PWM2 Data Register U
Bit
Initial value
Read/Write
H'CE
7
6
5
4
3
2
—
—
—
—
—
—
1
—
1
—
1
—
1
—
1
—
1
—
10-bit PWM
1
0
PWDRU21 PWDRU20
0
W
0
W
Upper 2 bits of PWM2 waveform generation data
378
PWDRL2—PWM2 Data Register L
Bit
7
6
H'CF
5
4
3
2
10-bit PWM
1
0
PWDRL27 PWDRL26 PWDRL25 PWDRL24 PWDRL23 PWDRL22 PWDRL21 PWDRL20
Initial value
Read/Write
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
Lower 8 bits of PWM2 waveform generation data
PWCR1—PWM1 control register
Bit
H'D0
10-bit PWM
7
6
5
4
3
2
1
0
—
—
—
—
—
—
Initial value
1
1
1
1
1
1
0
0
Read/Write
—
—
—
—
—
—
W
W
PWCR11 PWCR10
Clock select
0 The input clock is ø (tø* = 1/ø)
The conversion period is 512/ø, with a minimum modulation width of 1/2ø
The input clock is ø/2 (tø* = 2/ø)
The conversion period is 1,024/ø, with a minimum modulation width of 1/ø
1 The input clock is ø/4 (tø* = 4/ø)
The conversion period is 2,048/ø, with a minimum modulation width of 2/ø
The input clock is ø/8 (tø* = 8/ø)
The conversion period is 4,096/ø, with a minimum modulation width of 4/ø
Note: * tø: Period of PWM input clock
379
PWDRU1—PWM1 data register U
Bit
H'D1
10-bit PWM
7
6
5
4
3
2
—
—
—
—
—
—
Initial value
1
1
1
1
1
1
0
0
Read/Write
—
—
—
—
—
—
W
W
1
0
PWDUR11 PWDRU10
Upper 2 bits of data for generating PWM1 waveform
PWDRL1—PWM1 data register L
Bit
7
6
H'D2
5
4
3
10-bit PWM
2
1
0
PWDRL17 PWDRL16 PWDRL15 PWDRL14 PWDRL13 PWDRL12 PWDRL11 PWDRL10
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
Lower 8 bits of data for generating PWM1 waveform
PDR3—Port data register 3
Bit
H'D6
I/O ports
7
6
5
4
3
2
1
0
P3 7
P36
P35
P34
P33
P32
P31
—
Initial value
0
0
0
0
0
0
0
—
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
Stores data of port 3 pins
PDR4—Port data register 4
Bit
H'D7
I/O ports
7
6
5
4
3
2
1
0
—
—
—
—
P43
P42
P41
P40
Initial value
1
1
1
1
1
0
0
0
Read/Write
—
—
—
—
R
R/W
R/W
R/W
Stores data of port 4 pins
Reads P43 pin state
380
PDR5—Port data register 5
Bit
H'D8
I/O ports
7
6
5
4
3
2
1
0
P5 7
P56
P55
P54
P53
P52
P51
P50
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Stores data of port 5 pins
PDR6—Port data register 6
Bit
H'D9
I/O ports
7
6
5
4
3
2
1
0
P6 7
P66
P65
P64
P63
P62
P61
P60
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Stores data of port 6 pins
PDR7—Port data register 7
Bit
H'DA
I/O ports
7
6
5
4
3
2
1
0
P7 7
P76
P75
P74
P73
P72
P71
P70
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Stores data of port 7 pins
PDR8—Port data register 8
Bit
H'DB
I/O ports
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
P80
Initial value
—
—
—
—
—
—
—
0
Read/Write
—
—
—
—
—
—
—
R/W
Stores data of P80 pin
381
PDR9—Port data register 9
Bit
Initial value
Read/Write
H'DC
I/O ports
7
6
5
4
3
2
1
0
—
—
P95
P94
P93
P92
P91
P90
1
—
1
—
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
Stores data of port 9 pins
PDRA—Port data register A
Bit
H'DD
I/O ports
7
6
5
4
3
2
1
0
—
—
—
—
PA3
PA2
PA1
PA0
Initial value
1
1
1
1
0
0
0
0
Read/Write
—
—
—
—
R/W
R/W
R/W
R/W
Stores data of port A pins
PDRB—Port data register B
Bit
H'DE
I/O ports
7
6
5
4
3
2
1
0
—
—
—
—
PB 3
PB 2
PB 1
PB 0
—
—
—
—
R
R
R
R
Initial value
Read/Write
Reads states of port B pins
PUCR3—Port pull-up control register 3
Bit
7
6
5
H'E1
4
3
I/O ports
2
1
PUCR3 7 PUCR36 PUCR35 PUCR34 PUCR33 PUCR32 PUCR31
0
—
Initial value
0
0
0
0
0
0
0
—
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
382
PUCR5—Port pull-up control register 5
Bit
7
6
5
H'E2
4
3
I/O ports
2
1
0
PUCR5 7 PUCR56 PUCR55 PUCR54 PUCR53 PUCR52 PUCR51 PUCR50
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PUCR6—Port pull-up control register 6
Bit
7
6
5
H'E3
4
3
I/O ports
2
1
0
PUCR6 7 PUCR66 PUCR65 PUCR64 PUCR63 PUCR62 PUCR61 PUCR60
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PCR3—Port control register 3
Bit
H'E6
I/O ports
7
6
5
4
3
2
1
0
PCR3 7
PCR3 6
PCR3 5
PCR3 4
PCR3 3
PCR32
PCR31
—
Initial value
0
0
0
0
0
0
0
—
Read/Write
W
W
W
W
W
W
W
W
Port 3 input/output select
0 Input pin
1 Output pin
PCR4—Port control register 4
Bit
H'E7
I/O ports
7
6
5
4
3
2
1
0
—
—
—
—
—
PCR42
PCR41
PCR40
Initial value
1
1
1
1
1
0
0
0
Read/Write
—
—
—
—
—
W
W
W
Port 4 input/output select
0 Input pin
1 Output pin
383
PCR5—Port control register 5
Bit
H'E8
I/O ports
7
6
5
4
3
2
1
0
PCR57
PCR56
PCR55
PCR54
PCR53
PCR52
PCR51
PCR50
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
Port 5 input/output select
0 Input pin
1 Output pin
PCR6—Port control register 6
Bit
H'E9
I/O ports
7
6
5
4
3
2
1
0
PCR6 7
PCR6 6
PCR6 5
PCR6 4
PCR6 3
PCR6 2
PCR6 1
PCR6 0
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
Port 6 input/output select
0 Input pin
1 Output pin
PCR7—Port control register 7
Bit
H'EA
I/O ports
7
6
5
4
3
2
1
0
PCR77
PCR76
PCR75
PCR74
PCR73
PCR72
PCR71
PCR70
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
Port 7 input/output select
0 Input pin
1 Output pin
384
PCR8—Port control register 8
Bit
H'EB
I/O ports
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
PCR80
Initial value
—
—
—
—
—
—
—
0
Read/Write
W
W
W
W
W
W
W
W
Port 8 input/output select
0 Input pin
1 Output pin
PMR9—Port mode register 9
Bit
Initial value
Read/Write
H'EC
7
6
5
4
3
2
—
—
—
—
PIOFF
—
1
—
1
—
1
—
1
—
0
R/W
—
W
I/O ports
1
0
PWM2 PWM1
0
R/W
0
R/W
P90/PWM1 pin function switch
0 Functions as P90 output pin
1 Functions as PWM1 output pin
P91/PWM2 pin function switch
0 Functions as P91 output pin
1 Functions as PWM2 output pin
P92 to P90 step-up circuit control
0 Large-current port step-up circuit is turned on
1 Large-current port step-up circuit is turned off
385
PCRA—Port control register A
Bit
H'ED
I/O ports
7
6
5
4
3
2
—
—
—
—
PCRA 3
PCRA 2
Initial value
1
1
1
1
0
0
0
0
Read/Write
—
—
—
—
W
W
W
W
1
0
PCRA 1 PCRA 0
Port A input/output select
0 Input pin
1 Output pin
PMRB—Port mode register B
Bit
H'EE
I/O ports
7
6
5
4
3
2
1
0
—
—
—
—
IRQ1
—
—
—
Initial value
1
1
1
1
0
1
1
1
Read/Write
—
—
—
—
R/W
—
—
—
PB3/AN3/IRQ1 pin function switch
0 Functions as PB3/AN3 input pin
1 Functions as IRQ1 input pin
386
SYSCR1—System control register 1
Bit
H'F0
System control
7
6
5
4
3
2
1
0
SSBY
STS2
STS1
STS0
LSON
—
MA1
MA0
Initial value
0
0
0
0
0
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
—
R/W
R/W
Active (medium-speed)
mode clock select
0 0 øosc /16
1 øosc /32
1 0 øosc /64
1 ø osc /128
Low speed on flag
0 The CPU operates on the system clock (ø)
1 The CPU operates on the subclock (øSUB )
Standby timer select 2 to 0
0 0 0 Wait time = 8,192 states
1 Wait time = 16,384 states
1 0 Wait time = 1,024 states
1 Wait time = 2,048 states
1 0 0 Wait time = 4,096 states
1 Wait time = 2 states
1 0 Wait time = 8 states
1 Wait time = 16 states
Software standby
0 • When a SLEEP instruction is executed in active mode, a transition is
made to sleep mode
• When a SLEEP instruction is executed in subactive mode, a transition
is made to subsleep mode
1 • When a SLEEP instruction is executed in active mode, a transition is
made to standby mode or watch mode
• When a SLEEP instruction is executed in subactive mode, a transition
is made to watch mode
387
SYSCR2—System control register 2
Bit
H'F1
System control
7
6
5
4
3
2
1
0
—
—
—
NESEL
DTON
MSON
SA1
SA0
Initial value
1
1
1
1
0
0
0
0
Read/Write
—
—
—
R/W
R/W
R/W
R/W
R/W
Subactive mode clock select
Medium speed on flag
0 0 ø W /8
1 ø W /4
1 * ø W /2
*: Don’t care
0 Operates in active (high-speed) mode
1 Operates in active (medium-speed) mode
Direct transfer on flag
0 • When a SLEEP instruction is executed in active mode, a transition is
made to standby mode, watch mode, or sleep mode
• When a SLEEP instruction is executed in subactive mode, a transition is
made to watch mode or subsleep mode
1 • When a SLEEP instruction is executed in active (high-speed) mode, a direct
transition is made to active (medium-speed) mode if SSBY = 0, MSON = 1, and
LSON = 0, or to subactive mode if SSBY = 1, TMA3 = 1, and LSON = 1
• When a SLEEP instruction is executed in active (medium-speed) mode, a direct
transition is made to active (high-speed) mode if SSBY = 0, MSON = 0, and
LSON = 0, or to subactive mode if SSBY = 1, TMA3 = 1, and LSON = 1
• When a SLEEP instruction is executed in subactive mode, a direct
transition is made to active (high-speed) mode if SSBY = 1, TMA3 = 1, LSON = 0,
and MSON = 0, or to active (medium-speed) mode if SSBY = 1, TMA3 = 1,
LSON = 0, and MSON = 1
Noise elimination sampling frequency select
0 Sampling rate is øOSC /16
1 Sampling rate is øOSC /4
388
IEGR—IRQ edge select register
Bit
H'F2
System control
7
6
5
4
3
2
1
0
—
—
—
—
—
—
IEG1
IEG0
Initial value
1
1
1
—
—
—
0
0
Read/Write
—
—
—
W
W
W
R/W
R/W
IRQ0 edge select
0 Falling edge of IRQ0 pin input is detected
1 Rising edge of IRQ0 pin input is detected
IRQ1 edge select
0 Falling edge of IRQ1 pin input is detected
1 Rising edge of IRQ1 pin input is detected
389
IENR1—Interrupt enable register 1
Bit
H'F3
System control
7
6
5
4
3
2
1
0
IENTA
—
IENWP
—
—
IENEC2
IEN1
IEN0
Initial value
0
—
0
—
—
0
0
0
Read/Write
R/W
W
R/W
W
W
R/W
R/W
R/W
IRQ1 to IRQ0 interrupt enable
0 Disables IRQ1 to IRQ0 interrupt, requests
1 Enables IRQ1 to IRQ0 interrupt requests
IRQAEC interrupt enable
0 Disables IRQAEC interrupt requests
1 Enables IRQAEC interrupt requests
Wakeup interrupt enable
0 Disables WKP7 to WKP0 interrupt requests
1 Enables WKP7 to WKP0 interrupt requests
Timer A interrupt enable
0 Disables timer A interrupt requests
1 Enables timer A interrupt requests
390
IENR2—Interrupt enable register 2
Bit
H'F4
7
6
5
4
IENDT
IENAD
—
—
Initial value
0
0
—
—
0
Read/Write
R/W
R/W
W
W
R/W
3
System control
1
0
—
IENEC
0
—
0
R/W
W
R/W
2
IENTFH IENTFL
Asynchronous event counter interrupt enable
0 Disables asynchronous event counter
interrupt requests
1 Enables asynchronous event counter
interrupt requests
Timer FL interrupt enable
0 Disables timer FL interrupt requests
1 Enables timer FL interrupt requests
Timer FH interrupt enable
0 Disables timer FH interrupt requests
1 Enables timer FH interrupt requests
A/D converter interrupt enable
0 Disables A/D converter interrupt requests
1 Enables A/D converter interrupt requests
Direct transition interrupt enable
0 Disables direct transition interrupt requests
1 Enables direct transition interrupt requests
391
IRR1—Interrupt request register 1
Bit
H'F6
System control
7
6
5
4
3
2
1
0
IRRTA
—
—
—
—
IRREC2
IRRI1
IRRI0
Initial value
0
—
1
—
—
0
0
0
Read/Write
R/W*
W
—
W
W
R/W*
R/W*
R/W*
IRQ1 to IRQ0 interrupt request flags
0 Clearing conditions:
When IRRIn = 1, it is cleared by writing 0
1 Setting conditions:
When pin IRQn is designated for interrupt
input and the designated signal edge is input
(n = 1 or 0)
IRQAEC interrupt request flag
0 Clearing conditions:
When IRREC2 = 1, it is cleared by writing 0
1 Setting conditions:
When pin IRQAEC is designated for interrupt input and the
designated signal edge is input
Timer A interrupt request flag
0 Clearing conditions:
When IRRTA = 1, it is cleared by writing 0
1 Setting conditions:
When the timer A counter value overflows (from H'FF to H'00)
Note: * Bits 7 and 2 to 0 can only be written with 0, for flag clearing.
392
IRR2—Interrupt request register 2
Bit
H'F7
7
6
5
4
IRRDT
IRRAD
—
—
3
2
IRRTFH IRRTFL
System control
1
0
—
IRREC
Initial value
0
0
—
—
0
0
—
0
Read/Write
R/(W)*
R/(W)*
W
W
R/(W)*
R/(W)*
W
R/(W)*
Asynchronous event counter interrupt request flag
0 Clearing conditions:
When IRREC = 1, it is cleared by writing 0
1 Setting conditions:
When the asynchronous event counter value overflows
Timer FL interrupt request flag
0 Clearing conditions:
When IRRTFL = 1, it is cleared by writing 0
1 Setting conditions:
When counter FL and output compare register FL
match in 8-bit timer mode
Timer FH interrupt request flag
0 Clearing conditions:
When IRRTFH = 1, it is cleared by writing 0
1 Setting conditions:
When counter FH and output compare register FH match
in 8-bit timer mode, or when 16-bit counters FL and FH
and output compare registers FL and FH match in 16-bit timer mode
A/D converter interrupt request flag
0 Clearing conditions:
When IRRAD = 1, it is cleared by writing 0
1 Setting conditions:
When the A/D converter completes conversion and
ADSF is reset
Direct transition interrupt request flag
0 Clearing conditions:
When IRRDT = 1, it is cleared by writing 0
1 Setting conditions:
When a SLEEP instruction is executed while DTON is
set to 1, and a direct transition is made
Note: * Bits 7, 6, 3, 2, and 0 can only be written with 0, for flag clearing.
393
IWPR—Wakeup interrupt request register
Bit
H'F9
System control
7
6
5
4
3
2
1
0
IWPF7
IWPF6
IWPF5
IWPF4
IWPF3
IWPF2
IWPF1
IWPF0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
Wakeup interrupt request register
0 Clearing conditions:
When IWPFn = 1, it is cleared by writing 0
1 Setting conditions:
When pin WKPn is designated for wakeup input and a
falling edge is input at that pin
(n = 7 to 0)
Note: * All bits can only be written with 0, for flag clearing.
394
CKSTPR1—Clock stop register 1
Bit
H'FA
7
6
—
—
5
Initial value
1
1
1
Read/Write
—
—
R/W
4
System control
3
2
1
0
—
TFCKSTP
—
TACKSTP
1
1
1
1
1
R/W
—
R/W
—
R/W
S32CKSTP ADCKSTP
Timer A module standby mode control
0 Timer A is set to module standby mode
1 Timer A module standby mode is cleared
Timer F module standby mode control
0 Timer F is set to module standby mode
1 Timer F module standby mode is cleared
A/D converter module standby mode control
0 A/D converter is set to module standby mode
1 A/D converter module standby mode is cleared
SCI3 module standby mode control
0 SCI3 is set to module standby mode
1 SCI3 module standby mode is cleared
395
CKSTPR2—Clock stop register 2
Bit
H'FB
4
System control
7
6
5
—
—
—
Initial value
1
1
1
1
1
1
1
1
Read/Write
—
—
—
R/W
R/W
—
R/W
R/W
3
PW2CKSTP AECKSTP
1
2
—
0
PW1CKSTP LDCKSTP
LCD module standby mode control
0 LCD is set to module standby mode
1 LCD module standby mode is cleared
PWM1 module standby mode control
0 PWM1 is set to module standby mode
1 PWM1 module standby mode is cleared
Asynchronous event counter module standby mode control
0 Asynchronous event counter is set to module standby mode
1 Asynchronous event counter module standby mode is cleared
PWM2 module standby mode control
0 PWM2 is set to module standby mode
1 PWM2 module standby mode is cleared
396
Appendix C I/O Port Block Diagrams
C.1
Block Diagrams of Port 3
SBY
PUCR3n
VCC
PMR3n
P3n
PDR3n
VSS
Internal data bus
VCC
PCR3n
AEC module
AEVH(P36)
AEVL(P37)
PDR3:
Port data register 3
PCR3:
Port control register 3
PMR3:
Port mode register 3
PUCR3: Port pull-up control register 3
n=7 or 6
Figure C.1 (a) Port 3 Block Diagram (Pins P3 7 and P36)
397
SBY
PUCR35
VCC
PMR25
P35
PDR35
VSS
PDR3:
Port data register 3
PCR3:
Port control register 3
PUCR3:
Port pull-up control register 3
PMR2
Port mode register 2
PCR35
Figure C.1 (b) Port 3 Block Diagram (Pin P35)
398
Internal data bus
VCC
SBY
PUCR3
VCC
P3n
PDR3n
Internal data bus
VCC
PCR3n
VSS
PDR3: Port data register 3
PCR3: Port control register 3
n = 4 or 3
Figure C.1 (c) Port 3 Block Diagram (Pins P34 and P33)
399
SBY
TMOFH (P32)
TMOFL (P31)
PUCR3n
VCC
PMR3n
P3n
PDR3n
VSS
PCR3n
PDR3: Port data register 3
PCR3: Port control register 3
PMR3: Port mode register 3
PUCR3: Port pull-up control register 3
n = 2 or 1
Figure C.1 (d) Port 3 Block Diagram (Pins P32 and P31)
400
Internal data bus
VCC
C.2
Block Diagrams of Port 4
Internal data bus
PMR33
P43
IRQ0
PMR3: Port mode register 3
Figure C.2 (a) Port 4 Block Diagram (Pin P4 3)
401
SBY
SCINV3
VCC
SPC32
SCI3 module
TXD32
P42
PCR42
VSS
PDR4: Port data register 4
PCR4: Port control register 4
Figure C.2 (b) Port 4 Block Diagram (Pin P42)
402
Internal data bus
PDR42
SBY
VCC
SCI3 module
RE32
RXD32
P41
PCR41
VSS
Internal data bus
PDR41
SCINV2
PDR4: Port data register 4
PCR4: Port control register 4
Figure C.2 (c) Port 4 Block Diagram (Pin P41)
403
SBY
SCI3 module
SCKIE32
SCKOE32
VCC
SCKO32
SCKI32
P40
PCR40
VSS
PDR4: Port data register 4
PCR4: Port control register 4
Figure C.2 (d) Port 4 Block Diagram (Pin P40)
404
Internal data bus
PDR40
C.3
Block Diagram of Port 5
SBY
PUCR5n
VCC
VCC
P5n
PDR5n
VSS
PCR5n
Internal data bus
PMR5n
WKPn
PDR5: Port data register 5
PCR5: Port control register 5
PMR5: Port mode register 5
PUCR5: Port pull-up control register 5
n = 7 to 0
Figure C.3 Port 5 Block Diagram
405
C.4
Block Diagram of Port 6
SBY
VCC
PDR6n
VCC
PCR6n
P6n
VSS
PDR6: Port data register 6
PCR6: Port control register 6
PUCR6: Port pull-up control register 6
n = 7 to 0
Figure C.4 Port 6 Block Diagram
406
Internal data bus
PUCR6n
C.5
Block Diagram of Port 7
SBY
PDR7n
PCR7n
P7n
Internal data bus
VCC
VSS
PDR7: Port data register 7
PCR7: Port control register 7
n = 7 to 0
Figure C.5 Port 7 Block Diagram
407
C.6
Block Diagrams of Port 8
VCC
PDR8n
PCR8n
P80
VSS
PDR8:
Port data register 8
PCR8:
Port control register 8
Figure C.6 Port 8 Block Diagram (Pin P8 0)
408
Internal data bus
SBY
C.7
Block Diagrams of Port 9
PWM module
PWMn+1
Internal data bus
SBY
PMR9n
P9n
PDR9n
VSS
PDR9 : Port data register 9
n= 1 or 0
Figure C.7 (a) Port 9 Block Diagram (Pins P9 1 and P90)
P9n
PDR9n
Internal data bus
SBY
VSS
PDR9: Port data register 9
n= 5 to 2
Figure C.7 (b) Port 9 Block Diagram (Pins P95 to P92)
409
C.8
Block Diagram of Port A
SBY
VCC
PCRAn
PAn
VSS
PDRA: Port data register A
PCRA: Port control register A
n = 3 to 0
Figure C.8 Port A Block Diagram
410
Internal data bus
PDRAn
C.9
Block Diagram of Port B
Internal
data bus
PBn
A/D module
DEC
AMR3 to AMR0
VIN
n = 3 to 0
Figure C.9 Port B Block Diagram
411
Appendix D Port States in the Different Processing States
Table D.1
Port States Overview
Port
Reset
Sleep
Subsleep
Standby
P37 to
P31
High
impedance
Retained
Retained
High
Retained
impedance*
Functions
Functions
P43 to
P40
High
impedance
Retained
Retained
High
impedance
Retained
Functions
Functions
P57 to
P50
High
impedance
Retained
Retained
High
Retained
impedance*
Functions
Functions
P67 to
P60
High
impedance
Retained
Retained
High
impedance
Retained
Functions
Functions
P77 to
P70
High
impedance
Retained
Retained
High
impedance
Retained
Functions
Functions
P87 to
P80
High
impedance
Retained
Retained
High
impedance
Retained
Functions
Functions
P95 to
P90
High
impedance
Retained
Retained
High
Retained
impedance*
Functions
Functions
PA3 to
PA0
High
impedance
Retained
Retained
High
impedance
Functions
Functions
PB3 to
PB0
High
impedance
High
High
High
impedance impedance impedance
Note: * High level output when MOS pull-up is in on state.
412
Watch
Retained
Subactive Active
High
High
High
impedance impedance impedance
Appendix E List of Product Codes
Table E.1
H8/3802 Series Product Code Lineup
Product
Type
Product Code
H8/3802 H8/3802 Mask ROM HD6433802H
series
versions
HD64433802FP
ZTAT
versions
Mark Code
Package(Hitachi
Package Code)
HD6433802 (***) H
64-pin QFP (FP-64A)
HD6433802 (***) FP 64-pin LQFP (FP-64E)
HD6433802P
HD6433802 (***) P
64-pin DILP (DP-64S)
HD6473802H
HD6473802H
64-pin QFP (FP-64A)
HD6473802FP
HD6473802FP
64-pin LQFP (FP-64E)
HD6473802P
HD6473802P
64-pin DILP (DP-64S)
HD6433801 (***) H
64-pin QFP (FP-64A)
H8/3801 Mask ROM HD6433801H
versions
HD6433801FP
HD6433801P
H8/3800 Mask ROM HD6433800H
versions
HD6433800FP
HD6433800P
HD6433801 (***) FP 64-pin LQFP (FP-64E)
HD6433801 (***) P
64-pin DILP (DP-64S)
HD6433800 (***) H
64-pin QFP (FP-64A)
HD6433800 (***) FP 64-pin LQFP (FP-64E)
HD6433800 (***) P
64-pin DILP (DP-64S)
Note: For mask ROM versions, (***) is the ROM code.
413
Appendix F Package Dimensions
Dimensional drawings of H8/3802 Series packages FP-64A, FP-64E, and DP-64S are shown in
figures F.1, F.2, and F.3 below.
17.2 ± 0.3
Unit: mm
14
33
48
32
0.8
17.2 ± 0.3
49
64
17
1
0.10
*Dimension including the plating thickness
Base material dimension
*0.17 ± 0.05
0.15 ± 0.04
3.05 Max
1.0
2.70
0.15 M
0.10 +0.15
–0.10
*0.37 ± 0.08
0.35 ± 0.06
16
0° – 8°
0.8 ± 0.3
Hitachi Code
JEDEC
EIAJ
Weight (reference value)
Figure F.1 FP-64A Package Dimensions
414
1.6
FP-64A
—
Conforms
1.2 g
Unit: mm
12.0 ± 0.2
10
48
33
32
0.5
12.0 ± 0.2
49
64
17
0.10
*Dimension including the plating thickness
Base material dimension
*0.17 ± 0.05
0.15 ± 0.04
1.25
1.45
0.08 M
1.70 Max
16
0.10 ± 0.10
1
*0.22 ± 0.05
0.20 ± 0.04
1.0
0° – 8°
0.5 ± 0.2
Hitachi Code
JEDEC
EIAJ
Weight (reference value)
FP-64E
—
Conforms
0.4 g
Figure F.2 FP-64E Package Dimensions
415
Unit: mm
33
17.0
18.6 Max
64
57.6
58.5 Max
32
1.0
1.78 ± 0.25
0.48 ± 0.10
0.51 Min
1.46 Max
2.54 Min 5.08 Max
1
19.05
+ 0.11
0.25 – 0.05
0° – 15°
Hitachi Code
JEDEC
EIAJ
Weight (reference value)
Figure F.3 DP-64S Package Dimensions
416
DP-64S
—
Conforms
8.8 g
H8/3802 Series Hardware Manual
Publication Date: 1st Edition, November 1999
2nd Edition, January 2001
Published by:
Electronic Devices Sales & Marketing Group
Semiconductor & Integrated Circuits
Hitachi, Ltd.
Edited by:
Technical Documentation Group
Hitachi Kodaira Semiconductor Co., Ltd.
Copyright © Hitachi, Ltd., 1999. All rights reserved. Printed in Japan.