Data sheet acquired from Cypress Semiconductor Corporation. Data sheet modified to remove devices not offered. CY74FCT163245 CY74FCT163H245 16-Bit Transceivers SCCS051 - February 1997 - Revised March 2000 Features Functional Description • Low power, pin-compatible replacement for LCX and LPT families • 5V tolerant inputs and outputs • 24 mA balanced drive outputs • Power-off disable outputs permits live insertion • Edge-rate control circuitry for reduced noise • FCT-C speed at 4.1 ns • Latch-up performance exceeds JEDEC standard no. 17 • Typical output skew < 250ps • Industrial temperature range of –40˚C to +85˚C • TSSOP (19.6-mil pitch) or SSOP (25-mil pitch) • Typical Volp (ground bounce) performance exceeds Mil Std 883D • VCC = 2.7V to 3.6V • ESD (HBM) > 2000V CY74FCT163H245 • Bus hold on data inputs • Eliminates the need for external pull-up or pull-down resistors • Devices with bus hold are not recommended for translating rail-to-rail CMOS signals to 3.3V logic levels These 16-bit transceivers are designed for use in bidirectional synchronous communication between two buses, where high speed and low power are required. Direction of data flow is controlled by (DIR), the Output Enable (OE) transfers data when LOW and isolates the buses when HIGH. The outputs are 24-mA balanced output drivers with current limiting resistors to reduce the need for external terminating resistors and provide for minimal undershoot and reduced ground bounce.. The CY74FCT163H245 has “bus hold” on the data inputs, which retains the input’s last state whenever the input goes to high impedance. This eliminates the need for pull-up/down resistors and prevents floating inputs. The CY74FCT163245 is designed with inputs and outputs capable of being driven by 5.0V buses, allowing its use in mixed voltage systems as a translator. The outputs are also designed with a power off disable feature enabling its use in applications requiring live insertion. Logic Block Diagrams CY74FCT163245, CY74FCT163H245 1DIR Pin Configuration SSOP/TSSOP Top View 2DIR 1OE 1A1 2OE 1DIR 1 48 1OE 1B1 2 3 47 46 1A1 GND 1B3 4 5 45 44 GND 1A3 1B4 6 43 1A4 2B2 VCC 1B5 7 163245 42 8 163H245 41 VCC 1A5 1B6 9 40 1A6 2B3 GND 10 GND 1B7 11 39 38 1B8 12 13 37 36 1A8 GND 14 15 35 34 GND 2B3 16 33 2A3 2B4 17 32 2A4 VCC 2B5 18 31 19 30 VCC 2A5 2A1 1B1 1A2 1B2 2B1 2A2 1B2 1A3 2A3 1B3 1A4 2A4 1B4 1A5 2B4 2B1 2B2 2A5 1B5 1A6 2B5 2A6 1B6 1A7 2B6 2A7 1B7 1A8 2B7 2A8 1B8 2B8 Copyright 1A2 1A7 2A1 2A2 2B6 20 29 2A6 GND 21 28 GND 2B7 22 27 2A7 2B8 23 26 2A8 2DIR 24 25 2OE © 2000, Texas Instruments Incorporated CY74FCT163245 CY74FCT163H245 Maximum Ratings[3, 4] Pin Description Name (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –55°C to +125°C Description OE Three-State Output Enable Inputs (Active LOW) DIR Direction Control A Inputs or Three-State Outputs[1] Ambient Temperature with Power Applied............................................. –55°C to +125°C B Inputs or Three-State Outputs[1] Supply Voltage Range ........................................0.5V to 4.6V DC Input Voltage ........................................... –0.5V to +7.0V Function Table[2] DC Output Voltage......................................... –0.5V to +7.0V Inputs DC Output Current (Maximum Sink Current/Pin) ........................–60 to +120 mA OE DIR Outputs L L Bus B Data to Bus A L H Bus A Data to Bus B H X High Z State Power Dissipation .......................................................... 1.0W Operating Range Range Industrial Ambient Temperature VCC –40°C to +85°C 2.7V to 3.6V Electrical Characteristics for Non Bus Hold Devices Over the Operating Range VCC=2.7V to 3.6V Parameter Description Test Conditions VIH Input HIGH Voltage VIL Input LOW Voltage All Inputs VH Input Hysteresis[6] VIK Input Clamp Diode Voltage VCC=Min., IIN=–18 mA IIH Input HIGH Current IIL Min. Typ.[5] 2.0 Max. Unit 5.5 V 0.8 V 100 –0.7 mV –1.2 V VCC=Max., VI=5.5 ±1 µA Input LOW Current VCC=Max., VI=GND ±1 µA IOZH High Impedance Output Current (Three-State Output pins) VCC=Max., VOUT=5.5V ±1 µA IOZL High Impedance Output Current (Three-State Output pins) VCC=Max., VOUT=GND ±1 µA IOS Short Circuit Current[7] VCC=Max., VOUT=GND –240 mA IOFF Power-Off Disable VCC=0V, VOUT≤4.5V ±100 µA ICC Quiescent Power Supply Current VIN≤0.2V, VIN>VCC–0.2V VCC=Max. 0.1 10 µA ∆ICC Quiescent Power Supply Current (TTL inputs HIGH) VIN=VCC–0.6V[8] VCC=Max. 2.0 30 µA –60 –135 Note: 1. On the CY74FCT163H245, these pins have bus hold. 2. H = HIGH Voltage Level. L = LOW Voltage Level. X = Don’t Care. Z = High Impedance. 3. Operation beyond the limits set forth may impair the useful life of the device. Unless otherwise noted, these limits are over the operating free-air temperature range. 4. Unused inputs must always be connected to an appropriate logic voltage level, preferably either VCC or ground. 5. Typical values are at VCC=3.3V, TA = +25˚C ambient. 6. This parameter is specified but not tested. 7. Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample and hold techniques are preferable in order to minimize internal chip heating and more accurately reflect operational values. Otherwise prolonged shorting of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests. In any sequence of parameter tests, IOS tests should be performed last. 8. Per TTL driven input; all other inputs at VCC or GND. 2 CY74FCT163245 CY74FCT163H245 Electrical Characteristics For Bus Hold Devices Over the Operating Range VCC=2.7V to 3.6V Parameter Description Test Conditions VIH Input HIGH Voltage All Inputs VIL Input LOW Voltage VH Input Hysteresis[6] VIK Input Clamp Diode Voltage VCC=Min., IIN=–18 mA IIH Input HIGH Current VCC=Max., VI=VCC IIL Input LOW Current Min. Typ.[5] 2.0 Max. Unit VCC V 0.8 100 [9] VCC=Min. V mV –0.7 –1.2 V ±100 µA ±100 µA VI=2.0V –50 µA VI=0.8V +50 µA IBBH IBBL Bus Hold Sustain Current on Bus Hold Input IBHHO IBHLO Bus Hold Overdrive Current on Bus Hold Input[9] VCC=Max., VI=1.5V IOZH High Impedance Output Current (Three-State Output pins) IOZL ±500 µA VCC=Max., VOUT=VCC ±1 µA High Impedance Output Current (Three-State Output pins) VCC=Max., VOUT=GND ±1 µA IOS Short Circuit Current[7] VCC=Max., VOUT=GND –240 mA IOFF Power-Off Disable VCC=0V, VOUT≤4.5V ±100 µA ICC Quiescent Power Supply Current VIN≤0.2V, VIN>VCC–0.2V VCC=Max. +40 µA ∆ICC Quiescent Power supply Current (TTL inputs HIGH) VIN=VCC–0.6V[8] VCC=Max. +350 µA –60 –135 Electrical Characteristics For Balanced Drive Devices Over the Operating Range VCC=2.7V to 3.6V Parameter Test Conditions Max. Unit IODL Output LOW Dynamic VCC=3.3V, VIN=VIH or VIL, VOUT=1.5V 45 180 mA IODH Output HIGH Dynamic Current[7] VCC=3.3V, VIN=VIH or VIL, VOUT=1.5V –45 –180 mA VOH Output HIGH Voltage VCC=Min., IOH= –0.1 mA Output LOW Voltage Min. Typ.[5] Current[7] VOL Description VCC–0.2 V VCC=Min., IOH= –8 mA 2.4[10] 3.0 VCC=3.0V, IOH= –24 mA 2.0 3.0 VCC=Min., IOL= 0.1mA V V 0.2 VCC=Min., IOL= 24 mA 0.3 V 0.55 Notes: 9. Pins with bus hold are described in Pin Description. 10. VOH=VCC–0.6V at rated current. Capacitance[6](TA = +25˚C, f = 1.0 MHz) Parameter Description Test Conditions Typ.[5] Max. Unit CIN Input Capacitance VIN = 0V 4.5 6.0 pF COUT Output Capacitance VOUT = 0V 5.5 8.0 pF 3 CY74FCT163245 CY74FCT163H245 Power Supply Characteristics Parameter Description Test Conditions Typ.[5] Max. Unit ICCD Dynamic Power Supply Current[11] VCC=Max., One Input Toggling, VIN=VCC or 50% Duty Cycle, VIN=GND Outputs Open, OE=GND 50 75 µA/MHz IC Total Power Supply Current[12] VCC=Max., f1=10 MHz, 50% VIN=VCC or Duty Cycle, Outputs Open, One VIN=GND Bit Toggling, OE=GND VIN=VCC–0.6V or VIN=GND 0.5 0.8 mA 0.5 0.8 mA VCC=Max., f1=2.5 MHz, 50% VIN=VCC or Duty Cycle, Outputs Open, Six- VIN=GND teen Bits Toggling, OE=GND VIN=VCC–0.6V or VIN=GND 2.0 3.0[13] mA 2.0 3.3[13] mA Switching Characteristics Over the Operating Range VCC=3.0V to 3.6V[14,15] CY74FCT163245A CY74FCT163H245A CY74FCT163245C CY74FCT163H245C Description Min. Max. Min. Max. Unit Fig. No.[16] tPLH tPHL Propagation Delay Data to Output 1.5 4.8 1.5 4.1 ns 1, 3 tPZH tPZL Output Enable Time 1.5 6.2 1.5 5.8 ns 1, 7, 8 tPHZ tPLZ Output Disable Time 1.5 5.6 1.5 5.2 ns 1, 7, 8 tSK(O) Output Skew[17] 0.5 ns — Parameter 0.5 Notes: 11. This parameter is not directly testable, but is derived for use in Total Power Supply calculations. 12. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC+∆ICCDHNT+ICCD(f0/2 + f1N1) ICC = Quiescent Current with CMOS input levels ∆ICC = Power Supply Current for a TTL HIGH input (VIN=3.4V) DH = Duty Cycle for TTL inputs HIGH NT = Number of TTL inputs at DH ICCD = Dynamic Current caused by an input transition pair (HLH or LHL) = Clock frequency for registered devices, otherwise zero f0 = Input signal frequency f1 N1 = Number of inputs changing at f1 All currents are in milliamps and all frequencies are in megahertz. 13. Values for these conditions are examples of the ICC formula. These limits are specified but not tested. 14. Minimum limits are specified but not tested on Propagation Delays. 15. For VCC =2.7, propagation delay, output enable and output disable times should be degraded by 20%. 16. See “Parameter Measurement Information” in the General Information section. 17. Skew between any two outputs of the same package switching in the same direction. This parameter is ensured by design. Ordering Information CY74FCT163245 Speed (ns) 4.1 4.8 Ordering Code Package Name Package Type CY74FCT163245CPACT Z48 48-Lead (240-Mil) TSSOP CY74FCT163245CPVC/PVCT O48 48-Lead (300-Mil) SSOP CY74FCT163245APACT Z48 48-Lead (240-Mil) TSSOP CY74FCT163245APVC/PVCT O48 48-Lead (300-Mil) SSOP 4 Operating Range Industrial Industrial CY74FCT163245 CY74FCT163H245 Ordering Information CY74FCT163H245 Speed (ns) 4.1 4.8 Ordering Code Package Name Package Type 74FCT163H245CPACT Z48 48-Lead (240-Mil) TSSOP CY74FCT163H245CPVC O48 48-Lead (300-Mil) SSOP 74FCT163H245CPVCT O48 48-Lead (300-Mil) SSOP CY74FCT163H245APVC O48 48-Lead (300-Mil) SSOP 74FCT163H245APVCT O48 48-Lead (300-Mil) SSOP 5 Operating Range Industrial Industrial CY74FCT163245 CY74FCT163H245 Package Diagrams 48-Lead Shrunk Small Outline Package O48 48-Lead Thin Shrunk Small Outline Package Z48 6 PACKAGE OPTION ADDENDUM www.ti.com 30-Mar-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) 74FCT163H245APVCT OBSOLETE SSOP DL 48 TBD Call TI Call TI 74FCT163H245CPACT OBSOLETE TSSOP DGG 48 TBD Call TI Call TI 74FCT163H245CPVCT OBSOLETE SSOP DL 48 TBD Call TI Call TI CY74FCT163245APAC OBSOLETE TSSOP DGG 48 TBD Call TI Call TI CY74FCT163245APACT OBSOLETE TSSOP DGG 48 TBD Call TI Call TI CY74FCT163245APVC OBSOLETE SSOP DL 48 TBD Call TI Call TI CY74FCT163245APVCT OBSOLETE SSOP DL 48 TBD Call TI Call TI CY74FCT163245CPAC OBSOLETE TSSOP DGG 48 TBD Call TI Call TI CY74FCT163245CPACT OBSOLETE TSSOP DGG 48 TBD Call TI Call TI CY74FCT163245CPVC OBSOLETE SSOP DL 48 TBD Call TI Call TI CY74FCT163245CPVCT OBSOLETE SSOP DL 48 TBD Call TI Call TI CY74FCT163H245APVC OBSOLETE SSOP DL 48 TBD Call TI Call TI CY74FCT163H245CPAC OBSOLETE TSSOP DGG 48 TBD Call TI Call TI CY74FCT163H245CPVC OBSOLETE SSOP DL 48 TBD Call TI Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 1 MECHANICAL DATA MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001 DL (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0.025 (0,635) 0.0135 (0,343) 0.008 (0,203) 48 0.005 (0,13) M 25 0.010 (0,25) 0.005 (0,13) 0.299 (7,59) 0.291 (7,39) 0.420 (10,67) 0.395 (10,03) Gage Plane 0.010 (0,25) 1 0°–ā8° 24 0.040 (1,02) A 0.020 (0,51) Seating Plane 0.110 (2,79) MAX 0.004 (0,10) 0.008 (0,20) MIN PINS ** 28 48 56 A MAX 0.380 (9,65) 0.630 (16,00) 0.730 (18,54) A MIN 0.370 (9,40) 0.620 (15,75) 0.720 (18,29) DIM 4040048 / E 12/01 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). Falls within JEDEC MO-118 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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