ON MT9V024IA7XTM-TR 1/3-inch wide vga cmos digital image sensor Datasheet

MT9V024/D
1/3-Inch Wide VGA CMOS
Digital Image Sensor
Description
The MT9V024 is a 1/3−inch wide−VGA format CMOS active−pixel
digital image sensor with global shutter and high dynamic range
(HDR) operation. The sensor has specifically been designed to support
the demanding interior and exterior automotive imaging needs, which
makes this part ideal for a wide variety of imaging applications in
real−world environments.
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Table 1. KEY PERFORMANCE PARAMETERS
Parameter
Value
Optical Format
1/3-inch
Active Imager Size
4.51 mm (H) × 2.88 mm (V)
5.35 mm Diagonal
Active Pixels
752 H × 480 V
Pixel Size
6.0 m × 6.0 m
Color Filter Array
Monochrome or Color RGB Bayer or RCCC Pattern
Shutter Type
Global Shutter
Maximum Data Rate
Master Clock
27 Mp/s
27 MHz
Full Resolution
752 × 480
Frame Rate
60 fps (at Full Resolution)
ADC Resolution
10−bit Column−Parallel
Responsivity
4.8 V/lux−sec (550 nm)
Dynamic Range
> 55 dB Linear;
> 100 dB in HDR Mode
Supply Voltage
3.3 V ± 0.3 V (All Supplies)
Power Consumption
< 160 mW at Maximum Data Rate (LVDS
Disabled);
120 W Standby Power at 3
Operating Temperature
−40°C to + 105°C
Packaging
52−ball iBGA, Automotive−qualified; Wafer or Die
IBGA52
CASE 503AA
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of
this data sheet.
Features (continued)
• Window Size: User Programmable to Any
•
•
•
•
Features
• Array Format: Wide−VGA, Active 752 H x 480 V
(360,960 pixels)
•
Readout
RGB Bayer, Monochrome, or RCCC: NIR Enhanced Performance
for Use with Non−visible NIR Illumination
Readout Modes: Progressive or Interlaced
Shutter Efficiency: >99%
Simple Two−Wire Serial Interface
Real−Time Exposure Context Switching−Dual Register Set
Register Lock Capability
•
• Global Shutter Photodiode Pixels; Simultaneous Integration and
•
•
•
•
•
•
© Semiconductor Components Industries, LLC, 2006
December, 2017 − Rev. 7
1
Smaller Format (QVGA, CIF, QCIF). Data
Rate Can Be Maintained Independent of
Window Size
Binning: 2 x 2 and 4 x 4 of The Full Resolution
ADC: On−Chip, 10−bit Column−Parallel
(Option to Operate in 12−bit to 10−bit
Companding Mode)
Automatic Controls: Auto Exposure Control
(AEC) and Auto Gain Control (AGC); Variable Regional and Variable Weight AEC/
AGC
Support for Four Unique Serial Control
Register IDs to Control Multiple Imagers on
the Same Bus
Data Output Formats:
♦ Single Sensor Mode:
10−bit Parallel/Stand−Alone
8−bit or 10−bit Serial LVDS
♦ Stereo Sensor Mode: Interspersed 8−bit
Serial LVDS
High Dynamic Range (HDR) Mode
Publication Order Number:
MT9V024/D
MT9V024/D
•
•
•
•
Applications
• Automotive
• Unattended Surveillance
• Stereo Vision
Smart vision
Automation
Video as input
Machine vision
ORDERING INFORMATION
Table 2. AVAILABLE PART NUMBERS
Part Number
Product Description
Orderable Product Attribute Description
MT9V024D00XTCC13CC1−200
VGA 1/3” GS CIS
Die Sales, 200m Thickness
MT9V024D00XTMC13CC1−200
VGA 1/3” GS CIS
Die Sales, 200m Thickness
MT9V024D00XTRC13CC1-200
VGA 1/3” GS CIS
Die Sales, 200m Thickness
MT9V024D00XTRC13CC1-400
VGA 1/3” GS CIS
Die Sales, 400m Thickness
MT9V024IA7XTC-DP
VGA 1/3” GS CIS
Dry Pack with Protective Film
MT9V024IA7XTC-DR
VGA 1/3” GS CIS
Dry Pack without Protective Film
MT9V024IA7XTM-DP
VGA 1/3” GS CIS
Dry Pack with Protective Film
MT9V024IA7XTM-DR
VGA 1/3” GS CIS
Dry Pack without Protective Film
MT9V024IA7XTM-TP
WVGA 1/3” GS CIS
Tape & Reel with Protective Film
MT9V024IA7XTM-TR
WVGA 1/3” GS CIS
Tape & Reel without Protective Film
MT9V024IA7XTR-DP
VGA 1/3” GS CIS
Dry Pack with Protective Film
MT9V024IA7XTR-DR
VGA 1/3” GS CIS
Dry Pack without Protective Film
MT9V024IA7XTR-TP
VGA 1/3” GS CIS
Tape & Reel with Protective Film
MT9V024IA7XTR-TR
VGA 1/3” GS CIS
Tape & Reel without Protective Film
GENERAL DESCRIPTION
The MT9V024 is a 1/3−inch wide−VGA format CMOS
active−pixel digital image sensor with global shutter and
high dynamic range (HDR) operation. The sensor has
specifically been designed to support the demanding interior
and exterior automotive imaging needs, which makes this
part ideal for a wide variety of imaging applications in
real−world environments.
This wide−VGA CMOS image sensor features ON
Semiconductor’s breakthrough low−noise CMOS imaging
technology that achieves CCD image quality (based on
signal−to−noise ratio and low−light sensitivity) while
maintaining the inherent size, cost, and integration
advantages of CMOS.
The active imaging pixel array is 752H x 480V. It
incorporates sophisticated camera functions on−chip−such
as binning 2 x 2 and 4 x 4, to improve sensitivity when
operating in smaller resolutions−as well as windowing,
column and row mirroring. It is programmable through
a simple two−wire serial interface.
The MT9V024 can be operated in its default mode or be
programmed for frame size, exposure, gain setting, and
other parameters. The default mode outputs
a wide−VGA−size image at 60 frames per second (fps).
An on−chip analog−to−digital converter (ADC) provides
10 bits per pixel. A 12−bit resolution companded for 10 bits
for small signals can be alternatively enabled, allowing more
accurate digitization for darker areas in the image.
In addition to a traditional, parallel logic output the
MT9V024 also features a serial low−voltage differential
signaling (LVDS) output. The sensor can be operated in
a stereo−camera, and the sensor, designated as
a stereo−master, is able to merge the data from itself and the
stereo−slave sensor into one serial LVDS stream.
The sensor is designed to operate in a wide temperature
range (–40_C to + 105_C).
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MT9V024/D
Serial
Register
I/O
Control Register
Active−Pixel
Sensor (APS)
Array
752 H x 480 V
Timing and Control
Analog
Processing
ADCs
Parallel
Video
Data Out
Digital Processing
Slave Video LVDS In
(for stereo applications only)
Serial Video
LVDS Out
Figure 1. Block Diagram
1
2
VDD
LVDS
SER
DATA
OUT P
SER
DATA
OUT N
VDD
LVDS
SYS−
CLK
LVDS
GND
SHFT
CLKOUT
P
SHFT_
CLKOUT
N
VDD
PIXCLK
C
BYPASS
_CLKIN
_P
BYPASS
_CLKIN
_N
LVDS
GND
D
SER
DATA IN
_P
A
B
E
3
4
5
6
7
8
DOUT0
DOUT2
DOUT3
DOUT1
DOUT4
VAAPIX
DGND
AGND
VAA
SER
DATIN
_N
NC
NC
DOUT5
VDD
NC
NC
DOUT6
DOUT7
DGND
AGND
VAA
STAND−
BY
DOUT8
FRAME_
VALID
STLN_
OUT
SDATA
STFRM_
OUT
LED_
OUT
S_CTRL
_ADR0
RESET_
BAR
DOUT9
LINE_
VALID
EXPO−
SURE
SCLK
ERROR
OE
RSVD
S_CTRL
_ADR1
F
G
H
Figure 2. Top View (Ball Down)
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3
MT9V024/D
BALL DESCRIPTIONS
Table 3. BALL DESCRIPTIONS
52−Ball IBA
Numbers
Symbol
Type
H7
RSVD
Input
Connect to DGND
D2
SER_DATAIN_N
Input
Serial data in for stereoscopy (differential negative). Tie to 1 k pull−up (to 3.3 V)
in non−stereoscopy mode
D1
SER_DATAIN_P
Input
Serial data in for stereoscopy (differential positive). Tie to DGND in
non−stereoscopy mode
C2
BYPASS_CLKIN_N
Input
Input bypass shift−CLK (differential negative). Tie to 1 k pull−up
(to 3.3 V) in non−stereoscopy mode
C1
BYPASS_CLKIN_P
Input
Input bypass shift−CLK (differential positive). Tie to DGND in
non−stereoscopy mode
H3
EXPOSURE
Input
Rising edge starts exposure in snapshot and slave modes
H4
SCLK
Input
Two−wire serial interface clock. Connect to VDD with 1.5 k resistor even when no
other two−wire serial interface peripheral is attached
H6
OE
Input
DOUT enable pad, active HIGH
G7
S_CTRL_ADR0
Input
Two−wire serial interface slave address select (see Table 4 on page 12)
H8
S_CTRL_ADR1
Input
Two−wire serial interface slave address select (see Table 4 on page 12)
G8
RESET_BAR
Input
Asynchronous reset. All registers assume defaults
F8
STANDBY
Input
Shut down sensor operation for power saving
A5
SYSCLK
Input
Master clock (26.6 MHz; 13 MHz – 27 MHz)
G4
SDATA
I/O
Two−wire serial interface data. Connect to VDD with 1.5 k resistor even when no
other two−wire serial interface peripheral is attached
G3
STLN_OUT
I/O
Output in master mode−start line sync to drive slave chip in−phase; input in slave
mode
G5
STFRM_OUT
I/O
Output in master mode−start frame sync to drive a slave chip in−phase; input in
slave mode
H2
LINE_VALID
Output
Asserted when DOUT data is valid
G2
FRAME_VALID
Output
Asserted when DOUT data is valid
E1
DOUT5
Output
Parallel pixel data output 5
F1
DOUT6
Output
Parallel pixel data output 6
F2
DOUT7
Output
Parallel pixel data output 7
G1
DOUT8
Output
Parallel pixel data output 8
H1
DOUT9
Output
Parallel pixel data output 9
H5
ERROR
Output
Error detected. Directly connected to STEREO ERROR FLAG
G6
LED_OUT
Output
LED strobe output
B7
DOUT4
Output
Parallel pixel data output 4
A8
DOUT3
Output
Parallel pixel data output 3
A7
DOUT2
Output
Parallel pixel data output 2
B6
DOUT1
Output
Parallel pixel data output 1
A6
DOUT0
Output
Parallel pixel data output 0
B5
PIXCLK
Output
Pixel clock out. DOUT is valid on rising edge of this clock
B3
SHFT_CLKOUT_N
Output
Output shift CLK (differential negative)
B2
SHFT_CLKOUT_P
Output
Output shift CLK (differential positive)
Descriptions
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4
MT9V024/D
52−Ball IBA
Numbers
Symbol
Type
A3
SER_DATAOUT_N
Output
Serial data out (differential negative)
A2
SER_DATAOUT_P
Output
Serial data out (differential positive)
B4, E2
VDD
Supply
Digital power 3.3 V
C8, F7
VAA
Supply
Analog power 3.3 V
B8
VAAPIX
Supply
Pixel power 3.3 V
A1, A4
VDDLVDS
Supply
Dedicated power for LVDS pads
B1, C3
LVDSGND
Ground
Dedicated GND for LVDS pads
C6, F3
DGND
Ground
Digital GND
C7, F6
AGND
Ground
Analog GND
E7, E8, D7, D8
NC
NC
Descriptions
No connect (Note 3)
1. Pin H7 (RSVD) must be tied to GND.
2. Output enable (OE) tri−states signals DOUT0−DOUT9, LINE_VALID, FRAME_VALID, and PIXCLK.
3. No connect. These pins must be left floating for proper operation.
10K
1.5K
VDDLVDS
VDD
VAA
VDD
VAA
STANDBY from
Controller or
Digital GND
Two−Wire
Serial Interface
RSVD
VAAPIX
DOUT(9:0)
LINE_VALID
SYSCLK
OE
RESET_BAR
EXPOSURE
STANDBY
S_CTRL_ADR0
S_CTRL_ADR1
SCLK
SDATA
Master Clock
VAAPIX
FRAME_VALID
PIXCLK
LED_OUT
ERROR
DGND LVDSGND
To Controller
To LED Output
AGND
0.1F
NOTE:
LVDS signals are to be left floating.
Figure 3. Typical Configuration (Connection)−Parallel Output Mode
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MT9V024/D
PIXEL DATA FORMAT
Pixel Array Structure
753 columns by 481 rows of optically active pixels. While
the sensor’s format is 752 x 480, one additional active
column and active row are included for use when horizontal
or vertical mirrored readout is enabled, to allow readout to
start on the same pixel. This one pixel adjustment is always
performed, for monochrome or color versions. The active
area is surrounded with optically transparent dummy pixels
to improve image uniformity within the active area. Neither
dummy pixels nor barrier pixels can be read out.
The MT9V024 pixel array is configured as 809 columns
by 499 rows, shown in Figure 1. The dark pixels are optically
black and are used internally to monitor black level. Of the
left 52 columns, 36 are dark pixels used for row noise
correction. Of the top 14 rows of pixels, two of the dark rows
are used for black level correction. Also, three black rows
from the top black rows can be read out by setting the show
dark rows bit in the Read Mode register; setting show dark
columns will display the 36 dark columns. There are
(0, 0)
Active pixel
2 barrier + 8 (2 + 4 addressed + 2 light dummy)
4.92 x 3.05 mm2
Pixel Array
809 x 499 (753 x 481 active)
6.0 m pixel
Light dummy
pixel
Dark pixel
3 barrier + 36 addressed +1) dark
+ 9 barrier + light dummy
2 barrier + 2 light dummy)
2 barrier + 2 light dummy)
Barrier pixel
Figure 4. Pixel Array Description
Column Readout Direction
Column Readout Direction
..
.
..
.
Active Pixel (0, 0)
Array Pixel (4, 14)
G B
Row
Readout
Direction
G
B
G
B
G
Active Pixel (0, 0)
Array Pixel (4, 14)
B
C
C
C C
C R C
R C
C
C C
C
C C
C
R G
R G
G B
G
G
R G
R G
R G
R G
C R C
R C
G B
G
G
G
B
C C
C
R G
R G
R G
C R
B
B
B
R G
G
B
..
.
C
R
C
C
C C
C
C R
C R
C
..
.
Figure 5. Pixel Color Pattern Detail
(Top Right Corner)
C
R
R G
B
R G
C C
Row
Readout
Direction
Figure 6. Pixel Color Pattern Detail RCCC
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MT9V024/D
COLOR (RGB BAYER) DEVICE LIMITATIONS
The color version of the MT9V024 does not support or
offers reduced performance for the following
functionalities.
set (R0x0F[1] = 1). However, the color bit also applies
unequal offset to the color planes, and the results might not
be acceptable for some applications.
Other Limiting Factors
Black level correction and row−wise noise correction are
applied uniformly to each color. The row−wise noise
correction algorithm does not work well in color sensors.
Automatic exposure and gain control calculations are made
based on all three colors, not just the green channel. High
dynamic range does operate in color; however,
ON Semiconductor strongly recommends limiting use to
linear operation where good color fidelity is required.
Pixel Binning
Pixel binning is done on immediate neighbor pixels only,
no facility is provided to skip pixels according to a Bayer
pattern. Therefore, the result of binning combines pixels of
different colors. See “Pixel Binning” for additional
information.
Interlaced Readout
Interlaced readout yields one field consisting only of red
and green pixels and another consisting only of blue and
green pixels. This is due to the Bayer pattern of the CFA.
OUTPUT DATA FORMAT
The MT9V024 image data can be read out in a progressive
scan or interlaced scan mode. Valid image data is surrounded
by horizontal and vertical blanking, as shown in Figure 7.
The amount of horizontal and vertical blanking is
programmable through R0x05 and R0x06, respectively
(R0xCD and R0xCE for context B). LV is HIGH during the
shaded region of the figure. See “Output Data Timing” for
the description of FV timing.
Automatic Black Level Calibration
When the color bit is set (R0x0F[1]=1), the sensor uses
black level correction values from one green plane, which
are applied to all colors. To use the calibration value based
on all dark pixels’ offset values, the color bit should be
cleared.
Defective Pixel Correction
For defective pixel correction to calculate replacement
pixel values correctly, for color sensors the color bit must be
P0,0 P0,1 P0,2…………P0,n−1 P0,n
00 00 00 ………… 00 00 00
00 00 00 ………… 00 00 00
P1,0 P1,1 P1,2…………P1,n−1 P1,n
VALID iMAGE
HORIZONTAL
BLANKING
Pm−1,0 Pm−1,1…………Pm−1,n−1 Pm−1,n
Pm,0 Pm,1…………Pm,n−1 Pm,n
00 00 00 ………… 00 00 00
00 00 00 ………… 00 00 00
00 00 00 ………… 00 00 00
00 00 00 ………… 00 00 00
00 00 00 ………… 00 00 00
00 00 00 ………… 00 00 00
VERTICAL BLANKING
VERTICAL/HORIZONTAL
BLANKING
00 00 00 ………… 00 00 00
00 00 00 ………… 00 00 00
00 00 00 ………… 00 00 00
00 00 00 ………… 00 00 00
Figure 7. Spatial Illustration of Image Readout
Output Data Timing
The data output of the MT9V024 is synchronized with the
PIXCLK output. When LINE_VALID (LV) is HIGH, one
10−bit pixel datum is output every PIXCLK period.
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7
MT9V024/D
…
LINE_VALID
…
PIXCLK
Blanking
…
Valide Image Data
DOUT(9:0)
P2
(9:0)
P1
(9:0)
P0
(9:0)
P3
(9:0)
P4
(9:0)
…
Blanking
Pn−1
(9:0)
Pn
(9:0)
Figure 8. Timing Example of Pixel Data
The PIXCLK is a nominally inverted version of the master
clock (SYSCLK). This allows PIXCLK to be used as a clock
to latch the data. However, when column bin 2 is enabled, the
PIXCLK is HIGH for one complete master clock master
period and then LOW for one complete master clock period;
when column bin 4 is enabled, the PIXCLK is HIGH for two
complete master clock periods and then LOW for two
complete master clock periods. It is continuously enabled,
even during the blanking period. Setting R0x72 bit[4] = 1
causes the MT9V024 to invert the polarity of the PIXCLK.
The parameters P1, A, Q, and P2 in Figure 9 are defined
in Table 2.
...
FRAME_VALID
...
LINE_VALID
Number of master clocks
P1
A
Q
...
A
Q
A
P2
Figure 9. Row Timing and FRAME_VALID/LINE_VALID Signals
Table 4. FRAME TIME
Parameter
Name
A
Active data time
P1
Equation
Default Timing at 26.66 MHz
Context A: R0x04
Context B: R0xCC
752 pixel clocks
= 752 master = 28.20 s
Frame start blanking
Context A: R0x05 − 23
Context B: R0xCD − 23
71 pixel clocks
= 71master = 2.66 s
P2
Frame end blanking
23 (fixed)
23 pixel clocks
= 23 master = 0.86 s
Q
Horizontal blanking
Context A: R0x05
Context B: R0xCD
94 pixel clocks
= 94 master = 3.52 s
A+Q
Row time
Context A: R0x04 + R0x05
Context B: R0xCC + R0xCD
846 pixel clocks
= 846 master = 31.72 s
V
Vertical blanking
Context A: (R0x03) x (A + Q) + 4
Context B: (R0xCB) x (A + Q) + 4
38,074 pixel clocks
= 38,074 master = 1.43 ms
Nrows x (A + Q)
Frame valid time
Context A: (R0x03) x (A + Q)
Context B: (R0xCB) x (A + Q)
406,080 pixel clocks
= 406,080 master = 15.23 ms
F
Total frame time
V + (Nrows x (A + Q))
444,154 pixel clocks
= 444,154 master = 16.66 ms
Sensor timing is shown above in terms of pixel clock and
master clock cycles (refer to Figure 8). The recommended
master clock frequency is 26.66 MHz. The vertical blanking
and the total frame time equations assume that the
integration time (coarse shutter width plus fine shutter
width) is less than the number of active rows plus the
blanking rows minus the overhead rows:
Window Height ) Vertical Blanking * 2
(eq. 1)
If this is not the case, the number of integration rows must
be used instead to determine the frame time, as shown in
Table 3. In this example, it is assumed that the coarse shutter
width control is programmed with 523 rows and the fine
shutter width total is zero.
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MT9V024/D
For Simultaneous mode, if the exposure time registers
(coarse shutter width total plus Fine Shutter Width Total)
exceed the total readout time, then the vertical blanking time
is internally extended automatically to adjust for the
additional integration time required. This extended value is
not written back to the vertical blanking registers. The
vertical blank register can be used to adjust frame−to−frame
readout time. This register does not affect the exposure time
but it may extend the readout time.
Table 5. FRAME TIME − LONG INTEGRATION TIME
Parameter
Equation
(Number of Master Clock Cycles)
Name
Default Timing at 26.66 MHz
V’
Vertical blanking (long integration
time)
Context A: (R0x0B + 2 − R0x03) ×
(A + Q) + R0xD5 + 4
Context B: (R0xD2 + 2 − R0xCB) ×
(A + Q) + R0xD8 + 4
38,074 pixel clocks
= 38,074 master = 1.43ms
F”
Total frame time (long integration
exposure time)
(R0x0B + 2) × (A + Q) + 4
444,154 pixel clocks
= 444,154 master = 16.66ms
4. The MT9V024 uses column parallel analog−digital converters; thus short row timing is not possible. The minimum total row time is 704
columns (horizontal width + horizontal blanking). The minimum horizontal blanking is 61 for normal mode, 71 for column bin 2 mode, and 91
for column bin 4 mode. When the window width is set below 643, horizontal blanking must be increased. In binning mode, the minimum row
time is R0x04+R0x05 = 704.
SERIAL BUS DESCRIPTION
Registers are written to and read from the MT9V024
through the two−wire serial inter−face bus. The MT9V024
is a serial interface slave with four possible IDs (0x90, 0x98,
0xB0 and 0xB8) determined by the S_CTRL_ADR0 and
S_CTRL_ADR1 input pins. Data is transferred into the
MT9V024 and out through the serial data (SDATA) line. The
SDATA line is pulled up to VDD off−chip by a 1.5 k resistor.
Either the slave or master device can pull the SDATA line
down−the serial interface protocol determines which device
is allowed to pull the SDATA line down at any given time. The
registers are 16−bit wide, and can be accessed through 16−or
8−bit two−wire serial interface sequences.
indicates an acknowledge bit by pulling the data line LOW
during the acknowledge clock pulse.
No−Acknowledge Bit
The no−acknowledge bit is generated when the data line
is not pulled down by the receiver during the acknowledge
clock pulse. A no−acknowledge bit is used to terminate
a read sequence.
Stop Bit
The stop bit is defined as a LOW−to−HIGH transition of
the data line while the clock line is HIGH.
Sequence
Protocol
A typical READ or WRITE sequence begins by the
master sending a start bit. After the start bit, the master sends
the slave device’s 8−bit address. The last bit of the address
determines if the request is a read or a write, where a “0”
indicates a WRITE and a “1” indicates a READ. The slave
device acknowledges its address by sending an
acknowledge bit back to the master.
If the request was a WRITE, the master then transfers the
8−bit register address to which a WRITE should take place.
The slave sends an acknowledge bit to indicate that the
register address has been received. The master then transfers
the data 8 bits at a time, with the slave sending an
acknowledge bit after each 8 bits. The MT9V024 uses
16−bit data for its internal registers, thus requiring two 8−bit
transfers to write to one register. After 16 bits are transferred,
the register address is automatically incremented, so that the
next 16 bits are written to the next register address. The
master stops writing by sending a start or stop bit.
A typical READ sequence is executed as follows. First the
master sends the write mode slave address and 8−bit register
address, just as in the write request. The master then sends
a start bit and the read mode slave address. The master then
1. a start bit
2. the slave device 8−bit address
3. a(n) (no) acknowledge bit
4. an 8−bit message
5. a stop bit
Start Bit
The start bit is defined as a HIGH−to−LOW transition of
the data line while the clock line is HIGH.
Slave Address
The 8−bit address of a two−wire serial interface device
consists of 7 bits of address and
1 bit of direction. A “0” in the LSB of the address indicates
write mode, and a “1” indicates read mode. As indicated
above, the MT9V024 allows four possible slave addresses
determined by the two input pins, S_CTRL_ADR0 and
S_CTRL_ADR1.
Acknowledge Bit
The master generates the acknowledge clock pulse. The
transmitter (which is the master when writing, or the slave
when reading) releases the data line, and the receiver
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MT9V024/D
and then writing (or reading) the least significant 8 bits to
byte−wise address register (0x0F0).
clocks out the register data 8 bits at a time. The master sends
an acknowledge bit after each 8−bit transfer. The register
address is automatically incremented after every 16 bits is
transferred. The data transfer is stopped when the master
sends a no−acknowledge bit. The MT9V024 allows for 8−bit
data transfers through the two−wire serial interface by
writing (or reading) the most significant 8 bits to the register
Bus Idle State
The bus is idle when both the data and clock lines are
HIGH. Control of the bus is initiated with a start bit, and the
bus is released with a stop bit. Only the master can generate
the start and stop bits.
Table 6. SLAVE ADDRESS MODES
{S_CTRL_ADR1, S_CTRL_ADR0}
Slave Address
Write/Read Mode
00
0x90
Write
0x91
Read
0x98
Write
0x99
Read
0xB0
Write
0xB1
Read
01
10
11
Data Bit Transfer
0xB8
Write
0xB9
Read
the serial clock−it can only change when the two−wire serial
interface clock is LOW. Data is transferred 8 bits at a time,
followed by an acknowledge bit.
One data bit is transferred during each clock pulse. The
two−wire serial interface clock pulse is provided by the
master. The data must be stable during the HIGH period of
TWO−WIRE SERIAL INTERFACE SAMPLE READ AND WRITE SEQUENCES
16−Bit Write Sequence
After each 8−bit word is sent, the image sensor gives an
A typical write sequence for writing 16 bits to a register
acknowledge bit. All 16 bits must be written before the
is shown in Figure 10. A start bit given by the master,
register is updated. After 16 bits are transferred, the register
followed by the write address, starts the sequence. The
address is automatically incremented, so that the next 16 bits
image sensor then gives an acknowledge bit and expects the
are written to the next register. The master stops writing by
register address to come first, followed by the 16−bit data.
sending a start or stop bit.
SCLK
SDATA
R0x09
0xB8 ADDR
START
1000 0100
0000 0010
ACK
ACK
STOP
ACK
ACK
Figure 10. Timing Diagram Showing a Write to R0x09 with Value 0x0284
16−Bit Read Sequence
clocks out the register data 8 bits at a time. The master sends
an acknowledge bit after each 8−bit transfer. The register
address is auto−incremented after every 16 bits is
transferred. The data transfer is stopped when the master
sends a no−acknowledge bit.
A typical read sequence is shown in Figure 11. First the
master has to write the register address, as in a write
sequence. Then a start bit and the read address specify that
a read is about to happen from the register. The master then
SCLK
SDATA
0xB8 ADDR
START
0xB9 ADDR
R0x09
ACK
ACK
0000 0010
ACK
1000 0100
ACK
Figure 11. Timing Diagram Showing a Read from R0x09; Returned Value 0x0284
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10
STOP
NACK
MT9V024/D
8−Bit Write Sequence
To be able to write 1 byte at a time to the register, a special
register address is added. The 8−bit write is done by first
writing the upper 8 bits to the desired register and then
writing the lower 8 bits to the special register address
(R0xF0). The register is not updated until all 16 bits have
been written. It is not possible to just update half of a register.
In Figure 12, a typical sequence for 8−bit writing is shown.
The second byte is written to the special register (R0xF0).
SCLK
0xB8 ADDR
SDATA
START
0000 0010
R0x09
ACK
ACK
ACK
START
1000 0100
R0xF0
0xB8 ADDR
STOP
ACK
ACK
ACK
Figure 12. Timing Diagram Showing a Bytewise Write to R0x09 with Value 0x0284
8−Bit Read Sequence
To read one byte at a time the same special register address
is used for the lower byte. The upper 8 bits are read from the
desired register. By following this with a read from the
byte−wise address register (R0xF0) the lower 8 bits are
accessed (Figure 13). The master sets the no−acknowledge
bits shown.
SCLK
SDATA
0xB8 ADDR
0xB9 ADDR
R0x09
0000 0010
START
START
ACK
ACK
NACK
ACK
SCLK
SDATA
0xB8 ADDR
0xB9 ADDR
R0xF0
1000 0100
STOP
START
START
ACK
ACK
ACK
NACK
Figure 13. Timing Diagram Showing a Bytewise Read from R0x09; Returned Value 0x0284
Register Lock
Lock All Registers
Included in the MT9V024 is a register lock (R0xFE)
feature that can be used as a solution to reduce the
probability of an inadvertent noise−triggered two−wire
serial interface write to the sensor. All registers, or only read
mode registers − R0x0D and R0x0E can be locked. It is
important to prevent an inadvertent two−wire serial
interface write to the read mode registers in automotive
applications since this register controls the image
orientation and any unintended flip to an image can cause
serious results.
At power−up, the register lock defaults to a value of
0xBEEF, which implies that all registers are unlocked and
any two−wire serial interface writes to the register get
committed.
If a unique pattern (0xDEAD) to R0xFE is programmed,
any subsequent two−wire serial interface writes to registers
(except R0xFE) are NOT committed. Alternatively, if the
user writes a 0xBEEF to the register lock register, all
registers are unlocked and any subsequent two−wire serial
interface writes to the register are committed.
Lock Only Read More Registers (R0x0D and R0x0E)
If a unique pattern (0xDEAF) to R0xFE is programmed,
any subsequent two−wire serial interface writes to register
13 are NOT committed. Alternatively, if the user writes
a 0xBEEF to register lock register, register 13 is unlocked
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MT9V024/D
and any subsequent two−wire serial interface writes to this
register are committed.
change bit in register 0x07. This context switch will change
all registers (no shadowing) at the frame start time and have
the new values apply to the immediate next exposure and
readout time (frame n+1), except for shutter width and
V1−V4 control, which will take effect for next exposure but
will show up in the n+2 image.
Real-Time Context Switching
In the MT9V024, the user may switch between two full
register sets (listed in Table 5) by writing to a context switch
Table 7. REAL−TIME CONTEXT−SWITCHABLE REGISTERS
Register Name
Register Number (Hex) For Context A
Register Number (Hex) for
Context B
Column Start
0x01
0xC9
Row Start
0x02
0xCA
Window Height
0x03
0xCB
Window Width
0x04
0xCC
Horizontal Blanking
0x05
0xCD
Vertical Blanking
0x06
0xCE
Coarse Shutter Width 1
0x08
0xCF
Coarse Shutter Width 2
0x09
0xD0
Coarse Shutter Width Control
0x0A
0xD1
Coarse Shutter Width Total
0x0B
0xD2
Fine Shutter Width 1
0xD3
0xD6
Fine Shutter Width 2
0xD4
0xD7
Fine Shutter Width Total
0xD5
0xD8
Read Mode
0x0D [5:0]
0x0E [5:0]
High Dynamic Range enable
0x0F [0]
0x0F [8]
ADC Resolution Control
0x1C [1:0]
0x1C [9:8]
V1 Control − V4 Control
0x31 − 0x34
0x39 − 0x3C
Analog Gain Control
0x35
0x36
Row Noise Correction Control 1
0x70 [1:0]
0x70 [9:8]
Tiled Digital Gain
0x80 [3:0] − 0x98 [3:0]
0x80 [11:8] − 0x98 [11:8]
AEC/AGC Enable
0xAF [1:0]
0xAF [9:8]
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MT9V024/D
Recommended Register Settings
Table 8 describes new suggested register settings, and
descriptions of performance improvements and conditions:
Table 8. RECOMMENDED REGISTER SETTINGS AND PERFORMANCE IMPACT
(RESERVED REGISTERS)
Register
Current Default
New Setting
Performance Impact
R0x20
0x01C1
0x03C7
Recommended by design to improve performance in HDR
mode and when frame rate is low. We also recommended
using R0x13 = 0x2D2E with this setting for better column
FPN. NOTE: When coarse integration time set to 0 and fine
integration time less than 456, R0x20 should be set to
0x01C7
R0x24
0x0010
0x001B
Corrects pixel negative dark offset when global reset in
R0x20[9] is enabled.
R0x2B
0x0004
0x0003
Improves column FPN.
R0x2F
0x0004
0x0003
Improves FPN at near−saturation.
FEATURE DESCRIPTION
Operational Modes
modes must be selected through the two−wire serial
inter−face. Additional details on this mode can be found in
AND9255/D Master Exposure Mode Operation.
The MT9V024 works in master, snapshot, or slave mode.
In master mode the sensor generates the readout timing. In
snapshot mode it accepts an external trigger to start
integration, then generates the readout timing. In slave mode
the sensor accepts both external integration and readout
controls. The integration time is programmed through the
two−wire serial interface during master or snapshot modes,
or controlled through an externally generated control signal
during slave mode.
Simultaneous Master Mode
In simultaneous master mode, the exposure period occurs
during readout. The frame synchronization waveforms are
shown in Figure 14 and Figure 15. The exposure and readout
happen in parallel rather than sequential, making this the
fastest mode of operation.
Master Mode
There are two possible operation methods for master
mode: simultaneous and sequential. One of these operation
EXPOSURE TIME
LED_OUT
tLED2FV−SIM
tLED2FV−SIM
FRAME_VALID
tVBLANK
LINE_VALID
FRAME TIME
Figure 14. Simultaneous Master Mode Synchronization Waveforms #1
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13
MT9V024/D
EXPOSURE TIME
LED_OUT
tLED2FV−SIM
tLEDOFF
FRAME_VALID
tVBLANK
LINE_VALID
FRAME TIME
Figure 15. Simultaneous Master Mode Synchronization Waveforms #2
Sequential Master Mode
When exposure time is greater than the sum of vertical
blank and window height, the number of vertical blank rows
is increased automatically to accommodate the exposure
time.
In sequential master mode the exposure period is followed
by readout. The frame synchronization waveforms for
sequential master mode are shown in Figure 16. The frame
rate changes as the integration time changes.
EXPOSURE
TIME
LED_OUT
tLED2FV−SEQ
t2FVLED−SEQ
FRAME_VALID
tVBLANK
LINE_VALID
FRAME TIME
Figure 16. Simultaneous Master Mode Synchronization Waveforms
Snapshot Mode
integration period is complete the readout process
commences and the syncs and data are output. Sensor in
snapshot mode can capture a single image or a sequence of
images. The frame rate may only be controlled by changing
the period of the user supplied EXPOSURE pulse train. The
frame synchronization waveforms for snapshot mode are
shown in Figure 18. Additional details on this mode can be
found in AND9248/D−Snapshot Exposure Mode
Operation.
In snapshot mode the sensor accepts an input trigger
signal which initiates exposure, and is immediately
followed by readout. Figure 17 shows the interface signals
used in snapshot mode. In snapshot mode, the start of the
integration period is determined by the externally applied
EXPOSURE pulse that is input to the MT9V024. The
integration time is preprogrammed at R0x0B or R0xD2
through the two−wire serial interface. After the frame’s
EXPOSURE
SYSCLK
PIXCLK
CONTROLLER
LINE_VALID
MT9V024
FRAME_VALID
DOUT(9:0)
(9:0
)
Figure 17. Snapshot Mode Interface Signals
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MT9V024/D
TE2E
EXPOSURE
TEW
EXPOSURE
TIME
LED_OUT
TE2LED
TLED2FV
TFV2E
FRAME_VALID
TVBLANK
LINE_VALID
FRAME TIME
Figure 18. Snapshot Mode Frame Synchronization Waveforms
Slave Mode
It is also important to provide additional STLN_OUT
pulses to allow the sensors to read the vertical blanking rows.
It is recommended that the user program the vertical blank
register (R0x06) with a value of 4, and achieve additional
vertical blanking between frames by delaying the
application of the STFRM_OUT pulse.
The elapsed time between the rising edge of STLN_OUT
and the first valid pixel data is calculated for context A by
[horizontal blanking register (R0x05) + 4] clock cycles. For
context B, the time is (R0xCD + 4) clock cycles.
Additional details on this mode can be found in
AND9241/D − Slave Exposure Mode Operation.
In slave mode, the exposure and readout are controlled
using the EXPOSURE, STFRM_OUT, and STLN_OUT
pins. When the slave mode is enabled, STFRM_OUT and
STLN_OUT become input pins.
The start and end of integration are controlled by
EXPOSURE and STFRM_OUT pulses, respectively. While
a STFRM_OUT pulse is used to stop integration, it is also
used to enable the readout process.
After integration is stopped, the user provides
STLN_OUT pulses to trigger row readout. A full row of data
is read out with each STLN_OUT pulse. The user must
provide enough time between successive STLN_OUT
pulses to allow the complete readout of one row.
EXPOSURE
tEW
tSF2SF
TE2SF
tSFW
STFRM_OUT
STLN_OUT
tSF2FV
FRAME_VALID
tFV2SF
LINE_VALID
tE2LED
EXPOSURE
TIME
tSF2LED
LED_OUT
Figure 19. Exposure and Readout Timing (Simultaneous Mode)
NOTES: 1. No drawn to scale.
2. Frame readout shortened for clarity.
3. Simultaneous progressive scan readout mode shown.
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15
6.
MT9V024/D
tEW
EXPOSURE
tE2SF
tSF2SF
tSFW
STFRM_OUT
STLN_OUT
tSF2FV
tFV2E
FRAME_VALID
LINE_VALID
tE2LED
EXPOSURE
TIME
tSF2LED
LED_OUT
Figure 20. Exposure and Readout Timing (Sequential Mode)
NOTES: 1. Not drawn to scale.
2. Frame readout shortened for clarity
3. STLN_OUT pulses are optional during exposure time.
4. Sequential progressive scan readout mode shown.
Signal Path
“Black Level Calibration” for the programmable offset
operation description.
The MT9V024 signal path consists of a programmable
gain, a programmable analog offset, and a 10−bit ADC. See
Gain Selection
(R0x35 or R0x36 or
result of AGC)
Pixel Output
(reset minus signal)
Offset Correction
Voltage (R0x48 or
result of BLC)
×
+
Σ
VREF
(R0x2C)
10 (12) bit ADC
ADC Data
(9:0)
C1
C2
Figure 21. Signal Path
ON−CHIP BIASES
V_Step Voltage Reference
This voltage is used for pixel high dynamic range
operations, programmable from R0x31 through R0x34 for
context A, or R0x39 through R0x3B for context B.
ADC Voltage Reference
The ADC voltage reference is programmed through
R0x2C, bits 2:0. The ADC reference ranges from 1.0 V to
2.1 V. The default value is 1.4 V. The increment size of the
voltage reference is 0.1 V from 1.0 V to 1.6 V (R0x2C[2:0]
values 0 to 6). At R0x2C[2:0] = 7, the reference voltage
jumps to 2.1 V.
It is very important to preserve the correct values of the
other bits in R0x2C. The default register setting is 0x0004.
This corresponds to 1.4 V−at this setting 1 mV input to the
ADC equals approximately 1 LSB.
Chip Version
Chip version register R0x00 is read−only.
WINDOW CONTROL
Registers column start A/B, row start A/B, window height
A/B (row size), and window width (column size) A/B
control the size and starting coordinates of the window.
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MT9V024/D
The values programmed in the window height and width
registers are the exact window height and width out of the
sensor. The window start value should never be set below
four.
To read out the dark rows set bit 6 of R0x0D. In addition,
bit 7 of R0x0D can be used to display the dark columns in
the image. Note that there are Show Dark settings only for
context A.
•
BLANKING CONTROL
Horizontal blank and vertical blank registers R0x05 and
R0x06 (B: 0xCD and R0xCE), respectively, control the
blanking time in a row (horizontal blanking) and between
frames (vertical blanking).
• Horizontal blanking is specified in terms of pixel
clocks.
• Vertical blanking is specified in terms of numbers of
rows.
The actual imager timing can be calculated using Table 2
and Table 3, which describe “Row Timing and FV/LV
signals.” The minimum number of vertical blank rows is 4.
Row Timing
Context A:
Row time + (R0x04 ) R0x05)master clock periods
(eq. 2)
Context B:
Row time + (R0xCC ) R0xCD) master clock periods (eq. 3)
Typically, the value of the Coarse Shutter Width Total
registers is limited to the number of rows per frame (which
includes vertical blanking rows), such that the frame rate is
not affected by the integration time. If the Coarse Shutter
Width Total is increased beyond the total number of rows per
frame, the user must add additional blanking rows using the
Vertical Blanking registers as needed. See descriptions of
the Vertical Blanking registers, R0x06 and R0xCE in
Table 1and Table 2 of the MT9V024 register reference.
A second constraint is that tINT must be adjusted to avoid
banding in the image from light flicker. Under 60Hz flicker,
this means the frame time must be a multiple of 1/120 of
a second. Under 50Hz flicker, the frame time must be
a multiple of 1/100 of a second.
PIXEL INTEGRATION CONTROL
Total Integration
Total integration time is the result of coarse shutter width
and fine shutter width registers, and depends also on whether
manual or automatic exposure is selected.
The actual total integration time, tINT is defined as:
t INT + t INTCoarse ) t INTint
equals the value in R0x0B. or
If context B is enabled, the number of rows of integration
equals the value in R0xD2.
Number of pixels of Integration
The number of fine shutter width pixels is independent
of AEC mode (enabled or disabled):
♦ Context A: the number of pixels of integration
equals the values in R0xD5.
♦ Context B: the number of pixels of integration
equals the value in R0xD8.
(eq. 1)
= (number of rows of integration × row time)
+ (number of pixels of integration × pixel time)
Changes to Integration Time
where:
• Number of Rows of Integration
(Auto Exposure Control: Enabled)
When automatic exposure control (AEC) is enabled, the
number of rows of integration may vary from frame to
frame, with the limits controlled by R0xAC (minimum
coarse shutter width) and R0xAD (maximum coarse
shutter width).
• Number of Rows of Integration
(Auto Exposure Control: Disabled)
If AEC is disabled, the number of rows of integration
With automatic exposure control disabled (R0xAF[0] for
context A, or R0xAF[8] for context B) and if the total
integration time (R0x0B or R0xD2) is changed through the
two−wire serial interface while FV is asserted for frame n,
the first frame output using the new integration time is frame
(n + 2). Similarly, when automatic exposure control is
enabled, any change to the integration time for frame n first
appears in frame (n + 2) output. Additional details on this
latency can be found in AND9251/D − Latency of Exposure
or Gain Switch.
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MT9V024/D
(n + 1). The actual time that rows start integrating
using the new integration time is dependent on the
new value of the integration time.
3. When frame (n + 2) is read out, it is integrated
using the new integration time. If the integration
time is changed (R0x0B or R0xD2 written) on
successive frames, each value written is applied to
a single frame; the latency between writing a value
and it affecting the frame readout remains at two
frames.
The sequence is as follows:
1. During frame n, the new integration time is held
in the R0x0B or R0D2 live register.
2. Prior to the start of frame (n + 1) readout, the new
integration time is transferred to the exposure
control module. Integration for each row of frame
(n + 1) has been completed using the old
integration time. The earliest time that a row can
start integrating using the new integration time is
immediately after that row has been read for frame
write new exposure value (Exp “B”)
frame n
Two−wire
serial interface
(Input)
LED_OUT
(Output)
frame n+1
frame n+2
idle
idle
Exp “A”
FRAME_VALID
(Output)
AEC −sample writes
new exposure value
(Exp “B”)
Exp “B”
Exp “A”
Readout Exp “A”
AEC −sample writes
new exposure value
(Exp “B”)
Exp “B”
Readout Exp “B”
Readout Exp “A”
Frame start activates new exposure
value (Exp “B”)
Exp “B”
Readout Exp “B”
Readout Exp “B”
New image available
at output
Figure 22. Latency of Exposure Register in Master Mode
Exposure Indicator
•
In the MT9V024, high dynamic range (by setting R0x0F,
bit 0 or 8 to 1) is achieved by controlling the saturation level
of the pixel (HDR or high dynamic range gate) during the
exposure period. The sequence of the control voltages at the
HDR gate is shown in Figure 23. After the pixels are reset,
the step voltage, V_Step, which is applied to HDR gate, is
set up at V1 for integration time t1, then to V2 for time t2, then
V3 for time t3, and finally it is parked at V4, which also
serves as an antiblooming voltage for the photodetector.
This sequence of voltages leads to a piecewise linear pixel
response, illustrated (approximately) in Figure 23 and in
Figure 24.
The exposure indicator is controlled by:
R0x1B LED_OUT Control
The MT9V024 provides an output pin, LED_OUT, to
indicate when the exposure takes place. When R0x1B
bit 0 is clear, LED_OUT is HIGH during exposure. By
using R0x1B, bit 1, the polarity of the LED_OUT pin
can be inverted.
High Dynamic Range
High dynamic range is controlled by:
Table 9. HIGH DYNAMIC RANGE
Context A
Context B
R0x0F[0]
R0x0F[8]
Shutter Width 1
R0x08
R0xCF
Shutter Width 2
R0x09
R0xD0
Shutter Width Control
R0x0A
R0xD1
R0x31−R0x34
R0x39−R0x3C
High Dynamic Enable
V_Step Voltages
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MT9V024/D
Exposure
AA(3.3V)
VV
AA(3.3V)
V4~0.8V
t t11
HDR
Voltage
V3~1.0V
V3~1.0V
V2~1.2V
V2~1.2V
V1~1.4V
V1~1.4V
t t2
2
tt
33
Figure 23. Sequence of Control Voltages at the HDR Gate
dV3
Output
dV2
dV1
Light Intensity
1/t 1
1/t 3
1/t 2
Figure 24. Sequence of Voltages in a Piecewise Linear Pixel Response
context A by R0x0A[8] (where default is ON), and for
context B by R0xD1[8] (where default is OFF ).
When the knee point auto adjust enabler is enabled (set
HIGH), the MT9V024 calculates the knee points
automatically using the following equations:
The parameters of the step voltage V_Step, which take
values V1, V2, and V3, directly affect the position of the
knee points in Figure 24.
Light intensities work approximately as a reciprocal of the
partial exposure time. Typically, t1 is the longest exposure,
t2 shorter, and so on. Thus the range of light intensities is
shortest for the first slope, providing the highest sensitivity.
The register settings for V_Step and partial exposures are:
V1 = R0x31, bits 5:0 (Context B: R0x39, bits 5:0)
V2 = R0x32, bits 5:0 (Context B: R0x3A, bits 5:0)
V3 = R0x33, bits 5:0 (Context B: R0x3B, bits 5:0)
V4 = R0x34, bits 5:0 (Context B: R0x3C, bits 5:0)
tINT = t1 + t2 + t3
There are two ways to specify the knee points timing, the
first by manual setting and the second by automatic knee
point adjustment. Knee point auto adjust is controlled for
t 1 + t INT * t 2 * t 3
(eq. 4)
t 2 + t INTx(1ń2) R0x0A[3:0]orR0xD1[3:0]
(eq. 5)
t 3 + t INTx(1ń2) R0x0A[7:4]orR0xD1[7:4]
(eq. 6)
As a default for auto exposure, t2 is 1/16 of tINT, t3 is 1/64
of tINT.
When the auto adjust enabler is disabled (set LOW ), t1 , t2 ,
and t3 may be programmed through the two−wire serial
interface:
t 1 + Coarse SW1(row * times) ) Fine SW1(pixel * times)
(eq. 7)
t 2 + Coarse SW2 * Coarse SW1 ) Fine SW2 * Fine SW1
(eq. 8)
t 3 + Total Integration * t 1 * t 2 + Coarse Total Shutter Width ) Fine Shutter Width Totall * t 1 * t 2
For context A these become:
(eq. 9)
For context B these are:
t 1 + R0x08 ) R0xD3
(eq. 10)
t 1 + R0xCF ) R0xD6
(eq. 13)
t 3 + R0x09 * R0x08 ) R0xD4 * R0xD3
(eq. 11)
t 3 + R0xD0 * R0xCF ) R0xD7 * R0xD6
(eq. 14)
t 3 + R0x0B ) R0xD4 * t 1 * t 2
(eq. 12)
t 3 + R0xD2 ) R0xD8 * t 1 * t 2
(eq. 15)
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MT9V024/D
ADC Companding Mode
In all cases above, the coarse component of total
integration time may be based on the result of AEC or values
in R0x0B and R0xD2, depending on the settings.
Similar to Fine Shutter Width Total registers, the user
must not set the Fine Shutter Width 1 or Fine Shutter Width
2 register to exceed the row time (Horizontal Blanking +
Window Width). The absolute maximum value for the Fine
Shutter Width registers is 1774 master clocks.
By default, ADC resolution of the sensor is 10−bit.
Additionally, a companding scheme of 12−bit into 10−bit is
enabled by the ADC Companding Mode register. This mode
allows higher ADC resolution, which means less
quantization noise at low light, and lower resolution at high
light, where good ADC quantization is not so critical
because of the high level of the photon’s shot noise.
10−bit
Codes
1,024
8 to 1 Companding (2,048 − 4095
768
4 to 1 Companding (512− 2047
512
2 to 1 Companding (256− 511
256
No companding (0 −255
256
512 1,024
768 − 1023)
384 − 767)
256 −383)
12−bit
Codes
0 −255)
2,048
4,096
Figure 25. 12− to 10−Bit Companding Chart
GAIN SETTINGS
Changes to Gain Settings
Both analog and digital gain change regardless of whether
the integration time is also changed simultaneously. Digital
gain will change as soon as the register is written. Additional
details on this latency can be found in AND9251/D Latency
of Exposure or Gain Switch.
When the analog gain (R0x35 for context A or R0x36 for
context B) or the digital gain settings (R0x80–R0x98) are
changed, the gain is updated on the next frame start. The gain
setting must be written before the frame boundary to take
effect the next frame. The frame boundary is slightly after
the falling edge of Frame_Valid. In Figure 26 this is shown
by the dashed vertical line labeled Frame Start.
write new gain value (Gain “B”)
frame n
frame n+1
frame n+2
idle
Readout Gain “A”
AEC −sample point
Frame−start
idle
Readout Gain “A”
Readout Gain “B”
Frame−start writes new
gain value (Exp “B”)
Readout Gain “B”
AGC −sample activates new gain
value (Gain “B”)
Readout Gain “B”
New image available
at output
Figure 26. Latency of Gain Register(s) in Master Mode
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20
Readout Gain “B”
MT9V024/D
• R0x99−R0xA4 Tile Coordinates
• R0x80−R0x98 Tiled Digital Gain and Weight
Analog Gain
•
•
Analog gain is controlled by:
R0x35 Global Gain context A
R0x36 Global Gain context B
The formula for gain setting is:
Gain + Bits[6 : 0] x 0.0625
In the MT9V024, the gain logic divides the image into 25
tiles, as shown in Figure 27. The size and gain of each tile can
be adjusted using the above digital gain control registers.
Separate tile gains can be assigned for context A and context
B.
Registers 0x99–0x9E and 0x9F–0xA4 represent the
coordinates X0/5–X5/5 and Y0/5–Y5/5 in Figure 27 on page
31, respectively.
Digital gains of registers 0x80–0x98 apply to their
corresponding tiles. The MT9V024 supports a digital gain
of 0.25–3.75X.
When binning is enabled, the tile offsets maintain their
absolute values; that is, tile coordinates do not scale with row
or column bin setting. Digital gain is applied as soon as
register is written.
NOTE: There is one exception, for the condition when
Column Bin 4 is enabled (R0x0D[3:2] or
R0x0E[3:2] = 2). For this case, the value for
Digital Tile Coordinate X–direction must be
doubled.
The formula for digital gain setting is:
(eq. 16)
The analog gain range supported in the MT9V024 is
1X–4X with a step size of 6.25 percent. To control gain
manually with this register, the sensor must NOT be in AGC
mode. When adjusting the luminosity of an image, it is
recommended to alter exposure first and yield to gain
increases only when the exposure value has reached
a maximum limit.
Analog gain = bits (6:0) x 0.0625 for values 16–31
Analog gain = bits (6:0)/2 x 0.125 for values 32–64
For values 16–31: each LSB increases analog gain
0.0625v/v. A value of 16 = 1X gain.
Range: 1X to 1.9375X.
For values 32–64: each 2 LSB increases analog gain
0.125v/v (that is, double the gain increase for 2 LSB).
Range: 2X to 4X. Odd values do not result in gain increases;
the gain increases by 0.125 for values 32, 34, 36, and so on.
Digital Gain + Bits[3 : 0] x 0.25
(eq. 17)
Digital Gain
Digital gain is controlled by:
Y0/5
X0/5
X1/5
X2/5
X3/5
X4/5
X5/5
x0_y0
x1_y0
x4_y0
x0_y1
x1_y1
x4_y1
x0_y2
x1_y2
x4_y2
x0_y3
x1_y3
x4_y3
x0_y4
x1_y4
x4_y4
Y1/5
Y2/5
Y3/5
Y4/5
Y5/5
Figure 27. Tiled Sample
• Black Level Calibration Value Step Size: R0x4C
Black Level Calibration
•
•
•
•
Black level calibration is controlled by:
Frame Dark Average: R0x42
Dark Average Thresholds: R0x46
Black Level Calibration Control: R0x47
Black Level Calibration Value: R0x48
The MT9V024 has automatic black level calibration
on−chip, and if enabled, its result may be used in the offset
correction shown in Figure 28.
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21
MT9V024/D
Gain Selection
(R0x35 or R0x36 or
result of AGC)
Pixel Output
(reset minus signal)
Offset Correction
Voltage (R0x48 or
result of BLC)
×
+
VREF
(R0x2C)
ADC Data
(9:0)
10 (12) bit ADC
C1
Σ
C2
Figure 28. Black Level Calibration Flow Chart
To avoid oscillation of the black level from below to
above, the region the thresholds should be programmed so
the difference is at least two times the offset DAC step size.
In normal operation, the black level calibration
value/offset correction value is calculated at the beginning
of each frame and can be read through the two−wire serial
inter−face from R0x48. This register is an 8−bit signed two’s
complement value.
However, if R0x47, bit 0 is set to “1,” the calibration value
in R0x48 is used rather than the automatic black level
calculation result. This feature can be used in conjunction
with the “show dark rows” feature (R0x0D[6]) if using an
external black level calibration circuit.
The offset correction voltage is generated according to the
following formulas:
The automatic black level calibration measures the
average value of pixels from 2 dark rows (1 dark row if row
bin 4 is enabled) of the chip. (The pixels are averaged as if
they were light−sensitive and passed through the appropriate
gain.)
This row average is then digitally low−pass filtered over
many frames (R0x47, bits 7:5) to remove temporal noise and
random instabilities associated with this measurement.
Then, the new filtered average is compared to a minimum
acceptable level, low threshold, and a maximum acceptable
level, high threshold.
If the average is lower than the minimum acceptable level,
the offset correction voltage is increased by a programmable
offset LSB in R0x4C. (Default step size is 2 LSB Offset =
1 ADC LSB at analog gain = 1X.)
If it is above the maximum level, the offset correction
voltage is decreased by 2 LSB (default).
OffsetCorrectionVoltage + (8 * bit signed twoȀs complement calibration value, 127
ADC input voltage + (Pixel Output Voltage) * Analog Gain ) Offset Correction Voltage
0.25mV
(AnalogGain ) 1)
(eq. 18)
(eq. 19)
Defective Pixel Correction
Row−wise Noise Correction
Defective pixel correction is intended to compensate for
defective pixels by replacing their value with a value based
on the surrounding pixels, making the defect less notice−
able to the human eye. The locations of defective pixels are
stored in a ROM on chip during the manufacturing process;
the maximum number of defects stored is 32. There is no
provision for later augmenting the table of programmed
defects. In the defect correction block, bad pixels will be
substituted by either the average of its neighboring pixels, or
its nearest−neighbor pixel, depending on pixel location.
Defective Pixel Correction is enabled by R0x07[9]. By
default, correction is enabled, and pixels mapped in internal
ROM are replaced with corrected values. This might be
unacceptable to some applications, in which case pixel
correction should be disabled (R0x07[9] = 0).
For complete details on using Defective Pixel Correction,
refer to AND9554/D, “Defective Pixel Correction −
Description and Usage”.
Row−wise noise correction is controlled by the following
registers:
• R0x70 Row Noise Control
• R0x72 Row Noise Constant
Row−wise noise cancellation is performed by calculating
a row average from a set of optically black pixels at the start
of each row and then applying each average to all the active
pixels of the row. Read Dark Columns register bit and Row
Noise Correction Enable register bit must both be set to
enable row−wise noise cancellation to be performed. The
behavior when Read Dark Columns register bit = 0 and Row
Noise Correction Enable register bit = 1 is undefined.
The algorithm works as follows:
Logical columns 755−790 in the pixel array provide 36
optically black pixel values. Of the 36 values, two smallest
value and two largest values are discarded. The remaining
32 values are averaged by summing them and discarding the
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MT9V024/D
Automatic Gain Control and Automatic Exposure
Control
5 LSB of the result. The 10−bit result is subtracted from each
pixel value on the row in turn. In addition, a positive constant
will be added (Reg0x71, bits 7:0). This constant should be
set to the dark level targeted by the black level algorithm plus
the noise expected on the measurements of the averaged
values from dark columns; it is meant to prevent clipping
from negative noise fluctuations.
The integrated AEC/AGC unit is responsible for ensuring
that optimal auto settings of exposure and (analog) gain are
computed and updated every frame.
AEC and AGC can be individually enabled or disabled by
R0xAF. When AEC is disabled (R0xAF[0] = 0), the sensor
uses the manual exposure value in coarse and fine shutter
width registers. When AGC is disabled (R0xAF[1] = 0), the
sensor uses the manual gain value in R0x35 or R0x36. See
“Pixel Integration Control” for more information.
Pixel value + ADC value * dark column average ) R0x71[9 : 0]
(eq. 20)
Note that this algorithm does not work in color sensor.
EXP. LPF EXP. SKIP
(R6xA8)
(R0xA6)
1
DESIRED BIN
(desired luminance)
(R0xA5)
16
AEC
UNIT
MIN EXP
AEC
OUTPUT
To exposure
timing control
1
HISTOGRAM
GENERATOR
UNIT
AGC OUTPUT
1
AGC
UNIT
MIN GAIN
0
R0xBB
CURRENT BIN
(current luminance
(R0xBC)
MAX. EXPOSURE
(R6xBD)
MANUAL EXP. AEC ENABLE
(R0x08)
(R0Xaf[0])
To analog
gain control
0
MAX. GAIN
(R0x36)
R0xBA
GAIN LPF
(R0xAB)
GAIN SKIP MANUAL GAIN
(R0xA9)
(R0x35)
AGC ENABLE
(R0xAF[1])
Figure 29. Controllable and Observable AEC/AGC Registers
When binning is enabled, tuning of the AEC may be
required. The histogram pixel count register, R0xB0, may be
adjusted to reflect reduced pixel count. Desired bin register,
R0xA5, may be adjusted as required.
The exposure is measured in row−time by reading
R0xBB. The exposure range is 1 to 2047. The gain is
measured in gain−units by reading R0xBA. The gain range
is 16 to 63 (unity gain = 16 gain−units; multiply by 1/16 to
get the true gain).
When AEC is enabled (R0xAF), the maximum auto
exposure value is limited by R0xBD; minimum auto
exposure is limited by AEC Minimum Exposure, R0xAC.
NOTE: AEC does not support sub−row timing;
calculated exposure values are rounded down to
the nearest row−time. For smoother response,
manual control is recommended for short
exposure times.
When AGC is enabled (R0xAF), the maximum auto gain
value is limited by R0xAB; minimum auto gain is fixed to
16 gain−units.
The exposure control measures current scene luminosity
and desired output luminosity by accumulating a histogram
of pixel values while reading out a frame. All pixels are used,
whether in color or mono mode. The desired exposure and
gain are then calculated from this for subsequent frame.
Pixel Clock Speed
The pixel clock speed is same as the master clock
(SYSCLK) at 26.66 MHz by default. However, when
column binning 2 or 4 (R0x0D or R0x0E, bit 2 or 3) is
enabled, the pixel clock speed is reduced by half and
one−fourth of the master clock speed respectively. See
“Read Mode Options” and “Column Binning” for additional
information.
Hard Reset of Logic
The RC circuit for the MT9V024 uses a 10 k resistor and
a 0.1 F capacitor. The rise time for the RC circuit is 1 s
maximum.
Soft Reset of Logic
Soft reset of logic is controlled by:
• R0x0C Reset
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23
MT9V024/D
a programmable number of frames (R0xC0), then goes into
a sleep period for five minutes. The cycle of sleeping for five
minutes and waking up to capture a number of frames
continues until R0xD9[0] is cleared to return to normal
operation.
In some applications when monitor mode is enabled, the
purpose of capturing frames is to calibrate the gain and
exposure of the scene using automatic gain and exposure
control feature. This feature typically takes less than 10
frames to settle. In case a larger number of frames is needed,
the value of R0xC0 may be increased to capture more
frames.
During the sleep period, none of the analog circuitry and
a very small fraction of digital logic (including
a five−minute timer) is powered. The master clock
(SYSCLK) is therefore always required.
Bit 0 is used to reset the digital logic of the sensor while
preserving the existing two−wire serial interface
configuration. Furthermore, by asserting the soft reset, the
sensor aborts the current frame it is processing and starts
a new frame. Bit 1 is a shadowed reset control register bit to
explicitly reset the automatic gain and exposure control
feature.
These two bits are self−resetting bits and also return to “0”
during two−wire serial inter−face reads.
STANDBY Control
The sensor goes into standby mode by setting STANDBY
to HIGH. Once the sensor detects that STANDBY is
asserted, it completes the current frame before disabling the
digital logic, internal clocks, and analog power enable
signal. To release the sensor out from the standby mode,
reset STANDBY back to LOW. The LVDS must be powered
to ensure that the device is in standby mode. See ”Appendix
A: Power−On Reset and Standby Timing” for more
information on standby.
READ MODE OPTIONS
(Also see “Output Data Format” and “Output Data
Timing”.)
Monitor Mode Control
•
•
Column Flip
Monitor mode is controlled by:
R0xD9 Monitor Mode Enable
R0xC0 Monitor Mode Image Capture Control
By setting bit 5 of R0x0D or R0x0E the readout order of
the columns is reversed, as shown in Figure 30.
Row Flip
By setting bit 4 of R0x0D or R0x0E the readout order of
the rows is reversed, as shown in Figure 31.
The sensor goes into monitor mode when R0xD9[0] is set
to HIGH. In this mode, the sensor first captures
LINE_VALID
Normal readout
DOUT(9:0)
(9:0
)
Reverse readout
(9:0)
DOUT
OUT(9:0
)
P4,1
(9:0)
P4,n
(9:0)
P4,2
(9:0)
P4,3
(9:0)
P4,4
(9:0)
P4,5
(9:0)
P4,6
(9:0)
P4,n−1 P4,n−2 P4,n−3 P4,n−4 P4,n−5
(9:0)
(9:0)
(9:0)
(9:0)
(9:0)
Figure 30. Readout of Six Pixels in Normal and Column Flip Output Mode
FRAME_VALID
Normal readout
DOUT(9:0)
(9:0
)
Reverse readout
DOUT(9:0)
(9:0
)
Row4
(9:0)
Row5
(9:0)
Row6
(9:0)
Row7
(9:0)
Row8
7(9:0)
Row9
(9:0)
Row484 Row483 Row482 Row481 Row480 Row479
(9:0)
(9:0)
7(9:0)
(9:0)
(9:0)
(9:0)
Figure 31. Readout of Six Rows in Normal and Row Flip Output Mode
Pixel Binning
window from the sensor array, the MT9V024 also provides
the ability to down−sample the entire image captured by the
pixel array using pixel binning.
In addition to windowing mode in which smaller
resolutions (CIF, QCIF) are obtained by selecting a smaller
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MT9V024/D
The number of rows read out is half or one−fourth of the
value set in R0x03. The row binning result depends on the
difference in pixel values: for pixel signal differences less
than 200 LSBs, the result is the average of the pixel values.
For pixel differences of 200 LSBs or more, the result is the
value of the darker pixel value.
There are two resolution options: binning 2 and binning 4,
which reduce resolution by two or by four, respectively. Row
and column binning are separately selected. Image
mirroring options will work in conjunction with binning.
For column binning, either two or four columns are
combined by averaging to create the resulting column. For
row binning, the binning result value depends on the
difference in pixel values: for pixel signal differences of less
than 200 LSBs, the result is the average of the pixel values.
For pixel differences of greater than 200 LSBs, the result is
the value of the darker pixel value.
Column Binning
For column binning, either two or four columns are
combined by averaging to create the result. In setting bit 2
or 3 of R0x0D or R0x0E, the pixel data rate is slowed down
by a factor of either two or four, respectively. This is due to
the overhead time in the digital pixel data processing chain.
As a result, the pixel clock speed is also reduced accordingly.
Row Binning
By setting bit 0 or 1 of R0x0D or R0x0E, only half or
one−fourth of the row set is read out, as shown in Figure 32.
LINE_VALID
Normal readout
DOUT(9:0)
Row4
(9:0)
Row5
(9:0)
Row6
(9:0)
Row7
(9:0)
Row8
7(9:0)
Row9
(9:0)
Row10
(9:0)
Row11
(9:0)
LINE_VALID
Row Bin 2 readout
DOUT(9:0)
Row4
(9:0)
Row6 Row8 Row10
(9:0) (9:0)
(9:0)
Row4
(9:0)
Row8
(9:0)
LINE_VALID
Row Bin 4 readout
DOUT(9:0)
Figure 32. Readout of 8 Pixels in Normal and Row Bin Output Mode
LINE_VALID
Normal readout
DOUT(9:0)
(9:0
)
PIXCLK
D1 D2
(9:0) (9:0)
D3
(9:0)
D4
(9:0)
D5
(9:0)
D6
D7
(9:0) (9:0)
D8
(9:0)
LINE_VALID
Column Bin 2 readout
DOUT(9:0
(9:0)
D
) OUT
D12
(9:0)
D34
(9:0)
D56
(9:0)
D78
(9:0)
PIXCLK
LINE_VALID
Column Bin 4 readout
(9:0
D
DOUT
OUT(9:0)
)
d1234
(9:0)
d5678
(9:0)
PIXCLK
Figure 33. Readout of 8 Pixels in Normal and Column Bin Output Mode
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MT9V024/D
Interlaced Readout
The MT9V024 has two interlaced readout options. By
setting R0x07[2:0] = 1, all the even−numbered rows are read
out first, followed by a number of programmable field
blanking rows (set by R0xBF[7:0]), then the odd−numbered
rows, and finally the vertical blanking rows. By setting
R0x07[2:0] = 2 only one field row is read out.
Consequently, the number of rows read out is half what
is set in the window height register. The row start register
determines which field gets read out; if the row start register
is even, then the even field is read out; if row start address
is odd, then the odd field is read out.
P4,1 P4,2 P4,3…………P4,n−1 P4,n
P6,0 P6,1 P6,2…………P6,n−1 P6,n
00 00 00 ………… 00 00 00
00 00 00 ………… 00 00 00
VALID IMAGE − Even Field
HORIZONTAL
BLANKING
Pm−2,0 Pm−2,2………Pm−2,n−2 Pm−2,n
Pm,2 Pm,2…………Pm,n−1 Pm,n
00 00 00 …………………… 00 00 00
00 00 00 …………………… 00 00 00
P5,1 P5,2 P5,3…………P5,n−1 P5,n
P7,0 P7,1 P7,2…………P7,n−1 P7,n
VALID IMAGE − Odd Field
Pm−3,1 Pm−3,2………Pm−3,n−1 Pm−3,n
Pm,1 Pm,1…………Pm,n−1 Pm,n
FIELD BLANKING
00 00 00 ………… 00 00 00
00 00 00 ………… 00 00 00
00 00 00 ………… 00 00 00
00 00 00 ………… 00 00 00
VERTICAL BLANKING
00 00 00 ……………………………… 00 00 00
00 00 00 ……………………………… 00 00 00
Figure 34. Spatial Illustration of Interlaced Image Readout
When interlaced mode is enabled, the total number of
blanking rows are determined by both field blanking register
(R0xBF) and vertical blanking register (R0x06). The
followings are their equations.
Field Blanking + R0xBF[7 : 0]
Vertical Blanking + R0x06[8 : 0] * R0xBF[7 : 0] (contextA) or R0xCE[8 : 0] * R0xBF[7 : 0] (contextB)
(eq. 21)
(eq. 22)
with
minimum vertical blanking requirement + 4(absolute minimum operate; see Vertical Blanking Registers
description for VBlank minimums for valid image output)
Similar to progressive scan, FV is logic LOW during the
valid image row only. Binning should not be used in
conjunction with interlaced mode.
(eq. 23)
rows and two vertical blanking rows are shown in Figure 35.
In the last format, the LV signal is the XOR between the
continuous LV signal and the FV signal.
LINE_VALID
By setting bit 2 and 3 of R0x72, the LV signal can get three
different output formats. The formats for reading out four
Default
FRAME_VALID
LINE_VALID
Continuously
FRAME_VALID
LINE_VALID
XOR
FRAME_VALID
LINE_VALID
Figure 35. Different LINE_VALID Formats
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MT9V024/D
LVDS Serial (Stand−Alone/Stereo) Output
Irrespective of the mode (stereoscopy/stand−alone), LV and
FV are always embedded in the pixel data.
In stereoscopic mode, the two sensors run in lock−step,
implying all state machines are in the same state at any given
time. This is ensured by the sensor−pair getting their
sys−clks and sys−resets in the same instance. Configuration
writes through the two−wire serial interface are done in such
a way that both sensors can get their configuration updates
at once. The inter−sensor serial link is designed in such
a way that once the slave PLL locks and the data−dly,
shft−clk−dly and stream−latency−sel are configured, the
master sensor streams valid stereo content irrespective of
any variation voltage and/or temperature as long as it is
within specification. The configuration values of data−dly,
shft−clk−dly and stream−latency−sel are either
predetermined from the board−layout or can be empirically
determined by reading back the stereo−error flag. This flag
is asserted when the two sensor streams are not in sync when
merged. The combo_reg is used for out−of−sync diagnosis.
The LVDS interface allows for the streaming of sensor
data serially to a standard off−the−shelf deserializer up to
eight meters away from the sensor. The pixels (and controls)
are packeted−12−bit packets for stand−alone mode and
18−bit packets for stereoscopy mode. All serial signaling
(CLK and data) is LVDS. The LVDS serial output could
either be data from a single sensor (stand−alone) or
stream−merged data from two sensors (self and its
stereoscopic slave pair). The appendices describe in detail
the topologies for both stand−alone and stereoscopic modes.
There are two standard deserializers that can be used. One
for a stand−alone sensor stream and the other from
a stereoscopic stream. The deserializer attached to a stand−
alone sensor is able to reproduce the standard parallel output
(8−bit pixel data, LV, FV, and PIXCLK). The deserializer
attached to a stereoscopic sensor is able to reproduce 8− bit
pixel data from each sensor (with embedded LV and FV )
and pixel−clk. An additional (simple) piece of logic is
required to extract LV and FV from the 8−bit pixel data.
Internal
PIXCLK
Internal
Parallel
Data
Internal
Line_Valid
P41 P42 P43 P44 P45 P46
P51 P52 P53 P54
P55 P56
Internal
Frame_Valid
External
Serial
Data Out
1023
0 1023
1
P41 P42 P43 P44 P45 P46
2
1
P51 P52 P53 P54 P55 P56
3
NOTES: 1. External pixel values of 0, 1, 2, 3, are reserved (they only convey control information).
Any raw pixel of value 0, 1, 2 and 3 will be substituted with 4.
2. The external pixel sequence 1023, 0 1023 is a reserved sequence (conveys control
information). Any raw pixel sequence of 1023, 0, 1023 will be substituted with 1023, 4, 1023.
Figure 36. Serial Output Format for 6x2 Frame
LVDS Output Format
consists of a start bit, 8−bit pixel data (with sync codes), the
line valid bit, the frame valid bit and the stop bit. For 10−bit
pixel mode (R0xB6[0] = 1), the packet consists of a start bit,
10−bit pixel data, and the stop bit.
In stand−alone mode, the packet size is 12 bits (2 frame
bits and 10 payload bits); 10−bit pixels or 8−bit pixels can be
selected. In 8−bit pixel mode (R0xB6[0] = 0), the packet
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MT9V024/D
Table 10. LVDS PACKET FORMAT IN STAND−ALONE MODE (Stereoscopy Mode Bit De−Asserted)
12 Bit Packet
Use_10−bit_pixels Bit De−Asserted
(8−Bit Mode)
Use_10−bit_pixels Bit Asserted
(10−Bit Mode)
Bit [0]
1’b1(Start bit)
1’b1(Start bit)
Bit [1]
Pixel Data [2]
Pixel Data [0]
Bit [2]
Pixel Data [3]
Pixel Data [1]
Bit [3]
Pixel Data [4]
Pixel Data [2]
Bit [4]
Pixel Data [5]
Pixel Data [3]
Bit [5]
Pixel Data [6]
Pixel Data [4]
Bit [6]
Pixel Data [7]
Pixel Data [5]
Bit [7]
Pixel Data [8]
Pixel Data [6]
Bit [8]
Pixel Data [9]
Pixel Data [7]
Bit [9]
Line_Valid
Pixel Data [8]
Bit [10]
Frame_Valid
Pixel Data [9]
Bit [11]
1’b0(Stop bit)
1’b0(Stop bit)
5. In stereoscopic mode, the packet size is 18 bits (2 frame bits and 16 payload bits). The packet consists of a start bit, the master pixel byte
(with sync codes), the slave byte (with sync codes), and the stop bit.)
Table 11. LVDS PACKET FORMAT IN STEREOSCOPY MODE (Stereoscopy Mode Bit Asserted)
18−bit Packet
Function
Bit [0]
1’b1 (Start bit)
Bit [1]
Master Sensor Pixel Data [2]
Bit [2]
Master Sensor Pixel Data [3]
Bit [3]
Master Sensor Pixel Data [4]
Bit [4]
Master Sensor Pixel Data [5]
Bit [5]
Master Sensor Pixel Data [6]
Bit [6]
Master Sensor Pixel Data [7]
Bit [7]
Master Sensor Pixel Data [8]
Bit [8]
Master Sensor Pixel Data [9]
Bit [9]
Slave Sensor Pixel Data [2]
Bit [10]
Slave Sensor Pixel Data [3]
Bit [11]
Slave Sensor Pixel Data [4]
Bit [12]
Slave Sensor Pixel Data [5]
Bit [13]
Slave Sensor Pixel Data [6]
Bit [14]
Slave Sensor Pixel Data [7]
Bit [15]
Slave Sensor Pixel Data [8]
Bit [16]
Slave Sensor Pixel Data [9]
Bit [17]
1’b0 (Stop bit)
Control signals LV and FV can be reconstructed from their
respective preceding and succeeding flags that are always
embedded within the pixel data in the form of reserved
words.
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MT9V024/D
Table 12. RESERVED WORDS IN THE PIXEL DATA STREAM
Pixel Data Reserved Word
Flag
0
Precedes frame valid assertion
1
Precedes line valid assertion
2
Succeeds line valid de−assertion
3
Succeeds frame valid de−assertion
When LVDS mode is enabled along with column binning
(bin 2 or bin 4, R0x0D[3:2]), the packet size remains the
same but the serial pixel data stream repeats itself depending
on whether 2X or 4X binning is set:
• For bin 2, LVDS outputs double the expected data
(pixel 0,0 is output twice in sequence, followed by pixel
0, 1 twice, …).
• For bin 4, LVDS outputs 4 times the expected data
(pixel 0,0 is output 4 times in sequence followed by
pixel 0, 1 times 4, …).
The receiving hardware will need to undersample the
output stream,getting data either every 2 clocks (bin 2) or
every 4 (bin 4) clocks.
If the sensor provides a pixel whose value is 0, 1, 2, or 3
(that is, the same as a reserved word) then the outgoing serial
pixel value is switched to 4.
LVDS Enable and Disable
The Table 10 and Table 11 further explain the state of the
LVDS output pins depending on LVDS control settings.
When the LVDS block is not used, it may be left powered
down to reduce power consumption.
Table 13. SER_DATAOUT_*STATE
R0xB1[1]
LVDS power down
R0xB3[4]
LVDS data power down
SER_DATAOUT_*
0
0
Active
0
1
Active
1
0
Z
1
1
Z
Table 14. SER_DATAOUT_*STATE
R0xB1[1]
LVDS power down
R0xB2[4]
LVDS shift−clk power down
SHFT_CLKOUT_*
0
0
Active
0
1
Z
1
0
Z
1
1
Z
6. ERROR pin: When the sensor is not in stereo mode, the ERROR pin is at LOW.
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MT9V024/D
LVDS Data Bus Timing
The LVDS bus timing waveforms and timing
specifications are shown in Table 12 and Figure 37.
Data Rise/Fall Time
(10% − 90%)
Data Setup Time Data Hold Time
LVDS Data Output
(SER_DATAOUT_N/P)
LVDS Clock Output
(Shift_CLKOUT_N/P)
Clock Rise/Fall Time
(10% − 90%)
Clock Jitter
Figure 37. LVDS Timing
Table 15. LVDS AC TIMING SPECIFICATIONS
(VPWR = 3.3V ± 0.3V; TJ = –40_C to +105_C; output load = 100 ; frequency 27 MHz)
Minimum
Typical
Maximum
Unit
LVDS clock rise time
−
0.22
0.30
ns
LVDS clock fall time
−
0.22
0.30
ns
LVDS data rise time
−
0.28
0.30
ns
LVDS data fall time
−
0.28
0.30
ns
LVDS data setup time
0.3
0.67
−
ns
LVDS data hold time
0.1
1.34
−
ns
92
ps
Parameter
LVDS clock jitter
−
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MT9V024/D
ELECTRICAL SPECIFICATIONS
Table 16. DC ELECTRICAL CHARACTERISTICS OVER TEMPERATURE
(VPWR = 3.3V ± 0.3 V; TJ = −40°C to + 105°C; Output Load = 10pF; Frequency 13 MHz to 27 MHz; LVDS off)
Definition
Symbol
Condition
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
IIN
Input Leakage Current
No pull−up resistor; VIN = VPWR or VGND
VOH
Output HIGH Voltage
IOH = –4.0 mA
VOL
Output LOW Voltage
IOL = 4.0 mA
IOH
Output HIGH Current
VOH = VDD - 0.7
IOL
Output LOW Current
Min
Typ
VPWR − 1.4
−
Max
Unit
V
−
1.3
V
−5
–
5
A
VPWR − 0.3
–
–
V
–
–
0.3
V
−11
–
–
mA
VOL = 0.7
–
–
11
mA
Analog Supply Current
Default settings
–
12
20
mA
Pixel Supply Current
Default settings
–
1.1
3
mA
IPWRD
Digital Supply Current
Default settings, CLOAD = 10 pF
–
42
60
mA
ILVDS
IPWRA
IPIX
LVDS Supply Current
Default settings with LVDS on
–
13
16
mA
IPWRA
Standby
Analog Standby Supply Current
STDBY = VDD
−
0.2
3
A
IPWRD
Standby
Clock Off
Digital Standby Supply Current with
Clock off
STDBY = VDD, CLKIN = 0 MHz
−
0.1
10
A
IPWRD
Standby
Clock On
Digital Standby Supply Current with
Clock on
STDBY= VDD, CLKIN = 27 MHz
−
1
2
mA
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
Table 17. DC ELECTRICAL CHARACTERISTICS (VPWR = 3.3 V ± 0.3 V; TA = Ambient = 25 °C)
Symbol
Definition
Condition
Min
Typ
Max
Unit
RLOAD = 100 ±1%
250
–
400
mV
−
−
50
mV
1.0
1.2
1.4
V
−
−
35
mV
LVDS DRIVER DC SPECIFICATIONS
|VOD|
|DVOD|
VOS
DVOS
Output Differential Voltage
Change in VOD Between Complementary Output States
Output Offset Voltage
Pixel Array Current
IOS
Digital Supply Current
±10
mA
IOZ
Output Current When Driver is Tristate
±1
A
LVDS RECEIVER DC SPECIFICATIONS
VIDTH+
Iin
| VGPD| < 925 mV
Input Differential
Input Current
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31
–100
–
100
mV
–
–
±20
A
MT9V024/D
Table 18. ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Minimum
Maximum
Unit
VSUPPLY
Power supply voltage (all supplies)
–0.3
4.5
V
ISUPPLY
Total power supply current
–
200
mA
IGND
Total ground current
–
200
mA
VIN
DC input voltage
–0.3
VDD + 0.3
V
VOUT
DC output voltage
–0.3
VDD + 0.3
V
TSTG (Note 7)
Storage temperature
–50
+150
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
7. This is a stress rating only, and functional operation of the device at these other conditions above those indicated in the operational sections
of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Table 19. AC ELECTRICAL CHARACTERISTICS (VPWR = 3.3 V ± 0.3 V; TJ = −40°C to + 105°C; Output Load = 10pF)
Symbol
Definition
SYSCLK
Condition
Minimum
Typical
Maximum
Unit
Input Clock Frequency
13.0
26.6
27.0
MHz
Clock Duty Cycle
45.0
50.0
55.0
%
tR
Input Clock Rise Time
–
3
5
ns
tF
Input Clock Fall Time
–
3
5
ns
tPLH
P
SYSCLK to PIXCLK Propagation Delay
CLOAD = 10 pF
4
6
8
ns
tPD
PIXCLK to Valid DOUT(9:0) Propagation Delay
CLOAD = 10 pF
–3
0.6
3
ns
tSD
Data Setup Time
14
16
–
ns
tHD
Data Hold Time
14
16
–
tPFLR
PIXCLK to LV Propagation Delay
CLOAD = 10 pF
5
7
9
ns
tPFLF
PIXCLK to FV Propagation Delay
CLOAD = 10 pF
5
7
9
ns
Propagation Delays for PIXCLK and Data Out Signals
falling edge and the data output transition is typically 7 ns.
Note that the falling edge of the pixel clock occurs at
approximately the same time as the data output transitions.
See Table 16 for data setup and hold times.
The pixel clock is inverted and delayed relative to the
master clock. The relative delay from the master clock
(SYSCLK) rising edge to both the pixel clock (PIXCLK)
tR
tF
SYSCLK
tPLH
P
PIXCLK
tPD
t HD
t SD
DOUT(9:0)
DOUT
(9:0)
Figure 38. Propagation Delays for PIXCLK and Data Out Signals
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MT9V024/D
Propagation Delays for FRAME_VALID and
LINE_VALID Signals
The LV and FV signals change on the same rising master
clock edge as the data output. The LV goes HIGH on the
same rising master clock edge as the output of the first valid
pixel’s data and returns LOW on the same master clock
rising edge as the end of the output of the last valid pixel’s
data.
t
As shown in the “Output Data Timing”, FV goes HIGH
143 pixel clocks before the first LV goes HIGH. It returns
LOW 23 pixel clocks after the last LV goes LOW.
PP
P
t PFLF
FLR
PIXCLK
PIXCLK
FRAME_VALID
LINE_VALID
FRAME_VALID
LINE_VALID
Figure 39. Propagation Delays for FRAME_VALID and LINE_VALID Signals
Two-Wire Serial Bus Timing
Detailed timing waveforms and parameters for the
two−wire serial interface bus are shown in Figure 40 and
Table 17.
SDATA
tLOW
tf
tr
TSU;DAT
tf
SCLK
S
THD;STA
tHD;DAT
tHIGH
TSU;STA
Sr
Figure 40. Two−Wire Bus Timing Parameters
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MT9V024/D
Table 20. TWO−WIRE SERIAL BUS CHARACTERISTICS (VPWR = 3.3V +0.3V; TA = Ambient = 25°C)
Standard−Mode
Fast−Mode
Symbol
Min
Max
Min
Max
Unit
fSCL
0
100
0
400
kHz
tHD;STA
4.0
−
0.6
−
s
LOW period of the SCLK clock
tLOW
4.7
−
1.3
−
s
HIGH period of the SCLK clock
tHIGH
4.0
−
0.6
−
s
Set-up time for a repeated START condition
tSU;STA
4.7
−
0.6
−
s
Data hold time
tHD;DAT
0
(Note 11)
3.45
(Note 12)
0
(Note 13)
0.9
(Note 12)
s
Data set-up time
tSU;DAT
250
−
100
(Note 13)
−
ns
Rise time of both SDATA and SCLK signals
tr
−
1000
20 + 0.1Cb
(Note 14)
300
ns
Fall time of both SDATA and SCLK signals
tf
−
300
20 + 0.1Cb
(Note 14)
300
ns
tSU;STO
4.0
−
0.6
−
s
tBUF
4.7
−
1.3
−
s
Cb
−
400
−
400
pF
CIN_SI
−
3.3
−
3.3
pF
CLOAD_SD
−
30
−
30
pF
RSD
1.5
4.7
1.5
4.7
k
Parameter
SCLK Clock Frequency
After this period, the first clock pulse is generated
Set-up time for STOP condition
Bus free time between a STOP and START condition
Capacitive load for each bus line
Serial interface input pin capacitance
SDATA max load capacitance
SDATA pull−up resistor
8. This table is based on I2C standard (v2.1 January 2000). Philips Semiconductor.
9. Two-wire control is I2C-compatible.
10. All values referred to VIHmin = 0.9 VDD and VILmax = 0.1VDD levels. Sensor EXCLK = 27 MHz.
11. A device must internally provide a hold time of at least 300 ns for the SDATA signal to bridge the undefined region of the falling edge of SCLK.
12. The maximum tHD;DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCLK signal.
13. A Fast-mode I2C-bus device can be used in a Standard-mode I2C−bus system, but the requirement tSU;DAT 250 ns must then be met. This
will automatically be the case if the device does not stretch the LOW period of the SCLK signal. If such a device does stretch the LOW period
of the SCLK signal, it must output the next data bit to the SDATA line tr max + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard−mode
I2C−bus specification) before the SCLK line is released.
14. Cb = total capacitance of one bus line in pF.
Minimum Master Clock Cycles
certain minimum master clock cycles between transitions.
These are specified in Figures 41 through 46, in units of
master clock cycles.
In addition to the AC timing requirements described in
Table 17, the two−wire serial bus operation also requires
4
4
SCLK
SDATA
Figure 41. Serial Host Interface Start Condition Timing
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MT9V024/D
4
4
SCLK
SDATA
NOTE:
All timing are in units of master clock cycle.
Figure 42. Serial Host Interface Stop Condition Timing
4
4
SCLK
SDATA
NOTE:
SDATA is driven by an off-chip transmitter.
Figure 43. Serial Host Interface Data Timing for WRITE
5
SCLK
SDATA
NOTE:
SDATA is pulled LOW by the sensor, or allowed to be pulled HIGH by a pull-up resistor off-chip.
Figure 44. Serial Host Interface Data Timing for READ
6
3
SCLK
SDATA
Sensor pulls down
SDATA pin
Figure 45. Acknowledge Signal Timing After an 8-Bit WRITE to the Sensor
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35
MT9V024/D
7
6
SCLK
SDATA
NOTE:
Sensor tri−states S DATA pin
(turns off pull down)
After a READ, the master receiver must pull down SDATA to acknowledge receipt of data bits. When read sequence is
complete, the master must generate a “No Acknowledge” by leaving SDATA to float HIGH. On the following cycle,
a start or stop bit may be used.
Figure 46. Acknowledge Signal Timing After an 8-Bit READ from the Sensor
Figure 47. Typical Quantum Efficiency−Monochrome
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MT9V024/D
Quantum Efficiency (%)
60
50
40
30
20
10
0
350
450
550
650
750
850
950
Wavelength (nm)
Figure 48. Typical Quantum Efficiency − Monochrome
Figure 49. Typical Quantum Efficiency − RCCC
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1050
MT9V024/D
Appendix A: Power−On Reset and Standby Timing
requires reset to operate properly at power−up. Refer to
Figure 50 for the power−up, reset, and standby sequences.
There are no constraints concerning the order in which the
various power supplies are applied; however, the MT9V024
Non−Low−Power
Power
up
VDD, VDDLVDS,
VAA, VAAPIX
Active
Low−Power
Pre−Standby
Standby
Non−Low−Power
Wake
up
Active
Power
down
MIN 20 SYSCLK cycles
RESET_BAR
Note 3
STANDBY
MIN 20 SYSCLK cycles
SYSCLK
MIN 10 SYSCLK cycles
SCLK, SDATA
Twi−wire Serial I/F
DOUT [9:0]
DATA OUTPUT
Driven = 0
MIN 20 SYSCLK cycles
Does not
respond to
serial
Interface
when
STANDBY=1
DOUT [9:0]
Driven = 0
Figure 50. Power−up, Reset, Clock, and Standby Sequence
NOTES: 1. All output signals are defined during initial power−up with RESET_BAR held LOW without SYSCLK being active. To
properly reset the rest of the sensor, during initial power−up, assert RESET_BAR (set to LOW state) for at least 750ns
after all power supplies have stabilized and SYSCLK is active (being clocked). Driving RESET_BAR to LOW state does
not put the part in a low power state.
2. Before using two−wire serial interface, wait for 10 SYSCLK rising edges after RESET_BAR is de−asserted.
3. Once the sensor detects that STANDBY has been asserted, it completes the current frame readout before entering
standby mode. The user must supply enough SYSCLKs to allow a complete frame readout. See Table 2, “Frame Time,”
for more information
4. In standby, all video data and synchronization output signals are driven to a low state.
5. In standby, the two−wire serial interface is not active.
APPENDIX B: ELECTRICAL IDENTIFICATION
OF CFA TYPE
In order to identify the CFA type (RGB Bayer,
Monochrome, RCCC) that a specific MT9V024 has been,
the following table may be used.
CFA
R0x6B[11:9]
R0x6B[8:0]
RGB
6
4
RCCC
5
4
Mono
0
4
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MT9V024/D
IBGA52 9x9
CASE 503AA
ISSUE O
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39
MT9V024/D
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