MC74VHC157 Quad 2-- Channel Multiplexer The MC74VHC157 is an advanced high--speed CMOS quad 2--channel multiplexer, fabricated with silicon gate CMOS technology. It achieves high--speed operation similar to equivalent Bipolar--Schottky TTL, while maintaining CMOS low--power dissipation. It consists of four 2--input digital multiplexers with common select (S) and enable (E) inputs. When E is held High, selection of data is inhibited and all the outputs go Low. The select decoding determines whether the A or B inputs get routed to the corresponding Y outputs. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The inputs tolerate voltages up to 7 V, allowing the interface of 5 V systems to 3 V systems. • • • • • • • • • • • • High Speed: tPD = 4.1 ns (Typ) at VCC = 5 V Low Power Dissipation: ICC = 4 mA (Max) at TA = 25°C High Noise Immunity: VNIH = VNIL = 28% VCC Power Down Protection Provided on Inputs Balanced Propagation Delays Designed for 2 V to 5.5 V Operating Range Low Noise: VOLP = 0.8 V (Max) Pin and Function Compatible with Other Standard Logic Families Latchup Performance Exceeds 300 mA ESD Performance: HBM > 2000 V; Machine Model > 200 V Chip Complexity: 82 FETs These devices are available in Pb--free package(s). Specifications herein apply to both standard and Pb--free devices. Please see our website at www.onsemi.com for specific Pb--free orderable part numbers, or contact your local ON Semiconductor sales office or representative. S 1 16 VCC A0 2 15 E B0 3 14 A3 http://onsemi.com MARKING DIAGRAMS 16 SOIC--16 D SUFFIX CASE 751B 8 9 VHC 157 ALYW TSSOP--16 DT SUFFIX CASE 948F 1 8 16 SOIC EIAJ--16 M SUFFIX CASE 966 A L, WL Y, YY W, WW 9 74VHC157 ALYW 1 8 = Assembly Location = Wafer Lot = Year = Work Week ORDERING INFORMATION Device Package Shipping MC74VHC157D SOIC--16 48 Units/Rail MC74VHC157DR2 SOIC--16 2500 Units/Reel TSSOP--16 96 Units/Rail 4 13 B3 A1 5 12 Y3 B1 6 11 A2 MC74VHC157DT Y1 7 10 B2 GND 8 9 MC74VHC157DTR2 TSSOP--16 2500 Units/Reel Y2 Figure 1. Pin Assignment March, 2006 -- Rev. 5 1 16 Y0 © Semiconductor Components Industries, LLC, 2006 9 VHC157 AWLYYWW 1 MC74VHC157M SOIC EIAJ--16 50 Units/Rail MC74VHC157MEL SOIC EIAJ--16 2000 Units/Reel Publication Order Number: MC74VHC157/D MC74VHC157 A0 B0 A1 B1 NIBBLE INPUTS A2 B2 A3 B3 E S 2 4 3 Y0 5 7 6 Y1 DATA OUTPUTS 11 9 10 Y2 14 12 Y3 13 15 1 Figure 2. Expanded Logic Diagram E S A0 B0 A1 B1 15 1 EN G1 2 3 5 6 1 1 MUX 4 7 11 A2 10 B2 14 A3 13 B3 9 12 Figure 3. IEC Logic Symbol FUNCTION TABLE Inputs Outputs E S Y0 -- Y3 H L L X L H L A0--A3 B0--B3 A0 -- A3, B0 -- B3 = the levels of the respective Data--Word Inputs. http://onsemi.com 2 Y0 Y1 Y2 Y3 MC74VHC157 MAXIMUM RATINGS (Note 1) Symbol Parameter Value Unit −0.5 to +7.0 V VCC DC Supply Voltage VI DC Input Voltage −0.5 to VCC +7.0 V VO DC Output Voltage −0.5 to VCC +7.0 V IIK DC Input Diode Current VI < GND −20 mA IOK DC Output Diode Current VO < GND ±20 mA IO DC Output Sink Current ±25 mA ICC DC Supply Current per Supply Pin ±100 mA TSTG Storage Temperature Range −65 to +150 _C TL Lead Temperature, 1 mm from Case for 10 Seconds TJ Junction Temperature under Bias θJA Thermal Resistance PD Power Dissipation in Still Air at 85_C MSL Moisture Sensitivity FR Flammability Rating VESD ESD Withstand Voltage Human Body Model (Note 2) Machine Model (Note 3) Charged Device Model (Note 4) >2000 >200 N/A V ILatch--Up Latch--Up Performance Above VCC and Below GND at 85_C (Note 5) ±500 mA 260 _C +150 _C 250 _C/W 250 mW Level 1 Oxygen Index: 30% -- 35% UL--94--VO (0.125 in) 1. Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Extended exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum--rated conditions is not implied. 2. Tested to EIA/JESD22--A114--A. 3. Tested to EIA/JESD22--A115--A. 4. Tested to JESD22--C101--A. 5. Tested to EIA/JESD78. RECOMMENDED OPERATING CONDITIONS Symbol Characteristics VCC DC Supply Voltage VIN DC Input Voltage VOUT DC Output Voltage TA Operating Temperature Range, all Package Types tr, tf Input Rise or Fall Time (Note 6) VCC = 3.3 V ± 0.3 V VCC = 5.0 V ± 0.5 V Min Max Unit 2.0 5.5 V 0 5.5 V 0 VCC V −55 125 _C 0 0 100 20 ns/V 6. Unused inputs may not be left open. All inputs must be tied to a high--logic voltage level or a low--logic input voltage level. 90 419,300 47.9 100 178,700 20.4 110 79,600 9.4 120 37,000 4.2 130 17,800 2.0 140 8,900 1.0 TJ = 80_C 117.8 TJ = 90_C 1,032,200 TJ = 100_C 80 TJ = 110_C Time, Years TJ = 120_C Time, Hours FAILURE RATE OF PLASTIC = CERAMIC UNTIL INTERMETALLICS OCCUR TJ = 130_C Junction Temperature _C NORMALIZED FAILURE RATE DEVICE JUNCTION TEMPERATURE VERSUS TIME TO 0.1% BOND FAILURES 1 1 10 100 1000 TIME, YEARS Figure 4. Failure Rate vs. Time Junction Temperature http://onsemi.com 3 MC74VHC157 DC CHARACTERISTICS (Voltages Referenced to GND) VCC Symbol Parameter Condition TA = 25_C (V) Min 1.5 0.7 VCC VIH High--Level Input Voltage 2.0 3.0 to 5.5 VIL Low--Level Input Voltage 2.0 3.0 to 5.5 VOH High--Level Output Voltage VOL Low--Level Output Voltage TA ≤85_C Typ Max Min 2.0 3.0 4.5 1.9 2.9 4.4 VIN = VIH or VIL IOH = --4 mA IOH = --8 mA 3.0 4.5 2.58 3.94 VIN = VIH or VIL IOL = 50 mA 2.0 3.0 4.5 VIN = VIH or VIL IOH = 4 mA IOH = 8 mA Min 1.5 0.7 VCC 0.5 0.3 VCC VIN = VIH or VIL IOH = --50 mA --55_C ≤TA≤125_C Max 2.0 3.0 4.5 0.0 0.0 0.0 Max 1.5 0.7 VCC 0.5 0.3 VCC V 0.5 0.3 VCC 1.9 2.9 4.4 1.9 2.9 4.4 2.48 3.8 2.34 3.66 Unit V V 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 3.0 4.5 0.36 0.36 0.44 0.44 0.52 0.52 V IIN Input Leakage Current VIN = 5.5 V or GND 0 to 5.5 ±0.1 ±1.0 ±1.0 mA ICC Quiescent Supply Current VIN = VCC or GND 5.5 4.0 40.0 40.0 mA AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0 ns) TA = 25_C Symbol tPLH, tPHL tPLH, tPHL tPLH, tPHL CIN Characteristic Propagation Delay, A to B to Y Propagation Delay, S to Y Propagation Delay, E to Y Test Conditions Min TA ≤85_C --55_C ≤TA≤125_C Typ Max Typ Max Typ Max Unit ns VCC = 3.3 ± 0.3 V CL = 15 pF CL = 50 pF 6.2 8.7 9.7 13.2 1.0 1.0 11.5 15.0 1.0 1.0 11.5 15.0 VCC = 5.0 ± 0.5 V CL = 15 pF CL = 50 pF 4.1 5.6 6.4 8.4 1.0 1.0 7.5 9.5 1.0 1.0 7.5 9.5 VCC = 3.3 ± 0.3 V CL = 15 pF CL = 50 pF 8.4 10.9 13.2 16.7 1.0 1.0 15.5 19.0 1.0 1.0 15.5 19.0 VCC = 5.0 ± 0.5 V CL = 15 pF CL = 50 pF 5.3 6.8 8.1 10.1 1.0 1.0 9.5 11.5 1.0 1.0 9.5 11.5 VCC = 3.3 ± 0.3 V CL = 15 pF CL = 50 pF 8.7 11.2 13.6 17.1 1.0 1.0 16.0 19.5 1.0 1.0 16.0 19.5 VCC = 5.0 ± 0.5 V CL = 15 pF CL = 50 pF 5.6 7.1 8.6 10.6 1.0 1.0 10.0 12.0 1.0 1.0 10.0 12.0 4 10 Input Capacitance 10 10 ns ns pF Typical @ 25_C, VCC = 5.0 V CPD Power Dissipation Capacitance (Note 7) 20 pF 7. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD ¯ VCC ¯ fin + ICC. CPD is used to determine the no--load dynamic power consumption: PD = CPD ¯ VCC2 ¯ fin + ICC ¯ VCC. http://onsemi.com 4 MC74VHC157 NOISE CHARACTERISTICS (Input tr = tf = 3.0 ns; CL = 50 pF; VCC = 5.0 V) TA = 25_C Characteristic Symbol Typ Max Unit VOLP Quiet Output Maximum Dynamic VOL 0.3 0.8 V VOLV Quiet Output Minimum Dynamic VOL −0.3 −0.8 V VIHD Minimum High Level Dynamic Input Voltage 3.5 V VILD Maximum Low Level Dynamic Input Voltage 1.5 V VCC A, B, or S 50% tPLH Y VCC E 50% GND tPHL GND tPLH 50% VCC 50% VCC Y Figure 5. Switching Waveform tPHL Figure 6. Inverting Switching TEST POINT OUTPUT DEVICE UNDER TEST CL* *Includes all probe and jig capacitance. Figure 7. Test Circuit INPUT Figure 8. Input Equivalent Circuit http://onsemi.com 5 MC74VHC157 PACKAGE DIMENSIONS SOIC--16 D SUFFIX CASE 751B--05 ISSUE J --A-16 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 9 --B-1 P 8 PL 0.25 (0.010) 8 M B S G R K DIM A B C D F G J K M P R F X 45 _ C --T-- SEATING PLANE J M D 16 PL 0.25 (0.010) M T B S A S 0.10 (0.004) M T U V S S S K K1 2X L/2 16 9 J1 B --U-- L SECTION N--N J PIN 1 IDENT. 8 1 N 0.15 (0.006) T U S 0.25 (0.010) A --V-- M N F DETAIL E --W-- C 0.10 (0.004) --T-- SEATING PLANE D INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 TSSOP DT SUFFIX CASE 948F--01 ISSUE O 16X K REF 0.15 (0.006) T U MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 G H DETAIL E http://onsemi.com 6 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE --W--. DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 -----1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 -----0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ MC74VHC157 PACKAGE DIMENSIONS SOIC EIAJ--16 M SUFFIX CASE 966--01 ISSUE O 16 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). LE 9 Q1 E HE 1 M_ L 8 Z DETAIL P D e VIEW P A A1 b 0.13 (0.005) c M 0.10 (0.004) DIM A A1 b c D E e HE L LE M Q1 Z MILLIMETERS MIN MAX -----2.05 0.05 0.20 0.35 0.50 0.18 0.27 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 -----0.78 INCHES MIN MAX -----0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 -----0.031 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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