ETC OXFW911-TQ-A Ieee1394 to ata/atapi native bridge Datasheet

OXFW911
IEEE1394 to ATA/ATAPI Native Bridge
Data Sheet
FEATURES
•
•
•
•
•
•
•
•
•
•
S400 (50 Mbytes/s) compliant 1394-1995 Link and
Transaction layers
Compatible with 1394-1995 and 1394A Phys.
Microsoft Win98-Second Edition, Win2000 and Apple
MacOS generic driver support
SBP-2 Target Revision 4 compliant interface
Fully ATA-5 compliant (see T13-1321D)
Support for UDMA5 (ATA100)
Sustained data transfer of 35 MB/s
Supports PIO modes 0 to 4, DMA modes 0 to 2 and
Ultra DMA modes 0 to 5
ORB co-processor to accelerate translation of ORBs
to ATAPI commands
Supports ORB chaining for increased performance
•
•
•
•
•
•
•
•
•
High performance ATA command translation in
firmware using Reduced Block Command (RBC) set
Integrated 32-bit RISC processor (ARM7TDMI) with
on-chip scratch RAM
Optional External Serial ROM interface for
configuration data, user serial number, etc.
Integrated 512kb Flash memory
Blank Flash memory programming feature via 1394
bus
Firmware and Flash Programming Utilities supplied by
Oxford Semiconductor
3.3 Volts operation
Low Power CMOS
Ultra-thin 128-TQFP package (14 x 14 x 1 mm)
DESCRIPTION
The OXFW911 is a high-performance 1394 to
ATA/ATAPI (IDE) native bridge with an integrated target
Serial Bus Protocol (SBP-2 ) controller. By supporting
the SBP-2 protocol, the device can use generic SBP-2
drivers available in the Microsoft Windows 98SE, Microsoft
Windows 2000, Microsoft Millennium and Apple MacOS
(8.4 to 9.04) operating systems. MacOS support also
includes booting from Firewire disk.
The device is ideally suited for smart-cable or tailgate
interface applications for removable-media drives, compact
flash card readers, CD-ROM, CD-R, CD-RW, DVD-ROM,
DVD-RAM and hard disk drives, allowing IDE drives to be
connected to a 1394 serial bus in a plug-and-play fashion.
Both ATA and ATAPI devices are supported using the
same firmware.
This highly integrated device offers a two-chip solution to
native bridge applications using an external 1394 PHY. The
device is compatible with both 1394-1995 and 1394A
PHYs.
The LINK controller complies with 1394-1995 and 1394A
specifications. The 1394 transaction layer and SBP-2
protocol is implemented using a combination of the
ARM7TDMI (low-power 32-bit RISC processor), an ORB
(Operational Request Block) hardware co-processor and a
high performance buffer manager.
The buffer manager has a RAM bandwidth of 800Mbps. It
provides storage for 1394 and ATA/ATAPI packets,
Oxford Semiconductor Ltd.
25 Milton Park, Abingdon, Oxon, OX14 4SH, UK
Tel: +44 (0)1235 824900
Fax: +44(0)1235 821141
automatically storing them and passing them to the
appropriate destinations, without any intervention from the
processor. It also provides storage and manages the
sequencing of ORB fetching to reduce latency and improve
data throughput.
The configuration data including the IEEE OUI
(Organisational Unique Identifier) and device serial number
is stored in the Flash ROM which may be uploaded from
the 1394 bus, even when blank. The device also facilitates
firmware uploads from the 1394 bus.
The ORB co-processor translates ORBs as defined in the
SBP-2 protocol into ATA/ATAPI commands, and
automatically stores error/status messages at an address
specified by the host.
Concurrent operation of the ATA/ATAPI and 1394
interfaces are facilitated using the high throughput buffer
manager where LINK, ATAPI manager and ARM7TDMI
can perform interleaved accesses to the on-chip RAM
buffer. The high performance processor ensures that no
significant latency is incurred. The ATA command
translation is performed in firmware to meet RBC (Reduced
Block Commands) standard, T10-1228D. The ATA/ATAPI
Manager supports PIO modes 0 to 4, DMA modes 0 to 2
and Ultra DMA mode 0 to 5 and provides the interface to
the IDE bus. It is compliant with T13-1321D, ATA-5
specification, as well as support for ATA100.
 Oxford Semiconductor 2001
OXFW911 Data Sheet Revision 1.1 – Mar 2001
Part No. OXFW911-TQ-A
OXFORD SEMICONDUCTOR LTD.
OXFW911
CONTENTS
FEATURES ........................................................................................................................................1
DESCRIPTION ...................................................................................................................................1
CONTENTS........................................................................................................................................2
1
BLOCK DIAGRAM .......................................................................................................................3
2
PIN INFORMATION .....................................................................................................................4
3
PIN DESCRIPTIONS ....................................................................................................................5
4
OPERATING CONDITIONS ..........................................................................................................7
5
DC ELECTRICAL CHARACTERISTICS ........................................................................................7
6
AC ELECTRICAL CHARACTERISTICS ........................................................................................8
5.1
6.1
6.2
6.3
I/O BUFFERS ........................................................................................................................................................................ 7
IDE INTERFACE ................................................................................................................................................................... 8
1394 LINK-PHY INTERFACE ............................................................................................................................................. 11
EXTERNAL PROCESSOR INTERFACE............................................................................................................................ 13
7
TIMING WAVEFORMS...............................................................................................................14
8
PACKAGE INFORMATION ........................................................................................................29
9
ORDERING INFORMATION .......................................................................................................29
NOTES ............................................................................................................................................31
CONTACT DETAILS.........................................................................................................................32
DISCLAIMER ...................................................................................................................................32
Data Sheet Rev 1.1
Page 2
OXFW911
OXFORD SEMICONDUCTOR LTD.
1
BLOCK DIAGRAM
Buffer RAM
PD[7:0]
IDE_OE#
CTL[1:0]
PHY_CLK
LINK_ON
RAM
Manager
Link-Phy
interface
ID[15:0]
DMARQ
LPS
ATA/
ATAPI
manager
LREQ
DIOW#
DIOR#
IORDY
D[15:0]
A[16:0]
CS#[3:0]
External
Device
interface
OE#
Internal ARM7TDMI bus
DMACK#
INTRQ#
IA[2:0]
ORB Coprocessor
ICS#[1:0]
WE#
INT#
ARM7TDMI
Internal
FLASH
EE_DO
EE_DI
EE_CK
GPIO /
EEPROM
interface
SCRATCH
RAM
EE_CS
Figure 1: OXFW911 Block Diagram
Data Sheet Rev 1.1
Page 3
OXFW911
OXFORD SEMICONDUCTOR LTD.
PIN INFORMATION
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
GND
DMACK#
VDD
GND
IORDY
DIOR#
DIOW#
DMARQ
VDD
GND
ID15
ID0
VDD
GND
ID14
ID1
ID13
ID2
ID12
ID3
VDD
GND
ID11
ID4
ID10
ID5
ID9
ID6
VDD
GND
ID8
ID7
2
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
OXFW911-TQ-A
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
IRESET
IDE_OE#
INTRQ
INT#
A0
VDD
GPI
UIF
RESET#
GND
A1
A2
A3
A4
A5
A6
VDD
GND
A7
A8
A9
A10
A11
A12
VDD
GND
A13
A14
A15
A16
WE#
CS0#
NC
D15
D14
D13
D12
D11
GND
VDD
D10
D9
D8
D7
D6
GND
VDD
D5
D4
D3
D2
D1
VDD
TEST_SEL
VDD
D0
GND
GND
CS1#
OE#
GND
VDD
TEST0
TEST1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
IA1
IA0
IA2
ICS0#
ICS1#
LINKON
LPS
PD7
PD6
GND
VDD
PD5
PD4
PD3
PD2
GND
VDD
PD1
PD0
CTL1
CTL0
GND
PHYCLK
VDD
LREQ
NC
CS3#
CS2#
GPO1
GPO2
GPO3
CKOUT
Figure 2: Pinout (package = 128 TQFP)
Data Sheet Rev 1.1
Page 4
OXFW911
OXFORD SEMICONDUCTOR LTD.
3
PIN DESCRIPTIONS
Name
Description
I/O
PD[7:0]
Phy-Link Data Bus
I/O
I
O
IU
O
CTL[1:0]
PHYCLK
LREQ
LINKON
LPS
Phy-Link Control Bus
49.152 MHz clock sourced by PHY
Link Request
Requests link to power up when in a low power mode
Indicates to phy that link is powered and ready
T_I/O
D[15:0]
ARM external data bus
T_O
A[16:0]
ARM external address bus
T_O
CS#[3:0]
28
T_O
OE#
34
61
T_O
T_IU
WE#
INT#
ARM external chip selects. CS0# is always used for program
ROM.
ARM external output enable. Active when reading data from
external devices including program ROM
Write Enable. Active when writing to external devices
External ARM interrupt
T_I/O
ID[15:0]
IDE data bus
T_O
T_O
IA[2:0]
ICS#[1:0]
T_O
IDE_OE#
T_O
T_I
T_O
T_O
T_O
T_O
T_I
IRESET
DMARQ
DIOW#
DIOR#
IORDY
DMACK#
INTRQ
IDE address bus
IDE chip select. Used to select the Command Block or
Control Block registers.
IDE output enable. Only used when external buffering is
required to drive IDE data bus
IDE interface reset
O
O
O
T_IU
GPO1
GPO2
GPO3
GPI
General Purpose Output 1
General Purpose Output 2
General Purpose Output 3
General Purpose Input
IU
T_O
I
RESET#
CKOUT
TEST_SEL,
TEST[1:0]
UIF
Global reset for the OXFW911. Active Low.
Clock output. 49.152 MHz clock output.
‘100’ = NORMAL OPERATION. Other settings are for
foundry test purposes only.
Leave unconnected to use internal Flash, tie low to use only
external device
AC VDD
DC VDD
Supplies power to output buffers in switching (AC) state
Power supply. Supplies power to core logic, input buffers
and output buffers in steady state
1394 PHY-LINK interface
104, 105, 108, 109, 110, 111, 114,
115
116,117
119
121
102
103
ARM external interface
2, 3, 4, 5, 6, 9, 10, 11, 12, 13, 16,
17, 18, 19, 20, 24
35, 36, 37, 38, 41, 42, 43, 44, 45,
46, 49, 50, 51, 52, 53, 54, 60
123, 124, 27, 33
IDE interface
86, 82, 80, 78, 74, 72, 70, 66, 65,
69, 71, 73, 77, 79, 81, 85
99, 97, 98
101, 100
63
64
89
90
91
92
95
62
EEPROM interface
125
126
127
58
Miscellaneous Pins
56
128
22, 32, 31
Dir 1
57
IU
Power and ground2
15, 8, 40, 48, 59, 76, 94, 107, 113
30, 21, 23, 68, 84, 88, 120
VDD
VDD
Data Sheet Rev 1.1
IDE interface write strobe
IDE interface read strobe
Page 5
OXFW911
OXFORD SEMICONDUCTOR LTD.
14, 7, 39, 47, 55, 67, 75, 93, 96,
106, 112,
29, 25, 26, 83, 87, 118
Other
1, 122
GND
AC GND
Supplies GND to output buffers in switching (AC) state
GND
DC GND
Ground (0 volts). Supplies GND to core logic, input buffers
and output buffers in steady state
NC
No Connect
Table 1: Pin Descriptions
Note 1: Direction key:
I
IU
ID
O
I/O
Input
Input with internal pull-up
Input with external pull-down
Output
Bi-directional
T_I
5V tolerant input
T_O
T_I/O
5V tolerant output
5V tolerant bi-directional
GND
VDD
NC
Ground
3.3V power
No Connect
Note 2: Power & Ground
There are two GND and two VDD rails internally. One set of rails supply power and ground to output buffers while in switching
state (called AC power) and another rail supply the core logic, input buffers and output buffers in steady-state (called DC rail).
The rails are not connected internally. This precaution reduces the effects of simultaneous switching outputs and undesirable RF
radiation from the chip.
Data Sheet Rev 1.1
Page 6
OXFW911
OXFORD SEMICONDUCTOR LTD.
Configuration & Operation
4
OPERATING CONDITIONS
Symbol
VDD
VIN
VIN
IIN
T STG
Parameter
DC supply voltage
DC input voltage (3.3V IO)
DC input voltage (5V tolerant IO)
DC input current
Storage temperature
Min
-0.3
-0.3
-0.3
-40
Max
3.8
VDD + 0.3
5.5
+/- 10
125
Units
V
V
V
mA
°C
Min
3.15
0
Max
3.6
70
Units
V
°C
Table 2: Absolute maximum ratings
Symbol
VDD
TC
Parameter
DC supply voltage
Temperature
Table 3: Recommended operating conditions
5
5.1
DC ELECTRICAL CHARACTERISTICS
I/O Buffers
Symbol
VDD
VIH
Parameter
Supply voltage
Input high voltage
VIL
Input low voltage
CIL
COL
IIH
IIL
VOH
VOH
VOL
VOL
IOZ
Cap of input buffers
Cap of output buffers
Input high leakage current
Input low leakage current
Output high voltage
Output high voltage
Output low voltage
Output low voltage
3-state output leakage current
Symbol
ICC
Parameter
Operating supply current in
normal mode
Condition
Commercial
CMOS Interface
CMOS Schmitt trig
CMOS Interface 1
CMOS Schmitt trig
Min
3.0
2.0
2.0
Vin = VDD
Vin = VSS
IOH = -1 µA
IOH = -1mA to –24mA
IOL = 1 µA
IOL = 1mA to 24mA
-10
-10
Condition
VDD = 3.3V
T=25°C
VDD – 0.05
2.4
Max
3.6
Units
V
V
0.8
0.8
4.0
4.0
10
10
V
-10
0.05
0.4
10
Typical
85
Max
TBD
Operating supply current in
Power-down mode
pF
pF
µA
µA
V
V
V
V
µA
Units
mA
Table 4: Characteristics of OXFW911 I/O buffers
Data Sheet Rev 1.1
Page 7
OXFW911
OXFORD SEMICONDUCTOR LTD.
6
AC ELECTRICAL CHARACTERISTICS
6.1
IDE interface
Symbol
t0
t1
t2
t2i
t3
t4
t5
t6
t6z
t9
tRD
tA
tB
tA
Parameter
Cycle Time
Address Valid to DIOR# / DIOW#
setup
DIOR# / DIOW# pulse width
DIOR# / DIOW# recovery time
DIOW# data setup (min )
DIOW# data hold
DIOR# data setup ( min )
DIOR# data hold ( min )
DIOR# data tristate (max )
DIOR# / DIOW# to address valid
hold
Read Data Valid to IORDY active if
IORDY initially low after tA
IORDY Setup time
IORDY Pulse Width ( max )
IORDY assertion to release
Mode 0
600
80
Mode 1
400
80
Mode 2
360
40
Mode 3
200
40
Mode 4
120
40
Units
ns
ns
320
60
40
50
5
30
40
320
45
40
35
5
30
40
320
30
40
20
5
30
40
80
80
30
40
20
5
30
40
80
40
20
40
20
5
30
40
ns
ns
ns
ns
ns
ns
ns
ns
0
0
0
0
0
ns
35
1250
5
35
1250
5
35
1250
5
35
1250
5
35
1250
5
ns
ns
ns
Table 5: OXFW911 IDE PIO / Register Transfers
Data Sheet Rev 1.1
Page 8
OXFW911
OXFORD SEMICONDUCTOR LTD.
Symbol
t0
tD
tE
tF
tG
tH
tI
tJ
tKr
tKw
tLr
tLw
tM
tN
tZ
Parameter
Cycle time
DIOR# / DIOW#
DIOR# data access ( max )
DIOR# data hold ( min )
DIOR# / DIOW# data setup
DIOW# data hold
DMACK to DIOR# / DIOW# setup ( min )
DIOR# / DIOW# to DMACK hold ( min )
DIOR# negated pulse width
DIOW# negated pulse width
DIOR# to DMARQ delay ( max )
DIOW# to DMARQ delay ( max )
IDCS[1:0] valid to DIOR# / DIOW#
IDCS[1:0] hold
DMACK to tristate ( max )
Mode 0
480
240
150
5
100
20
0
20
80
240
120
40
80
40
20
Mode 1
160
80
60
5
30
15
0
5
80
80
40
40
40
40
25
Mode 2
120
80
50
5
20
10
0
5
40
40
35
35
40
40
25
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Table 6: OXFW911 Multiword DMA timings
Data Sheet Rev 1.1
Page 9
OXFW911
OXFORD SEMICONDUCTOR LTD.
Symbol
t2cyc
tcyc
t2cyc
tds
tdh
tdvs
tdvh
tfs
tli
tmli
tui
taz
tzah
tzad
tenv
tsr
trfs
trp
tiordyz
tziordy
tack
tss
Parameter
Typical sustained average two
cycle time
Cycle time allowing for clock
variations ( refer to ATA spec)
Two cycle time allowing for clock
variations ( refer to ATA spec )
Data setup time at recipient
Data hold time at recipient
Data valid setup time at sender
(from data bus being valid until
STROBE edge )
Data valid hold time at sender (from
STROBE edge until data may
become invalid
First STROBE time (for device to
first negate DSTROBE from STOP
during a data-in burst)
Limited interlock time
Interlock time with minimum
Unlimited interlock time
Maximum time allowed for output
drivers to release (from being
asserted or negated)
Minimum delay time required for
output drivers to assert or negate
(from released state)
Envelope time ( from DMACK# to
STOP and HDMARDY# during
data-out burst initiation
STROBE to DMARDY time ( refer
to ATA spec
Ready-to-final-STROBE time ( no
STROBE edges shall be sent this
long after the negation of
DDMARDY#
Ready-to-pause time ( time that
recipient shall wait to initiate pause
after negating DMARDY# )
Pull-up time before allowing IORDY
to be released
Minimum time a device shall wait
before driving IORDY
Setup and hold times for DMACK#
(before assertion or negation )
Time from STROBE edge to
negation of DMARQ or assertion of
STOP (when sender terminates a
burst )
Mode 0
min
240
Mode 0
max
Mode 1
min
160
Mode1
max
Mode 2
min
120
Mode 2
max
Units
ns
112
75
55
ns
230
156
117
ns
15
5
70
10
5
48
7
5
34
ns
ns
ns
6
6
6
ns
0
230
0
200
0
170
ns
0
20
0
150
0
20
0
150
0
20
0
150
ns
ns
ns
ns
10
20
0
20
10
20
0
70
20
10
20
0
70
20
ns
70
ns
50
30
20
ns
75
70
60
ns
160
125
20
100
20
ns
20
ns
0
0
0
ns
20
20
20
ns
50
50
50
ns
Table 7: OXFW911 Ultra DMA timings
Data Sheet Rev 1.1
Page 10
OXFW911
OXFORD SEMICONDUCTOR LTD.
Symbol
Parameter
t2cyctyp
Typical sustained average two
cycle time
Cycle time allowing for clock
variations ( refer to ATA spec)
Two cycle time allowing for clock
variations ( refer to ATA spec )
Data setup time at recipient
Data hold time at recipient
Data valid setup time at sender
(from data bus being valid until
STROBE edge )
Data valid hold time at sender
(from STROBE edge until data
may become invalid
First STROBE time (for device to
first negate DSTROBE from
STOP during a data-in burst)
Limited interlock time
Interlock time with minimum
Unlimited interlock time
Maximum time allowed for output
drivers to release (from being
asserted or negated)
Minimum delay time required for
output drivers to assert or negate
(from released state)
Envelope time ( from DMACK# to
STOP and HDMARDY# during
data-out burst initiation
Ready-to-final-STROBE time ( no
STROBE edges shall be sent this
long after the negation of
DDMARDY#
Ready-to-pause time ( time that
recipient shall wait to initiate
pause after negating DMARDY# )
Pull-up time before allowing
IORDY to be released
Minimum time a device shall wait
before driving IORDY
Setup and hold times for
DMACK# (before assertion or
negation )
Time from STROBE edge to
negation of DMARQ or assertion
of STOP (when sender terminates
a burst )
tcyc
t2cyc
tds
tdh
tdvs
tdvh
tfs
tli
tmli
tui
taz
tzah
tzad
tenv
trfs
trp
tiordyz
tziordy
tack
tss
Mode 3
min
100
Mode 3
max
Mode 4
min
60
Mode4
max
Mode5
min
40
Mode5
max
Unit
s
ns
39
25
20
ns
86
57
40
ns
7
5
20
5
5
6
4.0
4.6
4.8
ns
ns
ns
6
6
4.8
ns
0
130
0
120
0
90
ns
0
20
0
100
0
20
0
100
0
75
20
0
10
ns
ns
ns
ns
20
0
ns
50
ns
50
ns
85
ns
20
ns
10
20
0
20
10
20
0
55
20
60
100
55
20
60
100
20
20
0
0
0
ns
20
20
20
ns
50
50
50
ns
Table 7a: OXFW911 Ultra DMA timings (cont)
Data Sheet Rev 1.1
Page 11
OXFW911
OXFORD SEMICONDUCTOR LTD.
6.2
1394 Link-Phy interface
The timings for 1394 Link – Phy are shown below :
Symbol
tlsu
tlh
Tld1
Tld2
Tld3
tcyc
Parameter
Setup Time, PD[7:0] and CTL[1:0] before PhyClk
Hold Time, PD[7:0] and CTL[1:0] after PhyClk
Delay Time, PhyClk input high to initial instance of PD[7:0], CTL[1:0]
and Lreq outputs valid
Delay Time, PhyClk input high to subsequent instance(s) of PD[7:0],
CTL[1:0] and Lreq outputs valid
Delay Time, PhyClk input high to PD[7:0], CTL[1:0] and Lreq outputs
invalid (high impedance)
Duty Cycle
Min
8
0
2
Max
10
Units
ns
ns
ns
2
10
ns
2
10
ns
45
55
%
Table 8: OXFW911 Link-Phy interface timings
Data Sheet Rev 1.1
Page 12
OXFW911
OXFORD SEMICONDUCTOR LTD.
6.3
Name
tas
tws
taddr
tah
tdsa
tdha
twds
twdh
tcsw
tadw
twe
External Processor Interface
Description
Common Timings
CSx# and OE# falling to valid Address
Wait State Additional Delay (number of wait states (WS) * 20 ns)
Address Valid
Common Read Timings
Address hold after CSx# or OE# rising
Data setup to CSx# and OE# rising
Data hold after CSx# and OE# rising
Common Write Timings
Data valid to WE# rising
Data hold after WE# rising
CS# setup before WE# valid
Address setup before WE# valid
WE# valid
min (ns)
max (ns)
0
20
60
2
300
40+tws
0
44
0
-
17
4
7
5
20
17+(tws-20)
7
9
7
20+tws
Table 9: External Processor Interface timings
Data Sheet Rev 1.1
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7
TIMING WAVEFORMS
t0
ADDR valid
DIOR# /
DIOW#
t2
t9
t1
t2i
t3
t4
ID[7:0]
(WRITE)
t6z
t5
t6
ID[7:0]
(READ)
IORDY
(Note1)
tA
tC
IORDY
(Note2)
IORDY
(Note3)
tRD
tB
tC
Figure 3: PIO / Register Transfer to / from IDE device
Notes : Negation of IORDY by the drive is used to extend the PIO cycle. The determination of whether the cycle is ot be
extended is made by the host after tA from the Assertion of DIOR# or DIOW#. The assertion and negation of IORDY are
described in the following three cases : 1)
2)
3)
Device never negates IORDY and no wait is generated.
Device negates IORDY before tA, but causes IORDY to be asserted before tA. IORDY is released prior to negation and
may be asserted for no more than 5ns before release : no wait generated.
Device negated IORDY before tA. IORDY is released prior to negation and may be asserted for no more than 5ns before
release : wait generated. The cycle completes after IORDY is reasserted. For cycles where a wait is generated and DIOR#
is asserted, the device shall place read data on DD[7:0] for tRD before asserting IORDY
Data Sheet Rev 1.1
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TIMING WAVEFORMS
CS0# / CS1#
tM
tN
t0
DMARQ
tL
DMACK#
tI
tD
tK
tJ
DIOR# / DIOW#
tE
tZ
READ ID[15:0]
tG
tF
WRITE ID[15:0]
tG
tH
Figure 4: MultiWord DMA transfer to / from IDE device
Data Sheet Rev 1.1
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DMARQ
(device)
tui
tenv
tfs
tack
DMACK(host)
tzad
STOP(host)
(DIOW#)
HDMARDY(host)
(DIOR#)
tziordy
DSTROBE(device)
(IORDY)
taz
tdvs
tdvh
ID[15:0]
IA[2:0], ICS#[1:0]
tack
Figure 5: Initiating an Ultra DMA data-in burst
Data Sheet Rev 1.1
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t2cyc
tcyc
tcyc
DSTROBE(device)
(IORDY)
tdvh
tdvs
tdvh
tdvs
tdvh
ID[15:0]
(device)
DSTROBE(host)
IORDY
tds
tdh
tdh
tds
tdh
ID[15:0] (host)
Figure 6: Sustained Ultra DMA data-in burst
Data Sheet Rev 1.1
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DMARQ(device)
DMACK(host)
STOP(host)
DIOW#
trp
tsr
DSTROBE(device)
IORDY
trfs
DSTROBE(device)
IORDY
ID[15:0] (host)
Figure 7: Host pausing an Ultra DMA data-in burst
Data Sheet Rev 1.1
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DMARQ(device)
DMACK(host)
tli
tli
tmli
STOP(host)
DIOW#
tack
HDMARDY(host)
DIOR#
tss
tiordyz
DSTROBE(device)
IORDY
taz
ID[15:0] (host)
tzah
CRC
tack
IA[2:0],
ICS[1:0]
Figure 8: Device terminating an Ultra DMA data-in burst
Data Sheet Rev 1.1
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DMARQ(device)
DMACK(host)
tzah
trp
taz
STOP(host)
DIOW#
tack
HDMARDY(host)
DIOR#
trfs
tli
tmli
tiordyz
DSTROBE(device)
IORDY
tdvs
tdvh
CRC
ID[15:0] (host)
tack
IA[2:0],
ICS[1:0]
Figure 9: Host terminating an Ultra DMA data-in burst
Data Sheet Rev 1.1
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DMARQ
(device)
tui
tenv
tack
DMACK(host)
tli
tui
STOP(host)
(DIOW#)
HSTROBE(host)
(DIOR#)
tziordy
DDMARDY(device)
(IORDY)
tdvs
tdvh
ID[15:0]
IA[2:0], ICS#[1:0]
tack
Figure 10: Initiating an Ultra DMA data-out burst
Data Sheet Rev 1.1
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t2cyc
tcyc
tcyc
HSTROBE(host)
tdvh
tdvs
tdvh
tdvs
tdvh
ID[15:0] (host)
HSTROBE(device)
tds
tdh
tdh
tds
tdh
ID[15:0]
(device)
Figure 11: Sustained Ultra DMA data-out burst
Data Sheet Rev 1.1
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DMARQ(device)
trp
DMACK(host)
STOP(host)
DIOW#
tsr
DDMARDY(device)
IORDY#
trfs
HSTROBE(host)
DIOR#
ID[15:0] (host)
Figure 12: Device pausing an Ultra DMA data-in burst
Data Sheet Rev 1.1
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DMARQ(device)
DMACK(host)
tli
tli
tmli
STOP(host)
DIOW#
tack
DDMARDY(device)
IORDY#
tiordyz
tss
HSTROBE(host)
DIOR#
tdvs
ID[15:0] (host)
tdvh
CRC
tack
IA[2:0],
ICS[1:0]
Figure 13: Host Terminating an Ultra DMA data-out burst
Data Sheet Rev 1.1
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tli
DMARQ(device)
DMACK(host)
trp
STOP(host)
DIOW#
tack
DDMARDY(device)
IORDY#
trfs
tli
tmli
tiordyz
HSTROBE(device)
DIOR#
tdvs
ID[15:0] (host)
tdvh
CRC
tack
IA[2:0],
ICS[1:0]
Figure 14: Device Terminating an Ultra DMA data-out burst
Data Sheet Rev 1.1
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tcyc
CLK
1
2
3
4
PD[7:0]
CTL[1:0]
LReq
tlh
tlsu
Figure 15: Phy to Link timings
tcyc
CLK
1
2
3
4
PD[7:0]
CTL[1:0]
LReq
tld1
tld2
tld3
Figure 16: Link to Phy timings
Data Sheet Rev 1.1
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taddr
tws
Address
Data
tas
tdsa
tdha
CS#
tah
OE#
WE#
taddr
taddr
Address
Data
tas
tdsa
tdha
tdsa
tdha
CS#
tah
OE#
WE#
tws
tws
Figure 17: External Processor Bus read timings
Data Sheet Rev 1.1
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taddr
tws
Address
Data
tas
twds
twdh
CS#
tah
OE#
WE#
tcsw
twe
taddr
taddr
Address
Data
tas
twds
twdh
twds
twdh
CS#
tah
OE#
WE#
twe
tadw
twe
Figure 17a: External Processor Bus write timings
Data Sheet Rev 1.1
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8
PACKAGE INFORMATION
Figure 18: 128 TQFP package information
9
ORDERING INFORMATION
Data Sheet Rev 1.1
Page 29
OXFORD SEMICONDUCTOR LTD.
OXFW911
OXFW911-TQ - A
Revision
Package Type – 128 TQFP
Data Sheet Rev 1.1
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OXFW911
OXFORD SEMICONDUCTOR LTD.
NOTES
This page has been intentionally left blank
Data Sheet Rev 1.1
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OXFORD SEMICONDUCTOR LTD.
OXFW911
CONTACT DETAILS
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Data Sheet Rev 1.1
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