CY7C007A32 K/16 K × 8, 16 K × 9 Dual-Port Static RAM CY7C006A/CY7C007A CY7C016A/CY7C017A 32 K/16 K × 8, 16 K × 9 Dual-Port Static RAM 32 K/16 K × 8, 16 K × 9 Dual-Port Static RAM Features ■ Automatic power-down ■ Expandable data bus to 16/18 bits or more using Master/Slave chip select when using more than one device ■ On-chip arbitration logic ■ Semaphores included to permit software handshaking between ports ■ True dual-ported memory cells which allow simultaneous access of the same memory location ■ 16 K × 8 organization (CY7C006A) ■ 32 K × 8 organization (CY7C007A) ■ 16 K × 9 organization (CY7C016A) ■ 32 K × 9 organization (CY7C017A) ■ INT flags for port-to-port communication ■ 0.35-micron CMOS for optimum speed/power ■ Pin select for Master or Slave ■ Commercial temperature range 12[1]/15/20 ■ High-speed access: ns ■ Low operating power ❐ Active: ICC = 180 mA (typical) ❐ Standby: ISB3 = 0.05 mA (typical) ■ Available in 68-pin PLCC (CY7C006A, CY7C007A and CY7C017A), 64-pin TQFP (CY7C006A), and in 80-pin TQFP (CY7C007A and CY7C016A) ■ Fully asynchronous operation ■ Pb-Free packages available Logic Block Diagram R/WL R/WR CEL CER OEL OER [2] 8/9 8/9 I/O0L–I/O7/8L [4] A0L–A13/14L [4] A0L–A13/14L CEL OEL R/WL SEML BUSYL INTL I/O Control 14/15 Address Decode I/O Control Address Decode True Dual-Ported RAM Array 14/15 14/15 [4] A0R–A13/14R 14/15 [4] A0R–A13/14R CER OER R/WR SEMR Interrupt Semaphore Arbitration [3] [3] Notes 1. See page 7 for Load Conditions. 2. I/O0–I/O7 for x8 devices; I/O0–I/O8 for x9 devices. 3. BUSY is an output in master mode and an input in slave mode. 4. A0–A13 for 16K; A0–A14 for 32K devices. Cypress Semiconductor Corporation Document Number: 38-06045 Rev. *F [2] I/O0R–I/O7/8R • BUSYR INTR M/S 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised December 17, 2010 [+] Feedback CY7C006A/CY7C007A CY7C016A/CY7C017A Contents Pin Configurations ........................................................... 3 Selection Guide ................................................................ 4 Pin Definitions .................................................................. 5 Architecture ...................................................................... 5 Functional Description ..................................................... 5 Write Operation ........................................................... 5 Read Operation ........................................................... 5 Interrupts ..................................................................... 5 Busy ............................................................................ 6 Master/Slave ............................................................... 6 Semaphore Operation ................................................. 6 Maximum Ratings ............................................................. 7 Operating Range ............................................................... 7 Electrical Characteristics ................................................. 7 Capacitance Table ............................................................ 8 AC Test Loads and Waveforms ....................................... 8 AC Test Loads (Applicable to –12 only) ......................... 8 Switching Characteristics ................................................ 9 Data Retention Mode ...................................................... 10 Timing .............................................................................. 10 Document Number: 38-06045 Rev. *F Switching Waveforms .................................................... 11 Read Cycle No. 1 (Either Port Address Access) ....... 11 Read Cycle No. 2 (Either Port CE/OE Access) ......... 11 Read Cycle No. 3 (Either Port) .................................. 11 Write Cycle No. 1: R/W Controlled Timing ................ 12 Write Cycle No. 2: CE Controlled Timing .................. 12 Semaphore Read After Write Timing, Either Side ..... 13 Timing Diagram of Semaphore Contention ............... 13 Timing Diagram of Read with BUSY (M/S=HIGH) .... 14 Write Timing with Busy Input (M/S=LOW) ................. 14 CELValid First: ........................................................... 15 Left Address Valid First: ............................................ 15 Busy Timing Diagram No. 1 (CE Arbitration) ............. 15 Busy Timing Diagram No. 2 (Address Arbitration) .... 15 Interrupt Timing Diagrams ......................................... 16 Ordering Information ...................................................... 18 16K x 8 Asynchronous Dual-Port SRAM ................... 18 Ordering Code Definitions ......................................... 18 Package Diagrams .......................................................... 19 Document History Page ................................................. 21 Sales, Solutions, and Legal Information ...................... 22 Worldwide Sales and Design Support ....................... 22 Products .................................................................... 22 PSoC Solutions ......................................................... 22 Page 2 of 22 [+] Feedback CY7C006A/CY7C007A CY7C016A/CY7C017A Pin Configurations I/O2L I/O3L I/O4L 10 I/O5L GND I/O6L I/O7L 13 A11L A10L A9L A8L A7L A6L 64 63 62 61 VCC 68 67 65 A14L A13L 2 1 A12L CEL 3 66 SEML 4 [6] R/WL 5 I/O0L NC(I/O8L[5]) OEL 8 58 12 57 56 55 14 15 CY7C006A (16K x 8) CY7C007A (32K x 8) CY7C017A (32K x 9) 16 17 GND I/O0R I/O1R 18 I/O2R VCC 21 22 23 24 19 BUSYL GND M/S 51 50 42 43 BUSYR INTR A0R A1R A2R A3R A4R A6R A5R 41 A8R A7R A9R 40 38 39 36 37 A11R A10R A12R 35 GND A13R 32 33 34 31 44 CER A 14R[6] 26 30 46 45 SEMR 25 29 A0L 53 47 OER R/WR A3L A2L A1L INTL 49 48 27 28 A5L A4L 54 52 20 I/O7R I/O3R I/O4R I/O5R I/O6R 7 6 I/O1L 9 60 59 11 NC(I/O8R[5] ) VCC 68-pin PLCC Top View CE L NC A14L A13L[6] VCC A12L A11L A10L A9L A8L A7L A6L 74 72 71 70 69 68 67 66 65 64 63 62 61 NC NC SEM L 75 73 R/W L 76 NC OE L 78 77 1 79 NC I/O 2L I/O 3L 80 I/O1L I/O0L 80-pin TQFP Top View 60 NC A5L A4L 2 59 I/O 4L 3 4 58 57 I/O 5L 5 56 A3L A2L GND I/O 6L 6 55 A1L 7 54 A0L I/O 7L 8 53 V CC 9 10 52 51 50 INTL BUSYL GND M/S 49 BUSYR NC GND I/O0R I/O1R CY7C007A (32K x 8) CY7C016A (16K X 9) 11 12 37 38 39 40 A6R A5R NC NC A7R 34 A9R 35 36 33 A8R 32 A11R A10R GND OER NC I/O7R 31 NC A12R 41 29 30 20 A13R NC 28 A4R A 14R[6] 43 42 27 18 19 26 I/O 5R I/O 6R NC 44 CER 17 25 46 45 I/O 3R I/O 4R SEMR 15 16 A0R A1R 23 24 V CC 47 R/WR INTR 14 22 I/O2R 48 21 13 A2R A3R NC Notes 5. This pin is I/O for CY7C017A only. 6. A14 is a no connect pin for 16K devices. Document Number: 38-06045 Rev. *F Page 3 of 22 [+] Feedback CY7C006A/CY7C007A CY7C016A/CY7C017A Pin Configurations (continued) A6L A5L 49 54 A7L A12L 56 55 A8L VCC 57 51 50 CEL A13L A9L SEML 59 52 R/WL 60 53 OEL 62 61 A11L A10L I/O0L 63 58 I/O1L 64 64-pin TQFP Top View I/O2L 1 48 A4L I/O3L I/O4L 2 47 3 4 46 45 A3L A2L 5 44 A0L I/O6L I/O7L 6 43 7 42 INTL BUSYL GND M/S I/O5L GND CY7C006A (16K x 8) A1L A2R I/O5R 16 33 A4R 30 31 A7R 32 29 BUSYR A3R A6R A5R 28 A8R 41 A9R A11R A10R R/WR 27 35 34 25 26 14 15 24 I/O3R I/O4R A12R A0R A1R GND 36 23 13 22 VCC CER A13R 37 21 12 SEMR INTR I/O2R 19 20 38 OER 11 18 40 39 17 9 10 I/O6R 8 I/O7R VCC GND I/O0R I/O1R Selection Guide CY7C006A CY7C007A CY7C016A CY7C017A –12[7] CY7C006A CY7C007A CY7C016A CY7C017A –15 CY7C006A CY7C007A CY7C016A CY7C017A –20 Maximum Access Time (ns) 12 15 20 Typical Operating Current (mA) 195 190 180 Typical Standby Current for ISB1 (mA) (Both Ports TTL Level) 55 50 45 0.05 0.05 0.05 Typical Standby Current for ISB3 (mA) (Both Ports CMOS Level) Note 7. See page 7 for Load Conditions. Document Number: 38-06045 Rev. *F Page 4 of 22 [+] Feedback CY7C006A/CY7C007A CY7C016A/CY7C017A Pin Definitions Left Port Right Port Description CEL CER Chip Enable R/WL R/WR Read/Write Enable OEL OER Output Enable A0L–A14L A0R–A14R Address I/O0L–I/O8L I/O0R–I/O8R Data Bus Input/Output (I/O0–I/O7 for ×8 devices and I/O0–I/O8 for ×9) SEML SEMR Semaphore Enable INTL INTR Interrupt Flag BUSYL BUSYR Busy Flag M/S Master or Slave Select VCC Power GND Ground NC No Connect Architecture The CY7C006A, CY7C007A, CY7C016A and CY7C017A consist of an array of 32K/16K words of 8 bits and 32K words of 9 bits each of dual-port RAM cells, I/O and address lines, and control signals (CE, OE, R/W). These control pins permit independent access for reads or writes to any location in memory. To handle simultaneous writes/reads to the same location, a BUSY pin is provided on each port. Two Interrupt (INT) pins can be utilized for port-to-port communication. Two Semaphore (SEM) control pins are used for allocating shared resources. With the M/S pin, the devices can function as a master (BUSY pins are outputs) or as a slave (BUSY pins are inputs). The devices also have an automatic power-down feature controlled by CE. Each port is provided with its own Output Enable control (OE), which allows data to be read from the device. Functional Description The CY7C006A, CY7C007A, CY7C016A, and CY7C017A are low-power CMOS 32K × 8/9 and 16K × 8/9 dual-port static RAMs. Various arbitration schemes are included on the devices to handle situations when multiple processors access the same piece of data. Two ports are provided, permitting independent, asynchronous access for reads and writes to any location in memory. The devices can be utilized as standalone 8/9-bit dual-port static RAMs or multiple devices can be combined in order to function as a 16/18-bit or wider master/slave dual-port static RAM. An M/S pin is provided for implementing 16/18-bit or wider memory applications without the need for separate master and slave devices or additional discrete logic. Application areas include interprocessor/multiprocessor designs, communications status buffering, and dual-port video/graphics memory. Each port has independent control pins: Chip Enable (CE), Read or Write Enable (R/W), and Output Enable (OE). Two flags are provided on each port (BUSY and INT). BUSY signals that the port is trying to access the same location currently being accessed by the other port. The Interrupt flag Document Number: 38-06045 Rev. *F (INT) permits communication between ports or systems by means of a mail box. The semaphores are used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. The semaphore logic is comprised of eight shared latches. Only one side can control the latch (semaphore) at any time. Control of a semaphore indicates that a shared resource is in use. An automatic power-down feature is controlled independently on each port by a Chip Select (CE) pin. The CY7C006A, CY7C007A and CY7C017A are available in 68-pin PLCC packages, the CY7C006A is also available in 64-pin TQFP, and the CY7C007A and CY7C016A are also available in 80-pin TQFP packages. Write Operation Data must be set up for a duration of tSD before the rising edge of R/W in order to guarantee a valid write. A write operation is controlled by either the R/W pin (see Write Cycle No. 1 waveform) or the CE pin (see Write Cycle No. 2 waveform). Required inputs for non-contention operations are summarized in Table 1. If a location is being written to by one port and the opposite port attempts to read that location, a port-to-port flowthrough delay must occur before the data is read on the output; otherwise the data read is not deterministic. Data will be valid on the port tDDD after the data is presented on the other port. Read Operation When reading the device, the user must assert both the OE and CE pins. Data will be available tACE after CE or tDOE after OE is asserted. If the user wishes to access a semaphore flag, then the SEM pin must be asserted instead of the CE pin, and OE must also be asserted. Interrupts The upper two memory locations may be used for message passing. The highest memory location (7FFF) is the mailbox for the right port and the second-highest memory location Page 5 of 22 [+] Feedback CY7C006A/CY7C007A CY7C016A/CY7C017A (7FFE) is the mailbox for the left port. When one port writes to the other port’s mailbox, an interrupt is generated to the owner. The interrupt is reset when the owner reads the contents of the mailbox. The message is user defined. Each port can read the other port’s mailbox without resetting the interrupt. The active state of the busy signal (to a port) prevents the port from setting the interrupt to the winning port. Also, an active busy to a port prevents that port from reading its own mailbox and, thus, resetting the interrupt to it. If an application does not require message passing, do not connect the interrupt pin to the processor’s interrupt request input pin. The operation of the interrupts and their interaction with Busy are summarized in Table 2. Busy The CY7C006A, CY7C007A, CY7C016A and CY7C017A provide on-chip arbitration to resolve simultaneous memory location access (contention). If both ports’ CEs are asserted and an address match occurs within tPS of each other, the busy logic will determine which port has access. If tPS is violated, one port will definitely gain permission to the location, but it is not predictable which port will get that permission. BUSY will be asserted tBLA after an address match or tBLC after CE is taken LOW. Master/Slave A M/S pin is provided in order to expand the word width by configuring the device as either a master or a slave. The BUSY output of the master is connected to the BUSY input of the slave. This will allow the device to interface to a master device with no external components. Writing to slave devices must be delayed until after the BUSY input has settled (tBLC or tBLA), otherwise, the slave chip may begin a write cycle during a contention situation. When tied HIGH, the M/S pin allows the device to be used as a master and, therefore, the BUSY line is an output. BUSY can then be used to send the arbitration outcome to a slave. Semaphore Operation The CY7C006A, CY7C007A, CY7C016A and CY7C017A provide eight semaphore latches, which are separate from the Document Number: 38-06045 Rev. *F dual-port memory locations. Semaphores are used to reserve resources that are shared between the two ports. The state of the semaphore indicates that a resource is in use. For example, if the left port wants to request a given resource, it sets a latch by writing a zero to a semaphore location. The left port then verifies its success in setting the latch by reading it. After writing to the semaphore, SEM or OE must be deasserted for tSOP before attempting to read the semaphore. The semaphore value will be available tSWRD + tDOE after the rising edge of the semaphore write. If the left port was successful (reads a zero), it assumes control of the shared resource, otherwise (reads a one) it assumes the right port has control and continues to poll the semaphore. When the right side has relinquished control of the semaphore (by writing a one), the left side will succeed in gaining control of the semaphore. If the left side no longer requires the semaphore, a one is written to cancel its request. Semaphores are accessed by asserting SEM LOW. The SEM pin functions as a chip select for the semaphore latches (CE must remain HIGH during SEM LOW). A0–2 represents the semaphore address. OE and R/W are used in the same manner as a normal memory access. When writing or reading a semaphore, the other address pins have no effect. When writing to the semaphore, only I/O0 is used. If a zero is written to the left port of an available semaphore, a one will appear at the same semaphore address on the right port. That semaphore can now only be modified by the side showing zero (the left port in this case). If the left port now relinquishes control by writing a one to the semaphore, the semaphore will be set to one for both sides. However, if the right port had requested the semaphore (written a zero) while the left port had control, the right port would immediately own the semaphore as soon as the left port released it. Table 3 shows sample semaphore operations. When reading a semaphore, all data lines output the semaphore value. The read value is latched in an output register to prevent the semaphore from changing state during a write from the other port. If both ports attempt to access the semaphore within tSPS of each other, the semaphore will definitely be obtained by one side or the other, but there is no guarantee which side will control the semaphore. Page 6 of 22 [+] Feedback CY7C006A/CY7C007A CY7C016A/CY7C017A DC Input Voltage[10]........................................–0.5V to +7.0V Maximum Ratings[8] Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage............................................ >2001V Storage Temperature ................................. –65C to +150C Latch-Up Current ..................................................... >200 mA Ambient Temperature with Power Applied ............................................ –55C to +125C Operating Range Supply Voltage to Ground Potential................–0.3V to +7.0V Range Ambient Temperature DC Voltage Applied to Outputs in High Z State ................................................–0.5V to +7.0V VCC Commercial 0C to +70C 5V 10% Electrical Characteristics Over the Operating Range Parameter CY7C006A CY7C007A CY7C016A CY7C017A Description –12[9] Unit –15 –20 Min Typ Max Min Typ Max Min Typ Max – – 2.4 – – 2.4 – – V VOH Output HIGH Voltage (VCC = Min, IOH = –4.0 mA) 2.4 VOL Output LOW Voltage (VCC = Min, IOH = +4.0 mA) – 0.4 – 0.4 – 0.4 V VIH Input HIGH Voltage 2.2 – 2.2 – 2.2 – V VIL Input LOW Voltage – 0.8 – 0.8 – 0.8 V IOZ Output Leakage Current –10 10 –10 10 –10 10 A ICC Operating Current (VCC = Max, IOUT = 0 mA) Outputs Disabled Commercial 325 – 190 280 – 275 mA 215 305 Standby Current (Both Ports TTL Level) CEL & CER VIH, f = fMAX Commercial 50 70 65 95 Standby Current (One Port TTL Level) CEL | CER VIH, f = fMAX Commercial 120 180 135 205 Standby Current (Both Ports CMOS Level) CEL & CER VCC 0.2 V, f=0 Commercial 0.05 0.5 0.05 0.5 110 160 125 175 ISB1 ISB2 ISB3 ISB4 – 195 Industrial – 55 Industrial – 125 Industrial 205 – 0.05 Industrial Standby Current Commercial (One Port CMOS Level) CEL Industrial | CER VIH, f = fMAX[10, 11] 75 0.5 – 115 185 – 180 – 45 mA 65 – 110 mA 160 – 0.05 – mA mA 140 – mA mA 0.5 100 mA mA mA Notes 8. The Voltage on any input or I/O pin cannot exceed the power pin during power-up. 9. See page 7 for Load Conditions. 10. Pulse width < 20 ns. 11. fMAX = 1/tRC = All inputs cycling at f = 1/tRC (except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level standby ISB3. Document Number: 38-06045 Rev. *F Page 7 of 22 [+] Feedback CY7C006A/CY7C007A CY7C016A/CY7C017A Capacitance Table[12] Parameter Description Test Conditions Max TA = 25 C, f = 1 MHz, VCC = 5.0 V CIN Input Capacitance COUT Output Capacitance Unit 10 pF 10 pF AC Test Loads and Waveforms 5V 5V R1 = 893 OUTPUT OUTPUT C = 30 pF RTH = 250 R1 = 893 OUTPUT C = 30 pF R2 = 347 C = 5 pF R2 = 347 VTH = 1.4 V (a) Normal Load (Load 1) (c) Three-State Delay (Load 2) (Used for tLZ, tHZ, tHZWE, & tLZWE including scope and jig) (b) Thévenin Equivalent (Load 1) AC Test Loads (Applicable to –12 only)[13] OUTPUT ALL INPUT PULSES Z0 = 50 R = 50 3.0 V C 10% GND 90% 10% 90% 3 ns 3 ns VTH = 1.4 V (a) Load 1 (-12 only) 1 . 00 0. 90 (ns) for all -12 access times 0. 80 0. 70 0. 60 0. 50 0. 40 0. 30 0. 20 0. 1 0 0. 00 10 15 20 25 30 35 Capacitance (pF) (b) Load Derating Curve Notes 12. Tested initially and after any design or process changes that may affect these parameters. 13. Test Conditions: C = 10 pF. Document Number: 38-06045 Rev. *F Page 8 of 22 [+] Feedback CY7C006A/CY7C007A CY7C016A/CY7C017A Switching Characteristics Over the Operating Range[14] Parameter CY7C006A CY7C007A CY7C016A CY7C017A Description [15] –12 Unit –15 –20 Min Max Min Max Min Max READ CYCLE tRC Read Cycle Time 12 – 15 – 20 – ns tAA Address to Data Valid – 12 – 15 – 20 ns tOHA Output Hold From Address Change 3 – 3 – 3 – ns tACE[16] CE LOW to Data Valid – 12 – 15 – 20 ns tDOE OE LOW to Data Valid – 8 – 10 – 12 ns OE LOW to Low Z 3 – 3 – 3 – ns OE HIGH to High Z – 10 – 10 – 12 ns CE LOW to Low Z 3 – 3 – 3 – ns CE HIGH to High Z – 10 – 10 – 12 ns CE LOW to Power-Up 0 – 0 – 0 – ns CE HIGH to Power-Down – 12 – 15 – 20 ns tWC Write Cycle Time 12 – 15 – 20 – ns tSCE[16] CE LOW to Write End 10 – 12 – 15 – ns tLZOE [17, 18, 19] tHZOE[17, 18, 19] tLZCE[17, 18, 19] tHZCE[17, 18, 19] tPU[19] tPD[19] WRITE CYCLE tAW Address Valid to Write End 10 – 12 – 15 – ns tHA Address Hold From Write End 0 – 0 – 0 – ns tSA[16] Address Set-Up to Write Start 0 – 0 – 0 – ns tPWE Write Pulse Width 10 – 12 – 15 – ns tSD Data Set-Up to Write End 10 – 10 – 15 – ns tHD[22] Data Hold From Write End 0 – 0 – 0 – ns tHZWE[18, 19] tLZWE[18, 19] tWDD[20] tDDD[20] R/W LOW to High Z – 10 – 10 – 12 ns R/W HIGH to Low Z 3 – 3 – 3 – ns Write Pulse to Data Delay – 25 – 30 – 45 ns Write Data Valid to Read Data Valid – 20 – 25 – 30 ns [21] BUSY TIMING tBLA BUSY LOW from Address Match – 12 – 15 – 20 ns tBHA BUSY HIGH from Address Mismatch – 12 – 15 – 20 ns Notes: 14. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified IOI/IOH and 30-pF load capacitance. 15. See page 7 for Load Conditions. 16. To access RAM, CE = L, SEM = H. To access semaphore, CE = H and SEM = L. Either condition must be valid for the entire tSCE time. 17. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE. 18. Test conditions used are Load 3. 19. This parameter is guaranteed but not tested. 20. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform. 21. Test conditions used are Load 2. 22. For 15 ns industrial parts tHD Min. is 0.5 ns. Document Number: 38-06045 Rev. *F Page 9 of 22 [+] Feedback CY7C006A/CY7C007A CY7C016A/CY7C017A Switching Characteristics Over the Operating Range[14] (continued) Parameter CY7C006A CY7C007A CY7C016A CY7C017A Description –12[15] Min tBLC BUSY LOW from CE LOW Max Unit –15 Min –20 Max 12 Min Max 15 12 15 20 ns 17 ns tBHC BUSY HIGH from CE HIGH tPS Port Set-Up for Priority 5 5 5 ns tWB R/W HIGH after BUSY (Slave) 0 0 0 ns tWH R/W HIGH after BUSY HIGH (Slave) 11 13 15 ns tBDD[23] BUSY HIGH to Data Valid 12 15 20 ns INTERRUPT TIMING[24] tINS INT Set Time 12 15 20 ns tINR INT Reset Time 12 15 20 ns SEMAPHORE TIMING tSOP SEM Flag Update Pulse (OE or SEM) 10 10 10 ns tSWRD SEM Flag Write to Read Time 5 5 5 ns tSPS SEM Flag Contention Window 5 5 5 ns tSAA SEM Address Access Time Data Retention Mode The CY7C006A, CY7C007A, CY7C016A, and CY7C017A are designed with battery backup in mind. Data retention voltage and supply current are guaranteed over temperature. The following rules ensure data retention: 1. Chip Enable (CE) must be held HIGH during data retention, within VCC to VCC – 0.2 V. 2. CE must be kept between VCC – 0.2 V and 70% of VCC during the power-up and power-down transitions. 3. The RAM can begin operation >tRC after VCC reaches the minimum operating voltage (4.5 V). 12 15 20 ns Timing Data Retention Mode VCC 4.5V VCC 2.0V 4.5V VCC to VCC – 0.2V CE Parameter ICCDR1 Test Conditions[25] @ VCCDR = 2 V tRC V IH Max Unit 1.5 mA Notes: 23. tBDD is a calculated parameter and is the greater of tWDD–tPWE (actual) or tDDD–tSD (actual). 24. Test conditions used are Load 2. 25. CE = VCC, Vin = GND to VCC, TA = 25 C. This parameter is guaranteed but not tested. Document Number: 38-06045 Rev. *F Page 10 of 22 [+] Feedback CY7C006A/CY7C007A CY7C016A/CY7C017A Switching Waveforms Read Cycle No. 1 (Either Port Address Access)[26, 27, 28] tRC ADDRESS tOHA DATA OUT tAA tOHA PREVIOUS DATA VALID DATA VALID Read Cycle No. 2 (Either Port CE/OE Access)[26, 29, 30] tACE CE tDOE OE tHZCE tHZOE tLZOE DATA VALID DATA OUT tLZCE tPU tPD ICC CURRENT ISB Read Cycle No. 3 (Either Port)[26, 28, 29, 30] tRC ADDRESS tOHA tAA tLZCE tABE CE tHZCE tACE tLZCE DATA OUT Notes 26. R/W is HIGH for read cycles. 27. Device is continuously selected CE = VIL. This waveform cannot be used for semaphore reads. 28. OE = VIL. 29. Address valid prior to or coincident with CE transition LOW. 30. To access RAM, CE = VIL, SEM = VIH. To access semaphore, CE = VIH, SEM = VIL. Document Number: 38-06045 Rev. *F Page 11 of 22 [+] Feedback CY7C006A/CY7C007A CY7C016A/CY7C017A Switching Waveforms (continued) Write Cycle No. 1: R/W Controlled Timing [31, 32, 33, 34] tWC ADDRESS tHZOE [36] OE CE tAW [35] tPWE[34] tSA tHA R/W tHZWE[36] DATA OUT tLZWE NOTE 37 NOTE 37 tSD tHD DATA IN Write Cycle No. 2: CE Controlled Timing [31, 32, 33, 38] tWC ADDRESS tAW CE [35] tSA tSCE tHA R/W tSD tHD DATA IN Notes 31. R/W or CE must be HIGH during all address transitions. 32. A write occurs during the overlap (tSCE or tPWE) of a LOW CE or SEM. 33. tHA is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at the end of write cycle. 34. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or (tHZWE + tSD) to allow the I/O drivers to turn off and data to be placed on the bus for the required tSD. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tPWE. 35. To access RAM, CE = VIL, SEM = VIH. 36. Transition is measured ±500 mV from steady state with a 5-pF load (including scope and jig). This parameter is sampled and not 100% tested. 37. During this period, the I/O pins are in the output state, and input signals must not be applied. 38. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state. Document Number: 38-06045 Rev. *F Page 12 of 22 [+] Feedback CY7C006A/CY7C007A CY7C016A/CY7C017A Switching Waveforms (continued) Semaphore Read After Write Timing, Either Side[39] tOHA tAA A 0–A 2 VALID ADRESS VALID ADRESS tAW tACE tHA SEM tSCE tSOP tSD I/O0 DATAIN VALID tSA tPWE DATAOUT VALID tHD R/W tSWRD tDOE tSOP OE WRITE CYCLE READ CYCLE Timing Diagram of Semaphore Contention[40, 41, 42] A0L –A2L MATCH R/WL SEM L tSPS A 0R –A 2R MATCH R/WR SEM R Notes 39. CE = HIGH for the duration of the above timing (both write and read cycle). 40. I/O0R = I/O0L = LOW (request semaphore); CER = CEL = HIGH. 41. Semaphores are reset (available to both ports) at cycle start. 42. If tSPS is violated, the semaphore will definitely be obtained by one side or the other, but which side will get the semaphore is unpredictable. Document Number: 38-06045 Rev. *F Page 13 of 22 [+] Feedback CY7C006A/CY7C007A CY7C016A/CY7C017A Switching Waveforms (continued) Timing Diagram of Read with BUSY (M/S=HIGH)[43] tWC ADDRESSR MATCH tPWE R/WR tSD DATA INR tHD VALID tPS ADDRESSL MATCH tBLA tBHA BUSYL tBDD tDDD DATA OUTL VALID tWDD Write Timing with Busy Input (M/S=LOW) tPWE R/W BUSY tWB tWH Note 43. CEL = CER = LOW. Document Number: 38-06045 Rev. *F Page 14 of 22 [+] Feedback CY7C006A/CY7C007A CY7C016A/CY7C017A Switching Waveforms (continued) Busy Timing Diagram No. 1 (CE Arbitration)[44] CELValid First: ADDRESS L,R ADDRESS MATCH CEL tPS CER tBLC tBHC BUSYR CER Valid First: ADDRESS L,R ADDRESS MATCH CER tPS CE L tBLC tBHC BUSY L Busy Timing Diagram No. 2 (Address Arbitration)[44] Left Address Valid First: tRC or tWC ADDRESS L ADDRESS MATCH ADDRESS MISMATCH tPS ADDRESSR tBLA tBHA BUSY R Right Address Valid First: tRC or tWC ADDRESSR ADDRESS MATCH ADDRESS MISMATCH tPS ADDRESSL tBLA tBHA BUSY L Note 44. If tPS is violated, the busy signal will be asserted on one side or the other, but there is no guarantee to which side BUSY will be asserted. Document Number: 38-06045 Rev. *F Page 15 of 22 [+] Feedback CY7C006A/CY7C007A CY7C016A/CY7C017A Switching Waveforms (continued) Interrupt Timing Diagrams Left Side Sets INTR: tWC ADDRESSL WRITE 7FFF tHA[45] CE L R/W L INT R tINS [46] Right Side Clears INTR: tRC READ 7FFF ADDRESSR CE R tINR [46] R/WR OE R INTR Right Side Sets INTL: tWC ADDRESSR WRITE 7FFE tHA[45] CE R R/W R INT L tINS[46] Left Side Clears INTL: tRC READ 7FFE ADDRESSR CE L tINR[46] R/W L OE L INT L Notes 45. tHA depends on which enable pin (CEL or R/WL) is deasserted first. 46. tINS or tINR depends on which enable pin (CEL or R/WL) is asserted last. Document Number: 38-06045 Rev. *F Page 16 of 22 [+] Feedback CY7C006A/CY7C007A CY7C016A/CY7C017A Table 1. Non-Contending Read/Write Inputs CE Outputs R/W OE SEM H X X H High Z Deselected: Power-Down H H L L Data Out Read Data in Semaphore Flag X X H X High Z I/O Lines Disabled X L Data In Write into Semaphore Flag H L H Data Out Read L L X H Data In Write L X X L H L I/O0–I/O8 Operation Not Allowed Table 2. Interrupt Operation Example (assumes BUSYL=BUSYR=HIGH) Left Port Function Right Port R/WL CEL OEL A0L–14L INTL R/WR CER OER A0R–14R INTR Set Right INTR Flag L L X 7FFF X X X X X L[48] Reset Right INTR Flag X X X X X X L L 7FFF H[47] Set Left INTL Flag X X X X L[47] L L X 7FFE X 7FFE H[48] X X X X X Reset Left INTL Flag X L L Table 3. Semaphore Operation Example Function I/O0–I/O8 Left I/O0–I/O8Right 1 1 No action Status Semaphore free Left port writes 0 to semaphore 0 1 Left Port has semaphore token Right port writes 0 to semaphore 0 1 No change. Right side has no write access to semaphore Left port writes 1 to semaphore 1 0 Right port obtains semaphore token Left port writes 0 to semaphore 1 0 No change. Left port has no write access to semaphore Right port writes 1 to semaphore 0 1 Left port obtains semaphore token Left port writes 1 to semaphore 1 1 Semaphore free Right port writes 0 to semaphore 1 0 Right port has semaphore token Right port writes 1 to semaphore 1 1 Semaphore free Left port writes 0 to semaphore 0 1 Left port has semaphore token Left port writes 1 to semaphore 1 1 Semaphore free Notes 47. If BUSYR = L, then no change. 48. If BUSYL= L, then no change. Document Number: 38-06045 Rev. *F Page 17 of 22 [+] Feedback CY7C006A/CY7C007A CY7C016A/CY7C017A Ordering Information 16K x 8 Asynchronous Dual-Port SRAM Speed (ns) 20 Ordering Code Package Name Package Type Operating Range CY7C006A-20AC A65 64-Pin Thin Quad Flat Pack Commercial CY7C006A-20AXC A65 64-Pin Pb-Free Thin Quad Flat Pack Commercial CY7C006A-20AXI A65 64-Pin Pb-Free Thin Quad Flat Pack Industrial CY7C006A-20JXC J81 68-Pin Pb-Free Plastic Leaded Chip Carrier Commercial Ordering Code Definitions CY 7C 0 06A - 20 X X X Temperature Range: X = C or I C = Commercial; I = Industrial X = Pb-free (RoHS Compliant) Package Type: X = A or J A = 64-pin TQFP J = 68-pin PLCC Speed Grade: 20 ns 06A = Depth: 16K 0 = Width: × 8 7C = Dual Port SRAM CY = Cypress Device Document Number: 38-06045 Rev. *F Page 18 of 22 [+] Feedback CY7C006A/CY7C007A CY7C016A/CY7C017A Package Diagrams 64-Lead Thin Plastic Quad Flat Pack (14 x 14 x 1.4 mm) A65 64-Lead Pb-Free Thin Plastic Quad Flat Pack (14 x 14 x 1.4 mm) A65 51-85046 *D Document Number: 38-06045 Rev. *F Page 19 of 22 [+] Feedback CY7C006A/CY7C007A CY7C016A/CY7C017A Package Diagrams (continued) 80-Pin Thin Plastic Quad Flat Pack A80 80-Pin Pb-Free Thin Plastic Quad Flat Pack A80 51-85065 *C 68-Lead Plastic Leaded Chip Carrier J81 68-Lead Pb-Free Plastic Leaded Chip Carrier J81 51-85005 *B Document Number: 38-06045 Rev. *F Page 20 of 22 [+] Feedback CY7C006A/CY7C007A CY7C016A/CY7C017A Document History Page Document Title: CY7C006A/CY7C007A/CY7C016A/CY7C017A 32K/16K x 8, 16K x 9 Dual-Port Static RAM Document Number: 38-06045 Orig. of Change REV. ECN NO. Issue Date ** 110197 09/29/01 SZV Change from Spec number: 38-00831 to 38-06045 *A 122295 12/27/02 RBI Power up requirements added to Maximum Ratings Information *B 237620 See ECN YDT Removed cross information from features section *C 345376 See ECN AEQ Removed I-Temp versions for both packages, since they are not valid part numbers. *D 387333 See ECN PCX Included Pb-Free Logo Included package: CY7C006A-20AI Included Pb-Free packages: CY7C006A-15AXC, CY7C006A-20AXC, CY7C006A-20AXI, CY7C006A-20JXC, CY7C007A-20JXC, CY7C016A-15AXC *E 2896210 03/22/2010 RAME Updated Ordering Information Updated Package Diagram *F 3110296 12/14/2010 EYB Updated Ordering Information. Added Ordering Code Definitions. Minor edits and updated in new template. Document Number: 38-06045 Rev. *F Description of Change Page 21 of 22 [+] Feedback CY7C006A/CY7C007A CY7C016A/CY7C017A Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control PSoC Solutions cypress.com/go/automotive cypress.com/go/clocks psoc.cypress.com/solutions cypress.com/go/interface PSoC 1 | PSoC 3 | PSoC 5 cypress.com/go/powerpsoc cypress.com/go/plc Memory Optical & Image Sensing cypress.com/go/memory cypress.com/go/image PSoC Touch Sensing cypress.com/go/psoc cypress.com/go/touch USB Controllers Wireless/RF cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2001-2010. The information contained herein is subject to change without notice. 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Document Number: 38-06045 Rev. *F Revised December 17, 2010 Page 22 of 22 All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback