ON NBSG53AMNG 2.5 v/3.3 v sige selectable differential clock and data d flip-flop/clock divider Datasheet

NBSG53A
2.5 V/3.3 V SiGe Selectable
Differential Clock and Data
D Flip-Flop/Clock Divider
with Reset and OLS*
The NBSG53A is a multi-function differential D flip-flop (DFF) or
fixed divide by two (DIV/2) clock generator. This is a part of the
GigaCommt family of high performance Silicon Germanium
products. A strappable control pin is provided to select between the
two functions. The device is housed in a low profile 4x4 mm 16-pin
Flip-Chip BGA (FCBGA) or a 3x3 mm 16 pin QFN package.
The NBSG53A is a device with data, clock, OLS*, reset, and select
inputs. Differential inputs incorporate internal 50 W termination
resistors and accept NECL (Negative ECL), PECL (Positive ECL),
LVCMOS/LVTTL, CML, or LVDS. The OLS* input is used to
program the peak-to-peak output amplitude between 0 and 800 mV
in five discrete steps. The RESET and SELECT inputs are
single-ended and can be driven with either LVECL or
LVCMOS/LVTTL input levels.
Data is transferred to the outputs on the positive edge of the clock.
The differential clock inputs of the NBSG53A allow the device to also
be used as a negative edge triggered device.
Features
• Maximum Input Clock Frequency (DFF) > 8 GHz Typical
(See Figures 3, 5, 7, 9, and 10)
• Maximum Input Clock Frequency (DIV/2) > 10 GHz Typical
•
•
•
•
•
•
•
(See Figures 4, 6, 8, 9, and 10)
210 ps Typical Propagation Delay (OLS = FLOAT)
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QFN−16
MN SUFFIX
CASE 485G
MARKING DIAGRAM*
ÇÇÇ
ÇÇÇ
16
1
SG
53A
ALYWG
G
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
45 ps Typical Rise and Fall Times (OLS = FLOAT)
DIV/2 Mode (Active with Select Low)
ORDERING INFORMATION
DFF Mode (Active with Select High)
Selectable Swing PECL Output with Operating Range: VCC = 2.375 V
to 3.465 V with VEE = 0 V
Selectable Swing NECL Output with NECL Inputs with
Operating Range: VCC = 0 V with VEE = −2.375 V to −3.465 V
Selectable Output Level (0 V, 200 mV, 400 mV, 600 mV, or 800 mV
Peak-to-Peak Output)
50 W Internal Input Termination Resistors on all Differential Inputs
See detailed ordering and shipping information in the package
dimensions section on page 16 of this data sheet.
•
• These are Pb-Free Devices
*Output Level Select
© Semiconductor Components Industries, LLC, 2014
June, 2014 − Rev. 15
1
Publication Order Number:
NBSG53A/D
NBSG53A
VTCLK
1
CLK
2
VCC
R
SEL OLS
16
15
14
Exposed Pad
(EP)
13
12
VEE
11
Q
NBSG53A
CLK
3
10
Q
VTCLK
4
9
VCC
5
6
7
8
VTD
D
D
VTD
Figure 1. QFN−16 Pinout (Top View)
Table 1. PIN DESCRIPTION
Pin
Name
I/O
Description
1
VTCLK
−
2
CLK
ECL, CML,
LVCMOS, LVDS,
LVTTL Input
Inverted Differential Input.
3
CLK
ECL, CML,
LVCMOS, LVDS,
LVTTL Input
Noninverted Differential Input.
4
VTCLK
−
Internal 50 W Termination Pin. See Table 4.
5
VTD
−
Internal 50 W termination pin. See Table 4.
6
D
ECL, CML,
LVCMOS, LVDS,
LVTTL Input
Inverted Differential Input.
7
D
ECL, CML,
LVCMOS, LVDS,
LVTTL Input
Noninverted Differential Input.
8
VTD
−
Internal 50 W Termination Pin. See Table 4.
9,16
VCC
−
Positive Supply Voltage
10
Q
RSECL Output
NonInverted Differential Output. Typically Terminated with 50 W Resistor to
VTT = VCC − 2 V.
11
Q
RSECL Output
Inverted Differential Output. Typically Terminated with 50 W Resistor to
VTT = VCC − 2 V.
Internal 50 W Termination Pin. See Table 4.
12
VEE
−
13
OLS*
Input
Negative Supply Voltage
14
SEL
LVECL, LVCMOS,
LVTTL Input
Select Logic Input. Internal 75 kW to VEE.
15
R
LVECL, LVCMOS,
LVTTL Input
Reset D Flip-Flop. Internal 75 kW to VEE.
−
EP
Input Pin for the Output Level Select (OLS). See Table 2.
The Exposed Pad (EP) on the QFN−16 package bottom is thermally connected to the
die for improved heat transfer out of package. The exposed pad must be attached to
a heat-sinking conduit. The pad is not electrically connected to the die but may be
electrically and thermally connected to VEE on the PC board.
1. All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation. The thermally exposed pad (EP) on
package bottom (see case drawing) must be attached to a heat-sinking conduit.
2. In the differential configuration when the input termination pins (VTD, VTD, VTCLK, VTCLK) are connected to a common termination voltage,
and if no signal is applied then the device will be susceptible to self-oscillation.
3. When an output level of 400 mV is desired and VCC − VEE > 3.0 V, 2 kW resistor should be connected from OLS pin to VEE.
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NBSG53A
VCC
OLS
VTD
50 W
2
2
D
D
Flip−Flop
(DFF)
R
D
50 W
2
VTD
Q
1
Q
2
0
Q
2
2
D
VTCLK
50 W
Q
Flip−Flop
(DIV/2)
2
CLK
R
CLK
50 W
VTCLK
R
SEL
75 kW
75 kW
VEE
Figure 2. Simplified Logic Diagram
Table 2. OUTPUT LEVEL SELECT (OLS)
OLS
Q/Q VPP
Table 3. TRUTH TABLE
OLS Sensitivity
R
SEL
D
CLK
Q
Function
VCC
800 mV
OLS − 75 mV
H
x
x
x
L
Reset
VCC − 0.4 V
200 mV
OLS $ 150 mV
L
H
L
Z
L
DFF
VCC − 0.8 V
600 mV
OLS $ 100 mV
L
H
H
Z
H
DFF
VCC − 1.2 V
0
OLS $ 75 mV
L
L
x
Z
Q
DIV/2
VEE (Note 4)
400 mV
OLS + 100 mV
Float
600 mV
N/A
Z = LOW to HIGH Transition
4. When an output level of 400 mV is desired and
VCC − VEE > 3.0 V, 2.0 kW resistor should be connected from
OLS to VEE.
Table 4. INTERFACING OPTIONS
INTERFACING OPTIONS
CONNECTIONS
CML
Connect VTCLK, VTD and VTCLK, VTD to VCC
LVDS
Connect VTCLK, VTD and VTCLK, VTD Together
AC−COUPLED
Bias VTCLK, VTD and VTCLK, VTD Inputs within Common Mode Range (VIHCMR)
RSECL, PECL, NECL
Standard ECL Termination Techniques
LVTTL, LVCMOS
An External Voltage (Vth) should be Applied to the Unused Complementary Differential Input. Nominal Vth is
1.5 V for LVTTL and VCC/2 for LVCMOS Inputs. This Voltage must be within the Vth Specification.
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NBSG53A
Table 5. ATTRIBUTES
Characteristics
Value
Positive Operating Voltage Range for VCC (VEE = 0 V)
2.375 V to 3.465 V
Negative Operating Voltage Range for VEE (VCC = 0 V)
−2.375 V to −3.465 V
Internal Input Pulldown Resistor (R, SEL)
ESD Protection
75 kW
Human Body Model
Machine Model
Charged Device Model
> 1.5 kV
> 50 V
> 4 kV
Moisture Sensitivity (Note 5)
Level 1
Flammability Rating
UL 94 V−0 @ 0.125 in
Oxygen Index
28 to 34
Transistor Count
482
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
5. For additional information, refer to Application Note AND8003/D.
Table 6. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
Condition 2
Rating
Units
VCC
Positive Power Supply
VEE = 0 V
3.6
V
VEE
Negative Power Supply
VCC = 0 V
−3.6
V
Positive Input
Negative Input
VEE = 0 V
VCC = 0 V
3.6
−3.6
V
VCC − VEE ≥ 2.8 V
VCC − VEE < 2.8 V
2.8
|VCC − VEE|
V
Static
Surge
45
80
mA
Continuous
Surge
25
50
mA
VI
VINPP
IIN
IOUT
Differential Input Voltage
|D − D|
Input Current Through RT (50 W Resistor)
Output Current
VI ≤ VCC
VI ≥ VEE
TA
Operating Temperature Range
−40 to +85
°C
Tstg
Storage Temperature Range
−65 to +150
°C
qJA
Thermal Resistance (Junction-to-Ambient)
(Note 6)
0 lfpm
500 lfpm
41.6
35.2
°C/W
qJC
Thermal Resistance (Junction-to-Case)
2S2P (Note 6)
4.0
°C/W
Tsol
Wave Solder
< 3 sec @ 260°C
265
°C
Pb-Free
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
6. JEDEC standard multilayer board − 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
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NBSG53A
Table 7. DC CHARACTERISTICS, INPUT WITH PECL OUTPUT (VCC = 2.5 V; VEE = 0 V) (Note 7)
−40°C
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
33
45
57
33
45
57
33
45
57
mA
1460
1510
1560
1490
1540
1590
1515
1565
1615
mV
(OLS = VCC)
(OLS = VCC − 0.4 V)
(OLS = VCC − 0.8 V, OLS = FLOAT)
(OLS = VCC − 1.2 V)
(OLS = VEE)
555
1235
775
1455
1005
705
1295
895
1505
1095
855
1385
1015
1585
1215
595
1270
810
1490
1040
745
1330
930
1540
1130
895
1420
1050
1620
1250
625
1295
840
1510
1065
775
1355
960
1560
1155
925
1445
1080
1640
1275
Output Voltage Amplitude
(OLS = VCC)
(OLS = VCC − 0.4 V)
(OLS = VCC − 0.8 V, OLS = FLOAT)
(OLS = VCC − 1.2 V)
(OLS = VEE)
670
125
510
0
325
800
215
615
5
415
660
120
505
0
320
795
210
610
0
410
655
120
500
0
320
790
210
605
0
410
Symbol
Characteristic
POWER SUPPLY CURRENT
IEE
Negative Power Supply Current
PECL OUTPUTS (Note 8)
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
VOUTPP
mV
mV
DIFFERENTIAL CLOCK INPUTS DRIVEN SINGLE-ENDED (Figures 13 & 15) (Note 9)
VIH
Input HIGH
Voltage
CLK, invCLK, D, D
R, SEL
1200
1290
VCC
VCC
1200
1355
VCC
VCC
1200
1415
VCC
VCC
mV
VIL
Input LOW
Voltage
CLK, invCLK, D, D
0
VIH −
150
890
0
VIH −
150
955
0
VIH −
150
1015
mV
R, SEL
Vth
VISE
0
0
0
Input Threshold Voltage Range
(Note 10)
1125
VCC –
75
1125
VCC –
75
1125
VCC –
75
mV
Single-Ended Input Voltage
(VIH – VIL)
150
2600
150
2600
150
260
mV
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 14 & 16) (Note 11)
VIHD
Differential Input HIGH Voltage
1200
VCC
1200
VCC
1200
VCC
mV
VILD
Differential Input LOW Voltage
0
VIHD −
75
0
VIHD −
75
0
VIHD −
75
mV
VID
Differential Input Voltage
(VIHD – VILD)
75
2600
75
2600
75
2600
mV
1200
2500
1200
2500
1200
2500
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Note 12) (Figure 17)
IIH
Input HIGH Current (@VIH) R, SEL
CLK, inv_CLK, D, inv_D
35
5
100
50
35
5
100
50
35
5
100
50
mA
IIL
Input LOW Current (@VIL)
R, SEL
CLK, inv_CLK, D, inv_D
20
5
100
50
20
5
100
50
20
5
100
50
mA
50
55
50
55
50
55
W
TERMINATION RESISTORS
RTIN
Internal Input Termination Resistor
45
45
45
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
7. Input and output parameters vary 1:1 with VCC.
8. All outputs loaded with 50 W to VCC − 2.0 V.
9. Vth, VIH, VIL, and VISE parameters must be complied with simultaneously.
10. Vth is applied to the complementary input when operating in single-ended mode. Vth = (VIH − VIL) / 2.
11. VIHD, VILD, VID and VIHCMR parameters must be complied with simultaneously.
12. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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NBSG53A
Table 8. DC CHARACTERISTICS, INPUT WITH PECL OUTPUT (VCC = 3.3 V; VEE = 0 V) (Note 13)
−40°C
Symbol
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
35
47
59
35
47
59
35
47
59
mA
2260
2310
2360
2290
2340
2390
2315
2365
2415
mV
(OLS = VCC)
(OLS = VCC − 0.4 V)
(OLS = VCC − 0.8 V, OLS = FLOAT)
(OLS = VCC − 1.2 V)
**(OLS = VEE)
1320
2030
1550
2260
1785
1470
2090
1670
2310
1875
1620
2180
1790
2390
1995
1360
2065
1585
2290
1820
1510
2125
1705
2340
2030
1660
2215
1825
2420
2030
1390
2090
1615
2315
1850
1540
2150
1735
2365
1940
1690
2240
1855
2445
2060
Output Voltage Amplitude
(OLS = VCC)
(OLS = VCC − 0.4 V)
(OLS = VCC − 0.8 V, OLS = FLOAT)
(OLS = VCC − 1.2 V)
**(OLS = VEE)
705
130
535
0
345
815
220
640
0
435
695
125
530
0
340
805
215
635
0
430
590
125
525
0
335
800
215
630
0
425
Characteristic
POWER SUPPLY CURRENT
IEE
Negative Power Supply Current
PECL OUTPUTS (Note 14)
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
VOUTPP
mV
mV
DIFFERENTIAL CLOCK INPUTS DRIVEN SINGLE-ENDED (Figures 13 & 15) (Note 15)
VIH
Input HIGH
CLK, invCLK, D, D
Voltage (Single-Ended)
R, SEL
1200
VCC
1200
VCC
1200
VCC
2090
VCC
2155
VCC
2215
VCC
VIL
Input LOW
CLK, invCLK, D, D
Voltage (Single-Ended)
R, SEL
0
VIH −
150
1690
0
VIH −
150
1755
0
VIH −
150
1815
mV
Vth
Input Threshold Voltage Range
(Note 16)
1125
VCC –
75
1125
VCC –
75
1125
VCC –
75
mV
Single-Ended Input Voltage
(VIH – VIL)
150
2600
150
2600
150
260
mV
VISE
0
0
0
mV
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 14 & 16) (Note 17)
VIHD
Differential Input HIGH Voltage
1200
VCC
1200
VCC
1200
VCC
mV
VILD
Differential Input LOW Voltage
0
VIHD −
75
0
VIHD −
75
0
VIHD −
75
mV
VID
Differential Input Voltage
(VIHD – VILD)
75
2600
75
2600
75
2600
mV
1200
3300
1200
3300
1200
3300
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Note 18) (Figure 17)
IIH
Input HIGH Current (@VIH) R, SEL
CLK, inv_CLK, D, inv_D
35
5
100
50
35
5
100
50
35
5
100
50
mA
IIL
Input LOW Current (@VIL)
R, SEL
CLK, inv_CLK, D, inv_D
20
5
100
50
20
5
100
50
20
5
100
50
mA
50
55
50
55
50
55
W
TERMINATION RESISTORS
RTIN
Internal Input Termination Resistor
45
45
45
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
**When an output level of 400 mV is desired and VCC − VEE > 3.0 V, a 2 kW resistor should be connected from OLS to VEE.
13. Input and output parameters vary 1:1 with VCC.
14. All outputs loaded with 50 W to VCC − 2.0 V.
15. Vth, VIH, VIL, and VISE parameters must be complied with simultaneously.
16. Vth is applied to the complementary input when operating in single-ended mode. Vth = (VIH − VIL) / 2.
17. VIHD, VILD, VID and VIHCMR parameters must be complied with simultaneously.
18. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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NBSG53A
Table 9. DC CHARACTERISTICS, NECL INPUT WITH NECL OUTPUT
(VCC = 0 V; VEE = −3.465 V to −2.375 V) (Note 19)
−40°C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
35
47
59
35
47
59
35
47
59
mA
−1040
−990
−940
−1010
−960
−910
−985
−935
−885
mV
POWER SUPPLY CURRENT
IEE
Negative Power Supply Current
NECL OUTPUTS (Note 20)
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
−3.465 V ≤ VEE ≤ −3.0 V
(OLS = VCC)
(OLS = VCC − 0.4 V)
(OLS = VCC − 0.8 V, OLS = FLOAT)
(OLS = VCC − 1.2 V)
**(OLS = VEE)
−3.0 V < VEE ≤ −2.375 V
(OLS = VCC)
(OLS = VCC − 0.4 V)
(OLS = VCC − 0.8 V, OLS = FLOAT)
(OLS = VCC − 1.2 V)
(OLS = VEE)
VOUTPP
mV
−1980
−1270
−1750
−1040
−1515
−1830
−1210
−1630
−990
−1425
−1680
−1120
−1510
−910
−1305
−1940
−1235
−1715
−1010
−1480
−1790
−1175
−1595
−960
−1390
−1640
−1085
−1475
−880
−1270
−1910
−1210
−1685
−985
−1450
−1760
−1150
−1565
−935
−1360
−1610
−1060
−1445
−855
−1240
−1945
−1265
−1725
−1045
−1495
−1795
−1205
−1605
−995
−1405
−1645
−1115
−1485
−915
−1285
−1905
−1230
−1690
−1010
−1460
−1755
−1170
−1570
−960
−1370
−1605
−1080
−1450
−880
−1250
−1875
−1205
−1660
−900
−1435
−1725
−1145
−1540
−940
−1345
−1575
−1055
−1420
−860
−1225
Output Voltage Amplitude
−3.465 V ≤ VEE ≤ −3.0 V
(OLS = VCC)
(OLS = VCC − 0.4 V)
(OLS = VCC − 0.8 V, OLS = FLOAT)
(OLS = VCC − 1.2 V)
**(OLS = VEE)
−3.0 V < VEE ≤ −2.375 V
(OLS = VCC)
(OLS = VCC − 0.4 V)
(OLS = VCC − 0.8 V, OLS = FLOAT)
(OLS = VCC − 1.2 V)
(OLS = VEE)
mV
705
130
535
0
345
815
220
640
0
435
695
125
530
0
340
805
215
635
0
430
690
125
525
0
335
800
215
630
0
425
670
125
510
0
325
800
215
615
5
415
660
120
505
0
320
795
210
610
0
410
655
120
500
0
320
790
210
605
5
410
DIFFERENTIAL CLOCK INPUTS DRIVEN SINGLE-ENDED (Figures 13 & 15) (Note 21)
Input HIGH
CLK, invCLK, D, D
Voltage (Single-Ended)
R, SEL
VEE +
1200
−1210
VCC
VIL
Input LOW
CLK, invCLK, D, D
Voltage (Single-Ended)
R, SEL
VEE
Vth
Input Threshold Voltage (Note 22)
VIH
VISE
Single-Ended Input Voltage
(VIH – VIL)
VEE +
1200
−1145
VCC
VEE
VEE
VIH −
150
−1690
VEE +
1125
VCC –
75
150
2600
VCC
VEE +
1200
−1085
VCC
VEE
VEE
VIH −
150
−1485
mV
VEE
VIH −
150
−1545
VEE +
1125
VCC –
75
VEE +
1125
VCC –
75
mV
150
2600
150
260
mV
VCC
mV
VCC
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 14 & 16) (Note 23)
VIHD
Differential Input HIGH Voltage
VEE +
1200
VCC
VEE +
1200
VCC
VEE +
1200
VCC
mV
VILD
Differential Input LOW Voltage
VEE
VIHD −
75
VEE
VIHD −
75
VEE
VIHD −
75
mV
VID
Differential Input Voltage
(VIHD – VILD)
75
2600
75
2600
75
2600
mV
VEE +
1200
0.0
VEE +
1200
0.0
VEE +
1200
0.0
mV
100
50
mA
VIHCMR
IIH
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 24) (Figure 17)
Input HIGH Current (@VIH)
R, SEL
CLK, inv_CLK, D, inv_D
35
5
100
50
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35
5
100
50
35
5
NBSG53A
Table 9. DC CHARACTERISTICS, NECL INPUT WITH NECL OUTPUT (continued)
(VCC = 0 V; VEE = −3.465 V to −2.375 V) (Note 19)
−40°C
Symbol
Characteristic
Min
25°C
Typ
Max
Min
85°C
Typ
Max
Min
Typ
Max
Unit
mA
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 14 & 16) (Note 23)
IIL
Input LOW Current (@VIL)
R, SEL
CLK, inv_CLK, D, inv_D
IOLS
OLS Input Current (see Figure 11)
(OLS = VCC)
(OLS = VCC − 0.4 V)
(OLS = VCC − 0.8 V, OLS = FLOAT)
(OLS = VCC − 1.2 V)
−3.465 V ≤ VEE ≤ −3.0 V
*(OLS = VEE)
−3.0 V < VEE ≤ −2.375 V
(OLS = VEE)
20
5
100
50
20
5
100
50
20
5
100
50
900
300
100
−300
300
100
5
−100
900
300
100
−300
300
100
5
−100
900
300
100
−300
300
100
5
−100
−1500
−600
−1500
−600
−1500
−600
−1000
−400
−1000
−400
−1000
−400
45
50
45
50
45
50
mA
TERMINATION RESISTORS
RTIN
Internal Input Termination Resistor
55
55
55
W
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
*Typicals used for testing purposes.
**When an output level of 400 mV is desired and VCC − VEE > 3.0 V, a 2 kW resistor should be connected from OLS to VEE.
19. Input and output parameters vary 1:1 with VCC.
20. All outputs loaded with 50 W to VCC − 2.0 V.
21. Vth, VIH, VIL, and VISE parameters must be complied with simultaneously.
22. Vth is applied to the complementary input when operating in single-ended mode. Vth = (VIH − VIL) / 2.
23. VIHD, VILD, VID and VIHCMR parameters must be complied with simultaneously.
24. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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NBSG53A
Table 10. AC CHARACTERISTICS
(VCC = 0 V; VEE = −3.465 V to −2.375 V or VCC = 2.375 V to 3.465 V; VEE = 0 V)
−40°C
fmax
Min
Characteristic
Symbol
Maximum Input Clock Frequency
(See Figures 3, 5, 7, 9, and 10)
(See Figures 4, 6, 8, 9, and 10)
(Note 25)
Typ
DIV/2
10
10
10
RMS Random Clock Jitter
Max
Unit
ps
150
100
215
195
215
190
280
270
285
280
375
345
5
0.5
150
100
215
195
215
190
280
270
285
280
375
345
20
5
1
0.5
150
100
215
195
215
190
280
270
285
280
375
345
20
5
20
1
0.5
1
ps
ps
fin v 8 GHz
(See Figures 3 and 5) (Note 25)
Peak−to−Peak Data Dependent Jitter
fin = 8 Gb/s
VINPP
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 27)
tr
tf
Output Rise/Fall Times (20% − 80%)
@ 1 GHz
Q, Q
(OLS = VCC)
(OLS = VCC − 0.4 V)
(OLS = VCC − 0.8 V, OLS = FLOAT)
**(OLS = VEE)
Reset Recovery
Min
GHz
tJITTER
Hold Time
Max
8
Duty Cycle Skew (Notes 26 and 28) DFF
th
Typ
8
tSKEW
trr
Min
8
Propagation Delay to Output Differential
(Note 29)
CLK→Q, Q
SEL→Q, Q
R→Q, Q DIN/2
DFF
Setup Time
Max
85°C
DFF
tPLH,
tPHL
ts
Typ
25°C
TBD
75
TBD
2600
75
TBD
2600
75
2600
mV
ps
28
15
25
20
40
40
35
35
D→CLK
30
D→CLK
DFF, DIV/2
65
65
65
65
28
15
25
20
40
40
35
35
14
30
25
12
40
9
65
65
65
65
28
15
25
20
40
40
35
35
65
65
65
65
10
30
13
ps
25
7
25
0
ps
40
12
40
10
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
25. Measured using a 500 mV source, 50% duty cycle clock source. Repetitive 1010 input data pattern. All outputs loaded with 50 W to
VCC − 2.0 V. Input edge rates is 40 ps (20% − 80%).
26. See Figure 18. tSKEW = |tPLH − tPHL| for a nominal 50% differential clock input waveform.
27. VINPP (MAX) cannot exceed VCC − VEE (Applicable only when VCC − VEE < 2600 mV).
28. See Figure 9. Duty Cycle % vs. Frequency.
29. For all OLS Configuration.
**When an output level of 400 mV is desired and VCC − VEE > 3.0 V, a 2 kW resistor should be connected from OLS to VEE.
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NBSG53A
900
9
OLS = VCC
700
8
7
OLS = VCC − 0.8 V, OLS = FLOAT
600
500
6
*OLS = VEE
5
400
300
4
OLS = VCC − 0.4 V
3
200
JITTEROUT ps (RMS)
OUTPUT VOLTAGE AMPLITUDE
800
2
100
1
RMS JITTER
0
0
1
2
3
4
5
6
7
8
9
10
11
0
12
INPUT FREQUENCY (GHz)
Figure 3. Output Voltage Amplitude (VOUTPP) / RMS Jitter vs.
Input Frequency (fin) for DFF Mode (VCC − VEE = 3.3 V @ 255C; Repetitive 1010 Input Data Pattern)
900
OUTPUT VOLTAGE AMPLITUDE
OLS = VCC
800
700
OLS = VCC − 0.8 V, OLS = FLOAT
600
500
*OLS = VEE
400
300
OLS = VCC − 0.4 V
200
100
0
0
1
2
3
4
5
6
7
8
9
10
11
12
INPUT FREQUENCY (GHz)
Figure 4. Output Voltage Amplitude (VOUTPP) / RMS Jitter vs.
Input Frequency (fin) for DIV/2 Mode (VCC − VEE = 3.3 V @ 255C)
*When an output level of 400 mV is desired and VCC − VEE > 3.0 V, a 2 kW resistor should be connected from OLS to VEE.
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NBSG53A
900
700
8
7
OLS = VCC − 0.8 V, OLS = FLOAT
600
500
6
5
*OLS = VEE
400
300
4
OLS = VCC − 0.4 V
3
200
JITTEROUT ps (RMS)
OUTPUT VOLTAGE AMPLITUDE
800
9
OLS = VCC
2
100
1
RMS JITTER
0
0
1
2
3
4
5
6
7
8
9
10
11
0
12
INPUT FREQUENCY (GHz)
Figure 5. Output Voltage Amplitude (VOUTPP) / RMS Jitter vs.
Input Frequency (fin) for DFF Mode (VCC − VEE = 2.5 V @ 255C; Repetitive 1010 Input Data Pattern)
900
OUTPUT VOLTAGE AMPLITUDE
800
700
OLS = VCC
*OLS = VCC − 0.8 V, OLS = FLOAT
600
500
OLS = VEE
400
300
OLS = VCC − 0.4 V
200
100
0
0
1
2
3
4
5
6
7
8
9
10
11
12
INPUT FREQUENCY (GHz)
Figure 6. Output Voltage Amplitude (VOUTPP) / RMS Jitter vs.
Input Frequency (fin) for DIV/2 Mode (VCC − VEE = 2.5 V @ 255C)
*When an output level of 400 mV is desired and VCC − VEE > 3.0 V, a 2 kW resistor should be connected from OLS to VEE.
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11
NBSG53A
1200
VOH (Q)
1100
1000
VOH/VOL (mV)
900
VOH (Q)
800
700
600
VOL (Q)
500
400
300
VOL (Q)
200
100
0
0
1
2
3
4
5
6
7
8
9
10
11
12
INPUT FREQUENCY (GHz)
Figure 7. VOH/VOL (Q/Q) vs. Input Frequency (fin) for DFF Mode
(VCC − VEE = 3.3 V @ 255C and OLS = VCC − 0.8 V, OLS = FLOAT)
1200
VOH (Q)
1100
1000
VOH/VOL (mV)
900
VOH (Q)
800
700
600
VOL (Q)
500
400
300
VOL (Q)
200
100
0
0
1
2
3
4
5
6
7
8
9
10
11
12
INPUT FREQUENCY (GHz)
Figure 8. VOH/VOL (Q/Q) vs. Input Frequency (fin) for DIV/2 Mode
(VCC − VEE = 3.3 V @ 255C and OLS = VCC − 0.8 V, OLS = FLOAT)
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NBSG53A
100
90
DUTY CYCLE (%)
80
70
DIV/2 Mode
60
50
DFF Mode
40
30
20
10
0
0
1
2
3
4
5
6
7
8
9
10
11
12
11
12
INPUT FREQUENCY (GHz)
Figure 9. Duty Cycle % vs. Input Frequency (fin)
(VCC − VEE = 3.3 V @ 255C)
100
90
DUTY CYCLE (%)
80
70
DIV/2 Mode
60
50
DFF Mode
40
30
20
10
0
0
1
2
3
4
5
6
7
8
9
10
INPUT FREQUENCY (GHz)
Figure 10. Duty Cycle % vs. Input Frequency (fin)
(VCC − VEE = 2.5 V @ 705C)
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NBSG53A
300
200
100
IOLS (mA)
0
−100
−200
−300
−400
−500
−600
−700
VCC
VCC − 400
VCC − 800
VCC − 1200
VEE
VOLS (mV)
Figure 11. Typical OLS Input Current vs. OLS Input Voltage
(VCC − VEE = 3.3 V @ 255C)
1000
VCC − 75
800
Voutpp (mV)
VCC − 700
VCC − 900
600
VEE + 100
400
VCC − 250
VCC − 550
200
VCC − 1125
VCC − 1275
0
VCC
VCC − 400
VCC − 800
VCC − 1200
OLS (mV)
Figure 12. OLS Operating Area
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VEE
NBSG53A
IN
VIH
Vth
IN
VIL
IN
IN
Vth
Figure 13. Differential Input Driven
Single-Ended
VCC
Vthmax
Figure 14. Differential Inputs
Driven Differentially
VIHmax
VILmax
Vth
IN
Vthmin
VEE
VIH
Vth
VIL
IN
IN
VID = |VIHD(IN) − VILD(IN)|
VIHD
VILD
VIHmin
VILmin
Figure 15. Vth Diagram
Figure 16. Differential Inputs Driven
Differentially
VCC
VIHDmax
VIHCMRmax
VILDmax
VIHCMR
VIHDtyp
VID = VIHD − VILD
IN
IN
VILDtyp
VIHDmin
VIHCMRmin
VILDmin
VEE
Figure 17. VIHCMR Diagram
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15
NBSG53A
CLK
VINPP = VIH(CLK) − VIL(CLK)
CLK
Q
VOUTPP = VOH(Q) − VOL(Q)
Q
tPHL
tPLH
Figure 18. AC Reference Measurement
Q
Zo = 50 W
D
Receiver
Device
Driver
Device
Q
Zo = 50 W
D
50 W
50 W
VTT
VTT = VCC − 2.0 V
Figure 19. Typical Termination for Output Driver and Device Evaluation
(Refer to Application Note AND8020/D − Termination of ECL Logic Devices)
ORDERING INFORMATION
Package Type
Shipping†
NBSG53AMNG
QFN-16, 3x3 mm
(Pb-Free / Halide-Free)
123 Units / Tube
NBSG53AMNR2G
QFN-16, 3x3 mm
(Pb-Free / Halide-Free)
3000 / Tape & Reel
NBSG53AMNHTBG
QFN-16
(Pb-Free / Halide-Free)
100 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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16
NBSG53A
PACKAGE DIMENSIONS
QFN16 3x3, 0.5P
CASE 485G
ISSUE F
D
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
PIN 1
LOCATION
0.10 C
2X
L1
DETAIL A
ALTERNATE TERMINAL
CONSTRUCTIONS
E
ÉÉÉ
ÉÉÉ
TOP VIEW
DETAIL B
0.05 C
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
L
L
EXPOSED Cu
0.10 C
2X
A
B
(A3)
ÉÉ
ÉÉ
ÇÇ
MOLD CMPD
A3
A1
DETAIL B
A
0.05 C
ALTERNATE
CONSTRUCTIONS
NOTE 4
A1
SIDE VIEW
C
SEATING
PLANE
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
L1
MILLIMETERS
MIN
NOM MAX
0.80
0.90
1.00
0.00
0.03
0.05
0.20 REF
0.18
0.24
0.30
3.00 BSC
1.65
1.75
1.85
3.00 BSC
1.65
1.75
1.85
0.50 BSC
0.18 TYP
0.30
0.40
0.50
0.00
0.08
0.15
RECOMMENDED
SOLDERING FOOTPRINT*
16X
0.10 C A B
16X
L
DETAIL A
0.58
PACKAGE
OUTLINE
D2
8
4
1
9
2X
E2
16X
2X
1.84 3.30
K
1
16X
16
e
e/2
BOTTOM VIEW
0.30
16X
b
0.50
PITCH
0.10 C A B
0.05 C
NOTE 3
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
The products described herein (NBSG53A), may be covered by U.S. patents including 6,362,644. There may be other patents pending.
GigaComm is a trademark of Semiconductor Components Industries, LLC.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC
reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC
does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where
personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and
its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly,
any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture
of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
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Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
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For additional information, please contact your local
Sales Representative
NBSG53A/D