MC74VHC541 Octal Bus Buffer The MC74VHC541 is an advanced high speed CMOS octal bus buffer fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. The MC74VHC541 is a noninverting type. When either OE1 or OE2 are high, the terminal outputs are in the high impedance state. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V systems to 3.0 V systems. http://onsemi.com 1 Features • • • • • • • • • • • • High Speed: tPD = 3.7ns (Typ) at VCC = 5.0 V Low Power Dissipation: ICC = 4 mA (Max) at TA = 25°C High Noise Immunity: VNIH = VNIL = 28% VCC Power Down Protection Provided on Inputs Balanced Propagation Delays Designed for 2.0 V to 5.5 V Operating Range Low Noise: VOLP = 1.2 V (Max) Pin and Function Compatible with Other Standard Logic Families Latchup Performance Exceeds 300mA ESD Performance: HBM > 2000 V; Machine Model > 200 V Chip Complexity: 134 FETs or 33.5 Equivalent Gates These Devices are Pb−Free and are RoHS Compliant A1 A2 A3 DATA INPUTS A4 A5 A6 A7 A8 OUTPUT ENABLES SOIC−20WB SUFFIX DW CASE 751D 20 OE1 OE2 2 18 3 17 4 16 5 15 6 14 7 13 8 12 9 11 20 TSSOP−20 SUFFIX DT CASE 948E 1 SOEIAJ−20 SUFFIX M CASE 967 20 1 PIN ASSIGNMENT OE1 1 20 VCC A1 2 19 OE2 A2 3 18 Y1 A3 4 17 Y2 A4 5 16 Y3 A5 6 15 Y4 A6 7 14 Y5 A7 8 13 Y6 A8 9 12 Y7 10 11 Y8 Y1 Y2 Y3 Y4 NONINVERTING OUTPUTS GND Y5 Y6 FUNCTION TABLE Inputs Y7 Y8 1 OE1 OE2 A L L H X L L X H L H X X Output Y L H Z Z 19 ORDERING INFORMATION Figure 1. Logic Diagram See detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet. DEVICE MARKING INFORMATION See general marking information in the device marking section on page 4 of this data sheet. © Semiconductor Components Industries, LLC, 2012 May, 2012 − Rev. 7 1 Publication Order Number: MC74VHC541/D MC74VHC541 MAXIMUM RATINGS Symbol Value Unit VCC DC Supply Voltage Parameter – 0.5 to + 7.0 V Vin DC Input Voltage – 0.5 to + 7.0 V Vout DC Output Voltage – 0.5 to VCC + 0.5 V IIK Input Diode Current − 20 mA IOK Output Diode Current ± 20 mA Iout DC Output Current, per Pin ± 25 mA ICC DC Supply Current, VCC and GND Pins ± 50 mA PD Power Dissipation in Still Air, 500 450 mW Tstg Storage Temperature – 65 to + 150 _C SOIC Packages† TSSOP Package† This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND v (Vin or Vout) v VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V CC ). Unused outputs must be left open. Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. †Derating — SOIC Packages: – 7 mW/_C from 65_ to 125_C TSSOP Package: − 6.1 mW/_C from 65_ to 125_C RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit 2.0 5.5 V VCC DC Supply Voltage Vin DC Input Voltage 0 5.5 V Vout DC Output Voltage 0 VCC V −55 +125 _C 0 0 100 20 ns/V TA Operating Temperature, All Package Types tr, tf Input Rise and Fall Time VCC = 5.0V ±0.5V VCC = 3.3V ±0.3V DC ELECTRICAL CHARACTERISTICS Symbol Parameter Test Conditions Min 1.50 VCC x 0.7 VIH Minimum High−Level Input Voltage 2.0 3.0 to 5.5 VIL Maximum Low−Level Input Voltage 2.0 3.0 to 5.5 VOH Minimum High−Level Output Voltage VOL Maximum Low−Level Output Voltage TA = 25°C VCC V Typ TA = − 55 to 125°C Max Min 1.50 VCC x 0.7 0.50 VCC x 0.3 Vin = VIH or VIL IOH = − 50mA 2.0 3.0 4.5 1.9 2.9 4.4 Vin = VIH or VIL IOH = − 4mA IOH = − 8mA 3.0 4.5 2.58 3.94 Vin = VIH or VIL IOL = 50mA 2.0 3.0 4.5 Vin = VIH or VIL IOL = 4mA IOL = 8mA Max 2.0 3.0 4.5 Unit V 0.50 VCC x 0.3 V V 1.9 2.9 4.4 2.48 3.80 0.0 0.0 0.0 0.1 0.1 0.1 0.1 0.1 0.1 3.0 4.5 0.36 0.36 0.44 0.44 V Iin Maximum Input Leakage Current Vin = 5.5V or GND 0 to 5.5 ± 0.1 ± 1.0 mA IOZ Maximum 3−State Leakage Current Vin = VIL or VIH Vout = VCC or GND 5.5 ± 0.25 ± 2.5 mA ICC Maximum Quiescent Supply Current Vin = VCC or GND 5.5 4.0 40.0 mA http://onsemi.com 2 MC74VHC541 AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns) TA = 25°C Parameter Symbol tPLH, tPHL tPZL, tPZH tPLZ, tPHZ tOSLH, tOSHL Maximum Propagation Delay, A to Y Output Enable TIme, OE to Y Output Disable Time, OE to Y Output to Output Skew Min Test Conditions TA = − 55 to 125°C Typ Max Min Max Unit ns VCC = 3.3 ± 0.3V CL = 15pF CL = 50pF 5.0 7.5 7.0 10.5 1.0 1.0 8.5 12.0 VCC = 5.0 ± 0.5V CL = 15pF CL = 50pF 3.5 5.0 5.0 7.0 1.0 1.0 6.0 8.0 VCC = 3.3 ± 0.3V RL = 1kW CL = 15pF CL = 50pF 6.8 9.3 10.5 14.0 1.0 1.0 12.5 16.0 VCC = 5.0 ± 0.5V RL = 1kW CL = 15pF CL = 50pF 4.7 6.2 7.2 9.2 1.0 1.0 8.5 10.5 VCC = 3.3 ± 0.3V RL = 1kW CL = 50pF 11.2 15.4 1.0 17.5 VCC = 5.0 ± 0.5V RL = 1kW CL = 50pF 6.0 8.8 1.0 10.0 VCC = 3.3 ± 0.3V (Note 1) CL = 50pF 1.5 1.5 ns VCC = 5.0 ± 0.5V (Note 1) CL = 50pF 1.0 1.0 ns 10 10 pF Cin Maximum Input Capacitance 4 Cout Maximum Three−State Output Capacitance (Output in High Impedance State) 6 ns ns pF Typical @ 25°C, VCC = 5.0V CPD 18 Power Dissipation Capacitance (Note 2) pF 1. Parameter guaranteed by design. tOSLH = |tPLHm − tPLHn|, tOSHL = |tPHLm − tPHLn|. 2. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC / 8 (per bit). CPD is used to determine the no−load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC. NOISE CHARACTERISTICS (Input tr = tf = 3.0ns, CL = 50pF, VCC = 5.0V) TA = 25°C Typ Max Unit VOLP Quiet Output Maximum Dynamic VOL 0.9 1.2 V VOLV Quiet Output Minimum Dynamic VOL − 0.9 − 1.2 V VIHD Minimum High Level Dynamic Input Voltage 3.5 V VILD Maximum Low Level Dynamic Input Voltage 1.5 V Symbol Parameter SWITCHING WAVEFORMS VCC VCC OE1 or OE2 50% 50% GND A 50% tPZL tPLZ HIGH IMPEDANCE GND tPHL tPLH Y 50% VCC VOL +0.3V Y tPZH 50% VCC tPHZ VOH -0.3V Y Figure 2. 50% VCC Figure 3. http://onsemi.com 3 HIGH IMPEDANCE MC74VHC541 TEST CIRCUITS TEST POINT TEST POINT OUTPUT OUTPUT DEVICE UNDER TEST DEVICE UNDER TEST CL* CONNECT TO VCC WHEN TESTING tPLZ AND tPZL. CONNECT TO GND WHEN TESTING tPHZ AND tPZH. 1kW CL* *Includes all probe and jig capacitance *Includes all probe and jig capacitance Figure 4. Figure 5. INPUT Figure 6. Input Equivalent Circuit ORDERING INFORMATION Package Shipping† SOIC−20WB (Pb−Free) 1000 / Tape & Reel MC74VHC541DTG TSSOP−20 (Pb−Free) 75 Units / Rail MC74VHC541DTR2G TSSOP−20 (Pb−Free) 2500 / Tape & Reel MC74VHC541MELG SOEIAJ−20 (Pb−Free) 2000 / Tape & Reel Device MC74VHC541DWR2G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. MARKING DIAGRAMS SOIC−20WB 20 TSSOP−20 20 1 20 VHC 541 ALYWG G VHC541 AWLYYWWG SOEIAJ−20 74VHC541 AWLYWWG 1 1 http://onsemi.com 4 A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G or G = Pb−Free Package (Note: Microdot may be in either location) MC74VHC541 PACKAGE DIMENSIONS SOIC−20 WB DW SUFFIX CASE 751D−05 ISSUE G A 20 11 X 45 _ E h 1 10 20X B B 0.25 M T A S B S A L H M 10X 0.25 NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. q B M D 18X e A1 SEATING PLANE C T http://onsemi.com 5 DIM A A1 B C D E e H h L q MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_ MC74VHC541 PACKAGE DIMENSIONS TSSOP−20 CASE 948E−02 ISSUE C 20X 0.15 (0.006) T U 2X L K REF 0.10 (0.004) S L/2 20 M T U S V K K1 ÍÍÍÍ ÍÍÍÍ ÍÍÍÍ S J J1 11 B −U− PIN 1 IDENT SECTION N−N 0.25 (0.010) N 1 10 M 0.15 (0.006) T U S A −V− N F DETAIL E C G D H DETAIL E 0.100 (0.004) −T− SEATING NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. MILLIMETERS INCHES DIM MIN MAX MIN MAX A 6.40 6.60 0.252 0.260 B 4.30 4.50 0.169 0.177 ----C 1.20 0.047 D 0.05 0.15 0.002 0.006 F 0.50 0.75 0.020 0.030 G 0.65 BSC 0.026 BSC −W− H 0.27 0.37 0.011 0.015 J 0.09 0.20 0.004 0.008 J1 0.09 0.16 0.004 0.006 K 0.19 0.30 0.007 0.012 K1 0.19 0.25 0.007 0.010 L 6.40 BSC 0.252 BSC M 0_ 8_ 0_ 8_ PLANE SOLDERING FOOTPRINT 7.06 1 0.65 PITCH 16X 0.36 16X 1.26 DIMENSIONS: MILLIMETERS http://onsemi.com 6 MC74VHC541 PACKAGE DIMENSIONS SOEIAJ−20 M SUFFIX CASE 967 ISSUE A 20 LE 11 Q1 E HE 1 M_ L 10 DETAIL P Z D e VIEW P A DIM A A1 b c D E e HE L LE M Q1 Z A1 b 0.13 (0.005) c NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). M 0.10 (0.004) MILLIMETERS MIN MAX --2.05 0.05 0.20 0.35 0.50 0.15 0.25 12.35 12.80 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --0.81 INCHES MIN MAX --0.081 0.002 0.008 0.014 0.020 0.006 0.010 0.486 0.504 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 --0.032 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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