[ /Title (CD74 HC175 , CD74 HCT17 5) /Subject (High Speed CMOS Logic Quad DType Flip- CD54HC175, CD74HC175, CD54HCT175, CD74HCT175 Data sheet acquired from Harris Semiconductor SCHS160C High-Speed CMOS Logic Quad D-Type Flip-Flop with Reset August 1997 - Revised October 2003 Features advantage of standard CMOS ICs and the ability to drive 10 LSTTL devices. • Common Clock and Asynchronous Reset on Four D-Type Flip-Flops Information at the D input is transferred to the Q, Q outputs on the positive going edge of the clock pulse. All four Flip-Flops are controlled by a common clock (CP) and a common reset (MR). Resetting is accomplished by a low voltage level independent of the clock. All four Q outputs are reset to a logic 0 and all four Q outputs to a logic 1. • Positive Edge Pulse Triggering • Complementary Outputs • Buffered Inputs • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads Ordering Information • Wide Operating Temperature Range . . . -55oC to 125oC PART NUMBER TEMP. RANGE (oC) PACKAGE • Balanced Propagation Delay and Transition Times CD54HC175F3A -55 to 125 16 Ld CERDIP • Significant Power Reduction Compared to LSTTL Logic ICs CD54HCT175F3A -55 to 125 16 Ld CERDIP CD74HC175E -55 to 125 16 Ld PDIP CD74HC175M -55 to 125 16 Ld SOIC CD74HC175MT -55 to 125 16 Ld SOIC • HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH CD74HC175M96 -55 to 125 16 Ld SOIC CD74HCT175E -55 to 125 16 Ld PDIP CD74HCT175M -55 to 125 16 Ld SOIC CD74HCT175MT -55 to 125 16 Ld SOIC Description CD74HCT175M96 -55 to 125 16 Ld SOIC • HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V The ’HC175 and ’HCT175 are high speed Quad D-type FlipFlops with individual D-inputs and Q, Q complementary outputs. The devices are fabricated using silicon gate CMOS technology. They have the low power consumption NOTE: When ordering, use the entire part number. The suffix 96 denotes tape and reel. The suffix T denotes a small-quantity reel of 250. Pinout CD54HC175, CD54HCT175 (CERDIP) CD74HC175, CD74HCT175 (PDIP, SOIC) TOP VIEW MR 1 16 VCC Q0 2 15 Q3 Q0 3 14 Q3 D0 4 13 D3 D1 5 12 D2 Q1 6 11 Q2 Q1 7 10 Q2 GND 8 9 CP CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, Texas Instruments Incorporated 1 CD54HC175, CD74HC175, CD54HCT175, CD74HCT175 Functional Diagram 4 D0 2 D Q 9 CP CP 1 MR Q R 5 D1 Q CP Q1 6 Q R 12 Q1 10 D Q CP Q2 11 Q R 13 D3 Q0 7 D D2 Q0 3 Q2 15 D Q CP Q3 14 Q R Q3 TRUTH TABLE INPUTS OUTPUTS RESET (MR) CLOCK CP DATA Dn Qn Qn L X X L H H ↑ H H L H ↑ L L H H L X Q0 Q0 H = High Voltage Level, L = Low Voltage Level, X = Don’t Care, ↑ = Transition from Low to High Level, Q0 = Level Before the Indicated Steady-State Input Conditions Were Established. Logic Diagram 4 (5, 12, 13) Dn D CL CL p p n n CL CL 3( 6, 11, 14) Qn CL CL p p n n CL CL R ONE OF FOUR F/F CL CL 2( 7, 10, 15) Qn CP 1 MR TO OTHER THREE F/F 8 16 9 CP TO OTHER THREE F/F GND 2 VCC CD54HC175, CD74HC175, CD54HCT175, CD74HCT175 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA DC VCC or Ground Current, ICC or IGND . . . . . . . . . . . . . . . . . .±50mA Thermal Resistance (Typical, Note 1) θJA (oC/W) E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . 67 M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . 73 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. The package thermal impedance is calculated in accordance with JESD 51-7. DC Electrical Specifications TEST CONDITIONS PARAMETER SYMBOL VI (V) VIH - 25oC IO (mA) VCC (V) -40oC TO +85oC -55oC TO 125oC MIN TYP MAX MIN MAX MIN MAX UNITS 2 1.5 - - 1.5 - 1.5 - V 4.5 3.15 - - 3.15 - 3.15 - V 6 4.2 - - 4.2 - 4.2 - V HC TYPES High Level Input Voltage Low Level Input Voltage High Level Output Voltage CMOS Loads VIL VOH - VIH or VIL High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads VOL VIH or VIL Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current - - 2 - - 0.5 - 0.5 - 0.5 V 4.5 - - 1.35 - 1.35 - 1.35 V 6 - - 1.8 - 1.8 - 1.8 V -0.02 2 1.9 - - 1.9 - 1.9 - V -0.02 4.5 4.4 - - 4.4 - 4.4 - V -0.02 6 5.9 - - 5.9 - 5.9 - V -4 4.5 3.98 - - 3.84 - 3.7 - V -5.2 6 5.48 - - 5.34 - 5.2 - V 0.02 2 - - 0.1 - 0.1 - 0.1 V 0.02 4.5 - - 0.1 - 0.1 - 0.1 V 0.02 6 - - 0.1 - 0.1 - 0.1 V 4 4.5 - - 0.26 - 0.33 - 0.4 V 5.2 6 - - 0.26 - 0.33 - 0.4 V II VCC or GND - 6 - - ±0.1 - ±1 - ±1 µA ICC VCC or GND 0 6 - - 8 - 80 - 160 µA 3 CD54HC175, CD74HC175, CD54HCT175, CD74HCT175 DC Electrical Specifications (Continued) TEST CONDITIONS SYMBOL VI (V) High Level Input Voltage VIH - - Low Level Input Voltage VIL - High Level Output Voltage CMOS Loads VOH VIH or VIL PARAMETER 25oC IO (mA) VCC (V) -40oC TO +85oC -55oC TO 125oC MIN TYP MAX MIN MAX MIN MAX UNITS 4.5 to 5.5 2 - - 2 - 2 - V - 4.5 to 5.5 - - 0.8 - 0.8 - 0.8 V -0.02 4.5 4.4 - - 4.4 - 4.4 - V -4 4.5 3.98 - - 3.84 - 3.7 - V 0.02 4.5 - - 0.1 - 0.1 - 0.1 V 4 4.5 - - 0.26 - 0.33 - 0.4 V HCT TYPES High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads VOL VIH or VIL Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current Additional Quiescent Device Current Per Input Pin: 1 Unit Load II VCC to GND 0 5.5 - - ±0.1 - ±1 - ±1 µA ICC VCC or GND 0 5.5 - - 8 - 80 - 160 µA ∆ICC (Note 2) VCC -2.1 - 4.5 to 5.5 - 100 360 - 450 - 490 µA NOTES: 2. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. HCT Input Loading Table INPUT UNIT LOADS MR 1 CP 0.60 D 0.15 NOTE: Unit Load is ∆ICC limit specified in DC Electrical Specifications table, e.g. 360µA max at 25oC. Prerequisite For Switching Specifications PARAMETER SYMBOL TEST CONDITIONS tw - 25oC -40oC TO 85oC -55oC TO 125oC VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS HC TYPES Clock Pulse Width MR Pulse Width tw - 2 80 - - 100 - 120 - ns 4.5 16 - - 20 - 24 - ns 6 14 - - 17 - 20 - ns 2 80 - - 100 - 120 - ns 4.5 16 - - 20 - 24 - ns 6 14 - - 17 - 20 - ns 4 CD54HC175, CD74HC175, CD54HCT175, CD74HCT175 Prerequisite For Switching Specifications PARAMETER Setup Time, Data to Clock -40oC TO 85oC -55oC TO 125oC SYMBOL VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS tSU - 2 80 - - 100 - 120 - ns 4.5 16 - - 20 - 24 - ns 6 14 - - 17 - 20 - ns 2 5 - - 5 - 5 - ns 4.5 5 - - 5 - 5 - ns 6 5 - - 5 - 5 - ns 2 5 - - 5 - 5 - ns 4.5 5 - - 5 - 5 - ns 6 5 - - 5 - 5 - ns 2 6 - - 5 - 4 - MHz 4.5 30 - - 25 - 20 - MHz 6 35 - - 29 - 23 - MHz tH - tREM Clock Frequency 25oC TEST CONDITIONS Hold Time, Data to Clock Removal Time, MR to Clock (Continued) - fMAX - HCT TYPES Clock Pulse Width tw - 4.5 20 - - 25 - 30 - ns MR Pulse Width tw - 4.5 20 - - 25 - 30 - ns Setup Time Data to Clock tSU - 4.5 20 - - 25 - 30 - ns Hold Time Data to Clock tH - 4.5 5 - - 5 - 5 - ns Removal Time MR to Clock tREM - 4.5 5 - - 5 - 5 - ns Clock Frequency fMAX - 4.5 25 - - 20 - 16 - MHz Switching Specifications PARAMETER Input tr, tf = 6ns SYMBOL TEST CONDITIONS tPLH, tPHL CL = 50pF 25oC -40oC TO 85oC -55oC TO 125oC VCC (V) TYP MAX MAX MAX UNITS 2 - 175 220 265 ns 4.5 - 35 44 53 ns 6 - 30 37 45 ns CL = 15pF 5 14 - - - ns CL = 50pF 2 - 175 220 265 ns 4.5 - 35 44 53 ns 6 - 30 37 45 ns CL = 15pF 5 14 - - - ns CL = 50pF 2 - 75 95 110 ns 4.5 - 15 19 22 ns 6 - 13 16 19 ns HC TYPES Propagation Delay, Clock to Q or Q Propagation Delay, MR to Q or Q Output Transition Times tPLH, tPHL tTLH, tTHL Input Capacitance CIN - - - 10 10 10 pF Power Dissipation Capacitance (Notes 3, 4) CPD - 5 65 - - - pF 5 CD54HC175, CD74HC175, CD54HCT175, CD74HCT175 Switching Specifications Input tr, tf = 6ns (Continued) SYMBOL TEST CONDITIONS Propagation Delay, Clock to Q or Q tPLH, tPHL Propagation Delay, MR to Q or Q tPLH, tPHL Output Transition Times tTLH, tTHL PARAMETER 25oC -40oC TO 85oC -55oC TO 125oC VCC (V) TYP MAX MAX MAX UNITS CL = 50pF 4.5 - 33 41 50 ns CL = 15pF 5 13 - - - ns CL = 50pF 4.5 - 35 44 53 ns CL = 15pF 5 17 - - - ns CL = 50pF 4.5 - 15 19 22 ns HCT TYPES Input Capacitance CIN - - - 10 10 10 pF Power Dissipation Capacitance (Notes 3, 4) CPD - 5 67 - - - pF NOTES: 3. CPD is used to determine the dynamic power consumption, per flip-flop. 4. PD = VCC2 fi + ∑ (CL VCC2 + fO) where fi = Input Frequency, fO = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage. Test Circuits and Waveforms CLOCK INPUT trCL tfCL trCL VCC 90% GND tH(H) GND tH(H) VCC DATA INPUT 50% tH(L) 3V 1.3V 1.3V 1.3V GND tSU(H) tSU(H) tSU(L) tTLH 90% OUTPUT tTHL 90% 50% 10% tTLH 90% 1.3V OUTPUT tREM 3V SET, RESET OR PRESET GND tTHL 1.3V 10% FIGURE 1. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME, AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS tPHL 1.3V GND IC CL 50pF GND 90% tPLH 50% IC tSU(L) tPHL tPLH tREM VCC SET, RESET OR PRESET 1.3V 0.3V tH(L) DATA INPUT 3V 2.7V CLOCK INPUT 50% 10% tfCL CL 50pF FIGURE 2. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME, AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS 6 PACKAGE OPTION ADDENDUM www.ti.com 9-Oct-2007 PACKAGING INFORMATION (1) Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty 5962-8970101EA ACTIVE CDIP J 16 1 TBD A42 SNPB N / A for Pkg Type CD54HC175F3A ACTIVE CDIP J 16 1 TBD A42 SNPB N / A for Pkg Type CD54HCT175F3A ACTIVE CDIP J 16 1 TBD A42 SNPB N / A for Pkg Type CD74HC175E ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type CD74HC175EE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type CD74HC175M ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC175M96 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC175M96E4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC175M96G4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC175ME4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC175MG4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC175MT ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC175MTE4 ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC175MTG4 ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT175E ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type CD74HCT175EE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type CD74HCT175M ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT175M96 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT175M96E4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT175M96G4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT175ME4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT175MG4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT175MT ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT175MTE4 ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT175MTG4 ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM The marketing status values are defined as follows: Addendum-Page 1 Lead/Ball Finish MSL Peak Temp (3) PACKAGE OPTION ADDENDUM www.ti.com 9-Oct-2007 ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 4-Oct-2007 TAPE AND REEL BOX INFORMATION Device Package Pins Site Reel Diameter (mm) Reel Width (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant CD74HC175M96 D 16 SITE 27 330 16 6.5 10.3 2.1 8 16 Q1 CD74HCT175M96 D 16 SITE 27 330 16 6.5 10.3 2.1 8 16 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 4-Oct-2007 Device Package Pins Site Length (mm) Width (mm) Height (mm) CD74HC175M96 D 16 SITE 27 342.9 336.6 28.58 CD74HCT175M96 D 16 SITE 27 342.9 336.6 28.58 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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