ON NVMFS5C673NL Power mosfet Datasheet

NVMFS5C673NL
Power MOSFET
60 V, 9.2 mW, 50 A, Single N−Channel
Features
•
•
•
•
•
•
Small Footprint (5x6 mm) for Compact Design
Low RDS(on) to Minimize Conduction Losses
Low QG and Capacitance to Minimize Driver Losses
NVMFS5C673NLWF − Wettable Flank Option for Enhanced Optical
Inspection
AEC−Q101 Qualified and PPAP Capable
These Devices are Pb−Free and are RoHS Compliant
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V(BR)DSS
RDS(ON) MAX
ID MAX
9.2 mW @ 10 V
60 V
50 A
13 mW @ 4.5 V
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Symbol
Value
Unit
Drain−to−Source Voltage
VDSS
60
V
Gate−to−Source Voltage
VGS
±20
V
ID
50
A
Parameter
Continuous Drain
Current RqJC
(Notes 1, 3)
TC = 25°C
Power Dissipation
RqJC (Note 1)
Continuous Drain
Current RqJA
(Notes 1, 2, 3)
Steady
State
TC = 100°C
TC = 25°C
TA = 25°C
Power Dissipation
RqJA (Notes 1 & 2)
Steady
State
G (4)
35
PD
TC = 100°C
W
46
S (1,2,3)
23
ID
TA = 100°C
A
14
3.6
IDM
290
A
TJ, Tstg
−55 to
+ 175
°C
IS
52
A
Single Pulse Drain−to−Source Avalanche
Energy (IL(pk) = 2.3 A)
EAS
88
mJ
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
TL
260
°C
Pulsed Drain Current
TA = 100°C
TA = 25°C, tp = 10 ms
Operating Junction and Storage Temperature
Source Current (Body Diode)
1.8
THERMAL RESISTANCE MAXIMUM RATINGS
Symbol
Value
Unit
Junction−to−Case − Steady State
RqJC
3.2
°C/W
Junction−to−Ambient − Steady State (Note 2)
RqJA
42
1. The entire application environment impacts the thermal resistance values shown,
they are not constants and are only valid for the particular conditions noted.
2. Surface−mounted on FR4 board using a 650 mm2, 2 oz. Cu pad.
3. Maximum current for pulses as long as 1 second is higher but is dependent
on pulse duration and duty cycle.
© Semiconductor Components Industries, LLC, 2015
February, 2017 − Rev. 1
MARKING
DIAGRAM
W
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
Parameter
N−CHANNEL MOSFET
10
PD
TA = 25°C
D (5)
1
1
DFN5
(SO−8FL)
CASE 488AA
STYLE 1
D
S
S
S
G
D
XXXXXX
AYWZZ
D
D
XXXXXX = 5C673L
XXXXXX = (NVMFS5C673NL) or
XXXXXX = 673LWF
XXXXXX = (NVMFS5C673NLWF)
A
= Assembly Location
Y
= Year
W
= Work Week
ZZ
= Lot Traceability
ORDERING INFORMATION
See detailed ordering, marking and shipping information in the
package dimensions section on page 5 of this data sheet.
Publication Order Number:
NVMFS5C673NL/D
NVMFS5C673NL
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified)
Parameter
Symbol
Test Condition
Min
Drain−to−Source Breakdown Voltage
V(BR)DSS
VGS = 0 V, ID = 250 mA
60
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V(BR)DSS/
TJ
Typ
Max
Unit
OFF CHARACTERISTICS
Zero Gate Voltage Drain Current
IDSS
Gate−to−Source Leakage Current
V
28
VGS = 0 V,
VDS = 60 V
mV/°C
TJ = 25°C
10
TJ = 125°C
250
IGSS
VDS = 0 V, VGS = 20 V
VGS(TH)
VGS = VDS, ID = 35 mA
100
mA
nA
ON CHARACTERISTICS (Note 4)
Gate Threshold Voltage
Threshold Temperature Coefficient
VGS(TH)/TJ
Drain−to−Source On Resistance
Forward Transconductance
RDS(on)
1.2
2.0
−4.5
VGS = 10 V
ID = 25 A
7.7
9.2
VGS = 4.5 V
ID = 25 A
11
13
gFS
VDS =15 V, ID = 25 A
V
mV/°C
37
mW
S
CHARGES AND CAPACITANCES
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
880
VGS = 0 V, f = 1 MHz, VDS = 25 V
450
pF
11
Total Gate Charge
QG(TOT)
VGS = 4.5 V, VDS = 48 V; ID = 25 A
4.5
nC
Total Gate Charge
QG(TOT)
VGS = 10 V, VDS = 48 V; ID = 25 A
9.5
nC
Threshold Gate Charge
QG(TH)
1.0
Gate−to−Source Charge
QGS
Gate−to−Drain Charge
QGD
Plateau Voltage
VGP
2.9
td(ON)
6.0
VGS = 10 V, VDS = 48 V; ID = 25 A
2.0
nC
0.8
V
SWITCHING CHARACTERISTICS (Note 5)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
tr
td(OFF)
VGS = 10 V, VDS = 48 V,
ID = 25 A, RG = 2.5 W
tf
25
ns
16
2.0
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
Reverse Recovery Time
Charge Time
Discharge Time
Reverse Recovery Charge
VSD
VGS = 0 V,
IS = 25 A
TJ = 25°C
0.9
TJ = 125°C
0.8
tRR
ta
tb
1.2
V
28
VGS = 0 V, dIs/dt = 100 A/ms,
IS = 25 A
QRR
14
ns
14
18
nC
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Pulse Test: pulse width v 300 ms, duty cycle v 2%.
5. Switching characteristics are independent of operating junction temperatures.
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2
NVMFS5C673NL
TYPICAL CHARACTERISTICS
40
ID, DRAIN CURRENT (A)
3.2 V
30
3.0 V
25
20
2.8 V
15
10
2.6 V
5
2.4 V
0
0
1.0
0.5
1.5
2.0
30
25
20
15
TJ = 25°C
10
5
0
2.5
TJ = 125°C
0
TJ = −55°C
2.0
2.5
3.5
3.0
Figure 2. Transfer Characteristics
30
25
20
15
10
5
4
5
7
6
8
9
10
VGS, GATE−TO−SOURCE VOLTAGE (V)
4.0
20
TJ = 25°C
18
16
14
VGS = 4.5 V
12
10
VGS = 10 V
8
6
0
10
20
30
50
40
60
70
80
90 100
ID, DRAIN CURRENT (A)
Figure 3. On−Resistance vs. Gate−to−Source
Voltage
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
100,000
2.25
VGS = 10 V
ID = 25 A
TJ = 175°C
10,000
IDSS, LEAKAGE (nA)
RDS(on), NORMALIZED DRAIN−TO−
SOURCE RESISTANCE
1.5
Figure 1. On−Region Characteristics
TJ = 25°C
ID = 25 A
1.75
1.50
1.25
1.00
TJ = 125°C
1000
TJ = 85°C
100
10
0.75
0.50
−50
1.0
VGS, GATE−TO−SOURCE VOLTAGE (V)
35
2.00
0.5
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
40
3
VDS = 3 V
35
RDS(on), DRAIN−TO−SOURCE RESISTANCE (mW)
ID, DRAIN CURRENT (A)
35
RDS(on), DRAIN−TO−SOURCE RESISTANCE (mW)
40
VGS = 3.6 V to 10 V
1
−25
0
25
50
75
100
125
150
175
10
20
30
40
50
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
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3
60
NVMFS5C673NL
TYPICAL CHARACTERISTICS
VGS, GATE−TO−SOURCE VOLTAGE (V)
C, CAPACITANCE (pF)
10000
CISS
1000
COSS
100
10
VGS = 0 V
TJ = 25°C
f = 1 MHz
1
0
CRSS
10
20
30
40
50
60
6
5
3
VDS = 30 V
TJ = 25°C
ID = 25 A
2
1
0
1
0
3
2
4
5
6
7
8
9
Figure 8. Gate−to−Source vs. Total Charge
td(off)
td(on)
tf
1
QGD
QGS
4
Figure 7. Capacitance Variation
IS, SOURCE CURRENT (A)
t, TIME (ns)
7
100
10
VGS = 10 V
VDS = 48 V
ID = 25 A
1
10
10
VGS = 0 V
10
1
0.1
100
TJ = 125°C
0.3
0.4
TJ = 25°C
0.5
0.6
TJ = −55°C
0.7
0.8
0.9
1.0
RG, GATE RESISTANCE (W)
VSD, SOURCE−TO−DRAIN VOLTAGE (V)
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
1000
100
IPEAK, DRAIN CURRENT (A)
100
1 ms
ID, DRAIN CURRENT (A)
8
QG, TOTAL GATE CHARGE (nC)
tr
500 ms
10 ms
10
TC = 25°C
VGS ≤ 10 V
Single Pulse
1
RDS(on) Limit
Thermal Limit
Package Limit
0.1
0.01
QT
9
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
100
0.1
10
0.1
1
10
10
TJ (initial)= 25°C
TJ (initial)= 100°C
1
0.1
1.E−05
100
1.E−04
1.E−03
1.E−02
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
TAV, TIME IN AVALANCHE (s)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. Maximum Drain Current vs. Time in
Avalanche
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4
NVMFS5C673NL
RqJA, EFFECTIVE TRANSIENT THERMAL
RESISTANCE (°C/W)
TYPICAL CHARACTERISTICS
100
50% Duty Cycle
10 20%
10%
5%
1
2%
1%
0.1
Single Pulse
0.01
0.000001
0.00001
0.0001
0.001
0.01
0.1
1
10
100
1000
PULSE TIME (sec)
Figure 13. Thermal Characteristics
DEVICE ORDERING INFORMATION
Device
Marking
Package
Shipping†
NVMFS5C673NLT1G
5C673L
DFN5
(Pb−Free)
1500 / Tape & Reel
NVMFS5C673NLWFT1G
673LWF
DFN5
(Pb−Free, Wettable Flanks)
1500 / Tape & Reel
NVMFS5C673NLT3G
5C673L
DFN5
(Pb−Free)
5000 / Tape & Reel
NVMFS5C673NLWFT3G
673LWF
DFN5
(Pb−Free, Wettable Flanks)
5000 / Tape & Reel
NVMFS5C673NLAFT1G
5C673L
DFN5
(Pb−Free)
1500 / Tape & Reel
NVMFS5C673NLWFAFT1G
673LWF
DFN5
(Pb−Free, Wettable Flanks)
1500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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5
NVMFS5C673NL
PACKAGE DIMENSIONS
DFN5 5x6, 1.27P
(SO−8FL)
CASE 488AA
ISSUE M
2X
0.20 C
D
2
A
B
D1
2X
0.20 C
2
2
3
DIM
A
A1
b
c
D
D1
D2
E
E1
E2
e
G
K
L
L1
M
q
4X
E1
1
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION D1 AND E1 DO NOT INCLUDE
MOLD FLASH PROTRUSIONS OR GATE
BURRS.
q
E
c
A1
4
TOP VIEW
C
SEATING
PLANE
DETAIL A
0.10 C
A
0.10 C
SIDE VIEW
0.10
8X b
C A B
0.05
c
DETAIL A
RECOMMENDED
SOLDERING FOOTPRINT*
e/2
2X
0.495
e
L
1
MILLIMETERS
MIN
NOM
MAX
0.90
1.00
1.10
0.00
−−−
0.05
0.33
0.41
0.51
0.23
0.28
0.33
5.15
5.00
5.30
4.70
4.90
5.10
3.80
4.00
4.20
6.00
6.15
6.30
5.70
5.90
6.10
3.45
3.65
3.85
1.27 BSC
0.51
0.575
0.71
1.20
1.35
1.50
0.51
0.575
0.71
0.125 REF
3.00
3.40
3.80
0_
−−−
12 _
STYLE 1:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
4.560
2X
1.530
4
K
PIN 5
(EXPOSED PAD)
G
3.200
E2
L1
4.530
M
D2
1.330
2X
0.905
1
BOTTOM VIEW
0.965
4X
1.000
4X 0.750
1.270
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
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at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
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For additional information, please contact your local
Sales Representative
NVMFS5C673NL/D