MC100LVEP34 2.5V / 3.3V ECL ÷2, ÷4, ÷8 Clock Generation Chip The MC100LVEP34 is a low skew ÷2, ÷4, ÷8 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The VBB pin, an internally generated voltage supply, is available to this device only. For single−ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open. The common enable (EN) is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the LOW state. This avoids any chance of generating a runt clock pulse on the internal clock when the device is enabled/disabled as can happen with an asynchronous control. An internal runt pulse could lead to losing synchronization between the internal divider stages. The internal enable flip−flop is clocked on the falling edge of the input clock; therefore, all associated specification limits are referenced to the negative edge of the clock input. Upon start−up, the internal flip−flops will attain a random state; the master reset (MR) input allows for the synchronization of the internal dividers, as well as multiple LVEP34s in a system. Single−ended CLK input operation is limited to a VCC ≥ 3.0 V in PECL mode, or VEE ≤ −3.0 V in NECL mode. MARKING DIAGRAMS* 16 16 35 ps Output−to−Output Skew Synchronous Enable/Disable 100LVEP34G AWLYWW 1 SO−16 D SUFFIX CASE 751B 1 16 100 VP34 ALYWG G 16 1 TSSOP−16 DT SUFFIX CASE 948F A L, WL Y W, WW G or G Features • • • • • http://onsemi.com 1 = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) Master Reset for Synchronization *For additional marking information, refer to Application Note AND8002/D. The 100 Series Contains Temperature Compensation. PECL Mode Operating Range: VCC = 2.375 V to 3.8 V with VEE = 0 V ORDERING INFORMATION • NECL Mode Operating Range: VCC = 0 V See detailed ordering and shipping information in the package dimensions section on page 8 of this data sheet. with VEE = −2.375 V to −3.8 V Open Input Default State • • LVDS Input Compatible • These are Pb−Free Devices © Semiconductor Components Industries, LLC, 2014 April, 2014 − Rev. 11 1 Publication Order Number: MC100LVEP34/D MC100LVEP34 Q0 1 Q Q0 VCC 15 EN 14 NC 13 CLK 12 CLK ÷2 2 R VCC 16 Q D 3 R Q1 4 Q Q1 ÷4 5 R VCC 6 11 VBB Q2 7 10 MR 9 VEE Q ÷8 Q2 8 R Warning: All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation. Figure 1. 16−Lead Pinout (Top View) and Logic Diagram Table 1. PIN DESCRIPTION Pin Table 2. FUNCTION TABLE Function CLK*, CLK** ECL Diff Clock Inputs EN* ECL Sync Enable MR* ECL Master Reset Q0, Q0 ECL Diff ÷2 Outputs Q1, Q1 ECL Diff ÷4 Outputs Q2, Q2 ECL Diff ÷8 Outputs VBB Reference Voltage Output VCC Positive Supply VEE Negative Supply NC No Connect CLK EN MR FUNCTION Z ZZ X L H X L L H Divide Hold Q0−3 Reset Q0−3 Z = Low−to−High Transition ZZ = High−to−Low Transition * Pins will default LOW when left open. **Pins will default to VCC/2 when left open. http://onsemi.com 2 MC100LVEP34 Table 3. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor 75 kW Internal Input Pullup Resistor ESD Protection 37.5 kW Human Body Model Machine Model Charged Device Model > 2 kV > 200 V > 2 kV Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Flammability Rating Level 1 Oxygen Index: 28 to 34 UL 94 V−O @ 0.125 in Transistor Count 210 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional Moisture Sensitivity information, refer to Application Note AND8003/D. Table 4. MAXIMUM RATINGS Symbol Parameter Condition 1 Condition 2 Rating Unit VCC PECL Mode Power Supply VEE = 0 V 6 V VEE NECL Mode Power Supply VCC = 0 V −6 V VI PECL Mode Input Voltage NECL Mode Input Voltage VEE = 0 V VCC = 0 V 6 −6 V V Iout Output Current Continuous Surge 50 100 mA mA IBB VBB Sink/Source ± 0.5 mA TA Operating Temperature Range −40 to +85 °C Tstg Storage Temperature Range −65 to +150 °C qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm SOIC−16 SOIC−16 100 60 °C/W °C/W qJC Thermal Resistance (Junction−to−Case) Standard Board SOIC−16 33 to 36 °C/W qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm TSSOP−16 TSSOP−16 138 108 °C/W °C/W qJC Thermal Resistance (Junction−to−Case) Standard Board TSSOP−16 33 to 36 °C/W Tsol Wave Solder <2 to 3 sec @ 248°C 265 °C VI VCC VI VEE Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. http://onsemi.com 3 MC100LVEP34 Table 5. 100EP DC CHARACTERISTICS, PECL VCC = 2.5 V, VEE = 0 V (Note 2) −40°C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit 40 50 60 40 50 60 42 52 62 mA IEE Power Supply Current VOH Output HIGH Voltage (Note 3) 1355 1480 1605 1355 1480 1605 1355 1480 1605 mV VOL Output LOW Voltage (Note 3) 505 680 900 505 680 900 505 680 900 mV VIH Input HIGH Voltage (Single−Ended) (Note 4) 1335 1620 1335 1620 1275 1620 mV VIL Input LOW Voltage (Single−Ended) (Note 4) 505 900 505 900 505 900 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential) (Note 4, Note 5) 1.2 3.3 1.2 3.3 1.2 3.3 V IIH Input HIGH Current 150 mA IIL Input LOW Current 150 D D 0.5 −150 150 0.5 −150 0.5 −150 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 2. Input and output parameters vary 1:1 with VCC. 3. All loading with 50 W to VCC − 2.0 V. 4. Do not use VBB at VCC < 3.0 V. Single−Ended input CLK pin operation is limited to VCC 3.0 V in PECL mode. 5. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. http://onsemi.com 4 MC100LVEP34 Table 6. 100EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 6) −40°C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit 40 50 60 40 50 60 42 52 62 mA IEE Power Supply Current VOH Output HIGH Voltage (Note 7) 2155 2280 2405 2155 2280 2405 2155 2280 2405 mV VOL Output LOW Voltage (Note 7) 1305 1570 1700 1305 1570 1700 1305 1570 1700 mV VIH Input HIGH Voltage (Single−Ended) 2075 2420 2075 2420 2075 2420 mV VIL Input LOW Voltage (Single−Ended) 1305 1700 1305 1700 1305 1700 mV VBB Output Voltage Reference (Note 8) 1775 1975 1775 1975 1775 1975 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential) (Note 9) 1.2 3.3 1.2 3.3 1.2 3.3 V IIH Input HIGH Current 150 mA IIL Input LOW Current 1875 1875 150 D D 1875 150 0.5 −150 0.5 −150 mA 0.5 −150 NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 6. Input and output parameters vary 1:1 with VCC. VEE can vary +0.925 V to −0.5 V. 7. All loading with 50 W to VCC − 2.0 V. 8. Single−Ended input CLK pin operation is limited to VCC 3.0 V in PECL mode. 9. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. Table 7. 100EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = −3.8 V to −2.375 V (Note 10) −40°C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit 40 50 60 40 50 60 42 52 62 mA IEE Power Supply Current VOH Output HIGH Voltage (Note 11) −1145 −1020 −895 −1145 −1020 −895 −1145 −1020 −895 mV VOL Output LOW Voltage (Note 11) −1995 −1700 −1600 −1995 −1700 −1600 −1995 −1700 −1600 mV VIH Input HIGH Voltage (Single−Ended) −1225 −880 −1225 −880 −1225 −880 mV VIL Input LOW Voltage (Single−Ended) −1995 −1600 −1995 −1600 −1995 −1600 mV VBB Output Voltage Reference (Note 12) −1525 −1325 −1525 −1325 −1525 −1325 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential) (Note 13) 0.0 V IIH Input HIGH Current 150 mA IIL Input LOW Current −1425 VEE+1.2 0.0 VEE+1.2 150 D D 0.5 −150 −1425 0.0 VEE+1.2 150 0.5 −150 −1425 0.5 −150 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 10. Input and output parameters vary 1:1 with VCC. 11. All loading with 50 W to VCC − 2.0 V. 12. Single−Ended input CLK pin operation is limited to VEE −3.0 V in NECL mode. 13. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. http://onsemi.com 5 MC100LVEP34 Table 8. AC CHARACTERISTICS VCC= 0 V; VEE= −3.8 V to −2.375 V or VCC= 2.375 V to 3.8 V; VEE= 0 V (Note 14) −40°C Min Characteristic Symbol fmax Maximum Toggle Frequency (See Figure 4. Fmax) tPLH tPHL Propagation Delay to Output tJITTER RMS Clock Jitter (See Figure 4. Fmax/JITTER) Typ 25°C Max 2.8 CLK to Q0, Q1, Q2 MR to Q Min Typ 85°C Max 2.8 550 500 DIV2 v 2.5 GHz DIV2 v 3.0 GHz DIV4 v 2.5 GHz DIV4 v 3.0 GHz DIV8 v 2.5 GHz DIV8 v 3.0 GHz 650 600 750 700 0.36 0.34 0.26 0.32 0.27 0.32 0.4 600 550 0.4 0.4 Min Typ Max 2.8 700 650 800 750 0.30 0.40 0.29 0.38 0.30 0.39 0.4 650 600 0.5 0.5 Unit GHz 750 700 850 800 ps 0.35 0.63 0.33 0.60 0.34 1.10 0.6 ps 0.5 0.5 tS Setup Time EN 150 50 150 50 150 50 ps tH Hold Time EN 200 100 200 100 200 100 ps tRR Set/Reset Recovery 300 200 300 200 300 200 ps VPP Input Swing (Note 15) 150 tr tf Output Rise/Fall Times Q (20% − 80%) 90 170 1000 150 200 100 180 1000 150 250 120 200 1000 mV 280 ps NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 14. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to VCC − 2.0 V. 15. VPP(min) is minimum input swing for which AC parameters guaranteed. The device has a DC gain of ≈40. Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. http://onsemi.com 6 MC100LVEP34 There are two distinct functional relationships between the Master Reset and Clock: Internal Clock Disabled Internal Clock Enabled MR CLK Q0 Q1 Q2 EN CASE 1: If the MR is de−asserted (H−L), while the Clock is still high, the outputs will follow the second ensuing clock rising edge. Internal Clock Disabled Internal Clock Enabled MR CLK Q0 Q1 Q2 EN CASE 2: If the MR is de−asserted (H−L), after the Clock has transitioned low, the outputs will follow the third ensuing clock rising edge. Figure 2. Timing Diagrams The EN signal will “freeze” the internal divider flip−flops on the first falling edge of CLK after its assertion. The internal divider flip−flops will maintain their state during the freeze. When EN is deasserted (LOW), and after the next falling edge of CLK, then the internal divider flip−flops will “unfreeze” and continue to their next state count with proper phase relationships. TRR TRR CLOCK CLOCK MR MR OUTPUT OUTPUT CASE 1 CASE 2 Figure 3. Reset Recovery Time http://onsemi.com 7 MC100LVEP34 900 9 VOUTpp (mV) 800 8 B4 / 8 700 7 600 6 B2 500 5 400 4 300 3 200 2 100 1 0 0 1000 2000 3000 4000 5000 6000 FREQUENCY (MHz) Figure 4. Fmax Zo = 50 W Q D Receiver Device Driver Device Zo = 50 W Q D 50 W 50 W VTT VTT = VCC − 2.0 V Figure 5. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D − Termination of ECL Logic Devices.) ORDERING INFORMATION Device Package Shipping† MC100LVEP34DG SOIC−16 (Pb−Free) 48 Units / Rail MC100LVEP34DR2G SOIC−16 (Pb−Free) 2500 / Tape & Reel MC100LVEP34DTG TSSOP−16* 96 Units / Rail MC100LVEP34DTR2G TSSOP−16* 2500 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb−Free. http://onsemi.com 8 MC100LVEP34 Resource Reference of Application Notes AN1405/D − ECL Clock Distribution Techniques AN1406/D − Designing with PECL (ECL at +5.0 V) AN1503/D − ECLinPSt I/O SPiCE Modeling Kit AN1504/D − Metastability and the ECLinPS Family AN1568/D − Interfacing Between LVDS and ECL AN1672/D − The ECL Translator Guide AND8001/D − Odd Number Counters Design AND8002/D − Marking and Date Codes AND8020/D − Termination of ECL Logic Devices AND8066/D − Interfacing with ECLinPS AND8090/D − AC Characteristics of ECL Devices http://onsemi.com 9 MC100LVEP34 PACKAGE DIMENSIONS TSSOP−16 CASE 948F−01 ISSUE B 16X K REF 0.10 (0.004) 0.15 (0.006) T U T U M S V S S K ÉÉÉ ÇÇÇ ÇÇÇ ÉÉÉ K1 2X L/2 16 9 J1 B −U− L SECTION N−N J PIN 1 IDENT. N 0.25 (0.010) 8 1 M 0.15 (0.006) T U S A −V− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. N F DETAIL E −W− C 0.10 (0.004) −T− SEATING PLANE H D DETAIL E G DIM A B C D F G H J J1 K K1 L M SOLDERING FOOTPRINT* 7.06 1 0.65 PITCH 16X 0.36 16X 1.26 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 10 MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 −−− 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 −−− 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ MC100LVEP34 PACKAGE DIMENSIONS SOIC−16 CASE 751B−05 ISSUE K −A− 16 9 1 8 −B− P NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 8 PL 0.25 (0.010) B M S DIM A B C D F G J K M P R G R K F X 45 _ C −T− SEATING PLANE J M D MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 16 PL 0.25 (0.010) M T B S A S SOLDERING FOOTPRINT* 8X 6.40 16X 1 1.12 16 16X 0.58 1.27 PITCH 8 9 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). 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