Holtek HT36M4 Music synthesizer 8-bit mcu Datasheet

HT36M4
Music Synthesizer 8-Bit MCU
Technical Document
· Tools Information
· FAQs
· Application Note
Features
· Operating voltage: 2.6V~5.0V
· Independent pan and volume mix can be assigned to
· Operating frequency:
- Crystal: 8MHz~12MHz
- RC: 11.059MHz
· Sampling rate of 44.1kHz as 11.059MHz for system
· 12 bidirectional I/O lines
· Eight-level subroutine nesting
· Two 16-bit programmable timer/event counters with
· HALT function and wake-up feature reduce power
each sound component
frequency
overflow interrupts
consumption
· Watchdog Timer
· Bit manipulation instructions
· Built-in 8-bit MCU with 384´8 bits RAM
· 16-bit table read instructions
· Built-in 64K´16-bit ROM for program/data shared
· Low voltage reset 2.2V
· Mono 16-bit DAC
· 63 powerful instructions
· One external interrupt
· All instructions in 1 or 2 machine cycles
· Polyphonic up to 16 notes
· 20-pin SOP/TSSOP package
General Description
The HT36M4 has a built-in 8-bit microprocessor with
64K´16 program ROM, 384´8 data RAM, 12
bidirectional I/O, encapsulated in 20 TSSOP for applications where need tinny package such as ring tone generator for CELLULAR/DECT/CORDLESS PHONES.
The HT36M4 is an 8-bit high performance RISC
microcontroller specifically designed for music applications. It provides an 8-bit MCU and a 16 channel
wavetable synthesizer. The program ROM is composed
of both program control codes and wavetable voice
codes, which can easily be programmed.
Block Diagram
P A 0 ~ P A 7
P B 0 ~ P B 3
O S C 1
O S C 2
R E S
IN T
Rev. 1.00
P F 0 ~ 2
8 - B it
M C U
V D
V S
V D
V S
6 4 K ´ 1 6 - b it
R O M
D
S
D A
S A
3 8 4 ´ 8
R A M
M u ltip lie r /P h a s e
G e n e ra l
1
1 6 - B it
D A C
A U D IO
August 15, 2005
HT36M4
Pin Assignment
P B 1
1
2 0
P B 2
P B 1
1
2 0
P B 2
P B 0
2
1 9
P B 0
2
1 9
A U D IO
3
1 8
P B 3
P A 0
A U D IO
3
1 8
P B 3
P A 0
V D D A
4
1 7
P A 1
V D D A
4
1 7
P A 1
V S S /V S S A
5
1 6
V S S /V S S A
5
1 6
O S C 2
6
1 5
P A 2
P A 3
O S C 2
6
1 5
P A 2
P A 3
O S C 1
V D D
7
1 4
P A 4
7
1 4
P A 4
8
1 3
P A 5
O S C 1
V D D
8
1 3
P A 5
IN T
9
1 2
P A 6
IN T
9
1 2
P A 6
R E S
1 0
1 1
P A 7
R E S
1 0
1 1
P A 7
H T 3 6 M 4
2 0 S O P -A
H T 3 6 M 4
2 0 T S S O P -A
Pad Assignment
P B 3
2 1 2 0
V D D A
P B 2
1
P B 1
P B 0
A U D IO
1 9
1 8
2
3
V S S A
(0 ,0 )
V S S
1 7
P A 0
4
O S C 2
5
O S C 1
6
V D D
7
8
9
1 0
1 1
1 6
P A 1
1 5
P A 2
1 4
P A 3
1 3
P A 4
1 2
P A 5
P A 6
R E S
P A 7
IN T
Chip size: 2595´2815 (mm)2
* The IC substrate should be connected to VSS in the PCB layout artwork.
Rev. 1.00
2
August 15, 2005
HT36M4
Pad Coordinates
Unit: mm
Pad No.
X
Y
Pad No.
X
Y
1
2
3
4
5
6
7
8
9
10
11
-1108.950
-1076.600
-1076.600
-1146.750
-1146.750
-1146.750
-1146.750
-292.374
-187.326
-85.550
25.050
1261.050
1135.900
1030.900
-460.600
-1044.234
-1147.786
-1260.200
-1256.550
-1256.550
-1256.550
-1256.550
12
13
14
15
16
17
18
19
20
21
1146.750
1146.750
1146.750
1146.750
1146.750
1146.750
-153.300
-253.300
-363.900
-463.900
-1250.000
-1139.400
-1039.400
-928.800
-828.800
-286.200
1256.550
1256.550
1256.550
1256.550
Pad Description
Pad No.
Pad Name
I/O
Internal
Connection
Function
1
AUDIO
O
¾
Audio output
2, 3
VDDA, VSSA
¾
¾
DAC power supply
7, 4
VDD, VSS
¾
¾
Digital power supply, ground
O
¾
XOUT or 1/4 system frequency in R mode
5
OSC2
6
OSC1
I
8
INT
I
Pull-High
9
RES
I
¾
17~10
PA7~PA0
I/O
Pull-High
or None
Bidirectional 8-bit Input/Output port, wake-up by mask option
21~18
PB0~PB3
I/O
Pull-High
or None
Bidirectional 8-bit input/output port
X¢tal/Resistor XIN for X¢tal or ROSC in for resistor by mask option
External interrupt
Reset input, active low
Absolute Maximum Ratings
Supply Voltage ..........................VSS-0.3V to VSS+5.5V
Storage Temperature ...........................-50°C to 125°C
Input Voltage .............................VSS-0.3V to VDD+0.3V
Operating Temperature ..........................-25°C to 70°C
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those
listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
Rev. 1.00
3
August 15, 2005
HT36M4
D.C. Characteristics
Symbol
Parameter
Ta=25°C
Test Conditions
VDD
Conditions
¾
Min.
Typ.
Max.
Unit
2.6
3.6
5
V
¾
8
10
mA
VDD
Operating Voltage
¾
IDD
Operating Current
3.6V
ISTB
Standby Current
3.6V
¾
¾
1
3
mA
IOH
I/O Ports Source Current
3.6V
¾
2
¾
¾
mA
IOL
I/O Ports Sink Current
3.6V
¾
3
¾
¾
mA
VIH
Input High Voltage
¾
¾
0.8VDD
¾
VDD
V
VIL
Input Low Voltage
¾
¾
0
¾
0.2VDD
V
No load (OSC on)
A.C. Characteristics
Symbol
Parameter
Ta=25°C
Test Conditions
Conditions
VDD
Min.
Typ.
Max.
Unit
¾
11.059
¾
MHz
fOSC
System Frequency
5V
fSYS
System Clock
5V
¾
4
¾
16
MHz
tWDT
Watchdog Time-Out Period (RC)
¾
Without WDT prescaler
9
17
35
ms
tRES
External Reset Low Pulse Width
¾
¾
1
¾
¾
ms
Rev. 1.00
11.059MHz crystal
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August 15, 2005
HT36M4
Functional Description
Execution Flow
subroutine, the PC manipulates the program transfer by
loading the address corresponding to each instruction.
The system clock for the HT36M4 is derived from either
a crystal or an RC oscillator. The oscillator frequency divided by 2 is the system clock for the MCU and it is internally divided into four non-overlapping clocks. One
instruction cycle consists of four system clock cycles.
The conditional skip is activated by instruction. Once the
condition is met, the next instruction, fetched during the
current instruction execution, is discarded and a dummy
cycle replaces it to retrieve the proper instruction. Otherwise proceed with the next instruction.
Instruction fetching and execution are pipelined in such
a way that a fetch takes one instruction cycle while decoding and execution takes the next instruction cycle.
However, the pipelining scheme causes each instruction to effectively execute in one cycle. If an instruction
changes the program counter, two cycles are required
to complete the instruction.
The lower byte of the program counter (PCL) is a readable and writeable register (06H). Moving data into the
PCL performs a short jump. The destination will be
within 256 locations.
Once a control transfer takes place, an additional
dummy cycle is required.
Program Counter - PC
Program ROM
The 13-bit program counter (PC) controls the sequence
in which the instructions stored in program ROM are executed and its contents specify a maximum of 8192 addresses for each bank.
HT36M4 provides 17 address lines WA16~WA0 to read
the Program ROM which is up to 1M bits, and is commonly used for the wavetable voice codes and the program memory. It provides two address types, one type is
for program ROM, which is addressed by a bank pointer
PF2~PF0 and a 13-bit program counter PC12~PC0;
and the other type is for wavetable code, which is addressed by the start address ST15~ST0. On the program type, WA16~WA0= PF2~PF0´213+PC12~PC0.
O n t h e w a ve t a b l e R O M t yp e , WA 1 6 ~WA 0 =
ST15~ST0´25.
After accessing a program memory word to fetch an instruction code, the contents of the program counter are
incremented by one. The program counter then points
to the memory word containing the next instruction
code.
When executing a jump instruction, conditional skip execution, loading PCL register, subroutine call, initial reset, internal interrupt, external interrupt or return from
S y s te m C lo c k o f M C U
( S y s te m C lo c k /2 )
T 1
T 2
T 3
T 4
T 1
T 2
P C
P C
T 3
T 4
T 1
T 2
P C + 1
F e tc h IN S T (P C )
E x e c u te IN S T (P C -1 )
T 3
T 4
P C + 2
F e tc h IN S T (P C + 1 )
E x e c u te IN S T (P C )
F e tc h IN S T (P C + 2 )
E x e c u te IN S T (P C + 1 )
Execution Flow
Mode
Program Counter
*12
*11
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
Initial Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
Timer/Event Counter 0 Overflow
0
0
0
0
0
0
0
0
0
1
0
0
0
Timer/Event Counter 1 Overflow
0
0
0
0
0
0
0
0
0
1
1
0
0
Loading PCL
*12
*11
*10
*9
*8
@7
@6
@5
@4
@3
@2
@1
@0
Jump, Call Branch
#12
#11
#10
#9
#8
#7
#6
#5
#4
#3
#2
#1
#0
Return From Subroutine
S12
S11
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
Skip
Program Counter+2
Program Counter
Note:
*12~*0: Bits of Program Counter
S12~S0: Bits of Stack Register
@7~@0: Bits of PCL
@7~@0: Bits of PCL
#12~#0: Bits of Instruction Code
Rev. 1.00
5
August 15, 2005
HT36M4
Program Memory - ROM
0 0 0 0 H
The program memory is used to store the program instructions which are to be executed. It also contains
data, table, and interrupt entries, and is organized into
8192´16 bits, addressed by the bank pointer, program
counter and table pointer.
0 0 0 4 H
0 0 0 8 H
0 0 0 C H
Certain locations in the program memory of each bank
are reserved for special usage:
n 0 0 H
· Location 000H on bank0
n F F H
D e v ic e in itia liz a tio n p r o g r a m
E x te r n a l in te r r u p t s u b r o u tin e
T im e r /e v e n t C o u n te r 0 in te r r u p t s u b r o u tin e
T im e r /e v e n t C o u n te r 1 in te r r u p t s u b r o u tin e
P ro g ra m
R O M
L o o k - u p ta b le ( 2 5 6 w o r d s )
This area is reserved for the initialization program. After chip reset, the program always begins execution at
location 000H on bank0.
1 6 b its
This area is reserved for the external interrupt service
program. If the INT input pin is activated, the interrupt
is enabled and the stack is not full, the program will
jump to location 004H and begins execution.
N o te : n ra n g e s fro m
0 0 to 1 F .
Program Memory for Each Bank
be placed in the TBLP. The TBLH is read only and
cannot be restored. If the main routine and the ISR
(Interrupt Service Routine) both employ the table read
instruction, the contents of the TBLH in the main routine are likely to be changed by the table read instruction used in the ISR. Errors can occur. In this case,
using the table read instruction in the main routine and
the ISR simultaneously should be avoided. However,
if the table read instruction has to be applied in both
the main routine and the ISR, the interrupt should be
disabled prior to the table read instruction. It will not be
enabled until the TBLH has been backed up. All table
related instructions need 2 cycles to complete the operation. These areas may function as normal program
memory depending upon user requirements.
· Location 008H
This area is reserved for the Timer/Event Counter 0 interrupt service program on each bank. If timer interrupt
results from a Timer/Event Counter 0 overflow, and if the
interrupt is enabled and the stack is not full, the program
begins execution at location 008H corresponding to its
bank.
· Location 00CH
This area is reserved for the Timer/Event Counter 1
interrupt service program on each bank. If a timer interrupt results from a Timer/Event Counter 1 overflow,
and if the interrupt is enabled and the stack is not full,
the program begins execution at location 00CH corresponding to its bank.
· Bank pointer
· Table location
The program memory is organized into 8 banks and
each bank into 8192´16 of bits program ROM. PF2~
PF0 is used as the bank pointer only when PFC is
configured as output mode. PFC is the control register
for PF and is used to control the input/output configuration. To function as an output, the corresponding bit
of the control register must be ²0². After an instruction
has been executed to write data to the PF register to
select a different bank, note that the new bank will not
be selected immediately. It is not until the following instruction has completed execution that the bank will
be actually selected. It should be note that the PF register has to be cleared before setting to output mode.
Any location in the ROM space can be used as
look-up tables. The instructions ²TABRDC [m]² (the
current page, 1 page=256 words) and ²TABRDL [m]²
(the last page) transfer the contents of the lower-order
byte to the specified data memory, and the
higher-order byte to TBLH (08H). Only the destination
of the lower-order byte in the table is well-defined, the
higher-order byte of the table word are transferred to
the TBLH. The Table Higher-order byte register
(TBLH) is read only. The Table Pointer (TBLP) is a
read/write register (07H), which indicates the table location. Before accessing the table, the location must
Instruction (s)
L o o k - u p ta b le ( 2 5 6 w o r d s )
1 F F F H
· Location 004H
Table Location
*12
*11
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
TABRDC [m]
P12
P11
P10
P9
P8
@7
@6
@5
@4
@3
@2
@1
@0
TABRDL [m]
1
1
1
1
1
@7
@6
@5
@4
@3
@2
@1
@0
Table Location
Note:
*12~*0: Bits of table location
P12~P8: Bits of current Program Counter
@7~@0: Bits of table pointer
Rev. 1.00
6
August 15, 2005
HT36M4
Wavetable ROM
0 0 H
The ST15~ST0 are used to defined the start address of
each sample on the wavetable and read the waveform
data from the location. HT36M4 provides 17 output address lines from WA16~WA0, the ST15~ST0 are used
to locate the major 12 bits i.e. WA16~WA5 and the undefined data from WA4~WA0 are always set to 00000b.
So the start address of each sample have to be located
at a multiple of 32 bytes. Otherwise, the sample will not
be read out correctly because it has a wrong starting
code.
0 1 H
M P 0
0 2 H
In d ir e c t A d d r e s s in g R e g is te r 1
0 3 H
M P 1
In d ir e c t A d d r e s s in g R e g is te r 0
0 4 H
0 5 H
A C C
0 6 H
P C L
0 7 H
T B L P
0 8 H
T B L H
0 9 H
W D T S
0 A H
S T A T U S
0 B H
IN T C
0 C H
T M R 0 H
Stack Register - Stack
0 D H
T M R 0 L
This is a special part of the memory which is used to
save the contents of the program counter only. The
stack is organized into 8 levels and is neither part of the
data nor part of the program space, and is neither readable nor writeable. The activated level is indexed by the
stack pointer (SP) and is neither readable nor writeable.
At a subroutine call or interrupt acknowledgment, the
contents of the program counter are pushed onto the
stack. At the end of a subroutine or an interrupt routine,
signaled by a return instruction (RET or RETI), the program counter is restored to its previous value from the
stack. After a chip reset, the SP will point to the top of the
stack.
0 E H
T M R 0 C
0 F H
T M R 1 H
T M R 1 L
1 1 H
T M R 1 C
1 2 H
P A
1 3 H
P A C
1 4 H
P B
1 5 H
P B C
1 6 H
1 7 H
1 8 H
1 9 H
1 A H
1 B H
1 D H
P F
D A H
1 E H
1 F H
D A C
1 C H
If the stack is full and a non-masked interrupt takes
place, the interrupt request flag will be recorded but the
acknowledgment will be inhibited. When the stack
pointer is decremented (by RET or RETI), the interrupt
will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily.
In a similar case, if the stack is full and a CALL is subsequently executed, a stack overflow occurs and the first
entry will be lost (only the most recent eight return address are stored).
D A L
2 0 H
C h a n n e l n u m b e r s e le c t
2 1 H
F r e q u e n c y n u m b e r h ig h b y te
2 2 H
F r e q u e n c y n u m b e r lo w b y te
2 3 H
S ta r t a d d r e s s h ig h b y te
2 4 H
S ta r t a d d r e s s lo w
b y te
2 5 H
R e p e a t n u m b e r h ig h b y te
2 6 H
R e p e a t n u m b e r lo w
2 7 H
2 8 H
b y te
W a v e ta b le F u n c tio n
R e g is te r
C o n tr o l r e g is te r
2 9 H
Data Memory - RAM
2 A H
2 B H
The data memory is designed with 2´256´8 bits. The
data memory is divided into three functional groups:
special function registers, wavetable function register,
and general purpose data memory (2´192´8). Most of
them are read/write, but some are read only.
R ig h t v o lu m
c o n tro l
2 F H
3 0 H
G e n e ra l P u rp o s e
D A T A M E M O R Y
(2 0 8 B y te s )
The special function registers include the Indirect Addressing register 0 (00H), the Memory Pointer register 0
(MP0;01H), the Indirect Addressing register 1 (02H), the
Memory Pointer register 1 (MP1;03H), the Accumulator
(ACC;05H), the Program Counter Lower-byte register
(PCL;06H), the Table Pointer (TBLP;07H), the Table
Higher-order byte register (TBLH;08H), the Watchdog
Timer option Setting register (WDTS;09H), the Status
register (STATUS;0AH), the Interrupt Control register
(INTC;0BH), the Timer/Event Counter 0 higher-order
byte register (TMR0H;0CH), the Timer/Event Counter 0
lo w e r-o r d e r b y t e r egi s t er ( TM R 0L; 0 D H ) , t h e
Timer/Event Counter 0 control register (TMR0C;0EH),
Rev. 1.00
1 0 H
S p e c ia l P u r p o s e
D A T A M E M O R Y
: U n u s e d .
R e a d a s "0 0 "
F F H
RAM Mapping
the Timer/Event Counter 1 higher-order byte register
(TMR1H;0FH), the Timer/Event Counter 1 Lower-order
byte register (TMR1L;10H), the Timer/Event Counter 1
Control register (TMR1C;11H), the I/O registers
(PA;12H, PB;14H), the program ROM bank select
(PF;1CH) and the I/O Control registers (PAC;13H,
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August 15, 2005
HT36M4
The ALU provides the following functions:
PBC;15H). The wavetable function register is defined
between 20H~2AH. The remaining space before the
30H is reserved for future expanded usage and reading
these locations will return the result 00H. The general
purpose data memory, addressed from 40H to FFH, is
used for data and control information under instruction
command.
· Arithmetic operations (ADD, ADC, SUB, SBC, DAA)
· Logic operations (AND, OR, XOR, CPL)
· Rotation (RL, RR, RLC, RRC)
· Increment & Decrement (INC, DEC)
· Branch decision (SZ, SNZ, SIZ, SDZ, etc.)
The ALU not only saves the results of a data operation but
can also change the status register.
All data memory areas can handle arithmetic, logic, increment, decrement and rotate operations directly. Except for some dedicated bits, each bit in the data
memory can be set and reset by the ²SET [m].i² and
²CLR [m].i² instructions, respectively. They are also indirectly accessible through Memory pointer registers
(MP0;01H, MP1;03H).
Status Register - STATUS
This 8-bit register (0AH) contains the zero flag (Z), carry
flag (C), auxiliary carry flag (AC), overflow flag (OV),
power down flag (PDF) and Watchdog time-out flag
(TO). It also records the status information and controls the
operation sequence.
Indirect Addressing Register
With the exception of the TO and PDF flags, bits in the
status register can be altered by instructions like any
other register. Any data written into the status register
will not change the TO or PDF flags. In addition, it
should be noted that operations related to the status
register may give different results from those intended.
The TO and PDF flags can only be changed by system
power up, Watchdog Timer overflow, executing the
²HALT² instruction and clearing the Watchdog Timer.
Location 00H and 02H are indirect addressing registers
that are not physically implemented. Any read/write operation of [00H] and [02H] access data memory pointed
to by MP0 (01H) and MP1 (03H) respectively. Reading
location 00H or 02H directly will return the result 00H.
And writing directly results in no operation.
The function of data movement between two indirect addressing registers, is not supported. The memory
pointer registers, MP0 and MP1, are 8-bit register which
can be used to access the data memory by combining
corresponding indirect addressing registers.
The Z, OV, AC and C flags generally reflect the status of
the latest operations.
In addition, on entering the interrupt sequence or executing a subroutine call, the status register will not be
automatically pushed onto the stack. If the contents of
status are important and the subroutine can corrupt the
status register, the programmer must take precautions
to save it properly.
Accumulator
The accumulator closely relates to ALU operations. It is
mapped to location 05H of the data memory and it can
operate with immediate data. The data movement between two data memory locations must pass through
the accumulator.
Interrupt
Arithmetic and Logic Unit - ALU
The HT36M4 provides two internal timer/event counter
interrupts on each bank. The Interrupt Control register
This circuit performs 8-bit arithmetic and logic operation.
Bit No.
Label
Function
0
C
C is set if an operation results in a carry during an addition operation or if a borrow does not
take place during a subtraction operation; otherwise C is cleared. Also it is affected by a rotate
through carry instruction.
1
AC
AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from
the high nibble into the low nibble in subtraction; otherwise AC is cleared.
2
Z
Z is set if the result of an arithmetic or logical operation is zero; otherwise Z is cleared.
3
OV
OV is set if an operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit, or vice versa; otherwise OV is cleared.
4
PDF
PDF is cleared by either a system power-up or executing the ²CLR WDT² instruction. PDF is
set by executing the ²HALT² instruction.
5
TO
TO is cleared by a system power-up or executing the ²CLR WDT² or ²HALT² instruction. TO is
set by a WDT time-out.
6~7
¾
Unused bit, read as ²0²
STATUS (0AH) Register
Rev. 1.00
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August 15, 2005
HT36M4
During the execution of an interrupt subroutine, other interrupt acknowledgments are held until the RETI instruction is executed or the EMI bit and the related
interrupt control bit are set to 1 (if the stack is not full). To
return from the interrupt subroutine, the RET or RETI instruction may be invoked. RETI will set the EMI bit to enable an interrupt service, but RET will not.
(INTC;0BH) contains the interrupt control bits that sets
the enable/disable and the interrupt request flags.
Once an interrupt subroutine is serviced, all other interrupts will be blocked (by clearing the EMI bit). This
scheme may prevent any further interrupt nesting. Other
interrupt requests may occur during this interval but only
the interrupt request flag is recorded. If a certain interrupt needs servicing within the service routine, the programmer may set the EMI bit and the corresponding bit
of the INTC to allow interrupt nesting. If the stack is full,
the interrupt request will not be acknowledged, even if
the related interrupt is enabled, until the SP is decremented. If immediate service is desired, the stack must
be prevented from becoming full.
Interrupts occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding interrupts are enabled. In the case of simultaneous requests
the priorities in the following table apply. These can be
masked by resetting the EMI bit.
All these kinds of interrupt have a wake-up capability. As
an interrupt is serviced, a control transfer occurs by
pushing the program counter onto the stack and then
branching to subroutines at specified locations in the
program memory. Only the program counter is pushed
onto the stack. If the contents of the register and Status
register (STATUS) are altered by the interrupt service
program which may corrupt the desired control sequence, then the programmer must save the contents
first.
Interrupt Source
Priority
Vector
Timer/Event Counter 0 overflow
1
08H
Timer/Event Counter 1 overflow
2
0CH
The Timer/Event Counter 0/1 interrupt request flag
(T0F/T1F), Enable Timer/Event Counter 0/1 bit
(ET0I/ET1I), Enable Master Interrupt bit (EMI) constitute
an interrupt control register (INTC) which is located at
0BH in the data memory. EMI, ET0I, ET1I are used to
control the enabling/disabling of interrupts. These bits
prevent the requested interrupt from being serviced.
Once the interrupt request flags (T0F, T1F) are set, they
will remain in the INTC register until the interrupts are
serviced or cleared by a software instruction.
The internal Timer/Event Counter 0 interrupt is initialized by setting the Timer/Event Counter 0 interrupt request flag (T0F; bit 5 of the INTC), caused by a
Timer/Event Counter 0 overflow. When the interrupt is
enabled, and the stack is not full and the T0F bit is set, a
subroutine call to location 08H will occur. The related interrupt request flag (T0F) will be reset and the EMI bit
cleared to disable further interrupts.
It is recommended that a program does not use the
²CALL subroutine² within the interrupt subroutine. Because interrupts often occur in an unpredictable manner
or need to be serviced immediately in some applications, if only one stack is left and enabling the interrupt is
not well controlled, once the ²CALL subroutine² operates
in the interrupt subroutine, it may damage the original
control sequence.
The Timer/Event Counter 1 interrupt is operated in the
same manner as Timer/Event Counter 0. The related interrupt control bits ET1I and T1F of the Timer/Event
Counter 1 are bit 3 and bit 6 of the INTC respectively.
Bit No.
Label
Function
0
EMI
1
¾
2
ET0I
Controls the Timer/Event Counter 0 interrupt
(1=enable; 0=disable)
3
ET1I
Controls the Timer/Event Counter 1 interrupt
(1=enable; 0=disable)
4
¾
5
T0F
Internal Timer/Event Counter 0 request flag
(1=active; 0=inactive)
6
T1F
Internal Timer/Event Counter 1 request flag
(1=active; 0=inactive)
7
¾
Controls the Master (Global) interrupt
(1=enable; 0=disable)
Unused bit, read as ²0²
Unused bit, read as ²0²
Unused bit, read as ²0²
INTC (0BH) Register
Rev. 1.00
9
August 15, 2005
HT36M4
Oscillator Configuration
O S C 1
The HT36M4 provides two types of oscillator circuit for
the system clock, i.e., RC oscillator and crystal oscillator. No matter what type of oscillator, the signal divided
by 2 is used for the system clock. The HALT mode stops
the system oscillator and ignores external signal to conserve power. If the RC oscillator is used, an external resistor between OSC1 and VSS is required, and the
range of the resistance should be from 30kW to 680kW.
The system clock, divided by 4, is available on OSC2
with pull-high resistor, which can be used to synchronize
external logic. The RC oscillator provides the most cost
effective solution. However, the frequency of the oscillation may vary with VDD, temperature, and the chip itself
due to process variations. It is therefore, not suitable for
timing sensitive operations where accurate oscillator
frequency is desired.
V
fS
O S C 2
Y S
O S C 1
D D
/8
O S C 2
C r y s ta l O s c illa to r
R C
O s c illa to r
System Oscillator
temperature, VDD and process variations. By invoking
the WDT prescaler, longer time-out periods can be realized. Writing data to WS2, WS1, WS0 (bits 2, 1, 0 of the
WDTS) can give different time-out periods. If WS2,
WS1, WS0 all equal to 1, the division ratio is up to 1:128,
and the maximum time-out period is 2.6 seconds.
If the WDT oscillator is disabled, the WDT clock may still
come from the instruction clock and operate in the same
manner except that in the HALT state the WDT may stop
counting and lose its protecting purpose. In this situation
the logic can only be restarted by external logic. The
high nibble and bit 3 of the WDTS are reserved for user
defined flags, and the programmer may use these flags
to indicate some specified status.
On the other hand, if the crystal oscillator is selected, a
crystal across OSC1 and OSC2 is needed to provide the
feedback and phase shift required for the oscillator, and
no other external components are required. A resonator
may be connected between OSC1 and OSC2 to replace
the crystal and to get a frequency reference, but two external capacitors in OSC1 and OSC2 are required.
The WDT oscillator is a free running on-chip RC oscillator, and no external components are required. Even if
the system enters the power down mode, the system
clock is stopped, but the WDT oscillator still works with a
period of approximately 78ms. The WDT oscillator can
be disabled by mask option to conserve power.
WS2
WS1
WS0
Division Ratio
0
0
0
1:1
0
0
1
1:2
0
1
0
1:4
0
1
1
1:8
1
0
0
1:16
1
0
1
1:32
Watchdog Timer - WDT
1
1
0
1:64
The WDT clock source is implemented by a dedicated
RC oscillator (WDT oscillator) or instruction clock (system clock of the MCU divided by 4), determined by mask
options. This timer is designed to prevent a software
malfunction or sequence jumping to an unknown location with unpredictable results. The Watchdog Timer can
be disabled by mask option. If the Watchdog Timer is
disabled, all executions related to the WDT result in no
operation.
1
1
1
1:128
If the device operates in a noisy environment, using the
on-chip RC oscillator (WDT OSC) is strongly recommended, since the HALT will stop the system clock.
The WDT overflow under normal operation will initialize
a ²chip reset² and set the status bit TO. Whereas in the
HALT mode, the overflow will initialize a ²warm reset²
only the Program Counter and SP are reset to zero. To
clear the WDT contents (including the WDT prescaler ),
three methods are implemented; external reset (a low
level to RES), software instructions, or a HALT instruction. The software instructions include ²CLR WDT² and
Once the internal WDT oscillator (RC oscillator with a
period of 78ms normally) is selected, it is first divided by
256 (8-stages) to get the nominal time-out period of approximately 20ms. This time-out period may vary with
S y s te m
C lo c k /8
W D T
O S C
M a s k
O p tio n
S e le c t
W D T P r e s c a le r
8 - b it C o u n te r
7 - b it C o u n te r
8 -to -1 M U X
W S 0 ~ W S 2
W D T T im e - o u t
Watchdog Timer
Rev. 1.00
10
August 15, 2005
HT36M4
the other set - ²CLR WDT1² and ²CLR WDT2². Of these
two types of instructions, only one can be active depending on the mask option - ²CLR WDT times selection option². If the ²CLR WDT² is selected (i.e. CLRWDT
times equal one), any execution of the ²CLR WDT² instruction will clear the WDT. In case ²CLR WDT1² and
²CLR WDT2² are chosen (i.e. CLRWDT times equal
two), these two instructions must be executed to clear
the WDT; otherwise, the WDT may reset the chip due to
time-out.
instruction execution, this will be executed immediately
after a dummy period has finished. If an interrupt request flag is set to ²1² before entering the HALT mode,
the wake-up function of the related interrupt will be disabled.
To minimize power consumption, all I/O pins should be
carefully managed before entering the HALT status.
Reset
There are three ways in which a reset can occur:
· RES reset during normal operation
Power Down Operation - HALT
· RES reset during HALT
The HALT mode is initialized by a HALT instruction and
results in the following:
· WDT time-out reset during normal operation
The WDT time-out during HALT is different from other
chip reset conditions, since it can perform a ²warm re set² that resets the Program Counter and SP, leaving
the other circuits in their original state. Some registers
remain unchanged during other reset conditions. Most
registers are reset to the ²initial condition² when the reset conditions are met. By examining the PDF and TO
flags, the program can distinguish between different
²chip resets².
· The system oscillator will turn off but the WDT oscilla-
tor keeps running (if the WDT oscillator is selected).
Watchdog Timer - WDT
· The contents of the on-chip RAM and registers remain
unchanged.
· The WDT and WDT prescaler will be cleared and
starts to count again (if the clock comes from the WDT
oscillator).
· All I/O ports maintain their original status.
· The PDF flag is set and the TO flag is cleared.
V D D
· The HALT pin will output a high level signal to disable
R E S
the external ROM.
The system can leave the HALT mode by means of an
external reset, an interrupt, an external falling edge signal on port A or a WDT overflow. An external reset
causes a device initialization and the WDT overflow performs a ²warm reset². By examining the TO and PDF
flags, the cause for a chip reset can be determined. The
PDF flag is cleared when there is a system power-up or by
executing the ²CLR WDT² instruction and it is set when a
HALT instruction is executed. The TO flag is set if a WDT
time-out occurs, and causes a wake-up that only resets
the Program Counter and SP, the others remain in their
original status.
S T
C h ip R e s e t
Reset Timing Chart
V
D D
R E S
The port A wake-up and interrupt methods can be considered as a continuation of normal execution. Each bit
in port A can be independently selected to wake-up the
device by mask option. Awakening from an I/O port stimulus, the program will resume execution of the next instruction. If awakening from an interrupt, two sequences
may occur. If the related interrupts is disabled or the interrupts is enabled but the stack is full, the program will
resume execution at the next instruction. If the interrupt
is enabled and the stack is not full, a regular interrupt response takes place.
Reset Circuit
H A L T
W D T
W D T
W a rm
R e s e t
T im e - o u t
R e s e t
R E S
O S C I
Once a wake-up event occurs, it takes 1024 tSYS (system clock period) to resume to normal operation. In
other words, a dummy cycle period will be inserted after
a wake-up. If the wake-up results from an interrupt acknowledge, the actual interrupt subroutine will be delayed by one more cycle. If the wake-up results in next
Rev. 1.00
tS
S S T T im e - o u t
S S T
1 0 -s ta g e
R ip p le C o u n te r
C o ld
R e s e t
P o w e r - o n D e te c tin g
Reset Configuration
11
August 15, 2005
HT36M4
The registers¢ status is summarized in the following table:
Register
Reset
(Power On)
WDT Time-out
(Normal Operation)
RES Reset
(Normal Operation)
RES Reset
(HALT)
WDT Time-out
(HALT)*
Program Counter
0000H
0000H
0000H
0000H
0000H
MP0
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
MP1
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
ACC
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLP
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLH
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
WDTS
0000 0111
0000 0111
0000 0111
0000 0111
uuuu uuuu
STATUS
--00 xxxx
--1u uuuu
--uu uuuu
--01 uuuu
--11 uuuu
INTC
-000 0000
-000 0000
-000 0000
-000 0000
-uuu uuuu
TMR0H
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TMR0L
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TMR0C
00-0 1000
00-0 1000
00-0 1000
00-0 1000
uu-u 1uuu
TMR1H
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TMR1L
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TMR1C
00-0 1000
00-0 1000
00-0 1000
00-0 1000
uu-u 1uuu
PA
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PAC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PB
---- 1111
---- 1111
---- 1111
---- 1111
---- uuuu
PBC
---- 1111
---- 1111
---- 1111
---- 1111
---- uuuu
PF
---- -111
---- -111
---- -111
---- -111
---- -uuu
CHAN
00-- 0000
uu-- uuuu
uu-- uuuu
uu-- uuuu
uu-- uuuu
FreqNH
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
FreqNL
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
AddrH
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
AddrL
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
ReH
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
ReL
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
ENV
x-xx xxxx
u-uu uuuu
u-uu uuuu
u-uu uuuu
u-uu uuuu
RVC
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
DAH
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
DAL
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
DAC
---- --00
---- --uu
---- --00
---- --00
---- --uu
Note:
²*² stands for warm reset
²u² stands for unchanged
²x² stands for unknown
Rev. 1.00
12
August 15, 2005
HT36M4
TO
Writing TMR0L only writes the data into a low byte
buffer, and writing TMR0H will write the data and the
contents of the low byte buffer into the Timer/Event
Counter 0 preload register (16-bit) simultaneously. The
Timer/Event Counter 0 Preload register is changed by
writing TMR0H operations and writing TMR0L will keep
the Timer/Event Counter 0 Preload register unchanged.
RESET Conditions
0
0
RES reset during power-up
u
u
RES reset during normal operation
0
1
RES wake-up HALT
1
u
WDT time-out during normal operation
1
1
WDT wake-up HALT
Reading TMR0H will also latch the TMR0L into the low
byte buffer to avoid a false timing problem. Reading
TMR0L returns the contents of the low byte buffer. In
other words, the low byte of the Timer/Event Counter 0
cannot be read directly. It must read the TMR0H first to
make the low byte contents of the Timer/Event Counter
0 latched into the buffer.
Note: ²u² stands for ²unchanged²
To guarantee that the system oscillator has started and
stabilized, the SST (System Start-up Timer) provides an
extra-delay of 1024 system clock pulses during system
power up or when the system awakes from a HALT
state.
There are three registers related to the Timer/Event
Counter 1; TMR1H (0FH), TMR1L (10H), TMR1C (11H).
The Timer/Event Counter 1 operates in the same manner as Timer/Event Counter 0.
When a system power-up occurs, the SST delay is
added during the reset period. But when the reset comes from the RES pin, the SST delay is disabled. Any
wake-up from HALT will enable the SST delay.
The TMR0C is the Timer/Event Counter 0 control register, which defines the Timer/Event Counter 0 options.
The Timer/Event Counter 1 has the same options with
Timer/Event Counter 0 and is defined by TMR1C.
The functional units chip reset status are shown below.
Program Counter
000H
Interrupt
Disable
Prescaler
Clear
WDT
Clear. After master reset,
WDT begins counting
The Timer/Event Counter control registers define the
operating mode, counting enable or disable and active
edge.
The TM0, TM1 bits define the operating mode. The
Event count mode is used to count external events,
which means the clock source comes from an external
(TMR) pin. The Timer mode functions as a normal timer
with the clock source coming from the instruction clock.
The pulse width measurement mode can be used to
count the high or low level duration of the external signal
(TMR). The counting is based on the instruction clock.
Timer/Event Counter (0/1) Off
Input/output ports
Input mode
Stack Pointer
Points to the top of the
stack
Timer/Event Counter
Two timer/event counters are implemented in the
HT36M4. The Timer/Event Counter 0 and Timer/Event
Counter 1 contain 16-bit programmable count-up counters and the clock comes from the system clock divided
by 4.
In the Event count or Timer mode, once the timer/event
counter starts counting, it will count from the current
contents in the timer/event counter to FFFFH. Once
overflow occurs, the counter is reloaded from the
Timer/Event Counter Preload register and simultaneously generates the corresponding interrupt request
flag (T0F/T1F; bit 5/6 of INTC).
There are three registers related to Timer/Event Counter 0; TMR0H (0CH), TMR0L (0DH), TMR0C (0EH).
Bit No.
Label
Function
0~2
¾
Unused bit, read as ²0²
3
TE
Defines the TMR active edge of the Timer/Event Counter 0
(0=active on low to high; 1=active on high to low)
4
TON
5
¾
6
7
TM0
TM1
Enable/disable timer counting (0=disable; 1=enable)
Unused bit, read as ²0²
Defines the operating mode
01=Event count mode (External clock)
10=Timer mode (Internal clock)
11=Pulse width measurement mode
00=Unused
TMR0C/TMR1C (0EH/11H) Register
Rev. 1.00
13
August 15, 2005
HT36M4
Input/Output Ports
In pulse width measurement mode with the TON and TE
bits equal to one, once the TMR has received a transient
from low to high (or high to low; if the TE bit is 0) it will
start counting until the TMR returns to the original level
and resets the TON. The measured result will remain in
the timer/event counter even if the activated transient
occurs again. In other words, only one cycle measurements can be done. Until setting the TON, the cycle
measurement will function again as long as it receives
further transient pulse. Note that, in this operating
mode, the timer/event counter starts counting not according to the logic level but according to the transient
edges. In the case of counter overflow, the counter is reloaded from the timer/event counter preload register
and issues the interrupt request just like the other two
modes.
There are 12 bidirectional input/output lines labeled
from PA, which are mapped to the data memory of
[12H], [14H] respectively. All these I/O ports can be
used for input and output operations. For input operation, these ports are non-latching, that is, the inputs
must be ready at the T2 rising edge of instruction ²MOV
A,[m]² (m=12H, 14H). For output operation, all data is
latched and remains unchanged until the output latch is
rewritten.
Each I/O line has its own control register (PAC, PBC) to
control the input/output configuration. With this control
register, CMOS output or Schmitt Trigger input with or
without pull-high resistor (mask option) structures can
be reconfigured dynamically under software control. To
function as an input, the corresponding latch of the control register must write a ²1². The pull-high resistance
will exhibit automatically if the pull-high option is selected. The input source also depends on the control
register. If the control register bit is ²1², input will read
the pad state. If the control register bit is ²0², the contents of the latches will move to the internal bus. The latter
is possible in ²read-modify-write² instruction. For output
function, CMOS is the only configuration. These control
registers are mapped to locations 13H and 15H).
To enable the counting operation, the Timer ON bit
(TON; bit 4 of the TMR0C/TMR1C) should be set to 1. In
the pulse width measurement mode, the TON will be
cleared automatically after the measurement cycle is
completed. But in the other two modes the TON can only
be reset by instruction. The overflow of the timer/event
counter is one of the wake-up sources. No matter what
the operation mode is, writing a 0 to ET0I/ET1I can disable the corresponding interrupt service.
In the case of timer/event counter OFF condition, writing
data to the Timer/event counter preload register will also
reload that data to the timer/event counter. But if the
timer/event counter is turned on, data written to the
timer/event counter will only be kept in the timer/event
counter preload register. The timer/event counter will
still operate until overflow occurs.
After a chip reset, these input/output lines remain at high
levels or floating (mask option). Each bit of these input/output latches can be set or cleared by the ²SET
[m].i² or ²CLR [m].i² (m=12H or 14H) instruction.
Some instructions first input data and then follow the
output operations. For example, the ²SET [m].i², ²CLR
[m].i², ²CPL [m]² and ²CPLA [m]² instructions read the
entire port states into the CPU, execute the defined operations (bit-operation), and then write the results back
to the latches or the accumulator.
When the timer/event counter (reading TMR0H/
TMR1H) is read, the clock will be blocked to avoid errors. As this may result in a counting error, this must
be taken into consideration by the programmer.
The two timer counters of the HT36M4 are internal clock
mode only, so only Timer mode can be selected. Therefore the (TM1, TM0) bits can only be set to (TM1,TM0) =
(1,0), and the other clock modes are invalid.
S y s te m
C lo c k /8
G N D
Each line of port A has the capability to wake-up the device.
D a ta B u s
T M 1
T M 0
T im e r /e v e n t C o u n te r 0
P r e lo a d R e g is te r
R e lo a d
T E
T M 1
T M 0
T O N
T im e r /e v e n t
C o u n te r 0
P u ls e W id th
M e a s u re m e n t
M o d e C o n tro l
O v e r flo w
T o In te rru p t
L o w B y te
B u ffe r
Timer/Event Counter 0/1
Rev. 1.00
14
August 15, 2005
HT36M4
D a ta B u s
W r ite C o n tr o l R e g is te r
V
Q
D
C K
Q
S
V
W e a k
P u ll- u p
D D
C h ip R e s e t
M a s k O p tio n
R e a d C o n tr o l R e g is te r
D
W r ite I/O
P A
P B
P C
P D
Q
C K
S
Q
M
R e a d I/O
S y s te m
D D
U
0 ~
0 ~
0 ~
0 ~
P A
P B
P C
P D
7
7
3
7
X
W a k e - U p ( P A o n ly )
M a s k O p tio n
Input/Output Ports
16 Channel Wavetable Synthesizer
Register
Name
Register Function
B7
B6
B5
B4
B3
B2
B1
B0
1DH
DAC High Byte (No Default Value)
DA15 DA14 DA13 DA12 DA11 DA10
DA9
DA8
1EH
DAC Low Byte (No Default Value)
DA7
DA6
DA5
DA4
DA3
DA2
DA1
DA0
1FH
DAON=1: DAC ON
DANO=0: DAC OFF (Default)
SELW=1: DAC Data from Wavetable
SELW=0: DAC Data from MCU (Default)
¾
¾
¾
¾
¾
¾
DAON
SELW
¾
Right
20H
Channel Number Select
VM
FR
¾
¾
CH3
CH2
CH1
CH0
21H
High Byte Frequency Number
BL3
BL2
BL1
BL0 FR11 FR10
FR9
FR8
22H
Low Byte Frequency Number
FR7
FR6
FR5
FR4
FR2
FR1
FR0
23H
High Byte Start Address Selection
ST15 ST14 ST13 ST12 ST11 ST10
ST9
ST8
24H
Low Byte Start Address Selection
ST7
ST1
ST0
25H
Waveform Bit Selection
High Byte Repeat Number Selection
WBS RE14 RE13 RE12 RE11 RE10
RE9
RE8
26H
Low Byte Repeat Number Selection
RE7
RE6
RE5
RE4
RE3
RE2
RE1
RE0
27H
Envelope Control Selection
Left/Right Volume Control
A_R
¾
¾
¾
¾
¾
VR9
VR8
VR5
VR4
VR3
VR2
VR1
VR0
28H
ST5
ST4
ST3
ST2
¾
29H
2AH
ST6
FR3
Right Volume Controller
VR7
¾
2B~2FH
30H~1FFH Data Memory (RAM)
VR6
General Purpose Data Memory (Same As 8-bit MCU)
Wavetable Function Register Table
Note:
If the DAC circuit is not enabled, any DAH/DAL output is invalid. Writing a ²1² to DAC bit is to enable DAC circuit and writing a ²0² to DAC bit is to disable the DAC circuit.
Rev. 1.00
15
August 15, 2005
HT36M4
· CH3~CH0 channel number selection
· Waveform format definition
The HT36M4 has a built-in 16 output channels and
CH3~CH0 is used to define which channel is selected.
When this register is written to, the wavetable synthesizer will automatically output the dedicated PCM
code. So this register is also used as a start playing
key and it has to be written to after all the other
wavetable function registers are already defined.
The HT36M4 accepts two waveform formats to ensure a more economical data space. WBS is used to
define the sample format of each PCM code.
These two bits, VM and FR, are used to define which
register will be updated on this selected channel.
There are two modes that can be selected to reduce
the process of setting the register. Please refer to the
statements of the following table:
FR
0
0
Update all the parameter
0
1
Only update the frequency number
1
0
Only update the volume
WBS=1 means the sample format is 12-bit
8 - B it
1 B
2 B
3 B
4 B
5 B
6 B
7 B
8 B
A s a m p lin g d a ta c o d e ; B m e a n s o n e d a ta b y te .
1 2 - B it
Function
1 H
1 M
1 L
2 L
2 H
2 M
3 H
3 M
3 L
A s a m p lin g d a ta c o d e
N o te : " 1 H " H ig h N ib b le
" 1 M " M id d le N ib b le
" 1 L " L o w N ib b le
Waveform Format
· Output frequency definition
The data on BL3~BL0 and FR11~FR0 are used to define the output speed of the PCM file, i.e. it can be
used to generate the tone scale. When the FR11~FR0
is 800H and BL3~BL0 is 6H, each sample data of the
PCM code will be sent out sequentially.
When the fOSC is 12.8MHz, the formula of a tone frequency is:
50kHz FR11 ~ FR0
fOUT= fRECORDx
x (17 - BL3~BL0)
SR
2
where fOUT is the output signal frequency, fRECORD and
SR is the frequency and sampling rate on the sample
code, respectively.
So if a voice code of C3 has been recorded which has
the fRECORD of 261Hz and the SR of 11025Hz, the tone
frequency (fOUT) of G3: fOUT=196Hz.
Can be obtained by using the formula:
50kHz
FR11 ~ FR0]
196Hz= 261Hz x
x
11025Hz 2 (17 - BL3~BL0)
A pair of the values FR11~FR0 and BL3~BL0 can be
determined when the fOSC is 12.8MHz.
· Repeat number definition
The repeat number is used to define the address
which is the repeat point of the sample. When the repeat number is defined, it will be output from the start
code to the end code once and always output the
range between the repeat address to the end code
(80H) until the volume becomes close.
The RE14~RE0 is used to calculate the repeat address of the PCM code. The process for setting the
RE14~RE0 is to write the 2¢s complement of the repeat length to RE14~RE0, with the highest carry ignored. The HT36M4 will get the repeat address by
adding the RE14~RE0 to the address of the end code,
then jump to the address to repeat this range.
· Left and right volume control
The HT36M4 provides the left and right volume control independently. The left and right volume are controlled by VL9~VL0 and VR9~VR0 respectively. The
chip provides 1024 levels of controllable volume, the
000H is the maximum and 3FFH is the minimum output volume.
· Start address definition
The HT36M4 provides two address types for extended use, one is the program ROM address which is
program counter corresponding with PF value, the
other is the start address of the PCM code.
The ST15~ST0 is used to define the start address of
each PCM code and reads the waveform data from
this location. The HT36M4 provides 16 input data
lines from WA15~WA0, the ST15~ST0 is used to locate the major 16 bits i.e. WA15~WA5 and the undefined data from WA4~WA0 is always set as 00000b. In
other words, the WA15~WA0=ST15~ST0´25. So
each PCM code has to be located at a multiple of 32.
Otherwise, the PCM code will not be read out correctly
because it has a wrong start code.
Rev. 1.00
WBS=0 means the sample format is 8-bit
¨
The 12-bit sample format allocates location to each
sample data. Please refer to the waveform format
statement as shown below.
· Change parameter selection
VM
¨
· Envelope type definition
The HT36M4 provides a function to easily program
the envelope by setting the data of ENV1~ENV0 and
A_R. It forms a vibrato effect by a change of the
volume to attach and release alternately.
The A_R signal is used to define the volume change in
attach mode or release mode and ENV1~ENV0 is
used to define which volume control bit will be
changeable. On the attach mode, the control bits will
be sequentially signaled down to 0. On the release
mode, the control bits will be sequentially signaled up
to 1. The relationship is shown in the following table.
16
August 15, 2005
HT36M4
A_R
ENV1
ENV0
Volume Control Bit
Control Bit Final Value
0
0
0
VL2~VL0, VR2~VR0
111b
0
0
1
VL1~VL0, VR1~VR0
11b
0
1
0
VL0, VR0
1b
x
1
1
No Bit
Unchanged
1
0
0
VL2~VL0, VR2~VR0
000b
1
0
1
VL1~VL0, VR1~VR0
00b
1
1
0
VL0, VR0
0b
Mode
Release mode
No change mode
Attach mode
Envelope Type Definition
· The PCM code definition
The HT36M4 can only solve the voice format of the signed 8-bit raw PCM. And the MCU will take the voice code 80H
as the end code.
So each PCM code section must be ended with the end code 80H.
Digital to Analog Converter (DAC)
The HT36M4 provides one 16-bit voltage type DAC device controlled by the MCU or wavetable synthesizer for driving
an external speaker through an external NPN transistor. It is in fact an optional object used for Wavetable Synthesizer
DAC or general DAC, this is chosen by DAC control register. If general DAC is chosen for application, then Wavetable
synthesizer is disabled because the DAC is taken up and controlled by the MCU. If general DAC is selected, the programmer must write the voice data to register DAL and DAH to get the corresponding analog data. If Mask Option enables the DAC register and enables the SELW, then the following table comes useful.
Bit No.
Label
Function
Bit7~Bit3
¾
Unused
Bit2
¾
Unused
Bit1
DANO
Bit0
SELWR
DAON=1: DAC ON
DAON=0: DAC OFF (Default)
SELWR=1: Right Channel DAC data from Wavetable
SELWR=0: Right Channel DAC data from MCU (default)
DAC (1FH) Control Regulation
Mask Option
No
Mask Option
Description
1
WDT Source
On-chip RC/instruction clock/disable WDT
2
CLRWDT Times
One time, two times (CLR WDT1/WDT2)
3
Wake-up
PA only
4
Pull-high
PA, PB0~PB3 input
5
OSC Mode
Crystal or resistor type
6
LVR
Enable or disable
Rev. 1.00
17
August 15, 2005
HT36M4
Application Circuit
V
D D
1 0 W
V D D
4 7 m F
V D D A
0 .1 m F
O S C 1
1 1 .0 5 9 M H z
V
O S C 2
V
D D
IN T
D D
4 7 m F
A U D IO
1 0 0 k W
0 .1 m F
2 0 k W
2
R E S
V S S A
0 .1 m F
V re f
3
1 0 m F
V S S
H T 3 6 M 4
V
IN
8
V D D
O U T N
1
H T 8 2 V 7 3 3
5
V S S
4
S P K
8 W
7
O U T P
C E
D D
1 0 W
O S C 1
V D D
4 7 m F
V D D A
V
0 .1 m F
V
D D
D D
S P K
8 W
IN T
1 k W
A U D IO
1 0 0 k W
7 5 0 W
R E S
V S S A
0 .1 m F
V S S
H T 3 6 M 4
Rev. 1.00
18
August 15, 2005
HT36M4
Package Information
20-pin SOP (300mil) Outline Dimensions
1 1
2 0
A
B
1
1 0
C
C '
G
H
D
E
Symbol
Rev. 1.00
a
F
Dimensions in mil
Min.
Nom.
Max.
A
394
¾
419
B
290
¾
300
C
14
¾
20
C¢
490
¾
510
D
92
¾
104
E
¾
50
¾
F
4
¾
¾
G
32
¾
38
H
4
¾
12
a
0°
¾
10°
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August 15, 2005
HT36M4
20-pin TSSOP Outline Dimensions
2 0
1 1
E 1
1
1 0
E
D
L
A
R
A 2
0 .1 0
e
A 1
B
C
q
y
(4 C O R N E R S )
Symbol
Rev. 1.00
Dimensions in mm
Min.
Nom.
Max.
A
1.05
¾
1.2
A1
0.05
¾
0.15
A2
0.95
¾
1.05
B
¾
0.22
¾
C
0.13
¾
0.17
D
6.4
¾
6.6
E
6.3
¾
6.5
E1
4.3
¾
4.5
e
¾
0.65
¾
L
0.45
¾
0.75
y
¾
¾
0.1
q
0°
¾
8°
20
August 15, 2005
HT36M4
Product Tape and Reel Specifications
Reel Dimensions
D
T 2
A
C
B
T 1
SOP 20W
Symbol
Description
Dimensions in mm
A
Reel Outer Diameter
330±1
B
Reel Inner Diameter
62±1.5
C
Spindle Hole Diameter
13+0.5
-0.2
D
Key Slit Width
2±0.5
T1
Space Between Flange
24.8+0.3
-0.2
T2
Reel Thickness
30.2±0.2
Rev. 1.00
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August 15, 2005
HT36M4
Carrier Tape Dimensions
P 0
D
P 1
t
E
F
W
C
D 1
B 0
P
K 0
A 0
SOP 20W
Symbol
Description
Dimensions in mm
W
Carrier Tape Width
24+0.3
-0.1
P
Cavity Pitch
12±0.1
E
Perforation Position
1.75±0.1
F
Cavity to Perforation (Width Direction)
11.5±0.1
D
Perforation Diameter
1.5+0.1
D1
Cavity Hole Diameter
1.5+0.25
P0
Perforation Pitch
4±0.1
P1
Cavity to Perforation (Length Direction)
2±0.1
A0
Cavity Length
10.8±0.1
B0
Cavity Width
13.3±0.1
K0
Cavity Depth
3.2±0.1
t
Carrier Tape Thickness
0.3±0.05
C
Cover Tape Width
Rev. 1.00
21.3
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August 15, 2005
HT36M4
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No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan
Tel: 886-3-563-1999
Fax: 886-3-563-1189
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Tel: 886-2-2655-7070
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Fax: 510-252-9885
http://www.holmate.com
Copyright Ó 2005 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used
solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable
without further modification, nor recommends the use of its products for application that may present a risk to human life
due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices
or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,
please visit our web site at http://www.holtek.com.tw.
Rev. 1.00
23
August 15, 2005