MC14001B Series B-Suffix Series CMOS Gates MC14001B, MC14011B, MC14023B, MC14025B, MC14071B, MC14073B, MC14081B, MC14082B http://onsemi.com The B Series logic gates are constructed with P and N channel enhancement mode devices in a single monolithic structure (Complementary MOS). Their primary use is where low power dissipation and/or high noise immunity is desired. MARKING DIAGRAMS 14 PDIP−14 P SUFFIX CASE 646 Features • Supply Voltage Range = 3.0 Vdc to 18 Vdc • All Outputs Buffered • Capable of Driving Two Low−power TTL Loads or One Low−power • • • 1 14 SOIC−14 D SUFFIX CASE 751A Schottky TTL Load Over the Rated Temperature Range. Double Diode Protection on All Inputs Except: Triple Diode Protection on MC14011B and MC14081B Pin−for−Pin Replacements for Corresponding CD4000 Series B Suffix Devices Pb−Free Packages are Available 14 1 Unit −0.5 to +18.0 V −0.5 to VDD + 0.5 V Input or Output Current (DC or Transient) per Pin ± 10 mA PD Power Dissipation, per Package (Note 1) 500 mW TA Ambient Temperature Range −55 to +125 °C Tstg Storage Temperature Range −65 to +150 °C TL Lead Temperature (8−Second Soldering) 260 °C Vin, Vout Iin, Iout DC Supply Voltage Range Input or Output Voltage Range (DC or Transient) 14 0xxB ALYWG G TSSOP−14 DT SUFFIX CASE 948G Value VDD Parameter 140xxBG AWLYWW 1 MAXIMUM RATINGS (Voltages Referenced to VSS) Symbol MC140xxBCP AWLYYWWG 14 SOEIAJ−14 F SUFFIX CASE 965 MC140xxB ALYWG 1 Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Temperature Derating: Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS v (Vin or Vout) v VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. xx = Specific Device Code A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G or G = Pb−Free Package (Note: Microdot may be in either location) DEVICE INFORMATION Device Description MC14001B Quad 2−Input NOR Gate MC14011B Quad 2−Input NAND Gate MC14023B Triple 3−Input NAND Gate MC14025B Triple 3−Input NOR Gate MC14071B Quad 2−Input OR Gate MC14073B Triple 3−Input AND Gate MC14081B Quad 2−Input AND Gate MC14082B Dual 4−Input AND Gate ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 8 of this data sheet. © Semiconductor Components Industries, LLC, 2006 October, 2006 − Rev. 6 1 Publication Order Number: MC14001B/D MC14001B Series LOGIC DIAGRAMS NAND OR AND MC14001B Quad 2−Input NOR Gate MC14011B Quad 2−Input NAND Gate MC14071B Quad 2−Input OR Gate MC14081B Quad 2−Input AND Gate 2 INPUT NOR 1 2 3 1 2 3 1 2 3 1 2 3 5 6 4 5 6 4 5 6 4 5 6 4 8 9 10 8 9 10 8 9 10 8 9 10 12 13 11 12 13 11 12 13 11 12 13 11 3 INPUT MC14025B Triple 3−Input NOR Gate 1 2 8 3 4 5 11 12 13 9 6 10 MC14023B Triple 3−Input NAND Gate 1 2 8 3 4 5 11 12 13 MC14073B Triple 3−Input AND Gate 1 2 8 3 4 5 11 12 13 9 6 10 9 6 10 MC14082B Dual 4−Input AND Gate 2 3 4 5 9 10 11 12 1 13 NC = 6, 8 VDD = PIN 14 VSS = PIN 7 FOR ALL DEVICES PIN ASSIGNMENTS MC14001B Quad 2−Input NOR Gate MC14023B Triple 3−Input NAND Gate MC14011B Quad 2−Input NAND Gate MC14025B Triple 3−Input NOR Gate IN 1A 1 14 VDD IN 1A 1 14 VDD IN 1A 1 14 VDD IN 1A 1 14 VDD IN 2A 2 13 IN 2D IN 2A 2 13 IN 2D IN 2A 2 13 IN 3C IN 2A 2 13 IN 3C OUTA 3 12 IN 1D OUTA 3 12 IN 1D IN 1B 3 12 IN 2C IN 1B 3 12 IN 2C OUTB 4 11 OUTD OUTB 4 11 OUTD IN 2B 4 11 IN 1C IN 2B 4 11 IN 1C IN 1B 5 10 OUTC IN 1B 5 10 OUTC IN 3B 5 10 OUTC IN 3B 5 10 OUTC IN 2B 6 9 IN 2C IN 2B 6 9 IN 2C OUTB 6 9 OUTA OUTB 6 9 OUTA VSS 7 8 IN 1C VSS 7 8 IN 1C VSS 7 8 IN 3A VSS 7 8 IN 3A MC14071B Quad 2−Input OR Gate MC14073B Triple 3−Input AND Gate MC14081B Quad 2−Input AND Gate MC14082B Dual 4−Input AND Gate IN 1A 1 14 VDD IN 1A 1 14 VDD IN 1A 1 14 VDD OUTA 1 14 VDD IN 2A 2 13 IN 2D IN 2A 2 13 IN 3C IN 2A 2 13 IN 2D IN 1A 2 13 OUTB OUTA 3 12 IN 1D IN 1B 3 12 IN 2C OUTA 3 12 IN 1D IN 2A 3 12 IN 4B OUTB 4 11 OUTD IN 2B 4 11 IN 1C OUTB 4 11 OUTD IN 3A 4 11 IN 3B IN 1B 5 10 OUTC IN 3B 5 10 OUTC IN 1B 5 10 OUTC IN 4A 5 10 IN 2B IN 2B 6 9 IN 2C OUTB 6 9 OUTA IN 2B 6 9 IN 2C NC 6 9 IN 1B VSS 7 8 IN 1C VSS 7 8 IN 3A VSS 7 8 IN 1C VSS 7 8 NC NC = NO CONNECTION http://onsemi.com 2 MC14001B Series ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS) Characteristic Output Voltage Vin = VDD or 0 Symbol − 55_C 25_C 125_C VDD Vdc Min Max Min Typ (2) Max Min Max Unit “0” Level VOL 5.0 10 15 − − − 0.05 0.05 0.05 − − − 0 0 0 0.05 0.05 0.05 − − − 0.05 0.05 0.05 Vdc “1” Level VOH 5.0 10 15 4.95 9.95 14.95 − − − 4.95 9.95 14.95 5.0 10 15 − − − 4.95 9.95 14.95 − − − Vdc Input Voltage “0” Level (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) VIL 5.0 10 15 − − − 1.5 3.0 4.0 − − − 2.25 4.50 6.75 1.5 3.0 4.0 − − − 1.5 3.0 4.0 “1” Level VIH 5.0 10 15 3.5 7.0 11 − − − 3.5 7.0 11 2.75 5.50 8.25 − − − 3.5 7.0 11 − − − 5.0 5.0 10 15 – 3.0 – 0.64 – 1.6 – 4.2 − − − − – 2.4 – 0.51 – 1.3 – 3.4 – 4.2 – 0.88 – 2.25 – 8.8 − − − − – 1.7 – 0.36 – 0.9 – 2.4 − − − − IOL 5.0 10 15 0.64 1.6 4.2 − − − 0.51 1.3 3.4 0.88 2.25 8.8 − − − 0.36 0.9 2.4 − − − mAdc Input Current Iin 15 − ± 0.1 − ± 0.00001 ± 0.1 − ± 1.0 mAdc Input Capacitance (Vin = 0) Cin − − − − 5.0 7.5 − − pF Quiescent Current (Per Package) IDD 5.0 10 15 − − − 0.25 0.5 1.0 − − − 0.0005 0.0010 0.0015 0.25 0.5 1.0 − − − 7.5 15 30 mAdc IT 5.0 10 15 Vin = 0 or VDD (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) Source (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) Total Supply Current (3) (4) (Dynamic plus Quiescent, Per Gate, CL = 50 pF) Sink IOH Vdc Vdc mAdc IT = (0.3 mA/kHz) f + IDD/N IT = (0.6 mA/kHz) f + IDD/N IT = (0.9 mA/kHz) f + IDD/N mAdc 2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. 3. The formulas given are for the typical characteristics only at 25_C. 4. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL − 50) Vfk where: IT is in mA (per package), CL in pF, V = (VDD − VSS) in volts, f in kHz is input frequency, and k = 0.001 x the number of exercised gates per package. http://onsemi.com 3 MC14001B Series B−SERIES GATE SWITCHING TIMES ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ SWITCHING CHARACTERISTICS (5) (CL = 50 pF, TA = 25_C) Characteristic Symbol Output Rise Time, All B−Series Gates tTLH = (1.35 ns/pF) CL + 33 ns tTLH = (0.60 ns/pF) CL + 20 ns tTLH = (0.40 ns/PF) CL + 20 ns tTLH Output Fall Time, All B−Series Gates tTHL = (1.35 ns/pF) CL + 33 ns tTHL = (0.60 ns/pF) CL + 20 ns tTHL = (0.40 ns/pF) CL + 20 ns tTHL Propagation Delay Time MC14001B, MC14011B only tPLH, tPHL = (0.90 ns/pF) CL + 80 ns tPLH, tPHL = (0.36 ns/pF) CL + 32 ns tPLH, tPHL = (0.26 ns/pF) CL + 27 ns All Other 2, 3, and 4 Input Gates tPLH, tPHL = (0.90 ns/pF) CL + 115 ns tPLH, tPHL = (0.36 ns/pF) CL + 47 ns tPLH, tPHL = (0.26 ns/pF) CL + 37 ns 8−Input Gates (MC14068B, MC14078B) tPLH, tPHL = (0.90 ns/pF) CL + 155 ns tPLH, tPHL = (0.36 ns/pF) CL + 62 ns tPLH, tPHL = (0.26 ns/pF) CL + 47 ns VDD Vdc Min Typ (6) Max 5.0 10 15 − − − 100 50 40 200 100 80 5.0 10 15 − − − 100 50 40 200 100 80 Unit ns ns tPLH, tPHL ns 5.0 10 15 − − − 125 50 40 250 100 80 5.0 10 15 − − − 160 65 50 300 130 100 5.0 10 15 − − − 200 80 60 350 150 110 5. The formulas given are for the typical characteristics only at 25_C. 6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. 14 PULSE GENERATOR 20 ns VDD 20 ns INPUT INPUT OUTPUT 7 0V tPHL CL * VDD 90% 50% 10% OUTPUT INVERTING VSS tPLH 90% 50% 10% tTHL tPLH OUTPUT NON-INVERTING *All unused inputs of AND, NAND gates must be connected to VDD. All unused inputs of OR, NOR gates must be connected to VSS. tTLH Figure 1. Switching Time Test Circuit and Waveforms http://onsemi.com 4 VOH tTLH tPHL 90% 50% 10% tTHL VOL VOH VOL MC14001B Series CIRCUIT SCHEMATIC NOR, OR GATES MC14001B, MC14071B One of Four Gates Shown MC14025B One of Three Gates Shown VDD VDD 14 VDD 1, 3, 11 1, 6, 8, 13 * 2, 4, 12 2, 5, 9, 12 14 VDD 3, 4, 10, 11 * VSS VSS 7 9, 6, 10 VSS VDD *Inverter omitted in MC14001B 8, 5, 13 7 VSS VSS *Inverter omitted in MC14025B CIRCUIT SCHEMATIC NAND, AND GATES MC14023B, MC14073B One of Three Gates Shown MC14011B, MC14081B One of Four Gates Shown VDD 14 VDD * 3, 4, 10, 11 2, 4, 12 1, 3, 11 14 2, 5, 9, 12 VDD 1, 6, 8, 13 VSS 7 VSS *Inverter omitted in MC14011B * VDD 9, 6, 10 8, 5, 13 7 VSS VSS *Inverter omitted in MC14023B http://onsemi.com 5 MC14001B Series TYPICAL B−SERIES GATE CHARACTERISTICS N−CHANNEL DRAIN CURRENT (SINK) P−CHANNEL DRAIN CURRENT (SOURCE) - 10 5.0 ID , DRAIN CURRENT (mA) ID , DRAIN CURRENT (mA) - 9.0 4.0 TA = - 55°C 3.0 - 40°C + 85°C + 25°C 2.0 + 125°C 1.0 - 8.0 TA = - 55°C - 7.0 - 40°C - 6.0 - 5.0 + 25°C + 85°C - 4.0 + 125°C - 3.0 - 2.0 - 1.0 0 0 1.0 2.0 3.0 4.0 VDS, DRAIN-TO-SOURCE VOLTAGE (Vdc) 0 5.0 0 Figure 2. VGS = 5.0 Vdc - 50 - 45 TA = - 55°C 16 14 - 40°C 12 + 25°C + 85°C 10 ID , DRAIN CURRENT (mA) ID , DRAIN CURRENT (mA) 18 + 125°C 8.0 6.0 - 40 - 35 - 30 + 85°C - 15 2.0 - 5.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 VDS, DRAIN-TO-SOURCE VOLTAGE (Vdc) 9.0 0 10 - 40°C + 25°C - 20 - 10 0 TA = - 55°C - 25 4.0 + 125°C 0 Figure 4. VGS = 10 Vdc - 100 45 - 90 40 - 80 35 TA = - 55°C 30 - 40°C 25 + 25°C ID , DRAIN CURRENT (mA) ID , DRAIN CURRENT (mA) - 1.0 - 2.0 - 3.0 - 4.0 - 5.0 - 6.0 - 7.0 - 8.0 - 9.0 - 10 VDS, DRAIN-TO-SOURCE VOLTAGE (Vdc) Figure 5. VGS = − 10 Vdc 50 + 85°C 20 + 125°C 15 10 5.0 0 - 5.0 Figure 3. VGS = − 5.0 Vdc 20 0 - 1.0 - 2.0 - 3.0 - 4.0 VDS, DRAIN-TO-SOURCE VOLTAGE (Vdc) - 70 - 60 TA = - 55°C - 50 - 40°C + 25°C - 40 + 85°C - 30 + 125°C - 20 - 10 0 2.0 4.0 6.0 8.0 10 12 14 16 VDS, DRAIN-TO-SOURCE VOLTAGE (Vdc) 18 0 20 0 Figure 6. VGS = 15 Vdc - 2.0 - 4.0 - 6.0 - 8.0 - 10 - 12 - 14 - 16 VDS, DRAIN-TO-SOURCE VOLTAGE (Vdc) Figure 7. VGS = − 15 Vdc These typical curves are not guarantees, but are design aids. Caution: The maximum rating for output current is 10 mA per pin. http://onsemi.com 6 - 18 - 20 MC14001B Series TYPICAL B−SERIES GATE CHARACTERISTICS (cont’d) V out , OUTPUT VOLTAGE (Vdc) V out , OUTPUT VOLTAGE (Vdc) VOLTAGE TRANSFER CHARACTERISTICS SINGLE INPUT NAND, AND MULTIPLE INPUT NOR, OR 5.0 4.0 SINGLE INPUT NOR, OR MULTIPLE INPUT NAND, AND 3.0 2.0 1.0 0 0 1.0 2.0 SINGLE INPUT NAND, AND MULTIPLE INPUT NOR, OR 10 8.0 SINGLE INPUT NOR, OR MULTIPLE INPUT NAND, AND 6.0 4.0 2.0 0 3.0 4.0 5.0 Vin, INPUT VOLTAGE (Vdc) 0 2.0 Figure 8. VDD = 5.0 Vdc V out , OUTPUT VOLTAGE (Vdc) 6.0 8.0 10 Vin, INPUT VOLTAGE (Vdc) Figure 9. VDD = 10 Vdc DC NOISE MARGIN 16 SINGLE INPUT NAND, AND MULTIPLE INPUT NOR, OR 14 The DC noise margin is defined as the input voltage range from an ideal “1” or “0” input level which does not produce output state change(s). The typical and guaranteed limit values of the input values VIL and VIH for the output(s) to be at a fixed voltage VO are given in the Electrical Characteristics table. VIL and VIH are presented graphically in Figure 11. Guaranteed minimum noise margins for both the “1” and “0” levels = 12 SINGLE INPUT NOR, OR MULTIPLE INPUT NAND, AND 10 8.0 6.0 4.0 2.0 0 4.0 0 2.0 4.0 1.0 V with a 5.0 V supply 2.0 V with a 10.0 V supply 2.5 V with a 15.0 V supply 6.0 8.0 10 Vin, INPUT VOLTAGE (Vdc) Figure 10. VDD = 15 Vdc Vout VDD Vout VO VO VO VO VDD VDD 0 VDD Vin VIL 0 VIH Vin VIL VIH VSS = 0 VOLTS DC (a) Inverting Function (b) Non−Inverting Function Figure 11. DC Noise Immunity http://onsemi.com 7 MC14001B Series ORDERING INFORMATION Device Package MC14001BCP PDIP−14 MC14001BCPG PDIP−14 (Pb−Free) MC14001BD SOIC−14 MC14001BDG SOIC−14 (Pb−Free) MC14001BDR2 SOIC−14 MC14001BDR2G SOIC−14 (Pb−Free) MC14001BDTR2 TSSOP−14* MC14001BDTR2G TSSOP−14* (Pb−Free) MC14001BFEL SOEIAJ−14 MC14001BFELG SOEIAJ−14 (Pb−Free) MC14011BCP PDIP−14 MC14011BCPG PDIP−14 (Pb−Free) MC14011BD SOIC−14 MC14011BDG SOIC−14 (Pb−Free) MC14011BDR2 SOIC−14 MC14011BDR2G SOIC−14 (Pb−Free) MC14011BDTR2 TSSOP−14* MC14011BDTR2G TSSOP−14* (Pb−Free) MC14011BF SOEIAJ−14 MC14011BFG SOEIAJ−14 (Pb−Free) MC14011BFEL SOEIAJ−14 MC14011BFELG SOEIAJ−14 (Pb−Free) MC14023BCP PDIP−14 MC14023BCPG PDIP−14 (Pb−Free) MC14023BD SOIC−14 MC14023BDG SOIC−14 (Pb−Free) MC14023BDR2 SOIC−14 MC14023BDR2G SOIC−14 (Pb−Free) MC14023BFEL SOEIAJ−14 MC14023BFELG SOEIAJ−14 (Pb−Free) http://onsemi.com 8 Shipping† 25 Units / Rail 55 Units / Rail 2500 Units / Tape & Reel 2000 Units / Tape & Reel 25 Units / Rail 55 Units / Rail 2500 Units / Tape & Reel 50 Units / Rail 2000 Units / Tape & Reel 25 Units / Rail 55 Units / Rail 2500 Units / Tape & Reel 2000 Units / Tape & Reel MC14001B Series ORDERING INFORMATION Device Package MC14025BCP PDIP−14 MC14025BCPG PDIP−14 (Pb−Free) MC14025BD SOIC−14 MC14025BDG SOIC−14 (Pb−Free) MC14025BDR2 SOIC−14 MC14025BDR2G SOIC−14 (Pb−Free) MC14025BFEL SOEIAJ−14 MC14025BFELG SOEIAJ−14 (Pb−Free) MC14071BCP PDIP−14 MC14071BCPG PDIP−14 (Pb−Free) MC14071BD SOIC−14 MC14071BDG SOIC−14 (Pb−Free) MC14071BDR2 SOIC−14 MC14071BDR2G SOIC−14 (Pb−Free) MC14071BDT TSSOP−14* MC14071BDTG TSSOP−14* (Pb−Free) MC14071BDTR2 TSSOP−14* MC14071BDTR2G TSSOP−14* (Pb−Free) MC14071BFEL SOEIAJ−14 MC14071BFELG SOEIAJ−14 (Pb−Free) MC14073BCP PDIP−14 MC14073BCPG PDIP−14 (Pb−Free) MC14073BD SOIC−14 MC14073BDG SOIC−14 (Pb−Free) MC14073BDR2 SOIC−14 MC14073BDR2G SOIC−14 (Pb−Free) MC14073BFEL SOEIAJ−14 MC14073BFELG SOEIAJ−14 (Pb−Free) http://onsemi.com 9 Shipping† 25 Units / Rail 55 Units / Rail 2500 Units / Tape & Reel 2000 Units / Tape & Reel 25 Units / Rail 55 Units / Rail 2500 Units / Tape & Reel 96 Units per Rail 2500 Units / Tape & Reel 2000 Units / Tape & Reel 25 Units / Rail 55 Units / Rail 2500 Units / Tape & Reel 2000 Units / Tape & Reel MC14001B Series ORDERING INFORMATION Device Package MC14081BCP PDIP−14 MC14081BCPG PDIP−14 (Pb−Free) MC14081BD SOIC−14 MC14081BDG SOIC−14 (Pb−Free) MC14081BDR2 SOIC−14 MC14081BDR2G SOIC−14 (Pb−Free) MC14081BDTR2 TSSOP−14* MC14081BDTR2G TSSOP−14* (Pb−Free) MC14081BFEL SOEIAJ−14 MC14081BFELG SOEIAJ−14 (Pb−Free) MC14082BCP PDIP−14 MC14082BCPG PDIP−14 (Pb−Free) MC14082BD SOIC−14 MC14082BDG SOIC−14 (Pb−Free) MC14082BDR2 SOIC−14 MC14082BDR2G SOIC−14 (Pb−Free) Shipping† 25 Units / Rail 55 Units / Rail 2500 Units / Tape & Reel 2000 Units / Tape & Reel 2000 Units / Box 55 Units / Rail 2500 Units / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb−Free. http://onsemi.com 10 MC14001B Series PACKAGE DIMENSIONS PDIP−14 CASE 646−06 ISSUE P 14 8 1 7 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. B A F L N C −T− SEATING PLANE H G D 14 PL J K 0.13 (0.005) M M http://onsemi.com 11 DIM A B C D F G H J K L M N INCHES MIN MAX 0.715 0.770 0.240 0.260 0.145 0.185 0.015 0.021 0.040 0.070 0.100 BSC 0.052 0.095 0.008 0.015 0.115 0.135 0.290 0.310 −−− 10 _ 0.015 0.039 MILLIMETERS MIN MAX 18.16 19.56 6.10 6.60 3.69 4.69 0.38 0.53 1.02 1.78 2.54 BSC 1.32 2.41 0.20 0.38 2.92 3.43 7.37 7.87 −−− 10 _ 0.38 1.01 MC14001B Series PACKAGE DIMENSIONS SOIC−14 CASE 751A−03 ISSUE H NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. −A− 14 8 −B− P 7 PL 0.25 (0.010) M 7 1 G −T− D 14 PL 0.25 (0.010) T B S A DIM A B C D F G J K M P R J M K M F R X 45 _ C SEATING PLANE B M S SOLDERING FOOTPRINT* 7X 7.04 14X 1.52 1 14X 0.58 1.27 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 12 MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019 MC14001B Series PACKAGE DIMENSIONS TSSOP−14 CASE 948G−01 ISSUE B 14X K REF 0.10 (0.004) 0.15 (0.006) T U M T U V S S S N 2X 14 L/2 M B −U− L PIN 1 IDENT. N F 7 1 0.15 (0.006) T U 0.25 (0.010) 8 S DETAIL E K A −V− ÉÉÉ ÇÇÇ ÇÇÇ ÉÉÉ K1 J J1 SECTION N−N −W− C 0.10 (0.004) −T− SEATING PLANE D H G DETAIL E NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. MILLIMETERS INCHES DIM MIN MAX MIN MAX A 4.90 5.10 0.193 0.200 B 4.30 4.50 0.169 0.177 C −−− 1.20 −−− 0.047 D 0.05 0.15 0.002 0.006 F 0.50 0.75 0.020 0.030 G 0.65 BSC 0.026 BSC H 0.50 0.60 0.020 0.024 J 0.09 0.20 0.004 0.008 J1 0.09 0.16 0.004 0.006 K 0.19 0.30 0.007 0.012 K1 0.19 0.25 0.007 0.010 L 6.40 BSC 0.252 BSC M 0_ 8_ 0_ 8_ SOLDERING FOOTPRINT* 7.06 1 0.65 PITCH 14X 0.36 14X 1.26 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 13 MC14001B Series PACKAGE DIMENSIONS SOEIAJ−14 CASE 965−01 ISSUE A 14 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). LE 8 Q1 E HE M_ L 7 1 DETAIL P Z D VIEW P A e A1 b 0.13 (0.005) c M 0.10 (0.004) DIM A A1 b c D E e HE 0.50 LE M Q1 Z MILLIMETERS MIN MAX --2.05 0.05 0.20 0.35 0.50 0.10 0.20 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --1.42 INCHES MIN MAX --0.081 0.002 0.008 0.014 0.020 0.004 0.008 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 --0.056 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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