FUJITSU SEMICONDUCTOR DATA SHEET DS05-11404-2E MEMORY Mobile FCRAMTM CMOS 16 Mbit (1 M word × 16 bit) Mobile Phone Application Specific Memory MB82D01171A-80/80L/80LL/85/85L/85LL/90/90L/90LL CMOS 1,048,576-WORD × 16 BIT Fast Cycle Random Access Memory with Low Power SRAM Interface ■ DESCRIPTION The Fujitsu MB82D01171A is a CMOS Fast Cycle Random Access Memory (FCRAM) with asynchronous Static Random Access Memory (SRAM) interface containing 16,777,216 storages accessible in a 16-bit format. This MB82D01171A is suited for low power applications such as Cellular Handset and PDA. Note: FCRAM is a trademark of Fujitsu Limited, Japan. ■ PRODUCT LINEUP MB82D01171A Parameter 80 Access Time (tAA Max, tCE Max) 80L 80 ns Active Current (IDDA1 Max) 80LL 85 85L 85LL 85 ns 90 90L 90LL 90 ns 20 mA Standby Current (IDDS1 Max) 200 µA 100 µA 70 µA 200 µA 100 µA 70 µA 200 µA 100 µA 70 µA Power Down Current (IDDP Max) 10 µA ■ PACKAGES 48-ball plastic FBGA 48-ball plastic FBGA (BGA-48P-M16) (BGA-48P-M18) MB82D01171A-80/80L/80LL/85/85L/85LL/90/90L/90LL ■ FEATURES • • • • • • Asynchronous SRAM Interface 1 M word × 16 bit Organization Fast Random Cycle Time : tRC = 90 ns Fast Random Access Time : tAA = tCE = 80 ns, 85 ns, 90 ns Low Power Consumption : IDDS1 = 200 µA, 100 µA (L version) , 70 µA (LL version) Wide Operating Conditions : VDD = +2.3 V to +2.7 V +2.7 V to +3.1 V +3.1 V to +3.5 V TA = −30 °C to +85 °C • Byte Write Control • 4 words Address Access Capability • Power Down Control by CE2 2 MB82D01171A-80/80L/80LL/85/85L/85LL/90/90L/90LL ■ PIN ASSIGNMENTS (TOP VIEW) Flash Compatible FBGA (suffix PBT) SRAM Compatible FBGA (suffix PBN) 1 2 3 4 5 6 A A4 A17 UB CE2 A8 A12 B A3 A7 LB WE A9 C A2 A6 A18 NC D A1 A5 NC E A0 DQ1 DQ3 F CE1 DQ9 G OE DQ10 DQ12 VDD H VSS DQ2 DQ5 1 2 3 4 5 6 A LB OE A0 A1 A2 CE2 A13 B DQ9 UB A3 A4 CE1 DQ1 A10 A14 C DQ10 DQ11 A5 A6 DQ2 DQ3 A19 A11 A15 D VSS DQ12 A17 A7 DQ4 VDD DQ6 DQ8 A16 E VDD DQ13 NC A16 DQ5 VSS DQ11 DQ13 DQ15 NC F DQ15 DQ14 A14 A15 DQ6 DQ7 DQ14 DQ16 G DQ16 A19 A12 A13 WE DQ8 DQ7 H A18 A8 A9 A10 A11 NC DQ4 VSS (BGA-48P-M16) (BGA-48P-M18) ■ PIN DESCRIPTION Pin Name A0 to A19 Description Address Input CE1 Chip Enable (Low Active) CE2 Chip Enable (High Active) WE Write Enable (Low Active) OE Output Enable (Low Active) LB Lower Byte Write Control (Low Active) UB Upper Byte Write Control (Low Active) DQ1 to DQ8 Lower Byte Data Input/Output DQ9 to DQ16 Upper Byte Data Input/Output VDD Power Supply VSS Ground NC No Connection 3 MB82D01171A-80/80L/80LL/85/85L/85LL/90/90L/90LL ■ BLOCK DIAGRAM VDD VSS A0 to A19 DQ1 to DQ8 Address Latch & Buffer I/O Buffer DQ9 to DQ16 Row Decoder Input Data Latch & Control Memory Cell Array 16,777,216 bit Sense / Switch Column / Decoder Address Latch & Buffer CE2 CE1 WE LB UB OE 4 Power Control Timing Control Output Data Control MB82D01171A-80/80L/80LL/85/85L/85LL/90/90L/90LL ■ FUNCTION TRUTH TABLE *1 CE1 CE2 WE OE LB UB DQ1 to DQ8 DQ9 to DQ16 IDD Data Retention Power Down *2 X L X X X X High-Z High-Z IDDP No Standby (Deselect) H X X X X High-Z High-Z IDDS H X X High-Z High-Z L X X Output Valid Output Valid L L Input Valid Input Valid L H Input Valid Invalid H L Invalid Input Valid Mode Output Disable*3 H Read*4 Write Write (Lower Byte) L H L Write (Upper Byte) H IDDA Yes *1 : V = Valid, L = Logic Low, H = Logic High, X = either “L” or “H”, High-Z = High Impedance *2 : Power Down mode can be entered from Standby state and all DQ pins are in High-Z state. *3 : Output Disable mode should not be kept longer than 1 µs. *4 : Byte control at Read mode is not supported. 5 MB82D01171A-80/80L/80LL/85/85L/85LL/90/90L/90LL ■ ABSOLUTE MAXIMUM RATINGS Parameter Symbol Rating Unit Min Max VDD −0.5 +3.6 V VIN −0.5 +3.6 V VOUT −0.5 +3.6 V Short Circuit Output Current IOUT −50 +50 mA Storage Temperature TSTG −55 +125 °C Voltage of VDD Supply Relative to VSS Voltage at Any Pin Relative to VSS WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. ■ RECOMMENDED OPERATING CONDITIONS Parameter Supply Voltage *1 Symbol Value Max VDD (31) 3.1 3.5 V VDD (27) 2.7 3.1 V VDD (23) 2.3 2.7 V VSS 0 0 V VIH (31) 2.6 VDD + 0.3 and ≤ 3.6 V VIH (27) 2.2 VDD + 0.3 V VIH (23) 2.0 VDD + 0.3 V VIL (31) −0.3 0.5 V VIL (27) −0.3 0.5 V VIL (23) −0.3 0.4 V TA −30 85 °C High Level Input Voltage *1, *2 Low Level Input Voltage *1, *2 Ambient Temperature Unit Min *1 : All voltages are referenced to VSS. *2 : Minimum DC voltage on input or I/O pins are −0.3 V. During voltage transitions, inputs may undershoot VSS to −1.0 V for periods of up to 5 ns. Maximum DC voltage on input and I/O pins are VDD + 0.3 V. During voltage transitions, inputs may positive overshoot to VDD + 1.0 V for periods of up to 5 ns. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 6 MB82D01171A-80/80L/80LL/85/85L/85LL/90/90L/90LL ■ PIN CAPACITANCE Parameter Symbol Conditions Min (f = 1.0 MHz, TA = +25 °C) Value Unit Typ Max Address Input Capacitance CIN1 VIN = 0 V 5 pF Control Input Capacitance CIN2 VIN = 0 V 5 pF Data Input/Output Capacitance CIO VIO = 0 V 8 pF ■ ELECTRICAL CHARACTERISTICS 1. DC Characteristics Parameter Symbol Conditions Value Min Max Unit Input Leakage Current ILI VSS ≤ VIN ≤ VDD −1.0 +1.0 µA Output Leakage Current ILO 0 V ≤ VOUT ≤ VDD, Output Disable −1.0 +1.0 µA VOH(31) VDD = VDD(31), IOH = −0.5 mA 2.4 V VOH(27) VDD = VDD(27), IOH = −0.5 mA 2.25 V VOH(23) VDD = VDD(23), IOH = −0.5 mA 1.8 V IOL = 1 mA 0.4 V VDD = VDD(31) Max, VIN = VIH or VIL, CE2 ≤ 0.2 V 20 µA VDD = VDD(27, 23) Max, VIN = VIH or VIL, CE2 ≤ 0.2 V 10 µA 5.5 2.0 1.5 5 1.5 1 250 150 120 200 100 70 Output High Voltage Level Output Low Voltage Level VDD Power Down Current L Version VOL IDDP IDDS LL Version L Version VDD Standby Current IDDS LL Version L Version IDDS1 LL Version L Version LL Version IDDS1 VDD = VDD(31) Max, VIN = VIH or VIL CE1 = CE2 = VIH, IOUT = 0 mA VDD = VDD(27, 23) Max, VIN = VIH or VIL CE1 = CE2 = VIH, IOUT = 0 mA VDD = VDD(31) Max, VIN ≤ 0.2 V or VIN ≥ VDD − 0.2 V, CE1 = CE2 ≥ VDD − 0.2 V, IOUT = 0 mA VDD = VDD(27, 23) Max, VIN ≤ 0.2 V or VIN ≥ VDD − 0.2 V, CE1 = CE2 ≥ VDD − 0.2 V, IOUT = 0 mA mA mA µA µA (Continued) 7 MB82D01171A-80/80L/80LL/85/85L/85LL/90/90L/90LL (Continued) Parameter Symbol IDDA1 VDD Active Current IDDA2 Conditions VDD(31) = VDD Max, VIN = VIH or VIL, CE1 = VIL and CE2 = VIH, IOUT = 0 mA tRC / tWC = Min VDD(27, 23) = VDD Max, VIN = VIH or VIL, CE1 = VIL and CE2 = VIH, IOUT = 0 mA VDD(31) = VDD Max, VIN = VIH or VIL, CE1 = VIL and CE2 = VIH, IOUT = 0 mA tRC / tWC = 1 µs VDD(27, 23) = VDD Max, VIN = VIH or VIL, CE1 = VIL and CE2 = VIH, IOUT = 0 mA Notes: • All voltages are referenced to Vss. • DC Characteristics are measured after following POWER-UP timing. • IOUT depends on the output load conditions. 8 Value Min Max Unit 25 mA 20 4.0 mA 3.0 MB82D01171A-80/80L/80LL/85/85L/85LL/90/90L/90LL 2. AC Characteristics (1) Read Operation Parameter Symbol -80/-80L/ -80LL -85/-85L/ -85LL -90/-90L/ -90LL Min Max Min Max Min Max Unit Notes Read Cycle Time tRC 90 90 90 ns Chip Enable Access Time tCE 80 85 90 ns *1, *3 Output Enable Access Time tOE 45 45 45 ns *1 Address Access Time tAA 80 85 90 ns *1, *4 Output Data Hold Time tOH 5 5 5 ns *1 CE1 Low to Output Low-Z tCLZ 5 5 5 ns *2 OE Low to Output Low-Z tOLZ 0 0 0 ns *2 CE1 High to Output High-Z tCHZ 30 30 30 ns *2 OE High to Output High-Z tOHZ 25 25 25 ns *2 Address Setup Time to CE1 Low tASC −5 −5 −5 ns *5 tASO 45 45 45 ns *3, *6 tASO[ABS] 10 10 10 ns *7 tAX 5 5 5 ns *4 tCLAH 90 90 90 ns *4 OE Low to Address Hold Time tOLAH 45 45 45 ns *4, *8 CE1 High to Address Hold Time tCHAH −5 −5 −5 ns OE High to Address Hold Time tOHAH −5 −5 −5 ns CE1 Low to OE Low Delay Time tCLOL 45 1000 45 1000 45 1000 ns *3, *6, *8, *9 OE Low to CE1 High Delay Time tOLCH 45 45 45 ns *8 tCP 20 20 20 ns tOP 45 1000 45 1000 45 1000 ns *6, *8, *9 tOP[ABS] 20 20 20 ns *7 Address Setup Time to OE Low Address Invalid Time CE1 Low to Address Hold Time CE1 High Pulse Width OE High Pulse Width *1: The output load is 30 pF. *2: The output load is 5 pF. *3: The tCE is applicable if OE is brought to Low before CE1 goes Low and is also applicable if actual value of both or either tASO or tCLOL is shorter than specified value. *4: Applicable only to A0 and A1 when both CE1 and OE are kept at Low for the address access. *5: Applicable if OE is brought to Low before CE1 goes Low. *6: The tASO, tCLOL (Min) and tOP (Min) are reference values when the access time is determined by tOE. If actual value of each parameter is shorter than specified minimum value, tOE become longer by the amount of subtraction actual value from specified minimum value. For example, if actual tASO, tASO (actual) , is shorter than specified minimum value, tASO (Min) , during OE control access (i.e., CE1 stays Low) , the tOE become tOE (Max) + tASO (Min) − tASO (actual) . *7: The tASO[ABS] and tOP[ABS] is the absolute minimum value during OE control access. *8: If actual value of either tCLOL or tOP is shorter than specified minimum value, both tOLAH and tOLCH become tRC (Min) − tCLOL (actual) or tRC (Min) − tOP (actual) . *9: Maximum value is applicable if CE1 is kept at Low. 9 MB82D01171A-80/80L/80LL/85/85L/85LL/90/90L/90LL (2) Write Operation Parameter Symbol -80/-80L/ -80LL -85/-85L/ -85LL -90/-90L/ -90LL Min Max Min Max Min Max Unit Notes Write Cycle Time tWC 90 90 90 ns *1 Address Setup Time tAS 0 0 0 ns *2 Address Hold Time tAH 45 45 45 ns *2 CE1 Write Setup Time tCS 0 1000 0 1000 0 1000 ns CE1 Write Hold Time tCH 0 1000 0 1000 0 1000 ns WE Setup Time tWS 0 0 0 ns WE Hold Time tWH 0 0 0 ns LB and UB Setup Time tBS −5 −5 −5 ns LB and UB Hold Time tBH −5 −5 −5 ns OE Setup Time tOES 0 1000 0 1000 0 1000 ns *3 tOEH 45 1000 45 1000 45 1000 ns *3, *4 tOEH[ABS] 20 20 20 ns *5 OE High to CE1 Low Setup Time tOHCL −3 −3 −3 ns *6 Address Hold Time to OE High tOHAH 0 0 0 ns *7 CE1 Write Pulse Width tCW 60 60 60 ns *1, *8 WE Write Pulse Width tWP 60 60 60 ns *1, *8 CE1 Write Recovery Time tWRC 15 15 15 ns *1, *9 WE Write Recovery Time tWR 15 1000 15 1000 15 1000 ns *1, *3, *9 Data Setup Time tDS 20 20 20 ns Data Hold Time tDH 0 0 0 ns CE1 High Pulse Width tCP 20 20 20 ns OE Hold Time *9 *1: Minimum value must be equal or greater than the sum of actual tCW (or tWP) and tWRC (or tWR) . *2: New write address is valid from either CE1 or WE is brought to High. *3: Maximum value is applicable if CE1 is kept at Low and both WE and OE are kept at High. *4: The tOEH is specified from end of tWC (Min) and is a reference value when access time is determined by tOE. If actual value is shorter than specified minimum value, tOE become longer by the amount of subtracting actual value from specified minimum value. *5: The tOEH[ABS] is the absolute minimum value if write cycle is terminated by WE and CE1 stays Low. *6: tOHCL (Min) must be satisfied if read operation is not performed prior to write operation. In case OE is disabled after tOHCL (Min) , WE Low must be asserted after tRC (Min) from CE1 Low. In other words, read operation is initiated if tOHCL (Min) is not satisfied. *7: Applicable if CE1 stays Low after read operation. *8: tCW and tWP is applicable if write operation is initiated by CE1 and WE, respectively. *9: tWRC and tWR is applicable if write operation is terminated by CE1 and WE, respectively. The tWR (Min) can be ignored if CE1 is brought to High together or after WE is brought to High. In such case, the tCP (Min) must be satisfied. 10 MB82D01171A-80/80L/80LL/85/85L/85LL/90/90L/90LL (3) Power Down Parameters Parameter Symbol Value Min Max Unit CE2 Low Setup Time for Power Down Entry tCSP 10 ns CE2 Low Hold Time after Power Down Entry tC2LP 100 ns CE1 High Hold Time following CE2 High after Power Down Exit tCHH 350 µs CE1 High Setup Time following CE2 High after Power Down Exit tCHS 10 ns Note (4) Other Timing Parameters Parameter Symbol CE1 High to OE Invalid Time for Standby Entry Value Unit Note Min Max tCHOX 20 ns CE1 High to WE Invalid Time for Standby Entry tCHWX 20 ns *1 CE2 Low Hold Time after Power-up tC2LH 50 µs *2 CE2 High Hold Time after Power-up tC2HL 50 µs *3 CE1 High Hold Time following CE2 High after Power-up tCHH 350 µs *2 tT 1 25 ns *4 Input Transition Time *1: It may write some data into any address location if tCHWX is not satisfied. *2: Must satisfy tCHH (Min) after tC2LH (Min) . *3: Requires Power Down mode entry and exit after tC2HL. *4: The Input Transition Time (tT) at AC testing is 5 ns as shown in below. If actual tT is longer than 5 ns, it may violate some timing parameters of AC specification. (5) AC Test Conditions Parameter Input High Level Input Low Level Input Timing Measurement Level Input Transition Time Symbol VIH VIL VREF tT Conditions Measured Value Unit VDD = 3.1 V to 3.5 V 2.6 V VDD = 2.7 V to 3.1 V 2.3 V VDD = 2.3 V to 2.7 V 2.0 V VDD = 3.1 V to 3.5 V 0.5 V VDD = 2.7 V to 3.1 V 0.5 V VDD = 2.3 V to 2.7 V 0.4 V VDD = 3.1 V to 3.5 V 1.5 V VDD = 2.7 V to 3.1 V 1.3 V VDD = 2.3 V to 2.7 V 1.1 V Between VIL and VIH 5 ns Note 11 MB82D01171A-80/80L/80LL/85/85L/85LL/90/90L/90LL ■ TIMING DIAGRAM 1. READ Timing #1 (OE Control Access) tRC Address tRC Address Valid Address Valid tOHAH tASO tCE tOHAH CE1 tOLCH tCLOL tOE tOP tOE OE tOHZ tASO tOLZ tOHZ tOLZ tOH tOH DQ (Output) Valid Data Output Valid Data Output Note : CE2 and WE must be High for entire read cycle. 2. READ Timing #2 (CE1 Control Access) tRC tRC Address Address Valid tASC Address Valid tCE tCHAH tASC tCE tCHAH CE1 tOLCH tCP tOE tCHZ tCHZ OE tOH tCLZ tCLZ tOH DQ (Output) Valid Data Output Note : CE2 and WE must be High for entire read cycle. 12 Valid Data Output MB82D01171A-80/80L/80LL/85/85L/85LL/90/90L/90LL 3. READ Timing #3 (Address Access after OE Control Access) tRC tRC Address (A19 - A2) Address Valid Address Valid (No change) Address (A1, A0) Address Valid Address Valid tASO tOLAH tOHAH tAA tAX CE1 tOHZ tOE OE tOH tOH tOLZ DQ (Output) Valid Data Output Valid Data Output Note : CE2 and WE must be High for entire read cycle. 4. READ Timing #4 (Address Access after CE1 Control Access) tRC Address (A19-A2) Address Valid Address (A1, A0) Address Valid tRC Address Valid (No change) Address Valid tCLAH tASC tAA tCHAH tAX CE1 tCHZ tCE OE tOH tCLZ tOH DQ (Output) Valid Data Output Valid Data Output Note : CE2 and WE must be High for entire read cycle. 13 MB82D01171A-80/80L/80LL/85/85L/85LL/90/90L/90LL 5. WRITE Timing #1 (CE1 Control) tWC Address Address Valid tAS tAH tAS CE1 tCW tWRC tWS tWH tWS tBS tBH tBS WE UB, LB tOHCL OE tDS tDH DQ (Input) Valid Data Input Note : CE2 must be High for write cycle. 14 MB82D01171A-80/80L/80LL/85/85L/85LL/90/90L/90LL 6. WRITE Timing #2-1 (WE Control, Single Write Operation) tWC Address Address Valid tOHAH tAS tAH tAS tCH CE1 tCP tOHCL tCS tWP tWR WE tBS tBH UB, LB tOES OE tOHZ tDS tDH DQ (Input) Valid Data Input Note : CE2 must be High for write cycle. 15 MB82D01171A-80/80L/80LL/85/85L/85LL/90/90L/90LL 7. WRITE Timing #2 (WE Control, Continuous Write Operation) tWC Address Valid Address tOHAH tAS tAH tAS CE1 tOHCL tCS tWP tWR WE tBH tBS UB, LB tOES OE tOHZ tDS tDH DQ (Input) Valid Data Input 16 tBS MB82D01171A-80/80L/80LL/85/85L/85LL/90/90L/90LL 8. READ/WRITE Timing #1-1 (CE1 Control) tWC Write Address Address tCHAH tAS Read Address tASC tAH CE1 tCP tWH tWRC tWS tCW tWH tWS WE tBH tBS UB, LB tCLOL tOHCL OE tCHZ tOH tDS tDH tOLZ tCLZ DQ Read Data Output Write Data Input Note : Write address is valid from either CE1 or WE of last falling edge. 17 MB82D01171A-80/80L/80LL/85/85L/85LL/90/90L/90LL 9. READ/WRITE Timing #1-2 (CE1 Control) tRC Address Read Address Write Address tASC tCHAH tWRC tAS CE1 tWRC (Min) tWH tCP tWH tWS tWS WE tBH tBS tCE UB, LB tOHCL tOEH OE tCHZ tDH tCLZ tOH DQ Write Data Input Read Data Output Note : The tOEH is specified from the time satisfied both tWRC and tWR (Min) . 18 MB82D01171A-80/80L/80LL/85/85L/85LL/90/90L/90LL 10. READ (OE Control) /WRITE (WE Control) Timing #2-1 tWC Write Address Address tOHAH CE1 tAS Read Address tAH tASO Low tWR tWP WE tBH tBS UB, LB tOEH tOES OE tOHZ tOH tDS tDH tOLZ DQ Read Data Output Write Data Input Note : CE1 can be tied to Low for WE and OE controlled operation. When CE1 is tied to Low, output is exclusively controlled by OE. 19 MB82D01171A-80/80L/80LL/85/85L/85LL/90/90L/90LL 11. READ (OE Control) /WRITE (WE Control) Timing #2-2 tRC Address Read Address Valid Write Address tOHAH tASO CE1 tAS Low tWR WE tBS tBH UB, LB tOEH tOES tOE OE tOHZ tDH tOLZ tOH DQ Write Data Input Read Data Output Note : CE1 can be tied to Low for WE and OE controlled operation. When CE1 is tied to Low, output is exclusively controlled by OE. 20 MB82D01171A-80/80L/80LL/85/85L/85LL/90/90L/90LL 12. POWER DOWN Timing CE1 tCHS CE2 tCSP tC2LP tCHH High-Z DQ Power Down Entry Power Down Mode Power Down Exit 13. Standby Entry Timing after Read or Write CE1 tCHOX tCHWX OE WE Active (Read) Active (Write) Standby Standby Note : Both tCHOX and tCHWX define the earliest entry timing for Standby mode. If either of timing is not satisfied, it takes tRC (Min) period from either last address transition of A0 and A1, or CE1 Low to High transition. 14. POWER-UP Timing 1 CE1 tCHS tC2LH tCHH CE2 VDD VDD Min 0V Note : It is recommended to keep CE2 at Low during VDD power-up. The tC2LH specifies after VDD reaches specified minimum level. 21 MB82D01171A-80/80L/80LL/85/85L/85LL/90/90L/90LL 15. POWER-UP Timing 2 CE1 tCHS tC2HL tCSP tC2LP tCHH CE2 tC2HL VDD VDD Min 0V Note : The tC2HL specifies from CE2 Low to High transition after VDD reaches specified minimum level. CE1 must be brought to High prior to or together with CE2 Low to High transition. 22 MB82D01171A-80/80L/80LL/85/85L/85LL/90/90L/90LL ■ DATA RETENTION 1. Low VDD Characteristics Parameter Symbol VDD Data Retention Supply Voltage L Version VDR CE1 = CE2 ≥ VDD − 0.2 V or, CE1 = CE2 = VIH, IDR VDD = VDD (23) , VIN = VIH (23) or VIL CE1 = CE2 = VIH (23) , IOUT = 0 mA LL Version VDD Data Retention Supply Current L Version Value Test Conditions IDR1 LL Version Min Max 2.1 3.5 5 1.5 1 VDD = VDD (23) , VIN ≤ 0.2 V or VIN ≥ VDD − 0.2 V, CE1 = CE2 ≥ VDD − 0.2 V, IOUT = 0 mA 200 100 70 Unit V mA µA Data Retention Setup Time tDRS VDD = VDD (27) at data retention entry 0 ns Data Retention Recovery Time tDRR VDD = VDD (27) after data retention 90 ns 0.5 V/µs ∆V/∆t VDD Voltage Transition Time 2. Data Retention Timing tDRS tDRR 3.5 V VDD ∆V/∆t ∆V/∆t 2.7 V CE2 2.1 V CE1 CE1 = CE2 ≥ VDD - 0.2 V or VIH (23) Min 0.4 V VSS Data Retention Mode Data bus must be in High-Z at data retention entry. 23 MB82D01171A-80/80L/80LL/85/85L/85LL/90/90L/90LL ■ ORDERING INFORMATION Part Number 24 Package Remarks MB82D01171A-80PBT 48-ball plastic FBGA 0.8 mm pitch (BGA-48P-M16) tCE = 80 ns Max, IDDS1 = 200 µA Max Flash Compatible Package MB82D01171A-80LPBT 48-ball plastic FBGA 0.8 mm pitch (BGA-48P-M16) tCE = 80 ns Max, IDDS1 = 100 µA Max Flash Compatible Package MB82D01171A-80LLPBT 48-ball plastic FBGA 0.8 mm pitch (BGA-48P-M16) tCE = 80 ns Max, IDDS1 = 70 µA Max Flash Compatible Package MB82D01171A-85PBT 48-ball plastic FBGA 0.8 mm pitch (BGA-48P-M16) tCE = 85 ns Max, IDDS1 = 200 µA Max Flash Compatible Package MB82D01171A-85LPBT 48-ball plastic FBGA 0.8 mm pitch (BGA-48P-M16) tCE = 85 ns Max, IDDS1 = 100 µA Max Flash Compatible Package MB82D01171A-85LLPBT 48-ball plastic FBGA 0.8 mm pitch (BGA-48P-M16) tCE = 85 ns Max, IDDS1 = 70 µA Max Flash Compatible Package MB82D01171A-90PBT 48-ball plastic FBGA 0.8 mm pitch (BGA-48P-M16) tCE = 90 ns Max, IDDS1 = 200 µA Max Flash Compatible Package MB82D01171A-90LPBT 48-ball plastic FBGA 0.8 mm pitch (BGA-48P-M16) tCE = 90 ns Max, IDDS1 = 100 µA Max Flash Compatible Package MB82D01171A-90LLPBT 48-ball plastic FBGA 0.8 mm pitch (BGA-48P-M16) tCE = 90 ns Max, IDDS1 = 70 µA Max Flash Compatible Package MB82D01171A-80PBN 48-ball plastic FBGA 0.75 mm pitch (BGA-48P-M18) tCE = 80 ns Max, IDDS1 = 200 µA Max SRAM Compatible Package MB82D01171A-80LPBN 48-ball plastic FBGA 0.75 mm pitch (BGA-48P-M18) tCE = 80 ns Max, IDDS1 = 100 µA Max SRAM Compatible Package MB82D01171A-80LLPBN 48-ball plastic FBGA 0.75 mm pitch (BGA-48P-M18) tCE = 80 ns Max, IDDS1 = 70 µA Max SRAM Compatible Package MB82D01171A-85PBN 48-ball plastic FBGA 0.75 mm pitch (BGA-48P-M18) tCE = 85 ns Max, IDDS1 = 200 µA Max SRAM Compatible Package MB82D01171A-85LPBN 48-ball plastic FBGA 0.75 mm pitch (BGA-48P-M18) tCE = 85 ns Max, IDDS1 = 100 µA Max SRAM Compatible Package MB82D01171A-85LLPBN 48-ball plastic FBGA 0.75 mm pitch (BGA-48P-M18) tCE = 85 ns Max, IDDS1 = 70 µA Max SRAM Compatible Package MB82D01171A-90PBN 48-ball plastic FBGA 0.75 mm pitch (BGA-48P-M18) tCE = 90 ns Max, IDDS1 = 200 µA Max SRAM Compatible Package MB82D01171A-90LPBN 48-ball plastic FBGA 0.75 mm pitch (BGA-48P-M18) tCE = 90 ns Max, IDDS1 = 100 µA Max SRAM Compatible Package MB82D01171A-90LLPBN 48-ball plastic FBGA 0.75 mm pitch (BGA-48P-M18) tCE = 90 ns Max, IDDS1 = 70 µA Max SRAM Compatible Package MB82D01171A-80/80L/80LL/85/85L/85LL/90/90L/90LL ■ PACKAGE DIMENSIONS 48-ball plastic FBGA (BGA-48P-M16) +0.15 1.05 –0.10 +.006 .041 –.004 9.00±0.10(.354±.004) (Mounting height) (5.60(.220)) 0.36±0.10 (Stand off) (.014±.004) 0.80(.031) TYP 6 5 6.00±0.10 (.236±.004) 4 (4.00(.157)) 3 2 1 0.80(.031) TYP INDEX AREA H G F E D C B 48-Ø0.45±0.10 (48-Ø.018±.004) A 0.08(.003) M 0.20(.008) S S 0.10(.004) C 2000 FUJITSU LIMITED B48016S-1c-1 Dimensions in mm (inches) (Continued) 25 MB82D01171A-80/80L/80LL/85/85L/85LL/90/90L/90LL (Continued) 48-ball plastic FBGA (BGA-48P-M18) +0.15 1.05 –0.10 +.006 (Mounting height) .041 –.004 9.00±0.10(.354±.004) (5.25(.207)) 0.25±0.10 (.010±.004) (Stand off) 0.75(.030) TYP 6 5 6.00±0.10 (.236±.004) 4 (3.75(.148)) 3 2 1 0.75(.030) TYP INDEX AREA H G F E D C B A 48-ø0.35±0.10 (48-ø.014±.004) INDEX MARK 0.08(.003) M 0.20(.008) S S 0.10(.004) S C 2001 FUJITSU LIMITED B48018S-c-1-1 Dimensions in mm (inches) 26 MB82D01171A-80/80L/80LL/85/85L/85LL/90/90L/90LL FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. 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Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. F0112 FUJITSU LIMITED Printed in Japan