CMOS LSI No. 5485 LC665304A, 665306A, 665308A, 665312A, 665316A Four-Bit Single-Chip Microcontrollers with 4, 6, 8, 12, and 16 KB of On-Chip ROM Preliminary 3149-DIP48S 0.25 [LC665304A/665306A/665308A/665312A/665316A] 25 1 24 0.48 1.05 2.53 1.78 5.1max 3.8 46.0 0.51min 4.25 15.24 13.8 48 SANYO: DIP48S unit: mm 3156-QFP48E [LC665304A/665306A/665308A/665312A/665316A] 1.5 1.6 17.2 1.5 36 1.0 14.0 1.6 1.5 25 0.15 24 37 1.0 • On-chip ROM capacitiy of 4, 6, 8, 12, and 16 kilobytes, and an on-chip RAM capacity of 512 × 4 bits. • Fully supports the LC66000 Series common instruction set (128 instructions). • I/O ports: 42 pins • A sub-oscillator circuit can be used (option) This circuit allows power dissipation to be reduced by operating at lower speeds. • 8-bit serial interface: two circuits (can be connected in cascade to form a 16-bit interface) • Instruction cycle time: 0.95 to 10 µs (at 3 to 5.5 V) • Powerful timer functions and prescalers — Time limit timer, event counter, pulse width measurement, and square wave output using a 12-bit timer. — Time limit timer, event counter, PWM output, and square wave output using an 8-bit timer. — Time base function using a 12-bit prescaler. • Powerful interrupt system with 8 interrupt factors and 8 interrupt vector locations. — External interrupts: 3 factors/3 vector locations — Internal interrupts: 5 factors/5 vector locations • Flexible I/O functions 16-value comparator inputs, 20-mA drive outputs, inverter circuits, pull-up and open-drain circuits selectable as options. • Optional runaway detection function (watchdog timer) • 8-bit I/O functions • Power saving functions using halt and hold modes. • Packages: DIP48S, QIP48E (QFP48E) unit: mm 1.5 Features and Functions Package Dimensions 17.2 14.0 The LC665304A, LC665306A, LC665308A, LC665312A, and LC665316A are 4-bit CMOS microcontrollers that integrate on a single chip all the functions required in a system controller, including ROM, RAM, I/O ports, a serial interface, 16-value comparator inputs, timers, interrupt functions, and an optional sub-oscillator circuit. These microcontrollers are available in a 48-pin package. • Evaluation LSIs: LC66599 (evaluation chip) + EVA800/850-TB662YXX2 LC66E5316(on-chip EPROM microcontroller) 48 13 12 1 0.1 2.70 (STAND OFF) 0.35 3.0max Overview 0.8 15.6 SANYO: QFP48E SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN 22897HA (OT) No. 5485-1/26 LC665304A, 665306A, 665308A, 665312A, 665316A Series Organization Type No. No. of pins ROM capacity RAM capacity Package LC66304A/306A/308A 42 4 K/6 K/8 KB 512 W DIP42S QFP48E LC66404A/406A/408A 42 4 K/6 K/8 KB 512 W DIP42S QFP48E LC66506B/508B/512B/516B 64 6 K/8 K/12 K/16 KB 512 W DIP64S QFP64A LC66354A/356A/358A 42 4 K/6 K/8 KB 512 W DIP42S QFP48E LC66354S/356S/358S 42 4 K/6 K/8 KB 512 W QFP44M Features Normal versions 4.0 to 6.0 V/0.92 µs Low-voltage versions 2.2 to 5.5 V/3.92 µs LC66556A/558A/562A/566A 64 6 K/8 K/12 K/16 KB 512 W DIP64S QFP64E LC66354B/356B/358B 42 4 K/6 K/8 KB 512 W DIP42S QFP48E LC66556B/558B/562B/566B 64 6 K/8 K/12 K/16 KB 512 W DIP64S QFP64E Low-voltage high-speed versions 3.0 to 5.5 V/0.92 µs LC66354C/356C/358C 42 4 K/6 K/8 KB 512 W DIP42S QFP48E 2.5 to 5.5 V/0.92 µs LC662104A/06A/08A 30 4 K/6 K/8 KB 384 W DIP30SD MFP30S LC662304A/06A/08A/12A/16A 42 4 K/6 K/8 K/12 K/16 KB 512 W DIP42S QFP48E LC662508A/12A/16A 64 8 K/12 K/16 KB 512 W DIP64S QFP64E LC665304A/06A/08A/12A/16A 48 4 K/6 K/8 K/12 K/16 KB 512 W DIP48S QFP48E LC66E308 42 EPROM 8 KB 512 W DIC42S with window QFC48 with window LC66P308 42 OTPROM 8 KB 512 W DIP42S QFP48E DIC42S with window QFC48 with window LC66E408 42 EPROM 8 KB 512 W LC66P408 42 OTPROM 8 KB 512 W DIP42S QFP48E QFC64 with window LC66E516 64 EPROM 16 KB 512 W DIC64S with window LC66P516 64 OTPROM 16 KB 512 W DIP64S QFP64E LC66E2108* 30 EPROM 8 KB 384 W LC66E2316 42 EPROM 16 KB 512 W DIC42S with window QFC48 with window LC66E2516 64 EPROM 16 KB 512 W DIC64S with window QFC64 with window LC66E5316 52/48 EPROM 16 KB 512 W DIC52S with window QFC48 with window LC66P2108* 30 OTPROM 8 KB 384 W DIP30SD MFP30S LC66P2316* 42 OTPROM 16 KB 512 W DIP42S QFP48E LC66P2516 64 OTPROM 16 KB 512 W DIP64S QFP64E LC66P5316 48 OTPROM 16 KB 512 W DIP48S QFP48E On-chip DTMF generator versions 3.0 to 5.5 V/0.95 µs Dual oscillator support 3.0 to 5.5 V/0.95 µs Window and OTP evaluation versions 4.5 to 5.5 V/0.92 µs Window evaluation versions 4.5 to 5.5 V/0.92 µs OTP 4.0 to 5.5 V/0.95 µs Note: * Under development No. 5485-2/26 LC665304A, 665306A, 665308A, 665312A, 665316A Pin Assignments DIP48S P20/SI0 P21/SO0 P22/SCK0 P23/INT0 P30/INT1 P31/POUT0 P32/POUT1 VSS OSC1 OSC2 VDD RES PE0/XT1 PE1/XT2 TEST P33/HOLD P40/INV0I P41/INV0O P42/INV1I P43/INV1O P50 P51 P52 P53/INT2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 LC665304A 5306A 5308A 5312A 5316A 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 P13 P12 P11 P10 P03 P02 P01 P00 PD3/AN4/INV4O PD2/AN3/INV4I PD1/AN2/INV3O PD0/AN1/INV3I PC3/INV2O PC2/INV2I PC1 PC0 P83 P82 P81/DS1 P80/DS0 P63/PIN1 P62/SCK1 P61/SO1 P60/SI1 P01 P00 PD3/AN4/INV4O PD2/AN3/INV4I PD1/AN2/INV3O PD0/AN1/INV3I PC3/INV2O PC2/INV2I PC1 PC0 P83 P82 QFP48E 36 35 34 33 32 31 30 29 28 27 26 25 37 24 38 23 39 22 40 21 LC665304A 41 20 5306A 42 19 5308A 43 18 5312A 44 17 5316A 45 16 46 15 47 14 48 13 1 2 3 4 5 6 7 8 9 10 11 12 P32/POUT1 VSS OSC1 OSC2 VDD RES PE0/XT1 PE1/XT2 TEST P33/HOLD P40/INV0I P41/INV0O P02 P03 P10 P11 P12 P13 P20/S10 P21/SO0 P22/SCK0 P23/INT0 P30/INT1 P31/POUT0 P81/DS1 P80/DS0 P63/PIN1 P62/SCK1 P61/SO1 P60/SI1 P53/INT2 P52 P51 P50 P43/INV1O P42/INV1I Top view We recommend the use of reflow soldering techniques to solder-mount QFP packages. Please consult with your Sanyo representative for details on process conditions if the package itself is to be directly immersed in a dip-soldering bath (dip-soldering techniques). No. 5485-3/26 LC665304A, 665306A, 665308A, 665312A, 665316A System Block Diagram RAM STACK (512W) RES TEST OSC1 ROM 4K/6K/8K/12K/16KB C FLAG SYSTEM CONTROL E DD DD SP M P P P P R HL XY OSC2 HOLD E Z ALU A PC XT1 XT2 AN1 to 4 ADC PE PD MPX PRESCALER TIMER0 POUT0 SI0 SO0 SCK0 INT0 SERIAL I/O 0 MPX INT1, INT2 INTERRUPT CONTROL MPX SI1 SO1 SCK1 PIN1, POUT1 SERIAL I/O 1 TIMER1 PC INVxO P0 P1 P2 P3 P4 P5 P6 INVxI (x=0 to 4) P8 DS1 DS0 Differences between the LC6653XX Series and the LC663XX Series Item LC6630X Series (Including the LC66599 evaluation chip) LC6635XB Series LC6653XX Series System differences • Hardware wait time (number of cycles) when hold mode is cleared 65536 cycles About 64 ms at 4 MHz (Tcyc = 1 µs) 16384 cycles About 16 ms at 4 MHz (Tcyc = 1 µs) 16384 cycles About 16 ms at 4 MHz (Tcyc = 1 µs) Set to FFC. Set to FFC. • Value of timer 0 after a reset (Including the value after hold mode Set to FF0. is cleared) • Inverter array None (Tools are handled with external devices.) None Yes • Buffer array (data shaper circuit) None (Tools are handled with external devices.) None Yes • Sub-oscillator None None Yes (option) • Three-value inputs/comparator inputs Yes Yes Only a 16-value comparator • Three-state output from P31 and P32 None None Yes • Using P0 to clear halt mode In 4-bit groups In 4-bit groups Can be specified for each bit. • External extended interrupts None for INT3, INT4, and INT5. (Tools are handled with external devices.) None for INT3, INT4, and INT5. None for INT3, INT4, and INT5. • Other P53 functions Shared with INT2 (Tools are handled with external devices.) Shared with INT2 Shared with INT2 (The logic is inverted.) Differences in main characteristics • Operating power-supply voltage and operating speed (cycle time) • LC66304A/306A/308A 4.0 to 6.0 V/0.92 t 10 µs • LC66E308/P308 4.5 to 5.5 V/0.92 to 10 µs • 3.0 to 5.5 V/0.92 to 10 µs • LC6635XA 2.2 to 5.5 V/3.92 to 10 µs 3.0 to 5.5 V/1.96 to 10 µs • 3.0 to 5.5 V/0.95 to 10 µs (When the main oscillator is operating) • 3.0 to 5.5 V/25 to 127 µs (When the sub-oscillator is operating) • Pull-up resistors P0, P1, P4, and P5: about 3 to 10 kΩ P0, P1, P4, and P5: about 3 to 10 kΩ • Port voltage handling • P2 to P6 and PC: 15-V handling • P0, P1, PD, PE: Normal voltage handling • P2 to P6 and PC: 15-V handling • P0, P1, PD, PE: Normal voltage handling P0, P1, P4, and P5: about 100 kΩ All ports: normal voltage handling (7-V handling provided) For other differences and details, see the data sheets for the individual products. No. 5485-4/26 LC665304A, 665306A, 665308A, 665312A, 665316A Pin Function Overview Pin P00 P01 P02 P03 P10 P11 P12 P13 P20/SI0 P21/SO0 P22/SCK0 P23/INT0 P30/INT1 P31/POUT0 P32/POUT1 P33/HOLD P40/INV0I P41/INV0O P42/INV1I P43/INV1O I/O I/O I/O I/O I/O Overview Output driver type Options I/O ports P00 to P03 • Input or output in 4-bit or 1-bit units • P00 to P03 support the halt mode control function (This function can be specified in bit units.) • Pch: Pull-up MOS type • Nch: Intermediate sink current type • Pull-up MOS or Nch OD output • Output level on reset I/O ports P10 to P13 Input or output in 4-bit or 1-bit units • Pch: Pull-up MOS type • Nch: Intermediate sink current type • Pull-up MOS or Nch OD output • Output level on reset I/O ports P20 to P23 • Input or output in 4-bit or 1-bit units • P20 is also used as the serial input SI0 pin. • P21 is also used as the serial output SO0 pin. • P22 is also used as the serial clock SCK0 pin. • P23 is also used as the INT0 interrupt request pin, and also as the timer 0 event counting and pulse width measurement input. I/O ports P30 to P32 • Input or output in 3-bit or 1-bit units • P30 is also used as the INT1 interrupt request. • P31 is also used for the square wave output from timer 0. • P32 is also used for the square wave and PWM output from timer 1. • P31 and P32 also support 3-state outputs. I Hold mode control input • Hold mode is set up by the HOLD instruction when HOLD is low. • In hold mode, the CPU is restarted by setting HOLD to the high level. • This pin can be used as input port P33 along with P30 to P32. • When the P33/HOLD pin is at the low level, the CPU will not be reset by a low level on the RES pin. Therefore, applications must not set P33/HOLD low when power is first applied. I/O I/O ports P40 to P43 • Input or output in 4-bit or 1-bit units • Input or output in 8-bit units when used in conjunction with P50 to P53. • Can be used for output of 8-bit ROM data when used in conjunction with P50 to P53. • Dedicated inverter circuit (option) • Pch: CMOS type • Nch: Intermediate sink current type • Nch: +7-V handling when OD option selected • Pch: CMOS type • Nch: Intermediate sink current type • Nch: +7-V handling when OD option selected • Pch: Pull-up MOS type • CMOS type when the inverter circuit option is selected • Nch: Intermediate sink current type State after a Standby mode reset operation Hold mode: Output off High or low (option) Halt mode: Output retained Hold mode: Output off High or low (option) Halt mode: Output retained Hold mode: Output off CMOS or Nch OD output H Halt mode: Output retained Hold mode: Output off CMOS or Nch OD output H Halt mode: Output retained • Pull-up MOS or Nch OD output • Output level on reset • Inverter circuit High or low or inverter I/O (option) Hold mode: Port output off, inverter output off Halt mode: Port output retained, inverter output continues Continued on next page. No. 5485-5/26 LC665304A, 665306A, 665308A, 665312A, 665316A Pin P50 P51 P52 P53/INT2 P60/SI1 P61/SO1 P62/SCK1 P63/PIN1 P80/DS0 P81/DS1 P82 P83 PC0 PC1 PC2/INV2I PC3/INV2O PD0/AN1/ INV3I PD1/AN2/ INV3O PD2/AN3 INV4I PD3/AN4/ INV4O PE0/XT1 PE1/XT2 I/O Overview I/O I/O ports P50 to P53 • Input or output in 4-bit or 1-bit units • Input or output in 8-bit units when used in conjunction with P40 to P43. • Can be used for output of 8-bit ROM data when used in conjunction with P40 to P43. • P53 is also used as the INT2 interrupt request. • Pch: Pull-up MOS type • Nch: Intermediate sink current type I/O ports P60 to P63 • Input or output in 4-bit or 1-bit units • P60 is also used as the serial input SI1 pin. • P61 is also used as the serial output SO1 pin. • P62 is also used as the serial clock SCK1 pin. • P63 is also used for the event count input to timer 1. • Pch: MOS type • Nch: Intermediate sink current type • Nch: +7-V handling when OD option selected (P61 and P63 only) I/O O I/O I I Dedicated output ports P80 to P83 • Output in 4-bit or 1-bit units • The contents of the output latch are input using input instructions. • P80 is a buffer input or a zero-cross buffer input and P81 is a buffer input (options). Output driver type • Pch: CMOS type • Nch: Intermediate sink current type I/O ports PC0 to PC3 • Output in 4-bit or 1-bit units • Dedicated inverter circuits (option) • Pch: CMOS type • Nch: Intermediate sink current type Dedicated input ports PD0 to PD3 • Can be switched in software to function as 16-value analog inputs. • Dedicated inverter circuits (option) • Inverter circuits can be selected as options. • Pch: CMOS type • Nch: Intermediate sink current type Dedicated input ports and sub-oscillator connections Options • Pull-up MOS or Nch OD output • Output level on reset State after a Standby mode reset operation Hold mode: Output off High or low (option) Halt mode: Output retained Hold mode: Output off • CMOS or Nch OD output H Halt mode: Output retained • CMOS or Pch OD output • Output level at reset • Buffer circuit • Zero-cross detector buffer circuit • CMOS or Nch OD output • Inverter circuit Inverter circuit Sub-oscillator/port PE selection Hold mode: Port output off, buffer output off High or low Buffered I/O (option) Halt mode: Port output retained, buffer output continues with the buffer resistor off. Hold mode: Port output off, inverter output off H Normal input or inverter I/O (option) Selected as an option Halt mode: Port output retained, inverter output continues. Inverter: • Hold mode: Output off • Halt mode: Output continues Suboscillator: Hold mode: Oscillator stopped Halt mode: Oscillator operates Continued on next page. No. 5485-6/26 LC665304A, 665306A, 665308A, 665312A, 665316A Continued from preceding page. Pin I/O OSC1 I System clock oscillator connections OSC2 O When an external clock is used, leave OSC2 open and connect the clock signal to OSC1. RES I System reset input When the P33/HOLD pin is at the high level, a low level input to the RES pin will initialize the CPU. TEST I CPU test pin This pin must be connected to VSS during normal operation. VDD VSS Overview Output driver type State after a Standby mode reset operation Options Ceramic oscillator or external clock selection Hold mode: Oscillator stopped Selected as an option Halt mode: Oscillator operates Power supply pins Note: Pull-up MOS type: The output circuit includes a MOS transistor that pulls the pin up to VDD. CMOS output: Complementary output. OD output: Open-drain output. User Options 1. Port 0, 1, 4, 5, and 8 output level at reset option The output levels at reset for I/O ports 0, 1, 4, 5, and 8, in independent 4-bit groups, can be selected from the following two options. Option Conditions and notes 1. Output high at reset The four bits of ports 0, 1, 4, 5, or 8 are set in a group 2. Output low at reset The four bits of ports 0, 1, 4, 5, or 8 are set in a group 2. Oscillator circuit options • Main clock Option Circuit OSC1 1. External clock 2. Ceramic oscillator Conditions and notes The input has Schmitt characteristics C1 OSC1 Ceramic oscillator C2 OSC2 Note: There is no RC oscillator option. • Sub-clock Option Circuit Conditions and notes DSB 1. Ports PE0 and PE1 Input data 2 Sub-oscillator (crystal oscillator) C1 XT1 Crystal oscillator C2 XT2 No. 5485-7/26 LC665304A, 665306A, 665308A, 665312A, 665316A 3. Watchdog timer option A runaway detection function (watchdog timer) can be selected as an option. 4. Port output type options • The output type of each bit (pin) in ports P0, P1, P2, P3 (except for the P33/HOLD pin), P4, P5, P6, and PC can be selected individually from the following two options. Option Circuit Conditions and notes Output data 1. Open-drain output Input data The port P2, P3, P5, and P6 inputs have Schmitt characteristics. DSB Output data 2. Output with built-in pull-up resistor Input data The port P2, P3, P5, and P6 inputs have Schmitt characteristics. The CMOS outputs (ports P2, P3, P6, and PC) and the pull-up MOS outputs (P0, P1, P4, and P5) are distinguished by the drive capacity of the p-channel transistor. DSB • One of the following two options can be selected for P8, in bit units. Option 1. Open-drain output Circuit Conditions and notes Output data DSB Output data 2. Output with built-in pulldown resistor (CMOS output) DSB No. 5485-8/26 LC665304A, 665306A, 665308A, 665312A, 665316A 5. Inverter array circuit option One of the following options can be selected for each of the following port sets: P40/P41, P42/P43, PC2/PC3, PD0/PD1, and PD2/PD3. (PDs do not use option 1 because they are dedicated to inputs) Option Circuit Conditions and notes Output data Input data When the open-drain output type is selected DSB 1. Normal port I/O circuit Output data Input data When the built-in pull-up resistor output type is selected The CMOS outputs (PC) and the pull-up MOS outputs (P4) are distinguished by the drive capacity of the p-channel transistor. DSB Input Output data high Input data DSB 2. Inverter I/O circuit Output Output data high If this option is selected, The I/O circuit is disabled by the DSB signal. Also note that the open-drain port output type option and the high level at reset option must be selected. Input data DSB No. 5485-9/26 LC665304A, 665306A, 665308A, 665312A, 665316A 6. Buffer array circuit option In addition to normal port output, one of the following two options may also be selected for P80 and P81. Option Circuit Conditions and notes DSB Output data When the open-drain output type is selected 1. Normal port output Output data When the built-in pull-down resistor output type is selected (CMOS output) DSB Output data low P80 If this option is selected, the I/O circuit is disabled by the DSB signal. Also note that the open-drain port output type option and the high level at reset option must be selected. 2. Buffer input (P80) and buffer output (P81) circuits P81 DSB Output data low Output data low P80 If this option is selected, the I/O circuit is disabled by the DSB signal. Also note that the open-drain port output type option and the high level at reset option must be selected. 3. Buffer input (P80) and buffer output (P81) circuits with built-in zero-cross detection circuits P81 DSB Output data low No. 5485-10/26 LC665304A, 665306A, 665308A, 665312A, 665316A LC665316 Series Option Data Area and Definitions ROM area 3FF0H Bit P5 6 P4 Sub-oscillator option 0 = port PE, 1 = crystal oscillator Oscillator option 0 = external clock, 1 = ceramic oscillator 3 P8 2 P1 1 P0 Output level at reset Watchdog timer option 7 P13 6 P12 5 P11 4 P10 3 P03 2 P02 1 P01 7 3FF3H 0 = high level, 1 = low level 4 0 3FF2H Output level at reset Option/data relationship 5 0 3FF1H Option specified 7 0 = low level, 1 = high level 0 = none, 1 = yes (present) Output type 0 = OD, 1 = PU Output type 0 = OD, 1 = PU P00 Unused 6 P32 5 P31 4 P30 3 P23 2 P22 1 P21 0 P20 7 P53 6 P52 5 P51 4 P50 3 P43 2 P42 1 P41 0 P40 This bit must be set to 0. Output type 0 = OD, 1 = PU Output type 0 = OD, 1 = PU Output type 0 = OD, 1 = PU Output type 0 = OD, 1 = PU 7 6 5 3FF4H Unused This bit must be set to 0. 4 3 P63 2 P62 1 P61 0 P60 Output type 0 = OD, 1 = PU 7 6 5 3FF5H Unused This bit must be set to 0. 4 3 P83 2 P82 1 P81 0 P80 Output type 0 = OD, 1 = PD 7 6 5 3FF6H Unused This bit must be set to 0. Unused This bit must be set to 0. 4 3 2 1 0 Continued on next page. LC665304A, 665306A, 665308A, 665312A, 665316A Continued from preceding page. ROM area Bit Option specified Option/data relationship 7 6 5 3FF7H This bit must be set to 0. 4 3 PC3 2 PC2 1 PC1 0 3FF8H Unused Output type 0 = OD, 1 = PU PC0 7 Unused This bit must be set to 1. 6 Buffer output 0 = used, 1 = none 5 Buffer output with zero-cross bias input 0 = used, 1 = none 4 PD3 3 PD1 2 PC3 1 P43 0 P41 Inverter output 0 = inverter output, 1 = none 7 6 5 3FF9H Unused This bit must be set to 0. Unused This bit must be set to 0. Unused This bit must be set to 0. Unused This bit must be set to 0. Unused This bit must be set to 0. Unused This bit must be set to 0. Unused This bit must be set to 0. Unused This bit must be set to 0. 4 3 2 1 0 7 6 5 3FFAH 4 3 2 1 0 7 6 5 3FFBH 4 3 2 1 0 7 6 5 3FFCH 4 3 2 1 0 7 6 5 3FFDH 4 3 Reserved. Must be set to predefined data values. This data is generated by the assembler. If the assembler is not used, set this data to ‘00’. 2 1 0 Continued on next page. No. 5485-12/26 LC665304A, 665306A, 665308A, 665312A, 665316A Continued from preceding page. ROM area Bit Option specified Option/data relationship 7 6 5 4 3FFEH 3 Reserved. Must be set to predefined data values. This data is generated by the assembler. If the assembler is not used, set this data to ‘00’. Reserved. Must be set to predefined data values. This data is generated by the assembler. If the assembler is not used, set this data to ‘00’. 2 1 0 7 6 5 4 3FFFH 3 2 1 0 Specifications Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V Parameter Maximum supply voltage Input voltage Symbol VDD max VIN1 VIN2 Output voltage Output current per pin Total pin current Allowable power dissipation Conditions Ratings Unit Note VDD –0.3 to +7.0 V P2, P3 (except for the P33/HOLD pin), P61, and P63 –0.3 to +7.0 V 1 –0.3 to VDD + 0.3 V 2 –0.3 to +7.0 V 1 –0.3 to VDD + 0.3 V 2 20 mA 3 All other inputs VOUT1 P2, P3 (except for the P33/HOLD pin), P61, and P63 VOUT2 All other inputs ION1 P0, P1, P2, P3 (except for the P33/HOLD pin), P4, P5, P6, P8, PC, PD1, PD3 –IOP1 P0, P1, P4, P5 2 mA 4 –IOP2 P2, P3 (except for the P33/HOLD pin), P6,P8, and PC 4 mA 4 –IOP3 P41, P43, PC3, PD1, PD3, P81 10 mA 4 Σ ION1 P4, P5, P6, P8, PC 75 mA 3 Σ ION2 P0, P1, P2, P3 (except for the P33/HOLD pin), PD1, PD3 75 mA 3 Σ IOP1 P4, P5, P6, P8, PC 25 mA 4 Σ IOP2 P0, P1, P2, P3 (except for the P33/HOLD pin), PD1, PD3 25 mA 4 Pd max Ta = –30 to +70°C: DIP48S (QFP48E) 5 600 (430) mW Operating temperature Topr –30 to +70 °C Storage temperature Tstg –55 to +125 °C Note: 1. Applies to pins with open-drain output specifications. For pins with other than open-drain output specifications, the ratings in the pin column for that pin apply. 2. For the oscillator input and output pins, levels up to the free-running oscillation level are allowed. 3. Sink current (Applies to P8 and PD when either the CMOS output specifications or the inverter array specifications have been selected.) 4. Source current (Applies to all pins except P8 and PD for which the pull-up output specifications, the CMOS output specifications, or the inverter array specifications have been selected. Applies to PD pins for which the inverter array specifications have been selected.) Contact your Sanyo representative for the electrical characteristics when the inverter array or buffer array options are specified. 5. We recommend the use of reflow-soldering techniques to solder-mount QFP packages. Please consult with your Sanyo representative for details on process conditions if the package itself is to be directly immersed in a dip-soldering bath (dip-soldering spray techniques). No. 5485-13/26 LC665304A, 665306A, 665308A, 665312A, 665316A Allowable Operating Ranges at Ta = –30 to +70°C, VSS = 0 V, VDD = 3.0 to 5.5 V, unless otherwise specified. Parameter Operating supply voltage Memory retention supply voltage Input high-level voltage Input low-level voltage Operating frequency (instruction cycle time) Symbol VDD Conditions min typ max Unit Note VDD 3.0 5.5 V VDDH VDD: During hold mode 1.8 5.5 V VIH1 P2, P3 (except for the P33/HOLD pin), P61, and P63: N-channel output transistor off 0.8 VDD +7.0 V 1 VIH2 P33/HOLD, P60, P62, RES, OSC1: N-channel output transistor off 0.8 VDD VDD V 1 VIH3 P0, P1, P4, P5, PC, PD, PE: N-channel output transistor off 0.8 VDD VDD V 2 VIL1 P2, P3 (except for the P33/HOLD pin), P6, RES, and OSC1: N-channel output transistor off VSS 0.2 VDD V 3 VIL2 P0, P1, P4, P5, PC, PD, PE, TEST: N-channel output transistor off VSS 0.2 VDD V 2 VIL3 P33/HOLD: VDD = 1.8 to 5.5 V VSS 0.2 VDD When the main oscillator is operating 0.4 (10) 4.20 (0.95) MHz (µs ) When the sub-oscillator is operating 30 (133) 100 (25) kHz (µs) 4.20 MHz fop (Tcyc) 32.768 (122) V [External clock input conditions] Frequency fext OSC1: Defined by Figure 1. Input the clock signal to OSC1 and leave OSC2 open. (External clock input must be selected as the oscillator circuit option.) Pulse width textH, textL OSC1: Defined by Figure 1. Input the clock signal to OSC1 and leave OSC2 open. (External clock input must be selected as the oscillator circuit option.) Rise and fall times textR, textF OSC1: Defined by Figure 1. Input the clock signal to OSC1 and leave OSC2 open. (External clock input must be selected as the oscillator circuit option.) 0.4 100 ns 30 ns Note: 1. Applies to pins with open-drain specifications. However, VIH2 applies to the P33/HOLD pin. When ports P2, P3, and P6 have CMOS output specifications they cannot be used as input pins. 2. PC port pins with CMOS output specifications cannot be used as input pins. Contact your Sanyo representative for the allowable operating ranges for P4, PC, and PD when the inverter array is used, and for P8 when the buffer array is used. 3. Applies to pins with open-drain specifications. However, VIL3 applies to the P33/HOLD pin. P2, P3, and P6 port pins with CMOS output specifications cannot be used as input pins. No. 5485-14/26 LC665304A, 665306A, 665308A, 665312A, 665316A Electrical Characteristics at Ta = –30 to +70°C, VSS = 0 V, VDD = 3.0 to 5.5 V unless otherwise specified. Parameter Symbol Input high-level current Input low-level current Unit Note 5.0 µA 1 IIH2 P0, P1, P4, P5, P6, PC, OSC1, RES, and P33/HOLD (Does not apply to PD, PE, PC2, PC3, P61, and P63.): VIN = VDD, with the output Nch transistor off 1.0 µA 1 IIH3 PD, PE, PC2, PC3: VIN = VDD, with the output Nch transistor off 1.0 µA 1 IIL1 Input ports other than PD, PE, PC2, and PC3: VIN = VSS, with the output Nch transistor off –1.0 µA 2 IIL2 PC2, PC3, PD, PE0: VIN = VSS, with the output Nch transistor off –1.0 µA 2 IIL4 PE1 (When used as a port; does not apply when the sub-oscillator option is selected.): VIN = VSS µA 1 V 3 IIH1 VOH1 Output high-level voltage Value of the output pull-up resistor min typ max 20 P2, P3 (except for the P33/HOLD pin), P6, P8, and PC: IOH = –1 mA VDD – 1.0 P2, P3 (except for the P33/HOLD pin), P6, P8, and PC: IOH = –0.1 mA VDD – 0.5 RPO P0, P1, P4, P5 150 kΩ VOL1 P0, P1, P2, P3, P4, P5, P6, P8, and PC (except for the P33/HOLD pin): IOL = 1.6 mA 0.4 V VOL2 P0, P1, P2, P3, P4, P5, P6, P8, and PC (except for the P33/HOLD pin): IOL = 8 mA 1.5 V IOFF1 P2, P3, P61, P63: VIN = +7 V 5.0 µA 6 IOFF2 Does not apply to P2, P3, P61, P63, and P8.: VIN = VDD 1.0 µA 6 IOFF3 P8: VIN = VSS µA 7 Output low-level voltage Output off leakage current Conditions P2, P3 (except for the P33/HOLD pin), P61, and P63: VIN = +7 V, with the output Nch transistor off 30 100 –1.0 4 5 [Schmitt characteristics] Hysteresis voltage VHyS High-level threshold voltage Vt H Low-level threshold voltage Vt L 0.1 VDD P2, P3, P5, P6, OSC1 (EXT), RES V 0.5 VDD 0.8 VDD V 0.2 VDD 0.5 VDD V [Ceramic oscillator] Oscillator frequency fCF OSC1, OSC2: Figure 2, 4 MHz Oscillator stabilization time fCFS Figure 3, 4 MHz 4.0 MHz 10.0 ms [Crystal oscillator] Oscillator frequency fXT XT1, XT2: Figure 2, when the sub-oscillator option is selected, 32 kHz Oscillator stabilization time fXTS Figure 3, when the sub-oscillator option is selected, 32 kHz 32.768 1.0 kHz 5.0 s [Serial clock] Cycle time Input Output Low-level and high-level Input pulse widths Output Rise an fall times Output tCKCY tCKL SCK0, SCK1: With the timing of Figure 4 and the test load of Figure 5. tCKH 0.9 µs 2.0 Tcyc 0.4 µs 1.0 Tcyc tCKR, tCKF 0.1 µs [Serial input] Data setup time tICK Data hold time tCKI SI0, SI1: With the timing of Figure 4. Stipulated with respect to the rising edge (↑) of SCK0 or SCK1. 0.3 µs 0.3 µs [Serial output] Output delay time tCKO SO0, SO1: With the timing of Figure 5 and the test load of Figure 5. Stipulated with respect to the falling edge (↓) of SCK0 or SCK1. 0.3 µs Continued on next page. No. 5485-15/26 LC665304A, 665306A, 665308A, 665312A, 665316A Continued from preceding page. Parameter Symbol Conditions min typ max Unit tIOH, tIOL INT0: Figure 6, conditions under which the INT0 interrupt can be accepted, conditions under which the timer 0 event counter or pulse width measurement input can be accepted 2 Tcyc tIIH, tIIL INT1: Figure 6, conditions under which the corresponding interrupt can be accepted 2 Tcyc PIN1 high and low-level pulse widths tPINH, tPINL PIN1: Figure 6, conditions under which the timer 1 event counter input can be accepted 2 Tcyc RES high and low-level pulse widths tRSH, tRSL RES: Figure 6, conditions under which reset can be applied. 3 Tcyc Operating current drain IDD OP Note [Pulse conditions] INT0 high and low-level High and low-level pulse widths for interrupt inputs other than INT0 Halt mode current drain Hold mode current drain IDDHALT IDDHOLD VDD: 4-MHz ceramic oscillator 4.0 8.0 VDD: 4-MHz ceramic oscillator, VDD = 3.0 to 4.0 V 3.0 5.0 VDD: 4-MHz external clock 4.0 8.0 VDD: 4-MHz ceramic oscillator 2.0 3.5 VDD: 4-MHz ceramic oscillator, VDD = 3.0 to 4.0 V 1.0 2.0 VDD: 4-MHz external clock 2.0 3.5 VDD: 32 kHz (main oscillator stopped), sub-oscillator: crystal 10 100 VDD: 32 kHz (main oscillator stopped), sub-oscillator: crystal, VDD = 3.0 to 4.0 V 10 50 0.01 10 mA 8 mA mA mA µA VDD: VDD = 1.8 to 5.5 V µA Note: 1. With the output Nch transistor off in shared I/O ports with the open-drain output specifications. These pins cannot be used as input pins if the CMOS output specifications are selected.When the port option is selected for PE. 2. With the output Nch transistor off in shared I/O ports with the open-drain output specifications. The rating for the pull-up output specification pins is stipulated in terms of the output pull-up current IPO. These pins cannot be used as input pins if the CMOS output specifications are selected. 3. With the output Nch transistor off for CMOS output specification pins. (Also applies when the Pch open-drain option is selected for P8.) 4. With the output Nch transistor off for pull-up output specification pins. 5. When CMOS output specifications are selected for P8. 6. With the output Nch transistor off for open-drain output specification pins. 7. With the output Pch transistor off for open-drain output specification pins. 8. Reset state Comparator Characteristics at Ta = –30 to +70°C, VSS = 0 V Parameter Symbol Conditions min typ max Unit Note ±1/2 ±1 LSB 1 Absolute precision VCECM AN1 to AN4: VDD = 3.0 to 5.5 V Threshold voltage VTHCM VDD = 3.0 to 5.5 V VSS VDD Input voltage VINCM AN1 to AN4: VDD = 3.0 to 5.5 V VSS VDD Conversion time TCCM V V VDD = 3.0 to 5.5 V 20 ms VDD = 4.0 to 5.5 V 30 µs Note: 1. Does not include the quantization error. VDD 0.8VDD OSC1 0.2VDD (OSC2) VSS External Clock OPEN textL textF textH textR 1/fext Figure 1 External Clock Input Waveform No. 5485-16/26 LC665304A, 665306A, 665308A, 665312A, 665316A VDD OSC1 C1 XT1 OSC2 Rd Ceramic oscillator C2 XT2 Operating VDD minimum value 0V OSC Rd C1 Crystal oscillatorI Stable oscillation C2 Oscillator unstable period tCFS Figure 3 Oscillator Stabilization Period Figure 2 Ceramic Oscillator Circuit Table 1 Guaranteed Ceramic Oscillator Constants External capacitor type External capacitor type 4 MHz (Murata Mfg. Co., Ltd.) CSA4.00MG C1 = 33 pF ± 10% 4 MHz (Kyocera Corporation) KBR4.0MS C1 = 33 pF ± 10% Built-in capacitor type 4 MHz (Murata Mfg Co., Ltd) CST4.00MG C2 = 33 pF ± 10% Rd = 220 Ω ± 5% Rd = 220 Ω ± 5% 4 MHz (Kyocera Corporation) KBR4.0MES C2 = 33 pF ± 10% Rd = 0 Ω Table 2 Guaranteed Crystal Oscillator Constants C1 = 18 pF ± 10% 32 kHz (Seiko Epson) C-002RX C2 = 18 pF ± 10% Rd = 470 kΩ ± 5% tCKCY tCKL SCK0 SCK1 0.2VDD (input) 0.4VDD (output) tCKR tCKH tCKF 0.8VDD (input) VDD-1 (output) tICK tCKI SI0 0.8VDD 0.2VDD SI1 R=1kΩ tCK0 SO0 SO1 TEST point VDD-1 0.4VDD C=50pF O Load Figure 5 Timing Figure 4 Serial I/O Timing tI0H tI1H tPINH tRSH 0.8VDD 0.2VDD tI0L tI1L tPINL tRSL OTE Figure 6 Input Timing for the INT0, INT1, INT2, PIN1, and RES pins No. 5485-17/26 LC665304A, 665306A, 665308A, 665312A, 665316A LC66XXXX Series Instruction Table (by function) Abbreviations: AC: Accumulator E: E register CF: Carry flag ZF: Zero flag HL: Data pointer DPH, DPL XY: Data pointer DPX, DPY M: Data memory M (HL): Data memory pointed to by the DPH, DPL data pointer M (XY): Data memory pointed to by the DPX, DPY auxiliary data pointer M2 (HL): Two words of data memory (starting on an even address) pointed to by the DPH, DPL data pointer SP: Stack pointer M2 (SP): Two words of data memory pointed to by the stack pointer M4 (SP): Four words of data memory pointed to by the stack pointer in: n bits of immediate data t2: Bit specification PCh: PCm: PCl: Fn: TIMER0: TIMER1: SIO: P: P (i4): INT: ( ), [ ]: ←: : : : +: –: —: t2 11 10 01 00 Bit 23 22 21 20 Bits 8 to 11 in the PC Bits 4 to 7 in the PC Bits 0 to 3 in the PC User flag, n = 0 to 15 Timer 0 Timer 1 Serial register Port Port indicated by 4 bits of immediate data Interrupt enable flag Indicates the contents of a location Transfer direction, result Exclusive or Logical and Logical or Addition Subtraction Taking the one's complement No. 5485-18/26 Instruction code Mnemonic D 7 D6 D5 D4 D3 D2 D1 D0 Number of bytes Number of cycles LC665304A, 665306A, 665308A, 665312A, 665316A Operation Description Affected status bits Note [Accumulator manipulation instructions] CLA Clear AC 1 0 0 0 0 0 0 0 1 1 AC ← 0 Clear AC to 0. (Equivalent to LAI 0.) ZF DAA Decimal adjust AC in addition 1 1 0 0 0 0 1 0 1 1 1 1 0 1 1 0 2 2 AC ← (AC) + 6 Add six to AC. (Equivalent to ADI 6.) ZF DAS Decimal adjust AC in subtraction 1 1 0 0 0 0 1 0 1 1 1 1 1 0 1 0 2 2 AC ← (AC) + 10 (Equivalent to ADI 0AH.) Add 10 to AC. ZF CLC Clear CF 0 0 0 1 1 1 1 0 1 1 CF ← 0 Clear CF to 0. CF STC Set CF 0 0 0 1 1 1 1 1 1 1 CF ← 1 Set CF to 1. CF ZF Has a vertical skip function. CMA Complement AC 0 0 0 1 1 0 0 0 1 1 AC ← (AC) Take the one’s complement of AC. IA Increment AC 0 0 0 1 0 1 0 0 1 1 AC ← (AC) + 1 Increment AC. ZF, CF DA Decrement AC 0 0 1 0 0 1 0 0 1 1 AC ← (AC) – 1 Decrement AC. ZF, CF Shift AC (including CF) right. CF CF, ZF RAR Rotate AC right through CF 0 0 0 1 0 0 0 0 1 1 AC3 ← (CF), ACn ← (ACn + 1), CF ← (AC0) RAL Rotate AC left through CF 0 0 0 0 0 0 0 1 1 1 AC0 ← (CF), ACn + 1 ← (ACn), CF ← (AC3) Shift AC (including CF) left. Transfer the contents of AC to E. TAE Transfer AC to E 0 1 0 0 0 1 0 1 1 1 E ← (AC) TEA Transfer E to AC 0 1 0 0 0 1 1 0 1 1 AC ← (E) Transfer the contents of E to AC. ZF XAE Exchange AC with E 0 1 0 0 0 1 0 0 1 1 (AC) ↔ (E) Exchange the contents of AC and E. [Memory manipulation instructions] IM Increment M 0 0 0 1 0 0 1 0 1 1 M (HL) ← [M (HL)] + 1 Increment M (HL). ZF, CF DM Decrement M 0 0 1 0 0 0 1 0 1 1 M (HL) ← [M (HL)] – 1 Decrement M (HL). ZF, CF IMDR i8 Increment M direct 1 1 0 0 I7 I6 I5 I4 0 1 1 1 I3 I2 I1 I0 2 2 M (i8) ← [M (i8)] + 1 Increment M (i8). ZF, CF DMDR i8 Decrement M direct 1 1 0 0 I7 I6 I5 I4 0 0 1 1 I3 I2 I1 I0 2 2 M (i8) ← [M (i8)] – 1 Decrement M (i8). ZF, CF SMB t2 Set M data bit 0 0 0 0 1 1 t1 t0 1 1 [M (HL), t2] ← 1 Set the bit in M (HL) specified by t0 and t1 to 1. RMB t2 Reset M data bit 0 0 1 0 1 1 t1 t0 1 1 [M (HL), t2] ← 0 Clear the bit in M (HL) specified by t0 and t1 to 0. ZF 0 0 0 0 0 1 1 0 1 1 AC ← (AC) + [M (HL)] Add the contents of AC and M (HL) as two’s complement values and store the result in AC. ZF, CF 1 1 0 0 I7 I6 I5 I4 1 0 0 1 I3 I2 I1 I0 2 Add the contents of AC and M (i8) as two’s complement AC ← (AC) + [M (i8)] values and store the result in AC. Add the contents of AC, M (HL) and C as two’s complement values and store the result in AC. ZF, CF [Arithmetic, logic and comparison instructions] AD Add M to AC ADDR i8 Add M direct to AC 2 ZF, CF ADC Add M to AC with CF 0 0 0 0 0 0 1 0 1 1 AC ← (AC) + [M (HL)] + (CF) ADI i4 Add immediate data to AC 1 1 0 0 0 0 1 0 1 1 1 1 I3 I2 I1 I0 2 2 AC ← (AC) + I3, I2, I1, I0 Add the contents of AC and the immediate data as two’s complement values and store the result in AC. ZF SUBC Subtract AC from M with CF 0 0 0 1 0 1 1 1 1 1 AC ← [M (HL)] – (AC) – (CF) Subtract the contents of AC and CF from M (HL) as two’s complement values and store the result in AC. ZF, CF ANDA And M with AC then store AC 0 0 0 0 0 1 1 1 1 1 AC ← (AC) [M (HL)] Take the logical and of AC and M (HL) and store the result in AC. ZF ORA Or M with AC then store AC 0 0 0 0 0 1 0 1 1 1 AC ← (AC) [M (HL)] Take the logical or of AC and M (HL) and store the result in AC. ZF CF will be zero if there was a borrow and one otherwise. Continued on next page. No. 5485-19/26 LC665304A, 665306A, 665308A, 665312A, 665316A Instruction code Mnemonic D 7 D6 D5 D4 D3 D2 D1 D0 Number of bytes Number of cycles Continued from preceding page. Operation Affected status bits Description Note [Arithmetic, logic and comparison instructions] EXL Exclusive or M with AC then store AC 0 0 0 1 0 1 0 1 1 1 AC ← (AC) [M (HL)] Take the logical exclusive or of AC and M (HL) and store the result in AC. ZF ANDM And M with AC then store M 0 0 0 0 0 0 1 1 1 1 M (HL) ← (AC) [M (HL)] Take the logical and of AC and M (HL) and store the result in M (HL). ZF ORM Or M with AC then store M 0 0 0 0 0 1 0 0 1 1 M (HL) ← (AC) [M (HL)] Take the logical or of AC and M (HL) and store the result in M (HL). ZF Compare the contents of AC and M (HL) and set or clear CF and ZF according to the result. CM Compare AC with M 0 0 0 1 0 1 1 0 1 1 [M (HL)] + (AC) + 1 Magnitude comparison [M (HL)] > (AC) [M (HL)] = (AC) [M (HL)] < (AC) CF ZF 0 1 1 ZF, CF 0 1 0 Compare the contents of AC and the immediate data I3 I2 I1 I0 and set or clear CF and ZF according to the result. CI i4 Compare AC with immediate data 1 1 0 0 1 0 1 0 1 1 1 1 I3 I2 I1 I0 2 2 I3 I2 I1 I0 + (AC) + 1 Magnitude comparison I3 I2 I1 I0 > AC I3 I2 I1 I0 = AC I3 I2 I1 I0 < AC CLI i4 CMB t2 Compare DPL with immediate data Compare AC bit with M data bit 1 1 0 0 1 0 1 1 1 1 1 1 I3 I2 I1 I0 2 CF ZF 0 1 1 ZF, CF 0 1 0 2 ZF ← 1 if (DPL) = I3 I2 I1 I0 ZF ← 0 if (DPL) ≠ I3 I2 I1 I0 Compare the contents of DPL with the immediate data. Set ZF if identical and clear ZF if not. ZF Compare the corresponding bits specified by t0 and t1 in AC and M (HL). Set ZF if identical and clear ZF if not. ZF 1 1 0 0 1 1 0 1 1 1 1 1 0 0 t1 t0 2 2 ZF ← 1 if (AC, t2) = [M (HL), t2] ZF← 0 if (AC, t2) ≠ [M (HL), t2] [Load and store instructions] LAE Load AC and E from M2 (HL) 0 1 0 1 1 1 0 0 1 1 AC ← M (HL), E ← M (HL + 1) Load the contents of M2 (HL) into AC, E. LAI i4 Load AC with immediate data 1 0 0 0 I3 I2 I1 I0 1 1 AC ← I3 I2 I1 I0 Load the immediate data into AC. ZF LADR i8 Load AC from M direct 1 1 0 0 I7 I6 I5 I4 0 0 0 1 I3 I2 I1 I0 2 2 AC ← [M (i8)] Load the contents of M (i8) into AC. ZF S Store AC to M 0 1 0 0 0 1 1 1 1 1 M (HL) ← (AC) Store the contents of AC into M (HL). SAE Store AC and E to M2 (HL) 0 1 0 1 1 1 1 0 1 1 M (HL) ← (AC) M (HL + 1) ← (E) Store the contents of AC, E into M2 (HL). LA reg Load AC from M (reg) 0 1 0 0 1 0 t0 0 1 1 AC ← [M (reg)] Has a vertical skip function Load the contents of M (reg) into AC. The reg is either HL or XY depending on t0. ZF reg T0 HL XY 0 1 Continued on next page. No. 5485-20/26 LC665304A, 665306A, 665308A, 665312A, 665316A Instruction code Mnemonic D 7 D6 D5 D4 D3 D2 D1 D0 Number of bytes Number of cycles Continued from preceding page. Operation Description Affected status bits Note [Load and store instructions] LA reg, I Load AC from M (reg) 0 1 0 0 then increment reg Load AC from M (reg) LA reg, D 0 1 0 1 then decrement reg XA reg Exchange AC with M (reg) Exchange AC with XA reg, I M (reg) then increment reg 0 1 0 0 0 1 0 0 1 0 t0 1 1 0 t0 1 1 1 t0 0 1 1 t0 1 1 1 1 1 2 2 1 2 AC ← [M (reg)] DPL ← (DPL) + 1 or DPY ← (DPY) + 1 Load the contents of M (reg) into AC. (The reg is either HL or XY.) Then increment the contents of either DPL or DPY. ZF The relationship between t0 and reg is the same as that for the LA reg instruction. ZF is set according to the result of incrementing DPL or DPY. AC ← [M (reg)] DPL ← (DPL) – 1 or DPY ← (DPY) – 1 Load the contents of M (reg) into AC. (The reg is either HL or XY.) Then decrement the contents of either DPL or DPY. ZF The relationship between t0 and reg is the same as that for the LA reg instruction. ZF is set according to the result of decrementing DPL or DPY. (AC) ↔ [M (reg)] Exchange the contents of M (reg) and AC. The reg is either HL or XY depending on t0. reg T0 HL XY 0 1 (AC) ↔ [M (reg)] DPL ← (DPL) + 1 or DPY ← (DPY) + 1 Exchange the contents of M (reg) and AC. (The reg is either HL or XY.) Then increment the contents of either DPL or DPY. The relationship between t0 and reg is the same as that for the XA reg instruction. Exchange the contents of M (reg) and AC. (The reg is either HL or XY.) Then decrement the contents of either DPL or DPY. The relationship between t0 and reg is the same as that for the XA reg instruction. Exchange AC with XA reg, D M (reg) then decrement reg 0 1 0 1 1 1 t0 1 1 2 (AC) ↔ [M (reg)] DPL ← (DPL) – 1 or DPY ← (DPY) – 1 XADR i8 Exchange AC with M direct 1 1 0 0 I7 I6 I5 I4 1 0 0 0 I3 I2 I1 I0 2 2 (AC) ↔ [M (i8)] Exchange the contents of AC and M (i8). LEAI i8 Load E & AC with immediate data 1 1 0 0 I7 I6 I5 I4 0 1 1 0 I3 I2 I1 I0 2 2 E ← I7 I6 I5 I4 AC ← I3 I2 I1 I0 Load the immediate data i8 into E, AC. RTBL Read table data from 0 1 0 1 program ROM 2 E, AC ← [ROM (PCh, E, AC)] Load into E, AC the ROM data at the location determined by replacing the lower 8 bits of the PC with E, AC. RTBLP Read table data from program ROM then 0 1 0 1 output to P4, 5 Output from ports 4 and 5 the ROM data at the location determined by replacing the lower 8 bits of the PC with E, AC. 1 0 1 0 1 1 0 0 0 1 2 Port 4, 5 ← [ROM (PCh, E, AC)] ZF ZF is set according to the result of incrementing DPL or DPY. ZF ZF is set according to the result of decrementing DPL or DPY. [Data pointer manipulation instructions] LDZ i4 Load DPH with zero and DPL with immediate data respectively 0 1 1 0 I3 I2 I1 I0 1 1 DPH ← 0 DPL ← I3 I2 I1 I0 Load zero into DPH and the immediate data i4 into DPL. LHI i4 Load DPH with immediate data 1 1 0 0 0 0 0 0 1 1 1 1 I3 I2 I1 I0 2 2 DPH ← I3 I2 I1 I0 Load the immediate data i4 into DPH. LLI i4 Load DPL with immediate data 1 1 0 0 0 0 0 1 1 1 1 1 I3 I2 I1 I0 2 2 DPL ← I3 I2 I1 I0 Load the immediate data i4 into DPL. LHLI i8 Load DPH, DPL with immediate data 1 1 0 0 I7 I6 I5 I4 0 0 0 0 I3 I2 I1 I0 2 2 DPH ← I7 I6 I5 I4 DPL ← I3 I2 I1 I0 Load the immediate data into DLH, DPL. LXYI i8 Load DPX, DPY with immediate data 1 1 0 0 I7 I6 I5 I4 0 0 0 0 I3 I2 I1 I0 2 2 DPX ← I7 I6 I5 I4 DPY ← I3 I2 I1 I0 Load the immediate data into DLX, DPY. Continued on next page. No. 5485-21/26 LC665304A, 665306A, 665308A, 665312A, 665316A Instruction code Mnemonic D 7 D6 D5 D4 D3 D2 D1 D0 Number of bytes Number of cycles Continued from preceding page. Operation Description Affected status bits Note [Data pointer manipulation instructions] IL Increment DPL 0 0 0 1 0 0 0 1 1 1 DPL ← (DPL) + 1 Increment the contents of DPL. ZF DL Decrement DPL 0 0 1 0 0 0 0 1 1 1 DPL ← (DPL) – 1 Decrement the contents of DPL. ZF IY Increment DPY 0 0 0 1 0 0 1 1 1 1 DPY ← (DPY) + 1 Increment the contents of DPY. ZF DY Decrement DPY 0 0 1 0 0 0 1 1 1 1 DPY ← (DPY) – 1 Decrement the contents of DPY. ZF TAH Transfer AC to DPH 1 1 0 0 1 1 1 1 1 1 1 1 0 0 0 0 2 2 DPH ← (AC) Transfer the contents of AC to DPH. THA Transfer DPH to AC 1 1 0 0 1 1 1 0 1 1 1 1 0 0 0 0 2 2 AC ← (DPH) Transfer the contents of DPH to AC. XAH Exchange AC with DPH 0 1 0 0 0 0 0 0 1 1 (AC) ↔ (DPH) Exchange the contents of AC and DPH. TAL Transfer AC to DPL 1 1 0 0 1 1 1 1 1 1 1 1 0 0 0 1 2 2 DPL ← (AC) Transfer the contents of AC to DPL. TLA Transfer DPL to AC 1 1 0 0 1 1 1 0 1 1 1 1 0 0 0 1 2 2 AC ← (DPL) Transfer the contents of DPL to AC. XAL Exchange AC with DPL 0 1 0 0 0 0 0 1 1 1 (AC) ↔ (DPL) Exchange the contents of AC and DPL. TAX Transfer AC to DPX 1 1 0 0 1 1 1 1 1 1 1 1 0 0 1 0 2 2 DPX ← (AC) Transfer the contents of AC to DPX. TXA Transfer DPX to AC 1 1 0 0 1 1 1 0 1 1 1 1 0 0 1 0 2 2 AC ← (DPX) Transfer the contents of DPX to AC. XAX Exchange AC with DPX 0 1 0 0 0 0 1 0 1 1 (AC) ↔ (DPX) Exchange the contents of AC and DPX. TAY Transfer AC to DPY 1 1 0 0 1 1 1 1 1 1 1 1 0 0 1 1 2 2 DPY ← (AC) Transfer the contents of AC to DPY. TYA Transfer DPY to AC 1 1 0 0 1 1 1 0 1 1 1 1 0 0 1 1 2 2 AC ← (DPY) Transfer the contents of DPY to AC. XAY Exchange AC with DPY 0 1 0 0 0 0 1 1 1 1 (AC) ↔ (DPY) Exchange the contents of AC and DPY. ZF ZF ZF ZF [Flag manipulation instructions] SFB n4 Set flag bit 0 1 1 1 n 3 n2 n1 n0 1 1 Fn ← 1 Set the flag specified by n4 to 1. RFB n4 Reset flag bit 0 0 1 1 n 3 n2 n1 n0 1 1 Fn ← 0 Reset the flag specified by n4 to 0. Jump to the location in the same bank specified by the immediate data P12. ZF [Jump and subroutine instructions] JMP addr Jump in the current bank 1 1 1 0 P11P10P9 P8 P7 P6 P5 P4 P3 P2 P1 P0 2 2 PC13, 12 ← PC13, 12 PC11 to 0 ← P11 to P8 JPEA Jump to the address stored at E and AC in the current page 0 0 1 0 1 1 PC13 to 8 ← PC13 to 8, PC7 to 4 ← (E), PC3 to 0 ← (AC) Jump to the location determined by replacing the lower 8 bits of the PC by E, AC. 2 PC13 to 11 ← 0, PC10 to 0 ← P10 to P0, M4 (SP) ← (CF, ZF, PC13 to 0), SP ← (SP)-4 Call a subroutine. PC13 to 6, PC10 ← 0, PC5 to 2 ← P3 to P0, Call a subroutine on page 0 M4 (SP) ← in bank 0. (CF, ZF, PC12 to 0), SP ← SP-4 CAL addr Call subroutine 0 1 1 1 0 1 0 1 0 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0 2 CZP addr Call subroutine in the 1 0 1 0 zero page P3 P2 P1 P0 1 2 BANK Change bank 1 0 1 1 1 1 0 0 0 1 This becomes PC12 + (PC12) immediately following a BANK instruction. Change the memory bank and register bank. Continued on next page. No. 5485-22/26 LC665304A, 665306A, 665308A, 665312A, 665316A Instruction code Mnemonic D 7 D6 D5 D4 D3 D2 D1 D0 Number of bytes Number of cycles Continued from preceding page. Operation Affected status bits Description Note [Jump and subroutine instructions] Store the contents of reg in M2 (SP). Subtract 2 from SP after the store. PUSH reg Push reg on M2 (SP) 1 1 0 0 1 1 1 1 1 1 1 1 1 i 1 i0 0 2 2 M2 (SP) ← (reg) SP ← (SP) – 2 reg i1 i0 HL XY AE Illegal value 0 0 1 1 0 1 0 1 POP reg Pop reg off M2 (SP) 1 1 0 0 1 1 1 0 1 1 1 1 1 i 1 i0 0 2 2 SP ← (SP) + 2 reg ← [M2 (SP)] Add 2 to SP and then load the contents of M2(SP) into reg. The relation between i1i0 and reg is the same as that for the PUSH reg instruction. RT Return from subroutine 0 0 0 1 1 1 0 0 1 2 SP ← (SP) + 4 PC ← [M4 (SP)] Return from a subroutine or interrupt handling routine. ZF and CF are not restored. RTI Return from interrupt routine 0 0 0 1 1 1 0 1 1 2 SP ← (SP) + 4 PC ← [M4 (SP)] CF, ZF ← [M4 (SP)] Return from a subroutine or interrupt handling routine. ZF and CF are restored. 2 PC7 to 0 ← P7 P6 P5 P4 P3 P2 P1 P0 if (AC, t2) = 1 Branch to the location in the same page specified by P7 to P0 if the bit in AC specified by the immediate data t1 t0 is one. 2 PC7 to 0 ← P7 P6 P5 P4 P3 P2 P1 P0 if (AC, t2) = 0 Branch to the location in the same page specified by P7 to P0 if the bit in AC specified by the immediate data t1 t0 is zero. 2 PC7 to 0 ← P7 P6 P5 P4 P3 P2 P1 P0 if [M (HL),t2] =1 Branch to the location in the same page specified by P7 to P0 if the bit in M (HL) specified by the immediate data t1 t0 is one. 2 PC7 to 0 ← P7 P6 P5 P4 P3 P2 P1 P0 if [M (HL),t2] =0 Branch to the location in the same page specified by P7 to P0 if the bit in M (HL) specified by the immediate data t1 t0 is zero. ZF, CF [Branch instructions] BAt2 addr BNAt2 addr BMt2 addr BNMt2 addr BPt2 addr BNPt2 addr Branch on AC bit 1 1 0 1 0 0 t1 t0 P7 P6 P5 P4 P3 P2 P1 P0 Branch on no AC bit 1 0 0 1 0 0 t1 t0 P7 P6 P5 P4 P3 P2 P1 P0 Branch on M bit 1 1 0 1 0 1 t1 t0 P7 P6 P5 P4 P3 P2 P1 P0 Branch on no M bit 1 0 0 1 0 1 t1 t0 P7 P6 P5 P4 P3 P2 P1 P0 Branch on Port bit 1 1 0 1 1 0 t1 t0 P7 P6 P5 P4 P3 P2 P1 P0 1 0 0 1 1 0 t1 t0 Branch on no Port bit P7 P6 P5 P4 P3 P2 P1 P0 2 2 2 2 2 2 2 2 PC7 to 0 ← P7 P6 P5 P4 P3 P2 P1 P0 if [P (DPL), t2] =1 PC7 to 0 ← P7 P6 P5 P4 P3 P2 P1 P0 if [P (DPL), t2] =0 Branch to the location in the same page specified by P7 to P0 if the bit in port (DPL) specified by the immediate data t1 t0 is one. Internal control registers can also be tested by executing this instruction immediately after a BANK instruction. However, this is limited to registers that can be read out. Branch to the location in the same page specified by P7 to P0 if the bit in port (DPL) specified by the immediate data t1 t0 is zero. Internal control registers can also be tested by executing this instruction immediately after a BANK instruction. However, this is limited to registers that can be read out. Continued on next page. No. 5485-23/26 LC665304A, 665306A, 665308A, 665312A, 665316A Instruction code Mnemonic D 7 D6 D5 D4 D3 D2 D1 D0 Number of bytes Number of cycles Continued from preceding page. Operation Description Affected status bits Note [Branch instructions] 2 PC7 to 0 ← P7 P6 P5 P4 P3 P2 P1 P0 if (CF) = 1 Branch to the location in the same page specified by P7 to P0 if CF is one. BC addr Branch on CF 1 1 0 1 1 1 0 0 P7 P6 P5 P4 P3 P2 P1 P0 BNC addr Branch on no CF 1 0 0 1 1 1 0 0 P7 P6 P5 P4 P3 P2 P1 P0 2 2 PC7 to 0 ← P7 P6 P5 P4 P3 P2 P1 P0 if (CF) = 0 Branch to the location in the same page specified by P7 to P0 if CF is zero. BZ addr Branch on ZF 1 1 0 1 1 1 0 1 P7 P6 P5 P4 P3 P2 P1 P0 2 2 PC7 to 0 ← P7 P6 P5 P4 P3 P2 P1 P0 if (ZF) = 1 Branch to the location in the same page specified by P7 to P0 if ZF is one. Branch on no ZF 1 0 0 1 1 1 0 0 P7 P6 P5 P4 P3 P2 P1 P0 2 PC7 to 0 ← P7 P6 P5 P4 P3 P2 P1 P0 if (ZF) = 0 Branch to the location in the same page specified by P7 to P0 if ZF is zero. 2 PC7 to 0 ← P7 P6 P5 P4 P3 P2 P1 P0 if (Fn) = 1 Branch to the location in the same page specified by P0 to P7 if the flag (of the 16 user flags) specified by n3 n2 n1 n0 is one. Branch to the location in the same page specified by P0 to P7 if the flag (of the 16 user flags) specified by n3 n2 n1 n0 is zero. BNZ addr BFn4 addr BNFn4 addr Branch on flag bit Branch on no flag bit 1 1 1 1 n 3 n2 n1 n0 P7 P6 P5 P4 P3 P2 P1 P0 2 2 2 1 0 1 1 n 3 n2 n1 n0 P7 P6 P5 P4 P3 P2 P1 P0 2 2 PC7 to 0 ← P7 P6 P5 P4 P3 P2 P1 P0 if (Fn) = 0 [I/O instructions] IP0 Input port 0 to AC 0 0 1 0 0 0 0 0 1 1 AC ← (P0) Input the contents of port 0 to AC. ZF IP Input port to AC 0 0 1 0 0 1 1 0 1 1 AC ← [P (DPL)] Input the contents of port P (DPL) to AC. ZF IPM Input port to M 0 0 0 1 1 0 0 1 1 1 M (HL) ← [P (DPL)] Input the contents of port P (DPL) to M (HL). IPDR i4 Input port to AC direct 1 1 0 0 0 1 1 0 1 1 1 1 I3 I2 I1 I0 2 2 AC ← [P (i4)] Input the contents of P (i4) to AC. IP45 Input port 4, 5 to E, AC respectively 1 1 0 0 1 1 0 1 1 1 1 1 0 1 0 0 2 2 E ← [P (4)] AC ← [P (5)] Input the contents of ports P (4) and P (5) to E and AC respectively. OP Output AC to port 0 0 1 0 0 1 0 1 1 1 P (DPL) ← (AC) Output the contents of AC to port P (DPL). OPM Output M to port 0 0 0 1 1 0 1 0 1 1 P (DPL) ← [M (HL)] Output the contents of M (HL) to port P (DPL). OPDR i4 Output AC to port direct 1 1 0 0 0 1 1 1 1 1 1 1 I3 I2 I1 I0 2 2 P (i4) ← (AC) Output the contents of AC to P (i4). OP45 Output E, AC to port 4, 5 respectively 1 1 0 0 1 1 0 1 1 1 1 1 0 1 0 1 2 2 P (4) ← (E) P (5) ← (AC) Output the contents of E and AC to ports P (4) and P (5) respectively. SPB t2 Set port bit 0 0 0 0 1 0 t1 t0 1 1 [P (DPL), t2] ← 1 Set to one the bit in port P (DPL) specified by the immediate data t1 t0. RPB t2 Reset port bit 0 0 1 0 1 0 t1 t0 1 1 [P (DPL), t2] ← 0 Clear to zero the bit in port P (DPL) specified by the immediate data t1 t0. And port with ANDPDR immediate data then i4, p4 output 1 1 0 0 0 1 0 1 I3 I2 I1 I0 P3 P2 P1 P0 2 2 P (P3 to P0) ← [P (P3 to P0)] I3 to I0 Take the logical AND of P (P3 to P0) and the immediate data ZF I3 I2 I1 I0 and output the result to P (P3 to P0). Or port with immediate data then output 1 1 0 0 0 1 0 0 I3 I2 I1 I0 P3 P2 P1 P0 2 2 P (P3 to P0) ← [P (P3 to P0)] I3 to I0 Take the logical OR of P (P3 to P0) and the immediate data ZF I3 I2 I1 I0 and output the result to P (P3 to P0). ORPDR i4, p4 ZF ZF Continued on next page. No. 5485-24/26 LC665304A, 665306A, 665308A, 665312A, 665316A Instruction code Mnemonic D 7 D6 D5 D4 D3 D2 D1 D0 Number of bytes Number of cycles Continued from preceding page. Operation Description Affected status bits Note [Timer control instructions] WTTM0 Write timer 0 1 1 0 0 1 0 1 0 1 2 Write the contents of M2 (HL), TIMER0 ← [M2 (HL)], AC into the timer 0 reload (AC) register. WTTM1 Write timer 1 1 1 0 0 1 1 1 1 1 1 1 1 0 1 0 0 2 2 Write the contents of E, AC TIMER1 ← (E), (AC) into the timer 1 reload register A. RTIM0 Read timer 0 1 1 0 0 1 0 1 1 1 2 M2 (HL), AC ← (TIMER0) Read out the contents of the timer 0 counter into M2 (HL), AC. RTIM1 Read timer 1 1 1 0 0 1 1 1 1 1 1 1 1 0 1 0 1 2 2 E, AC ← (TIMER1) Read out the contents of the timer 1 counter into E, AC. START0 Start timer 0 1 1 0 0 1 1 1 0 1 1 1 1 0 1 1 0 2 2 Start timer 0 counter Start the timer 0 counter. START1 Start timer 1 1 1 0 0 1 1 1 0 1 1 1 1 0 1 1 1 2 2 Start timer 1 counter Start the timer 1 counter. STOP0 Stop timer 0 1 1 0 0 1 1 1 1 1 1 1 1 0 1 1 0 2 2 Stop timer 0 counter Stop the timer 0 counter. STOP1 Stop timer 1 1 1 0 0 1 1 1 1 1 1 1 1 0 1 1 1 2 2 Stop timer 1 counter Stop the timer 1 counter. [Interrupt control instructions] MSET Set interrupt master enable flag 1 1 0 0 0 1 0 1 1 1 0 1 0 0 0 0 2 2 MSE ← 1 Set the interrupt master enable flag to one. MRESET Reset interrupt master enable flag 1 1 0 0 1 0 0 1 1 1 0 1 0 0 0 0 2 2 MSE ← 0 Clear the interrupt master enable flag to zero. EIH i4 Enable interrupt high 1 1 0 0 0 1 0 1 1 1 0 1 I3 I2 I1 I0 2 2 EDIH ← (EDIH) EIL i4 Enable interrupt low 1 1 0 0 0 1 0 0 1 1 0 1 I3 I2 I1 I0 2 2 EDIL ← (EDIL) DIH i4 Disable interrupt high 1 1 0 0 1 0 0 1 1 1 0 1 I3 I2 I1 I0 2 2 EDIH ← (EDIH) DIL i4 Disable interrupt low 1 1 0 0 1 0 0 0 1 1 0 1 I3 I2 I1 I0 2 2 EDIL ← (EDIL) WTSP Write SP 1 1 0 0 1 1 0 1 1 1 1 1 1 0 1 0 2 2 SP ← (E), (AC) Transfer the contents of E, AC to SP. RSP Read SP 1 1 0 0 1 1 0 1 1 1 1 1 1 0 1 1 2 2 E, AC ← (SP) Transfer the contents of SP to E, AC. i4 i4 i4 i4 Set the interrupt enable flag to one. Set the interrupt enable flag to one. Clear the interrupt enable flag to zero. ZF Clear the interrupt enable flag to zero. ZF [Standby control instructions] HALT HALT 1 1 0 0 1 1 0 1 1 1 1 1 1 1 1 0 2 2 HALT Enter halt mode. HOLD HOLD 1 1 0 0 1 1 0 1 1 1 1 1 1 1 1 1 2 2 HOLD Enter hold mode. STARTS Start serial I O 1 1 0 0 1 1 1 0 1 1 1 1 1 1 1 0 2 2 START SI O Start SIO operation. WTSIO Write serial I O 1 1 0 0 1 1 1 0 1 1 1 1 1 1 1 1 2 2 SIO ← (E), (AC) Write the contents of E, AC to SIO. RSIO Read serial I O 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 2 2 E, AC ← (SIO) Read out the contents of SIO into E, AC. [Serial I/O control instructions] [Other instructions] NOP No operation 0 0 0 0 0 0 0 0 1 1 No operation Consume one machine cycle without performing any operation. SB i2 Select bank 1 1 0 0 1 1 0 0 1 1 1 1 0 0 I1 I0 2 2 PC13, PC12 ← I1 I0 Specify the memory bank. No. 5485-25/26 LC665304A, 665306A, 665308A, 665312A, 665316A ■ No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. ■ Anyone purchasing any products described or contained herein for an above-mentioned use shall: ➀ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: ➁ Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. ■ Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of February, 1997. Specifications and information herein are subject to change without notice. No. 5485-26/26