APL3225 Li+ Charger Protection IC Features General Description • The APL3225 provides complete Li+ charger protection against input over-voltage, input over-current and over- Provide OUT Pin 5V Voltage Clamping Protection • Thermal Charging Regulation Protection • Provide Input Over-voltage Protection • Provide Input Over-current Protection • Provide Over Temperature Protection • Provide Reverse Current Blocking • High Immunity of False Triggering • High Accuracy Protection Threshold • Low On Resistance 0.3Ω Typ. • Compact TDFN2x2-8 and DFN3x3-8 Packages • Lead Free and Green Devices Available temperature. When any of the monitored parameters is over the threshold, the IC turns off the charging current. All protections also have deglitch time against false triggering due to voltage spikes or current transients. The APL3225 integrates a 5.5V LDO to prevent ACIN overshoot reaching CHR_LDO and OUT. When any transient peak voltage above 5.5V presenting in ACIN pin, but below OVP threshold, the internal LDO will clamp its output at 5.5V. When ACIN voltage exceeds OVP threshold, the device will turn off charging current. The charging current is controlled by the GATDRV pin. When sourcing a current from the GATDRV pin, the OUT pin delivers the charging current which is 200-fold magnified in amplitude based on GATDRV’s current. (RoHS Compliant) Other features include accurate VVCDT/VACIN voltage divider, reverse current blocking from OUT to ACIN and OTP Applications • protection. The APL3225 provides complete Li+ charger protections, and saves the external MOSFET and Schottky diode for the charger of cell phone’s PMIC. The above Cell Phones features and small package make the APL3225 an ideal part for cell phones applications. Pin Configuration ACIN 1 ACIN 2 GND 3 VCDT 4 Simplified Application Circuit 8 OUT 7 OUT 6 CHR_LDO 5 GATDRV 5V Adapter DFN3x3-8 (Top View) ACIN CHR_LDO CHR_LDO APL3225 ACIN 1 ACIN 2 GND 3 VCDT 4 PMIC GATDRV 8 OUT 7 OUT 6 CHR_LDO 5 GATDRV GATDRV VCDT VCDT OUT ISENS GND Li+ Battery TDFN2x2-8 (Top View) VBAT = Exposed Pad (connected to ground plane for better heat dissipation) ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.1 - Nov., 2012 1 www.anpec.com.tw APL3225 Ordering and Marking Information Package Code QA : DFN3x3-8 QB : TDFN2x2-8 Operating Ambient Temperature Range I : -40 to 85 oC Handling Code TR : Tape & Reel Assembly Material G : Halogen and Lead Free Device APL3225 Assembly Material Handling Code Temperature Range Package Code APL3225 QB: L25 X X - Date Code APL3225 QA: APL 3225 XXXXX X - Date Code Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). Absolute Maximum Ratings Symbol VACIN (Note 1) Parameter Rating Unit V ACIN Input Voltage (ACIN to GND) -0.3 ~ 28 VCHR_LDO CHR_LDO to GND Voltage -0.3 ~ 7 V VGATDRV GATDRV to GND Voltage -0.3 ~ VCHR_LDO V VCDT VCDT to GND Voltage -0.3 ~ 7 V VOUT OUT to GND Voltage -0.3 ~ 7 V IOUT TJ Output Current (OUT to GND) 2 Maximum Junction Temperature TSTG Storage Temperature TSDR Maximum Lead Soldering Temperature (10 Seconds) A 150 o -65 ~ 150 o 260 o C C C Note 1:Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under ”recommended operating conditions”is not implied. Exposure to absolute maximum rating conditions for extended periods may affect vice reliability. Thermal Characteristic Symbol θJA θJA Parameter Typical Value TDFN2x2-8 Junction-to-Ambient Resistance in free air DFN3x3-8 Junction-to-Ambient Resistance in free air (Note 2) (Note 2) Unit 75 o 65 o C/W C/W Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. The exposed pad of TDFN2x2-8 is soldered directly on the PCB. Copyright ANPEC Electronics Corp. Rev. A.1 - Nov., 2012 2 www.anpec.com.tw APL3225 Recommended Operating Conditions Symbol Parameter VACIN ACIN Input Voltage IOUT Output Current TA Ambient Temperature TJ Junction Temperature CCHR_LDO (Note 3) Range Unit 4.5 ~ 6.5 V 0~1 A -40 ~ 85 o -40 ~ 125 o CHR_LDO Output Capacitor C C µF 1 Note 3: Refer to the typical application circuit Electrical Characteristics Unless otherwise specified, these specifications apply over VACIN=5V, TA= -40 ~ 85 oC. Typical values are at TA=25oC. Symbol Parameter APL3225 Test Conditions Unit Min. Typ. Max. IOUT=0A, ICHR_LDO=0A - 350 600 µA In OTP - - 550 µA VACIN>VOVP - - 550 µA VACIN rising 2.4 2.6 2.8 V ACIN POR Hysteresis - 250 - mV ACIN Power-On Blanking Time - 8 - ms - 0.3 0.35 Ω - 500 - Ω 5.265 5.5 5.735 V 2.4 3 3.6 kΩ 6.6 6.8 7 V 150 200 250 mV ACIN INPUT CURRENT and POWER-ON-RESET (POR) IACIN VPOR TB(ACIN) ACIN Supply Current ACIN POR Threshold INTERNAL SWITCH ON RESISTANCE ACIN to OUT On Resistance IOUT = 1A CHR_LDO Discharge VACIN = 12V , VCHR_LDO = 2V Resistnace INPUT OVER-VOLTAGE PROTECTION (OVP) VREG Internal LDO Output Voltage VOVP Input OVP Threshold VACIN = 6V, IOUT = 10mA, TJ = -40 ~ 125 oC LDO Output Series Resistance APL3225 VACIN rising, TJ = -40 ~ 125 oC Input OVP Hysteresis TOVP TON(OVP) Input OVP Propagation Delay - - 1 µs Input OVP recovery time - 1 - ms OVER-CURRENT PROTECTION (OCP) IOC Over-Current Trip Threshold TJ = 25 oC, TJ = -40 ~ 25 oC 1.5 - - A ICL Current Limit Level TJ = 25 oC, TJ = -40 ~ 25 oC 1.2 - - A 0.1035 0.1056 0.1078 V/V 100 200 300 A/A VCDT INTERNAL DIVIDER Divider Ratio VVCDT/VACIN CHARGE CURRENT CONTROL Current Mirror Gain Copyright ANPEC Electronics Corp. Rev. A.1 - Nov., 2012 IOUT = 0.6A, IOUT/IGATDRV 3 www.anpec.com.tw APL3225 Electrical Characteristics (Cont.) Unless otherwise specified, these specifications apply over VACIN=5V, TA= -40 ~ 85 oC. Typical values are at TA=25oC. Symbol Parameter APL3225 Test Conditions Unit Min. Typ. Max. - 20 - mV - 150 - mV - - 1 µA REVERSE CURRENT BLOCKING PMOS Lockout Threshold PMOS Lockout Release Threshold OUT Input Current (Reverse Current Blocking) VOUT OVERSHOOT CLAMP VCCAMP VACIN = 0V, VOUT = 4.2V, VGATDRV=0V Overshoot Clamp Rising Threshold VOUT rising slew rate > 0.2V/µs 4.6 4.8 5.0 V Overshoot Clamp Pull Low Resistance VOUT rising slew rate > 0.2V/µs - 3 - Ω Overshoot Clamp Active Time From Overshoot Clamp Threshold being surpassed - 150 - µs TJ rising - 160 - °C - 40 - °C Thermal Shutdown Protection TOTP Thermal Shutdown Threshold Thermal Shutdown Hysteresis Copyright ANPEC Electronics Corp. Rev. A.1 - Nov., 2012 4 www.anpec.com.tw APL3225 Pin Description PIN NO 1 FUNCTION NAME ACIN Power Supply Input. Connect this pin to external DC supply. Bypass to GND with a 1µF (minimum) ceramic capacitor. 3 GND Ground terminal. 4 VCDT Provide an interval voltage divider. This pin divides ACIN voltage into 39/369 ratio. 5 GATDRV 6 CHR_LDO 2 7 OUT 8 Exposed Pad Charging current control pin. When sourcing a current from this pin, the OUT pin will source out a current whose magnitude is 200xIGATDRV . Output Pin. The pin provides supply voltage to the PMIC input. Bypass to GND with a 1µF (minimum) ceramic capacitor. Output Pins. The pin provides supply source current in series with a resistor to battery. This pin possesses the overshoot clamp function to limit peak voltage. - Exposed Thermal Pad. Must be electrically connected to the GND pin. Copyright ANPEC Electronics Corp. Rev. A.1 - Nov., 2012 5 www.anpec.com.tw APL3225 Block Diagram ACIN VCDT CHR_LDO GATDRV GND OUT OVERSHOOT CLAMP Typical Application Circuit 5V Adapter 1, 2 ACIN CHR_LDO C1 1µF 6 CHR_LDO C2 1µF APL3225 5 GATDRV 4 VCDT 7, 8 OUT 3 GATDRV VCDT ISENS 0.2Ω GND Li+ Battery Designation CACIN PMIC VBAT Description 1µF, 25V, X5R, 0603 Murata GRM188R61E105K 1µF, 16V, X5R, 0603 Murata GRM188R61C105K CCHR_LDO Copyright ANPEC Electronics Corp. Rev. A.1 - Nov., 2012 1µF, 6.3V, X5R, 0603 Murata GRM185R60J225KE26 6 www.anpec.com.tw APL3225 Function Description ACIN Power-On-Reset (POR) Current Limit The APL3225 is built-in a power-on-reset circuit to keep The output current is monitored by the internal current limit circuit. When the output current reaches the current the output shut off until internal circuitry is operating properly. The POR circuit has hysteresis and a de-glitch limit threshold, the device limits the output current at current limit threshold. The current limit level decrease as feature so that it will typically ignore undershoot transients on the input. When input voltage exceeds the POR thresh- the junction temperature increase. When the Junction temperature increases, the internal current limit circuit old and after 8ms blanking time, the output voltage starts a soft-start to reduce the inrush current. reduces the current limit level, allowing the device’s Junction temperature to cool down. ACIN Over-Voltage Protection (OVP) and LDO Mode Operation Internal P-MOSFET and Reverse Current Blocking The CHR_LDO output of the IC operates similar to a lin- The APL3225 integrates a P-channel MOSFET with the ear regulator. When the ACIN input voltage is less than VREG, and above the ACIN POR VACIN, the internal LDO body diode reverse protection to replace the external PNP transistor and Schottky diode for cell phone’s PMIC. The output voltage tracks the input voltage with a voltage drop caused by RDS(on) of MOSFET Q1. When the ACIN input body diode reverse protection prevents battery voltage supplies to CHR_LDO and ACIN pin. When the P-chan- voltage is greater than VREG plus the RDS(on) drop of Q1, and less than VOVP, the internal LDO output voltage is nel MOSFET’s negative VSD voltage is detected, the internal bulk selection circuitry will switch the body diode of regulated to VREG, and this is also referred as LDO mode operation. If the input voltage rises above VOVP, the inter- the P-channel MOSFET forward biased from source to drain, meanwhile the P-channel is turned off regardless nal FET Q1 and Q2 will be turned off within 1µs to protect connected system on OUT pin. When the input voltage of GATDRV’s current. This after the detection of negative VSD, the P-channel MOSFET is in lockout state to prevent returns below the input OVP threshold minus the hysteresis, the FETs is turned on again after 1ms recov- battery discharging from ACIN and CHR_LDO to external circuitry. The P-channel MOSFET lockout will be releases ery time. The input OVP circuit has a 200mV hysteresis and a recovery time of TON(OVP) to provide noise immunity when positive VSD is detected. against transient conditions. OUT Overshoot Clamp This OUT pin possesses the overshoot clamp function to Charging Current Control limit peak voltage. Since the clamping function needs a low resistance path between OUT pin and external high The charging current is controlled by the GATDRV pin. When sourcing a current from the GATDRV pin, the OUT voltage source (in abnormal condition), please connect this OUT pin directly to outside circuit to let clamping work. pin delivers the charging current which is 200-fold magnified in amplitude based on GATDRV’s current. The IOUT current can be calculated by this following equation: IOUT=200xI GATDRV where The IOUT is the current flowing out from OUT pin. The IGATDRV is the current flowing out from GATDRV pin. Copyright ANPEC Electronics Corp. Rev. A.1 - Nov., 2012 7 www.anpec.com.tw APL3225 Application Information Recommended Minimum Footprint Capacitor Selection The input capacitor is for decoupling and prevents the input voltage from overshooting to dangerous levels. In Thermal Via diameter 12mil X 5 0.572mm the AC adapter hot plug-in applications or load current step-down transient, the input voltage has a transient Ground plane for Thermal PAD 0.222mm 0.241mm 1.295mm spike due to the parasitic inductance of the input cable. A 25V, X5R, dielectric ceramic capacitor with a value between 1µF and 4.7µF placed close to the ACIN pin is recommended. The output capacitor of CHR_LDO is for CHR_LDO voltage decoupling. And also can be as the input capacitor of 0.508mm the charging circuit. At least, a 1µF, 10V, X5R capacitor is recommended. 0.8mm TDFN2x2-8 Layout Consideration In some failure modes, a high voltage may be applied to the device. Make sure the clearance constraint of the PCB layout must satisfy the design rule for high voltage. The exposed pad of the TDFN2x2-8 and DFN3x3-8 performs Thermal Via diameter 12mil X 5 Ground plane for Thermal PAD 0.305mm 0.61mm the function of channeling heat away. It is recommended that connect the exposed pad to a large copper ground 0.305mm 2.146mm plane on the backside of the circuit board through several thermal vias to improve heat dissipation. The input and output capacitors should be placed close to the IC. The high current traces like input trace and output trace must be wide and short. 0.66mm 1.575mm DFN3X3-8 Copyright ANPEC Electronics Corp. Rev. A.1 - Nov., 2012 8 www.anpec.com.tw APL3225 Package Information TDFN2x2-8 A b E D D2 A1 E2 A3 L Pin 1 Corner e S Y M B O L MIN. MAX. MIN. MAX. A 0.70 0.80 0.028 0.031 0.05 0.000 0.002 0.012 0.083 A1 TDFN2x2-8 MILLIMETERS 0.00 A3 INCHES 0.20 REF 0.008 REF b 0.18 0.30 0.007 D 1.90 2.10 0.075 D2 1.00 1.60 0.039 0.063 E 1.90 2.10 0.075 0.083 E2 0.60 1.00 0.024 0.039 0.45 0.012 e L 0.50 BSC 0.30 0.020 BSC 0.018 Note : 1. Follow from JEDEC MO-229 WCCD-3. Copyright ANPEC Electronics Corp. Rev. A.1 - Nov., 2012 9 www.anpec.com.tw APL3225 Package Information DFN3x3-8 D b E A Pin 1 A1 D2 A3 L K E2 Pin 1 Corner e S Y M B O L DFN3x3-8 MILLIMETERS INCHES MIN. MAX. MIN. MAX. A 0.80 1.00 0.031 0.039 A1 0.00 0.05 0.000 0.002 A3 0.20 REF 0.008 REF b 0.25 0.35 0.010 0.014 D 2.90 3.10 0.114 0.122 D2 1.90 2.40 0.075 0.094 E 2.90 3.10 0.114 0.122 E2 1.40 1.75 0.055 0.069 e 0.65 BSC L 0.30 K 0.20 Copyright ANPEC Electronics Corp. Rev. A.1 - Nov., 2012 0.026 BSC 0.012 0.50 0.020 0.008 10 www.anpec.com.tw APL3225 Carrier Tape & Reel Dimensions P0 P2 P1 A B0 W F E1 OD0 K0 A0 A OD1 B B T SECTION A-A SECTION B-B H A d T1 Application TDFN2x2-8 Application DFN3x3-8 A H T1 C d D W E1 F 178.0±2.00 50 MIN. 8.4+2.00 -0.00 13.0+0.50 -0.20 1.5 MIN. 20.2 MIN. 8.0±0.20 1.75±0.10 3.50±0.05 P0 P1 P2 D0 D1 T A0 B0 K0 4.0±0.10 4.0±0.10 2.0±0.05 1.5+0.10 -0.00 1.5 MIN. 0.6+0.00 -0.4 2.35 MIN 2.35 MIN 1.00±0.20 A H T1 C d D W E1 F 178.0±2.00 50 MIN. 12.4+2.00 -0.00 13.0+0.50 -0.20 1.5 MIN. 20.2 MIN. 12.0±0.30 1.75±0.10 5.5±0.05 P0 P1 P2 D0 D1 T A0 B0 K0 4.0±0.10 8.0±0.10 2.0±0.05 1.5+0.10 -0.00 1.5 MIN. 0.6+0.00 -0.40 3.30±0.20 3.30±0.20 1.30±0.20 (mm) Devices Per Unit Package Type Unit Quantity TDFN2x2-8 Tape & Reel 3000 DFN3x3-8 Tape & Reel 3000 Copyright ANPEC Electronics Corp. Rev. A.1 - Nov., 2012 11 www.anpec.com.tw APL3225 Taping Direction Information TDFN2x2-8 USER DIRECTION OF FEED DFN3x3-8 USER DIRECTION OF FEED Copyright ANPEC Electronics Corp. Rev. A.1 - Nov., 2012 12 www.anpec.com.tw APL3225 Classification Profile Copyright ANPEC Electronics Corp. Rev. A.1 - Nov., 2012 13 www.anpec.com.tw APL3225 Classification Reflow Profiles Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly 100 °C 150 °C 60-120 seconds 150 °C 200 °C 60-120 seconds 3 °C/second max. 3°C/second max. 183 °C 60-150 seconds 217 °C 60-150 seconds See Classification Temp in table 1 See Classification Temp in table 2 Time (tP)** within 5°C of the specified classification temperature (Tc) 20** seconds 30** seconds Average ramp-down rate (Tp to Tsmax) 6 °C/second max. 6 °C/second max. 6 minutes max. 8 minutes max. Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) Average ramp-up rate (Tsmax to TP) Liquidous temperature (TL) Time at liquidous (tL) Peak package body Temperature (Tp)* Time 25°C to peak temperature * Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum. ** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum. Table 1. SnPb Eutectic Process – Classification Temperatures (Tc) Package Thickness <2.5 mm ≥2.5 mm Volume mm <350 235 °C 220 °C 3 Volume mm ≥350 220 °C 220 °C 3 Table 2. Pb-free Process – Classification Temperatures (Tc) Package Thickness <1.6 mm 1.6 mm – 2.5 mm ≥2.5 mm Volume mm <350 260 °C 260 °C 250 °C 3 Volume mm 350-2000 260 °C 250 °C 245 °C 3 Volume mm >2000 260 °C 245 °C 245 °C 3 Reliability Test Program Test item SOLDERABILITY HOLT PCT TCT HBM MM Latch-Up Copyright ANPEC Electronics Corp. Rev. A.1 - Nov., 2012 Method JESD-22, B102 JESD-22, A108 JESD-22, A102 JESD-22, A104 MIL-STD-883-3015.7 JESD-22, A115 JESD 78 14 Description 5 Sec, 245°C 1000 Hrs, Bias @ Tj=125°C 168 Hrs, 100%RH, 2atm, 121°C 500 Cycles, -65°C~150°C VHBM≧2KV VMM≧200V 10ms, 1tr≧100mA www.anpec.com.tw APL3225 Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838 Copyright ANPEC Electronics Corp. Rev. A.1 - Nov., 2012 15 www.anpec.com.tw