A-Data ADS8608A8A Synchronous DRAM 8M x 8 Bit x 4 Banks General Description Features The ADS8608A8A are four-bank Synchronous DRAMs organized as 8,388,608 words x 8 bits x 4 banks. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth high performance memory system applications •JEDEC standard LVTTL 3.3V power supply •MRS Cycle with address key programs -CAS Latency (2 & 3) -Burst Length (1,2,4,8,& full page) -Burst Type (sequential & Interleave) •4 banks operation •All inputs are sampled at the positive edge of the system clock •Burst Read single write operation •Auto & Self refresh •DQM for masking •8192 Refresh Cycles •Package:54-pins 400 mil TSOP-Type II Ordering Information. Part No. Frequency Interface Package ADS8608A8A-75 133Mhz-333 LVTTL 400mil 54pin TSOPII ADS8608A8A-75A 133Mhz-222 LVTTL 400mil 54pin TSOPII Pin Assignment VCC 1 54 Vss DQ0 2 53 DQ7 VCCQ 3 52 VssQ NC 4 51 NC DQ1 5 50 DQ6 VSSQ 6 49 VCCQ NC 7 48 NC DQ2 8 47 DQ5 VCCQ 9 46 VSSQ NC 10 45 NC DQ3 11 44 DQ4 VSSQ 12 43 VCCQ NC 13 42 NC VCC 14 41 VSS NC 15 40 NC /WE 16 39 DQM /CAS 17 38 CLK /RAS 18 37 CKE /CS 19 36 A12 BS0 20 35 A11 BS1 21 34 A9 A10/AP 22 33 A8 A0 23 32 A7 A1 24 31 A6 A2 25 30 A5 A3 26 29 A4 VCC 27 28 VSS 54-pin plastic TSOP II 400 mil Rev 1.0 December, 2001 1 A-Data ADS8608A8A Pin Description PIN NAME FUNCTION CLK System Clock Active on the positive edge to sample all inputs. CKE Clock Enable Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least on cycle prior new command. Disable input buffers for power down in standby /CS Chip Select Disables or Enables device operation by masking or enabling all input except CLK, CKE and L(U)DQM A0~A12 Address Row / Column address are multiplexed on the same pins. Row address : A0~A12 Column address : A0~A9 BS0~BS1 Banks Select Selects bank to be activated during row address latch time. Selects bank for read / write during column address latch time. DQ0~DQ7 Data Data inputs / outputs are multiplexed on the same pins. /RAS Row Address Strobe Latches row addresses on the positive edge of the CLK with /RAS low /CAS Column Address Strobe Latches Column addresses on the positive edge of the CLK with /CAS low /WE Write Enable Enables write operation and row recharge. VCC/VSS Power Supply/Ground Power and Ground for the input buffers and the core logic. VCCQ/VSSQ Data Output Power/Ground Power supply for output buffers. NC No Connection This pin is recommended to be left No Connection on the device. Block Diagram CLK CKE Clock Generator Bank3 Bank2 Bank1 Mode Register Address Buffer & Refresh Counter Row Decoder Address Bank0 /CAS /WE Rev 1.0 December, 2001 Column Address Buffer & Refresh Counter DQM Column Decoder Data Control Circuit 2 Data Latch /RAS Control Logic /CS Command Decoder Amplifier DQ A-Data ADS8608A8A Absolute Maximum Ratings Parameter Voltage on any pin relative to Vss Voltage on VDD supply relative to Vss Symbol Value Unit VIN, Vout -0.3 ~Vcc+0.3 V VCC, VCCQ -0.3 ~ 4.6 V TSTG -55 ~ +150 ℃ PD 1 W IOUT 50 mA Storage temperature Power dissipation Short circuit current Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATING are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. DC Operating Condition Voltage referenced to Vss = 0V, TA = 0 to 70 ℃ Parameter Symbol Min Typ Max Unit VCC, VCCQ 3.0 3.3 3.6 V Input logic high voltage VIH 2.0 3.0 VCC+0.3 V 2 Input logic low voltage VIL -0.3 - 0.8 V 2 Supply voltage Note Note : 1. VIH (max)=Vcc/ VccQ+1.2V for pulse width ≦ 5ns acceptable. 2.VIL(min)=-Vss/ VssQ-1.2V for pulse width ≦ 5ns acceptable. AC Operating Condition Voltage referenced to Vss = 0V, TA = 0 to 70 ℃ Parameter Symbol Value Unit VIH / VIL 2.4 / 0.4 V Vtrip 1.4 V Input rise / fall time TR / tF 2 Ns Output timing measurement reference level Voutfef 1.4 V CL 50 pF AC input high / low level voltage Input timing measurement reference level voltage Output load capacitance for access time measurement Note: 1. 3.15V ≦ VDD Note 2 ≦ 3.6V is applied for ADS8608A8A55. 2. Output load to measure access times is equivalent to two TTL gates and one capacitor (30pF). For details, refer to AC/DC output load circuit. Rev 1.0 December, 2001 3 A-Data ADS8608A8A Capacitance TA=25℃, f-=1Mhz, VCC=3.3V Parameter Pin Input capacitance Symbol Min Max Unit CLK Cclk - 3.5 pF A0~A12,BS0 ,BS1,CKE,/CS,/RAS, Cl1 - 3.8 pF CI/O - 6.5 pF /CAS,/WE,LDQM Data input / output capacitance Output load circuit 3.3 V 50 ohms Output Z= 50 ohms 50 pF DC Characteristics I Parameter Symbol Min Max Unit Note Input leakage current ILI -5 5 uA Output leakage current ILO -5 5 uA Output high voltage VOH 2.4 - V IOH = -4mA Output low voltage VOL - 0.4 V IOL = 4mA Note : 1.VIN = 0 TO 3.6V, All other pins are not tested under VIN = 0V. 2.DOUT is disabled, VOUT = 0 to 3.6. Rev 1.0 December, 2001 4 A-Data ADS8608A8A DC Characteristics II Speed Parameter Symbol Test condition Unit 75 75A 80 75 Note Burst length=1, One bank active Operating Current Precharge standby ICC1 tRC≧tRC(min),IOL=0mA ICC2P CKE≦VIL(max), tCK=min 1 1 ICC2PS CKE≦VIL(max), tCK=∞ 1 1 40 35 10 10 1 current in power down mode CKE≧VIH(min), /CS≧VIH(min), tCK=min input signals are Precharge standby ICC2 changed one time during 2clks. All current in Non power other pins ≧VDD-0.2V or ≦ down mode 0.2V CKE≧VIH(min), tCK=∞ ICC2S Input signals are stable. mA No Operating Current ICC3 CKE≦VIL(max), tCK=min 60 55 in power down mode CKE≦VIL(max), tCK=∞ 10 10 100 95 1 170 160 2 ICC3P tCK≧tCK(min),IOL=0 mA Burst mode operating ICC4 current All banks active tCK≧tCK(min),IOL=0 mA Auto refresh current ICC5 All banks active ICC6 Standard 3 3 ICC6L Lower Power 1 - Self refresh current Note: 1. ICC1 and ICC4 depend on output loading and cycle rates. Specified values are measured with the output open. 2. Min. of tCK is shown at AC characteristics. Rev 1.0 December, 2001 5 A-Data ADS8608A8A AC Characteristics Speed Parameter 75 Symbol 75A Unit Min Max Min Max Note System clock /CAS Latency = 2 tCK2 7.5 1000 10 10 Cycle time /CAS Latency = 3 tCK3 7 1000 7.5 7 Clock high pulse width tCHW 2.5 2.5 ns 1 Clock low pulse width tCLW 2.5 2.5 ns 1 Access time form /CAS Latency = 2 tAC2 5.4 clock 2 tAC3 5.4 ns /CAS Latency = 3 Write Recovery /CAS Latency = 2 tWR2 7.5 10 Time /CAS Latency = 3 tWR3 7 7.5 /RAS cycle time tRC 56 65 ns /RAS to /CAS delay tRCD 15 20 ns /RAS active time tRAS 40 /RAS precharge time tRP 15 20 ns /RAS to /RAS bank active delay tRRD 15 15 ns /CAS to /CAS delay tCCD 1 1 CLK Data – input setup time tDS 1.5 1.5 ns 1 Data – input hold time tDH 0.8 0.8 ns 1 Address setup time tAS 1.5 1.5 ns 1 Address hold time tAH 0.8 0.8 ns 1 CKE setup time tCKS 1.5 1.5 ns 1 CKE hold time tCKH 0.8 0.8 ns 1 Command setup time tCMS 1.5 1.5 ns 1 Command hold time tCMH 0.8 0.8 ns 1 Output Data Hold Time tOH 3 3 ns Output Data High Impedance Time tHZ 3 Output Data Low Impedance Time tLZ 0 0 ns Mode register Set Cycle Time tRSC 14 15 ns Refresh time tREF 100K 7 64 Note : 1. Assume tR / tF (input rise and fall time) is 1 ns. 2. Access times to be measured with input signals of 1v / ns edge rate. 3.A new command can be given tRRC after self refresh exit. Rev 1.0 December, 2001 6 45 3 ns 7.5 100K 7.5 64 ns ns ms A-Data ADS8608A8A Command Truth-Table Command CKEn-1 CKEn /CS /RAS /CAS /WE DQM Mode Register Set H X L L L L X OP code H X X X No Operation H X X X L H H H Bank Active H X L L H H X H X L H L H X ADDR A10/AP RA Read BA V L CA Read with Auto Precharge Write H X L H L L X CA Write with Auto Precharge H X L L H L X Precharge select Bank Burst Stop H DQM H Auto Refresh H H L L L Entry H L L L X L H H H X Exit L H L X X L H X X X H X X X Precharge L H H H Power down H X X X L H H H H X X X L V V V Exit Rev 1.0 December, 2001 L X X L X H X X L Clock Suspend V H H H L X H L X V H H H X L Entry V X X X Self Refresh Exit L H Precharge All Bank Entry V H X H X 7 X X A-Data ADS8608A8A Package Information SYMBOL A A1 A2 B c D HE E e L L1 S θ MIN. MILLIMETER NOM. 0.05 ----0.24 ----- 0.10 1.00 0.32 0.15 MAX. 1.20 0.15 ----0.40 ------ 22.12 22.22 22.62 11.56 10.06 ----0.40 0° 11.76 10.16 0.80 BSC 0.50 0.80 REF 0.71 REF - MIN. 11.96 10.26 ----0.60 0.002 ----0.009 ----0.871 0.455 0.396 ----0.016 8° 0° 400mil 54pin TSOP II Package Rev 1.0 December, 2001 8 INCH NOM. 0.004 0.039 0.012 0.005 MAX. 0.047 0.006 ----0.016 ----- 0.875 0.905 0.463 0.400 0.031 0.020 0.032 REF 0.028 REF - 0.471 0.404 ----0.024 8°