ON FAN53202 5 a, 2.4 mhz, digitally programmable tinybuck regulator Datasheet

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FAN53202
5 A, 2.4 MHz, Digitally Programmable TinyBuck®
Regulator
Features
Description



The FAN53202 is a step-down switching voltage
regulator that delivers a digitally programmable output
from an input voltage supply of 2.5 V to 5.5 V. The
2
output voltage is programmed through an I C interface
capable of operating up to 3.4 MHz.
Up to 91% Efficiency
Quiescent Current in PFM Mode: 60 µA (Typical)
Digitally Programmable Output Voltage:
- 0.6-1.3875 V in 12.5 mV Steps










Best-in-Class Load Transient
Continuous Output Current Capability: 5 A
2.5 V to 5.5 V Input Voltage Range
Programmable Slew Rate for Voltage Transitions
Fixed-Frequency Operation: 2.4 MHz
2
I C-Compatible Interface Up to 3.4 Mbps
Internal Soft-Start
Input Under-Voltage Lockout (UVLO)
Thermal Shutdown and Overload Protection
20-Bump Wafer-Level Chip Scale Package (WLCSP)
Applications

Application, Graphic, and DSP Processors
- ARM™, Krait™, OMAP™, NovaThor™,
ARMADA™




Hard Disk Drives
Tablets, Netbooks, Ultra-Mobile PCs
Using a proprietary architecture with synchronous
rectification, the FAN53202 is capable of delivering 5 A
continuous at over 80% efficiency, while maintaining
over 80% efficiency at load currents as low as 10 mA.
The device can also support a 7 A 500 ms pulse. The
regulator operates at a nominal fixed frequency of
2.4 MHz, which reduces the value of the external
components to 330 nH for the inductor and as low as
22 µF for the output capacitor. Additional output
capacitance can be added to improve regulation during
load transients without affecting stability. Inductance up
to 1.2 µH may be used with additional output
capacitance.
At moderate and light loads, Pulse Frequency Modulation
(PFM) is used to operate in Power-Save Mode with a
typical quiescent current of 60 µA. Even with such a low
quiescent current, the part exhibits excellent transient
response during large load swings. At higher loads, the
system automatically switches to fixed-frequency control,
operating at 2.4 MHz. In Shutdown Mode, the supply
current drops below 1 µA, reducing power consumption.
PFM Mode can be disabled if constant frequency is
desired. The FAN53202 is available in a 20-bump, 1.6 x
2 mm, WLCSP.
Smart Phones
Gaming Devices
PVIN
CIN
EN
VOUT
SCA
SCL
FAN53202
SW
COUT
VSEL
GND
AGND
All trademarks are the property of their respective owners.
© 2015 Fairchild Semiconductor Corporation
FAN53202 • Rev. 1.0
L1
Figure 1.
VDD
Core
Processor
(System Load)
Typical Application
www.fairchildsemi.com
FAN53202 — 5 A. 2.4 MHz, Digitally Programmable TinyBuck® Regulator
April 2015
Power-Up
Defaults
Part Number
Max
Pulse Temperature
Packing Device
Package
Current
Range
Method Marking
(500ms)
I2C Slave
Address
VSEL0 VSEL1
FAN53202UC23X
1.15 V
1.15 V
C0
7.0 A
-40 to 85°C
WLCSP20
Tape
& Reel
CK
Pin Configuration
VSEL*
EN
SCL
VOUT
A1
A2
A3
A4
B2
B3
B4
C2
C3
C4
D1
D2
D3
D4
E1
E2
E3
E4
SDA
AGND
B1
GND
C1
VIN
SW
Figure 2.
Top View
Pin Definitions
Pin #
Name
Description
A1
VSEL
Voltage Select. When this pin is LOW, VOUT is set by the VSEL0 register. When this pin is
HIGH, VOUT is set by the VSEL1 register.
A2
EN
Enable. The device is in Shutdown Mode when this pin is LOW. All register values are kept
during shutdown. All registers go to default values when EN pin is LOW.
A3
SCL
I C Serial Clock
A4
VOUT
B1
SDA
I C Serial Data
B2, B3,
C1 – C4
GND
Ground. Low-side MOSFET is referenced to this pin. CIN and COUT should be returned with a
minimal path to these pins.
B4
AGND
Analog Ground. All signals are referenced to this pin. Avoid routing high dV/dt AC currents
through this pin.
D1, D2,
E1, E2
VIN
Power Input Voltage. Connect to the input power source. Connect to CIN with minimal path.
D3, D4,
E3, E4
SW
Switching Node. Connect to the inductor.
2
VOUT. Sense pin for VOUT. Connect to COUT.
2
© 2015 Fairchild Semiconductor Corporation
FAN53202 • Rev. 1.0
www.fairchildsemi.com
2
FAN53202 — 5 A, 2.4 MHz, Digitally Programmable TinyBuck® Regulator
Ordering Information
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
VIN
Voltage on SW, VIN Pins
Voltage on All Other Pins
VOUT
Parameter
Min.
Max.
IC Not Switching
-0.3
7.0
IC Switching
-0.3
6.5
IC Not Switching
-0.3
Voltage on VOUT Pin
(1)
VINOV_SLEW Maximum Slew Rate of VIN > 6.5 V, PWM Switching
ESD
Electrostatic Discharge
Protection Level
V
VIN
-0.3
Human Body Model,
ANSI/ESDA/JEDEC JS-001-2012
2500
Charged Device Model per JESD22-C101
1500
Unit
V
3.0
V
100
V/ms
V
TJ
Junction Temperature
-40
+150
°C
TSTG
Storage Temperature
-65
+150
°C
+260
°C
TL
Lead Soldering Temperature, 10 Seconds
Note:
1. Lesser of 7 V or VIN+0.3 V.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
Parameter
VIN
Supply Voltage Range
IOUT
Output Current
L
CIN
COUT
Min.
Max.
Unit
2.5
5.5
V
0
5
A
Inductor
Typ.
0.33
µH
Input Capacitor
10
µF
Output Capacitor
44
µF
TA
Operating Ambient Temperature
-40
+85
°C
TJ
Operating Junction Temperature
-40
+125
°C
Max.
Unit
Thermal Properties
Symbol
JA
Parameter
Junction-to-Ambient Thermal Resistance
Min.
(2)
Typ.
38
°C/W
Note:
2. See Thermal Considerations in the Application Information section.
© 2015 Fairchild Semiconductor Corporation
FAN53202 • Rev. 1.0
www.fairchildsemi.com
3
FAN53202 — 5 A, 2.4 MHz, Digitally Programmable TinyBuck® Regulator
Absolute Maximum Ratings
Minimum and maximum values are at VIN = 2.5 V to 5.5 V, TA=-40°C to +85°C, unless otherwise noted. Typical values
are at TA=25°C, VIN = 5V and EN=HIGH.
Symbol
Parameter
Condition
Min.
Typ. Max. Unit
Power Supplies
IQ
I SD
Quiescent Current
ILOAD=0
60
100
µA
H/W Shutdown Supply Current
EN=GND
0.1
5.0
µA
41
75
µA
2.35
2.45
V
S/W Shutdown Supply Current
EN= VIN, BUCK_ENx=0
VUVLO
Under-Voltage Lockout Threshold
VIN Rising
VUVHYST
Under-Voltage Lockout Hysteresis
350
mV
EN, VSEL, SDA, SCL
VIH
HIGH-Level Input Voltage
VIL
LOW-Level Input Voltage
VLHYST
Logic Input Hysteresis Voltage
IIN
Input Bias Current for Logic Pin
1.1
V
0.4
160
Input Tied to GND or 1.8V
V
mV
0.01
1.00
µA
1
mA
0.01
1.00
µA
4.0
%
11.5
A
PGOOD
IOUTL
PGOOD Pull-Down Current
IOUTH
PGOOD HIGH Leakage Current
VOUT Regulation
VREG
VOUT DC Accuracy
IOUT(DC)=0 to 5A, Auto Mode,
2.5 V ≤ VIN ≤ 4.5 V
-2.0
Open Loop
8.5
Power Switch and Protection
ILIMPK
P-MOS Peak Current Limit
VSDWN
Input OVP Shutdown
Rising Threshold
Falling Threshold
10.0
6.15
V
5.50
5.85
V
2.05
2.40
Frequency Control
fSW
ROFF
Oscillator Frequency (FPWM)
VOUT Pull-Down Resistance, Disabled
EN=0 or VIN<VUVLO
160
2.75
MHz
Ω
Note:
3. Monotonicity assured by design.
© 2015 Fairchild Semiconductor Corporation
FAN53202 • Rev. 1.0
www.fairchildsemi.com
4
FAN53202 — 5 A, 2.4 MHz, Digitally Programmable TinyBuck® Regulator
Electrical Characteristics
The following table is verified by design and verified while using the following external components: L = 0.33 µH,
DFE252012F (TOKO), CIN = C2012X5R1A106M (TDK), COUT = 2 x C2012X5R0J226M (TDK) These parameters are
not verified in production. Minimum and maximum values are at VIN = 2.5 V to 5.5 V, VEN = 1.8 V, TA = -40°C to +85°C;
circuit of Figure 1, unless otherwise noted. Typical values are at TA = 25°C, VIN = 3.6V, VEN = 1.8 V.
Symbol
ΔVOUT1
ΔVOUT2
VOUT_RIPPLE

Parameter
Load Regulation
Line Regulation
Ripple Voltage
Efficiency
Min.
Typ.
IOUT = 0 A to 2.5 A, VIN = 3.8 V
(Auto)
0.3
IOUT = 1 A to 5 A, VIN = 3.8 V
(PWM)
0.1
3.6 V ≤ VIN ≤ 4.0 V, IOUT = 3 A
0.03
Unit
%/A
VIN = 3.8 V, IOUT = 100 mA,
PFM Mode
15
VIN = 3.8 V, IOUT = 2000 mA,
PWM Mode
5
PVIN = 3.6 V, VOUT = 1.15 V,
IOUT = 100 mA
PVIN = 3.6 V, VOUT = 1.15 V,
IOUT = 500 mA
PVIN = 3.6 V, VOUT = 1.15 V,
IOUT = 2 A
Max.
%/V
mV
87
89
%
89
Soft-Start
EN High to 95% of Target_ VOUT.
(1.15 V), RLOAD = 50 Ω
340
µs
VOUT_LOAD
Load Transient
IOUT = 0.1 A  1.2 A,
TR= TF =100 ns
±40
mV
VOUT_LINE
Line Transient
VIN = 3.0 V3.6 V,
TR = TF = 10 s, IOUT = 500 mA
±25
mV
150
°C
TSS
TLIMIT
Thermal Shutdown
© 2015 Fairchild Semiconductor Corporation
FAN53202 • Rev. 1.0
www.fairchildsemi.com
5
FAN53202 — 5 A, 2.4 MHz, Digitally Programmable TinyBuck® Regulator
System Characteristics
95%
95%
90%
90%
85%
85%
80%
80%
Efficiency
Efficiency
Unless otherwise specified, VIN = 3.6 V, VOUT = 1.15 V, VEN = 1.8 V, TA = 25°C; circuit and components according to
Figure 1.
75%
70%
75%
70%
65%
65%
60%
2.7 Vin
60%
55%
3.6 Vin
55%
4.2 Vin
50%
50%
1
10
100
-40℃
25℃
85℃
1
1000
10
Output Current (mA)
Figure 3.
Efficiency vs. Load Current and Input
Voltage
Figure 4.
0.875
Efficiency vs. Load Current and
Temperature
0.865
2.7 Vin
1.18
3.6 Vin
Output Voltage (V)
Output Voltage (V)
1000
1.185
2.7 Vin
0.87
4.2 Vin
0.86
0.855
0.85
3.6 Vin
1.175
4.2 Vin
1.17
1.165
1.16
1.155
1.15
0.845
0
1000
2000
3000
4000
1.145
5000
0
Output Current (mA)
Figure 5.
Output Regulation vs. Load Current and
Input Voltage, VOUT=0.85 V
Figure 6.
1000
900
900
800
800
Output Current (mA)
1000
Output Current (mA)
100
Output Current (mA)
700
600
500
1000
2000
3000
Output Current (mA)
4000
5000
Output Regulation vs. Load Current and
Input Voltage, VOUT=1.15 V
700
600
500
400
400
PFM Exit
300
300
PFM Exit
PFM Enter
PFM Enter
200
200
2.5
Figure 7.
3
3.5
4
4.5
Input Voltage (V)
5
PFM Entry / Exit Level vs. Input Voltage,
VOUT=0.85 V
© 2015 Fairchild Semiconductor Corporation
FAN53202 • Rev. 1.0
2.5
5.5
Figure 8.
3
3.5
4
4.5
Input Voltage (V)
5
5.5
PFM Entry / Exit Level vs. Input Voltage,
VOUT=1.15 V
www.fairchildsemi.com
6
FAN53202 — 5 A, 2.4 MHz, Digitally Programmable TinyBuck® Regulator
Typical Characteristics
Unless otherwise specified, VIN = 3.6 V, VOUT = 1.15 V, VEN = 1.8 V, TA = 25°C; circuit and components according to
Figure 1.
3000
25
Switching Freq. (KHz)
Ripple Voltage (mVpp)
30
3.6 Vin, 1.15 Vout, Auto
3.6 Vin, 1.15 Vout, FPWM
5 Vin, 1.15 Vout, Auto
5 vin, 1.15 Vout, FPWM
20
15
10
5
2500
2000
1500
3.6Vin, 0.85Vout, Auto
3.6Vin, 1.15Vout, Auto
1000
5Vin, 0.85Vout, Auto
500
0
5Vin, 1.15Vout, Auto
0
0
1000
2000
3000
4000
5000
0
1000
Output Current (mA)
Figure 9.
2000
3000
4000
Output Ripple vs. Load Current
Figure 10.
80
Frequency vs. Load Current
5
4.5
70
-40℃
4
25℃
3.5
60
Isd (μA)
Input Current (μA)
5000
Output Current (mA)
50
40
2.5
2
1.5
-40℃
30
85℃
3
25℃
1
85℃
0.5
20
0
2.5
3
3.5
4
4.5
5
5.5
2.5
Input Voltage (V)
Figure 11.
Quiescent Current vs. Input Voltage and
Temperature, Auto PWM
Figure 13. Line Transient, VIN = 3.0 V  3.6 V,
TR=TF=10 µs Auto Mode IOUT = 250 mA
© 2015 Fairchild Semiconductor Corporation
FAN53202 • Rev. 1.0
3
3.5
4
4.5
5
5.5
Input Voltage (V)
Figure 12.
Shutdown Current vs. Input Voltage
and Temperature
Figure 14. Line Transient, VIN = 3.0 V  3.6 V,
TR=TF=10 µs Auto Mode IOUT = 2 A
www.fairchildsemi.com
7
FAN53202 — 5 A, 2.4 MHz, Digitally Programmable TinyBuck® Regulator
Typical Characteristics (Continued)
Unless otherwise specified, VIN = 3.6 V, VOUT = 1.15 V, VEN = 1.8 V, TA = 25°C; circuit and components according to
Figure 1.
Load Transient, IOUT = 0.1 A 1.6 A,
Auto Mode TR = TF = 100 ns
Figure 16. Load Transient, IOUT = 0.1 A 1.6 A,
FPWM Mode TR = TF = 100 ns
Figure 17. Load Transient, IOUT = 1.5 A  3 A,
Auto Mode TR = TF = 100 ns
Figure 18. Load Transient, IOUT = 3.5 A  5 A,
Auto Mode TR = TF = 100 ns
Figure 15.
© 2015 Fairchild Semiconductor Corporation
FAN53202 • Rev. 1.0
www.fairchildsemi.com
8
FAN53202 — 5 A, 2.4 MHz, Digitally Programmable TinyBuck® Regulator
Typical Characteristics (Continued)
The FAN53202 is a step-down switching voltage
regulator that delivers a programmable output voltage
from an input voltage supply of 2.5 V to 5.5 V. Using a
proprietary architecture with synchronous rectification, the
FAN53202 is capable of delivering 5 A at over 80%
efficiency. The regulator operates at a nominal frequency
of 2.4 MHz at full load, which reduces the value of the
external components to 330 nH for the output inductor
and 22 µF for the output capacitor. High efficiency is
maintained at light load with single-pulse PFM.
2
The FAN53202 integrates an I C-compatible interface,
allowing transfers up to 3.4 Mbps. This communication
interface can be used to:

Dynamically re-program the output voltage in
12.5 mV



Reprogram the mode to enable or disable PFM;
Control voltage transition slew rate; or
If large output capacitance values are used, the regulator
may fail to start. Maximum COUT capacitance for
successfully starting with a heavy constant-current load is
approximately:
COUTMAX  ILIMPK  ILOAD  
(1)
where COUTMAX is expressed in F and ILOAD is the
load current during soft-start, expressed in A.
If the regulator is at its current limit for 16 consecutive
current limit cycles, the regulator shuts down and enters
3-state before reattempting soft-start 1700 ms later. This
limits the duty cycle of full output current during soft-start
to prevent excessive heating.
The IC allows for software enable of the regulator, when
EN is HIGH, through the BUCK_EN bits. BUCK_EN0 and
BUCK_EN1 are both initialized HIGH.
Table 1.
Enable / disable the regulator.
Hardware and Software Enable
Pins
Control Scheme
The FAN53202 uses a proprietary non-linear, fixedfrequency PWM modulator to deliver a fast load transient
response, while maintaining a constant switching
frequency over a wide range of operating conditions. The
regulator performance is independent of the output
capacitor ESR, allowing for the use of ceramic output
capacitors. Although this type of operation normally
results in a switching frequency that varies with input
voltage and load current, an internal frequency loop holds
the switching frequency constant over a large range of
input voltages and load currents.
320 
VOUT
EN VSEL
BITS
BUCK_EN0
BUCK_EN1
Output
0
X
X
X
OFF
1
0
0
X
OFF
1
0
1
X
ON
1
1
X
0
OFF
1
1
X
1
ON
VSEL Pin and I2C Programming Output
Voltage
For very light loads, the FAN53202 operates in
Discontinuous Current Diode (DCM) single-pulse PFM,
which produces low output ripple compared with other
PFM architectures. Transition between PWM and PFM is
relatively seamless, providing a smooth transition
between DCM and CCM Modes.
The output voltage is set by the NSELx control bits in
VSEL0 and VSEL1 registers. The output voltage is given
as:
PFM can be disabled by programming the MODE bit
HIGH in the VSEL registers.
Output voltage can also be controlled by toggling the
VSEL pin LOW or HIGH. VSEL LOW corresponds to
VSEL0 and VSEL HIGH corresponds to VSEL1. Upon
POR, VSEL0 and VSEL1 are reset to their default
voltages, shown in Table 5.
Enable and Soft-Start
When the EN pin is LOW; the IC is shutdown, all internal
circuits are off, and the part draws very little current. In
2
this state, I C cannot be written to or read from. All
registers are reset to default values when EN pin is LOW.
VOUT  0.60V  NSELx  12.5mV
(2)
When the OUTPUT_DISCHARGE bit in the CONTROL
register is enabled (logic HIGH) and the EN pin is LOW or
the BUCK_ENx bit is LOW, a load is connected from
VOUT to GND to discharge the output capacitors.
Raising EN while the BUCK_ENx bit is HIGH activates
the part and begins the soft-start cycle. During soft-start,
the modulator’s internal reference is ramped slowly to
minimize surge currents on the input and prevent
overshoot of the output voltage. Synchronous
rectification is inhibited during soft-start, allowing the IC
to start into a pre-charged capacitive load.
© 2015 Fairchild Semiconductor Corporation
FAN53202 • Rev. 1.0
www.fairchildsemi.com
9
FAN53202 — 5 A, 2.4 MHz, Digitally Programmable TinyBuck® Regulator
Operation Description
Current Limiting
When transitioning from a low- to high-voltage, the IC
can be programmed for one of eight possible slew rates
using the SLEW bits in the CONTROL register (Table 5
and Table 6).
A heavy load or short circuit on the output causes the
current in the inductor to increase until a maximum
current threshold is reached in the high-side switch. Upon
reaching this point, the high-side switch turns off,
preventing high currents from causing damage. Sixteen
consecutive current limit cycles in current limit cause the
regulator to shut down and stay off for about 1700 s
before attempting a restart.
Table 2.
Transition Slew Rate
Decimal
Bin
Slew Rate
0
000
80
mV / µs
1
001
40
mV / µs
Thermal Shutdown
2
010
20
mV / µs
3
011
10
mV / µs
4
100
5
mV / µs
5
101
2.5
mV / µs
When the die temperature increases, due to a high load
condition and/or high ambient temperature, the output
switching is disabled until the die temperature falls
sufficiently. The junction temperature at which the thermal
shutdown activates is nominally 150°C with a 17°C
2
hysteresisI C Interface
6
110
1.25
mV / µs
7
111
0.625
mV / µs
Transitions from high to low voltage rely on the output
load to discharge VOUT to the new set point. Once the
high-to-low transition begins, the IC stops switching until
VOUT has reached the new set point.
Under-Voltage Lockout
When EN is HIGH, the under-voltage lockout keeps the
part from operating until the input supply voltage rises
HIGH enough to properly operate. This ensures proper
operation of the regulator during startup or shutdown.
I2C Interface
The FAN53202’s serial interface is compatible with
2
Standard, Fast, Fast Plus, and HS Mode I C-Bus®
specifications. The FAN53202’s SCL line is an input and
its SDA line is a bi-directional open-drain output; it can
only pull down the bus when active. The SDA line only
pulls LOW during data reads and when signaling ACK. All
data is shifted in MSB (bit 7) first.
I2C Slave Address
In hex notation, the slave address assumes a 0 LS Bit.
The hex slave address is C0.
Table 3.
2
I C Slave Address
Input Over-Voltage Protection (OVP)
When VIN exceeds VSDWN (about 6.2 V) the IC stops
switching to protect the circuitry from internal spikes
above 6.5 V. An internal filter prevents the circuit from
shutting down due to noise spikes.
Bits
Hex
C0
7
6
5
4
3
2
1
0
1
1
0
0
0
0
0
R/ W
Other slave addresses can be assigned. Contact a
Fairchild Semiconductor representative.
© 2015 Fairchild Semiconductor Corporation
FAN53202 • Rev. 1.0
www.fairchildsemi.com
10
FAN53202 — 5 A, 2.4 MHz, Digitally Programmable TinyBuck® Regulator
Transition Slew Rate Limiting
Slave Releases
As shown in Figure 19, data is normally transferred when
SCL is LOW. Data is clocked in on the rising edge of
SCL. Typically, data transitions shortly at or after the
falling edge of SCL to allow ample time for the data to set
up before the next SCL rising edge.
Figure 22.
REPEATED START Timing
High-Speed (HS) Mode
The protocols for High-Speed (HS), Low-Speed (LS), and
Fast-Speed (FS) Modes are identical, except the bus
speed for HS mode is 3.4 MHz. HS Mode is entered
when the bus master sends the HS master code
00001XXX after a START condition. The master code is
sent in Fast or Fast-Plus Mode (less than 1 MHz clock);
slaves do not ACK this transmission.
tH
tSU
The master generates a REPEATED START condition
(Figure 20 that causes all slaves on the bus to switch to
2
HS Mode. The master then sends I C packets, as
described above, using the HS Mode clock rate and
timing.
Data Transfer Timing
Each bus transaction begins and ends with SDA and SCL
HIGH. A transaction begins with a START condition,
which is defined as SDA transitioning from 1 to 0 with
SCL HIGH, as shown in Figure 20
tHD;STA
SDA
SLADDR
MS Bit
SCL
SDA
Figure 19.
tHD;STA
ACK(0) or
NACK(1)
SDA
Data change allowed
SCL
tSU;STA
The bus remains in HS Mode until a STOP bit (Figure 21)
is sent by the master. While in HS Mode, packets are
separated by REPEATED START conditions (Figure 22)
Read and Write Transactions.
Slave Address
MS Bit
The following figures outline the sequences for data read
and write. Bus control is signified by the shading of the
SCL
Figure 20.
START Bit
packet,
A transaction ends with a STOP condition, which is
defined as SDA transitioning from 0 to 1 with SCL HIGH,
as shown in Figure 21.
defined
Master Drives Bus
as
Slave Drives Bus
and
. All addresses and data are MSB
first.
2
Slave Releases
Master Drives
Table 4. I C Bit Definitions for Figure 23 &
Figure 24
tHD;STO
ACK(0) or
NACK(1)
SDA
Symbol
SCL
Figure 21.
STOP Bit
7 bits
S
Slave Address
0
S
Slave Address
0
P
STOP, see Figure 21
S
START, see Figure 20
ACK. The slave drives SDA to 0 to
acknowledge the preceding packet.
NACK. The slave sends a 1 to NACK the
preceding packet.
A
R
REPEATED START, see Figure 22
P
STOP, see Figure 21
0
8 bits
0
8 bits
0
Reg Addr
A
Data
A
P
Write Transaction
0
8 bits
0
A
Reg Addr
A
Figure 24.
© 2015 Fairchild Semiconductor Corporation
FAN53202 • Rev. 1.0
REPEATED START, see Figure 22
A
Figure 23.
7 bits
R
A
During a read from the FAN53202, the master issues a
REPEATED START after sending the register address,
and before resending the slave address. The REPEATED
START is a 1 to 0 transition on SDA while SCL is HIGH,
as shown in Figure 22.
Definition
7 bits
R
Slave Address
1
0
8 bits
1
A
Data
A
P
Read Transaction
www.fairchildsemi.com
11
FAN53202 — 5 A, 2.4 MHz, Digitally Programmable TinyBuck® Regulator
Bus Timing
Table 5.
Map
Hex
Address
Name
00
VSEL0
Controls VOUT settings when VSEL pin = 0
01
VSEL1
Controls VOUT settings when VSEL pin = 1
02
CONTROL
03
ID1
Read-only register identifies vendor and chip type
04
ID2
Read-only register identifies die revision
05
MONITOR
Table 6.
Function
Determines whether VOUT output discharge is enabled and also the slew rate of
positive transitions
Indicates device status
Bit Definitions
The following table defines the operation of each register bit. Bold indicates power-on default values.
Bit
Name
VSEL0
Value
R/W
7
BUCK_EN0
6
MODE0
5:0
NSEL0
VSEL1
BUCK_EN1
6
MODE1
5:0
NSEL1
CONTROL
1
Software buck enable. When EN pin is LOW, the regulator is off. When EN pin is
HIGH, BUCK_EN bit takes precedent.
0
Allow Auto-PFM Mode during light load.
1
Forced PWM Mode.
Sets VOUT value from 0.6V to 1.3875 V in 12.5 mV steps
R/W
7
Description
Register Address: 00
Register Address: 01
1
Software buck enable. When EN pin is LOW, the regulator is off. When EN pin is
HIGH, BUCK_EN bit takes precedent.
0
Allow AUTO-PFM Mode during light load.
1
Forced PWM Mode.
Sets VOUT value from 0.6V to 1.3875 V in 12.5 mV steps
R/W
Register Address: 02
0
When the regulator is disabled, VOUT is not discharged.
1
When the regulator is disabled, VOUT discharges through an internal pull-down.
7
OUTPUT_DISCHARGE
6:4
SLEW
000
3
Reserved
0
Always reads back 0
2
Reserved
0
Always reads back 0
1:0
Reserved
00
Always reads back 00
ID1
R
7:5
VENDOR
4
Reserved
0
DIE_ID
0000
3:0
Sets the slew rate for positive voltage transitions (see Table 2).
Register Address: 03
100
Signifies Fairchild as the IC vendor
Always reads back 0
Refer to ordering information
ID2
R
7:4
Reserved
0000
Always reads back 0000
3:0
DIE_REV
1100
IC mask revision
MONITOR
Register Address: 04
R
Register Address: 05
7
PGOOD
0
6:0
Not used
000 0000
© 2015 Fairchild Semiconductor Corporation
FAN53202 • Rev. 1.0
1: buck is enabled and soft-start is completed
Always reads back 000 0000
www.fairchildsemi.com
12
FAN53202 — 5 A, 2.4 MHz, Digitally Programmable TinyBuck® Regulator
Register Description
Selecting the Inductor
The output inductor must meet both the required
inductance and the energy-handling capability of the
application. The inductor value affects the average
current limit, the output voltage ripple, and the efficiency.
The ripple current (∆I) of the regulator is:
 V  VOUT 

  IN
(3)

 L  fSW 
The maximum average load current, IMAX(LOAD), is related
to the peak current limit, ILIM(PK), by the ripple current
such that:
I 
VOUT
VIN
IMAX(LOAD )  ILIM(PK )
I

2
(4)
The FAN53202 is optimized for operation with
L=330 nH, but is stable with inductances up to 1.0 H
(nominal). The inductor should be rated to maintain at
least 80% of its value at ILIM(PK). Failure to do so will
lower the amount of DC current the IC can deliver.
Efficiency is affected by the inductor DCR and
inductance value. Decreasing the inductor value for a
given physical size typically decreases the DCR; but
since ∆I increases, the RMS current increases, as do
core and skin-effect losses.
IRMS 
IOUT(DC) 2 
I 2
12
(5)
The increased RMS current produces higher losses
through the RDS(ON) of the IC MOSFETs as well as the
inductor ESR.
Increasing the inductor value produces lower RMS
currents, but degrades transient response. For a given
physical inductor size, increased inductance usually
results in an inductor with lower saturation current.
Table 7. Effects of Inductor Value (from
330 nH
Recommended)
on
Regulator
Performance
IMAX(LOAD)
Increase
∆VOUT
(Eq.(7))
Decrease
Transient Response
Degraded
Inductor Current Rating
The current limit circuit can allow substantial peak
currents to flow through L1 under worst-case conditions.
If it is possible for the load to draw such currents, the
inductor should be capable of sustaining the current or
failing in a safe manner.
For space-constrained applications, a lower current rating
for L1 can be used. The FAN53202 may still protect these
inductors in the event of a short circuit, but may not be
able to protect the inductor from failure if the load is able
to draw higher currents than the DC rating of the inductor.
Output Capacitor and VOUT Ripple
voltage effects, the 0603 capacitors have a lower incircuit capacitance than the 0805 package, which can
degrade transient response and output ripple.
Increasing COUT has negligible effect on loop stability
and can be increased to reduce output voltage ripple or
to improve transient response. Output voltage ripple,
∆VOUT, is calculated by:
f

C
 ESR2
1
VOUT  IL  SW OUT


2  D  1  D
8  fSW  COUT 

where COUT is the effective output capacitance.
(6)
The capacitance of COUT decreases at higher output
voltages, which results in higher ∆VOUT. Equation (6) is
only valid for Continuous Current Mode (CCM) operation,
which occurs when the regulator is in PWM Mode.
For large COUT values, the regulator may fail to start under
a load. If an inductor value greater than 1.0 H is used, at
least 30 F of COUT should be used to ensure stability.
The lowest ∆VOUT is obtained when the IC is in PWM
Mode and, therefore, operating at 2.4 MHz. In PFM
Mode, fSW is reduced, causing ∆VOUT to increase.
ESL Effects
The Equivalent Series Inductance (ESL) of the output
capacitor network should be kept low to minimize the
square-wave component of output ripple that results from
the division ratio COUT ESL and the output inductor (LOUT).
The square-wave component due to the ESL can be
estimated as:
VOUT(SQ )  VIN 
ESLCOUT
L1
(7)
A good practice to minimize this ripple is to use multiple
output capacitors to achieve the desired COUT value. For
example, to obtain COUT=20 F, a single 22 F 0805
would produce twice the square wave ripple as two x
10 F 0805.
To minimize ESL, try to use capacitors with the lowest
ratio of length to width. 0805s have lower ESL than
1206s. If low output ripple is a chief concern, some
vendors produce 0508 or 0612 capacitors with ultra-low
ESL. Placing additional small-value capacitors near the
load also reduces the high-frequency ripple components.
Input Capacitor
The ceramic input capacitors should be placed as close
as possible between the VIN pin and PGND to minimize
the parasitic inductance. If a long wire is used to bring
power to the IC, additional “bulk” capacitance (electrolytic
or tantalum) should be placed between CIN and the power
source lead to reduce under-damped ringing that can
occur between the inductance of the power source leads
and CIN.
The effective CIN capacitance value decreases, as VIN
increases due to DC bias effects. This has no significant
impact on regulator performance.
The reference BOM suggests 0805 capacitors, but 0603
capacitors may be used if space is at a premium. Due to
© 2015 Fairchild Semiconductor Corporation
FAN53202 • Rev. 1.0
www.fairchildsemi.com
13
FAN53202 — 5 A, 2.4 MHz, Digitally Programmable TinyBuck® Regulator
Application Information
Estimate inductor copper losses using:
Heat is removed from the IC through the solder bumps to
the PCB copper. The junction-to-ambient thermal
resistance (JA) is largely a function of the PCB layout
(size, copper weight, and trace width) and the
temperature rise from junction to ambient (T).
PL  ILOAD  DCR L
3.
For the FAN53202UC, JA is 38°C/W when mounted on
its four-layer evaluation board in still air with two-ounce
outer layer copper weight and one-ounce inner layers.
Halving the copper thickness results in an increased JA
of 48°C/W.
4.
For long-term reliable operation, the IC’s junction
temperature (TJ) should be maintained below 125°C.
To calculate maximum operating temperature (<125°C)
for a specific application:
1.
Use efficiency graphs to determine efficiency for the
desired VIN, VOUT, and load conditions.
2.
Calculate total power dissipation using:
1 
PT  VOUT  ILOAD    1
 
2
(9)
Determine IC losses by removing inductor losses
(step 3) from total dissipation:
PIC  PT  PL
(10)
Determine device operating temperature:
T  PIC   JA
and
(11)
TIC  TA  T
It is important to note that the RDS(ON) of the IC’s power
MOSFETs increases linearly with temperature at about
1.21%/°C. This causes the efficiency () to degrade with
increasing die temperature.
(8)
where η is efficiency from Figure 3 and Figure 4.
Recommended External Components
Table 8.
Recommended Capacitors
Component
Quantity
Vendor
Vendor
C (µF)
Size
Rated
COUT
2 Pieces
C2012X5R0J226M
TDK
22
0805
6.3 V
CIN
1 Piece
C2012X5R1A106M
TDK
10
0805
6.3 V
Table 9.
Recommended Inductors
Part#
L (nH)
DCR (mΩ)
DFE201610E-R47M
470
16
TOKO
DFE252012F_R33M
330
TOKO
FDSD0412-H-R33M
330
Mag. Layers
MMD-04ABNR33M-M1-RU
CYNTEC
TDK
Manufacturer
(4)
TOKO
ISAT
(4)
L
W
H
6.3
2.0
1.6
1.0
14
8.5
2.5
2.0
1.2
16
10
4.0
4.0
1.2
330
12.5
7.5
4.5
4.1
1.2
PIMB041B-R33MS
330
17
8.4
4.4
4.2
1.0
VLC5020T-R47M
470
15
5.4
5.0
5.0
2.0
Note:
4. This inductor is recommended for applications with IOUT < 3 A.
© 2015 Fairchild Semiconductor Corporation
FAN53202 • Rev. 1.0
www.fairchildsemi.com
14
FAN53202 — 5 A, 2.4 MHz, Digitally Programmable TinyBuck® Regulator
Thermal Considerations
Connect VOUT to “+’ side of COUT cap
Do not connect AGND to GND. Place via in pad of AGND
and connect directly to System GND
Dedicated GND bumps for CIN and COUT, which
connect directly to System GND of phone board
Route all logic on this layer or inner layer
VSEL
EN
SCL
VOUT
SDA
GND
GND
AGND
GND
GND
GND
GND
VIN
VIN
SW
SW
VIN
VIN
SW
SW
COUT
CIN
CIN1
VIN vias bring power to device
L
VOUT bus should be taken from + side
capacitor
Figure 25.
Guidance for Layer 1
Dedicated GND bumps for CIN and COUT, which
connect directly to System GND of phone board
Route all logic on this layer or inner layer
VSEL
EN
SCL
VOUT
SDA
GND
GND
AGND
GND
GND
GND
GND
VIN
VIN
SW
SW
VIN
VIN
SW
SW
Figure 26.
© 2015 Fairchild Semiconductor Corporation
FAN53202 • Rev. 1.0
Connect VOUT to “+’ side of COUT cap
Guidance for Layer 2
www.fairchildsemi.com
15
FAN53202 — 5 A, 2.4 MHz, Digitally Programmable TinyBuck® Regulator
Layout Recommendation
VSEL
EN
SCL
VOUT
SDA
GND
GND
AGND
GND
GND
GND
GND
VIN
VIN
SW
SW
VIN
VIN
SW
SW
Connect AGND directly to this layer
Dedicated System Ground
Figure 27.
Guidance for Layer 3
PVIN
CIN
EN
VOUT
SCA
SCL
1.FB trace connect to the “+” side of the COUT cap.
2.Do not place COUT near FAN53202. Place cap near load.
FAN53202
SW
L1
VDD
COUT
VSEL
GND
Length should be less than 0.5 inches.
AGND
Core
Processor
(System Load)
3.Max trace resistance between FAN53202 and CPU
should not exceed 30mΩ.
Width (mils) Length (mils) Copper (Oz) Resistance (mΩ)
25
5000
2
4.2
The table provided for resistance
25
500
1.5
4.9
for the given value of copper
25
500
1
5.8
25
500
0.5
7.6
Figure 28.
© 2015 Fairchild Semiconductor Corporation
FAN53202 • Rev. 1.0
Remote Sensing Schematic
www.fairchildsemi.com
16
FAN53202 — 5 A, 2.4 MHz, Digitally Programmable TinyBuck® Regulator
Dedicated GND bumps for CIN and COUT, which
connect directly to System GND of phone board
Dedicated GND bumps for CIN and COUT, which
connect directly to System GND of phone board
Route all logic on this layer or inner layer
CIN
CIN1
VSEL
EN
SCL
VOUT
SDA
GND
GND
AGND
GND
GND
GND
GND
VIN
VIN
SW
SW
VIN
VIN
SW
SW
VIN vias bring power to device
L
Length of VOUT bus leading to CPU
should be less than 0.5inches
Figure 29.
© 2015 Fairchild Semiconductor Corporation
FAN53202 • Rev. 1.0
Remote Sensing Guidance, Top Layer
www.fairchildsemi.com
17
FAN53202 — 5 A, 2.4 MHz, Digitally Programmable TinyBuck® Regulator
Connect VOUT to “+’ side of COUT cap
Do not connect AGND to GND. Place via in pad of AGND
and connect directly to System GND
BALL A1
INDEX AREA
F
A
E
1.20
B
1.20
Ø0.20 A1
Cu Pad
0.03 C
2X
1.60
D
0.40
Ø0.30 Solder
Mask Opening
0.40
0.03 C
TOP VIEW
Ø0.315 Solder
Mask Opening
0.40
option 1
2X
Ø0.215
Cu Pad
A1
option 2
RECOMMENDED LAND PATTERN
(NSMD TYPE)
0.06 C
0.625
0.547
0.05 C
0.378±0.018
0.208±0.021
E
C
SEATING PLANE
SIDE VIEWS
D
NOTES:
0.005
1.20
A. NO JEDEC REGISTRATION APPLIES.
C A B
B. DIMENSIONS ARE IN MILLIMETERS.
Ø0.260±0.02
20X
0.40
E
D
C
B
A
1.60
0.40
C. DIMENSIONS AND TOLERANCE
PER ASMEY14.5M, 1994.
D. DATUM C IS DEFINED BY THE SPHERICAL
CROWNS OF THE BALLS.
(Y) ±0.018
E. PACKAGE NOMINAL HEIGHT IS 586 MICRONS
±39 MICRONS (547-625 MICRONS).
F
1 2 3 4
(X) ±0.018
F. FOR DIMENSIONS D, E, X, AND Y SEE
PRODUCT DATASHEET.
BOTTOM VIEW
Figure 30.
G. DRAWING FILNAME: MKT-UC020AArev3.
20-Ball, Wafer-Level Chip-Scale Package (WLCSP), 4x5 Array, 0.4 mm Pitch, 250 µm Ball
Product-Specific Dimensions
Product
D
E
X
Y
FAN53202UC23X
2.015 ±0.03
1.615 ±0.03
0.2075
0.2075
© 2015 Fairchild Semiconductor Corporation
FAN53202 • Rev. 1.0
www.fairchildsemi.com
18
FAN53202 — 5 A, 2.4 MHz, Digitally Programmable TinyBuck® Regulator
Physical Dimensions
FAN53202 — 5 A, 2.4 MHz, Digitally Programmable TinyBuck® Regulator
© 2015 Fairchild Semiconductor Corporation
FAN53202 • Rev. 1.0
www.fairchildsemi.com
19
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