TI1 MSP430F2619SKGD1 Mixed-signal microcontroller Datasheet

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MSP430F2619S-HT
SLAS697E – MARCH 2010 – REVISED NOVEMBER 2016
MSP430F2619S-HT Mixed-Signal Microcontroller
1 Device Overview
1.1
Features
1
• Low-Supply Voltage Range 1.8 V to 3.6 V
• Ultra-Low Power Consumption
– Active Mode: 365 μA at 1 MHz, 2.2 V
– Standby Mode (VLO): 0.5 μA
– Off Mode (RAM Retention): 0.1 μA
• Wake-Up From Standby Mode in Less than 1 μs
• 16-Bit RISC Architecture, 62.5-ns Instruction Cycle
Time
• Three-Channel Internal DMA
• 12-Bit Analog-to-Digital (A/D) Converter With
Internal Reference, Sample-and-Hold, and
Autoscan Feature
• Dual 12-Bit Digital-to-Analog (D/A) Converters With
Synchronization
• 16-Bit Timer_A With Three Capture/Compare
Registers
• 16-Bit Timer_B With Seven Capture/CompareWith-Shadow Registers
• On-Chip Comparator
1.2
•
Applications
Supports Extreme Temperature Applications:
– Controlled Baseline
– One Assembly/Test Site
– One Fabrication Site
– Extended Product Life Cycle
– Extended Product-Change Notification
– Product Traceability
1.3
• Four Universal Serial Communication Interfaces
(USCIs)
– USCI_A0 and USCI_A1
– Enhanced UART Supporting Auto-Baud-Rate
Detection (LIN)
– IrDA Encoder and Decoder
– Synchronous SPI
– USCI_B0 and USCI_B1
– I2C
– Synchronous SPI
• Supply Voltage Supervisor/Monitor With
Programmable Level Detection
• Brownout Detector
• Bootstrap Loader
• Serial Onboard Programming, No External
Programming Voltage Needed Programmable
Code Protection by Security Fuse
• MSP430F2619S 120KB + 256B Flash Memory,
4KB RAM
• Available in 64-Pin QFP Package or 64-Pin and
80-Pin KGD Options
• For Complete Module Descriptions, Refer to
MSP430x2xx Family User's Guide (SLAU144).
•
•
This device is qualified for 1000 hours of
continuous operation at maximum rated
temperature.
TI high-temperature products use highly-optimized
silicon (die) solutions with design and process
enhancements to maximize performance over
extended temperatures.
Description
The MSP430F2619S ultra-low-power microcontroller features different sets of peripherals targeted for
various applications. The architecture, combined with five low-power modes, is optimized to achieve
extended battery life in portable measurement applications. The device features a powerful 16-bit RISC
CPU, 16-bit registers, and constant generators that attribute to maximum code efficiency. The digitally
controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 1 μs.
The MSP430F2619S is a microcontroller configuration with two built-in 16-bit timers, a fast 12-bit A/D
converter, a comparator, dual 12-bit D/A converters, four universal serial communication interface (USCI)
modules, DMA, and up to 64 I/O pins.
Typical applications include sensor systems that capture analog signals, convert them to digital values,
and then process the data for display or for transmission to a host system. Stand-alone RF sensor front
end is another area of application.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
MSP430F2619S-HT
SLAS697E – MARCH 2010 – REVISED NOVEMBER 2016
www.ti.com
Device Information (1)
PART NUMBER
PACKAGE
MSP430F2619SPM
QFP (PM)
MSP430F2619S64KGD1
KGD 64-Pin Functionality (2)
MSP430F2619SKGD1
KGD 80-Pin Functionality (2)
(1)
(2)
1.4
TA
–55°C to 150°C
For more information, see Section 8, Mechanical Packaging and Orderable Information.
KGD = Known good die.
Functional Block Diagram
XIN/
XT2IN
XOUT/
XT2OUT
2
2
DVCC
ACLK
Oscillators
Basic Clock SMCLK
System+
MCLK
16MHz
CPU
1MB
incl. 16
Registers
Emulation
JTAG
Interface
Flash
120kB
116kB
92kB
92kB
56kB
DVSS
AVCC
RAM
4kB
8kB
8kB
4kB
4kB
ADC12
12-Bit
8
Channels
AVSS 1.x/P2.x
P
DAC12
12-Bit
2
Channels
Voltage
Out
P3.x/P4.x
P5.x/P6.x
2x8
4x8
Ports
P1/P2
2x8 I/O
Interrupt
capability
Ports
P3/P4
P5/P6
USCI A0
UART/
LIN,
IrDA, SPI
4x8 I/O
USCI B0
SPI, I2C
MAB
MDB
Brownout
Protection
SVS,
SVM
Hardware
Multiplier
MPY,
MPYS,
MAC,
MACS
DMA
Controller
3
Channels
Timer_B7
Watchdog
WDT+
15-Bit
Timer_A3
3 CC
Registers
Comp_A+
7 CC
Registers,
Shadow
Reg
8
Channels
USCI A1
UART/
LIN,
IrDA, SPI
USCI B1
SPI, I2C
RST/NMI
2
Device Overview
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SLAS697E – MARCH 2010 – REVISED NOVEMBER 2016
Table of Contents
1
Device Overview ......................................... 1
1.1
2
3
4.36
4.37
Typical Characteristics – XT2 Oscillator ............ 40
4.38
Timer_A – Electrical Characteristics ................ 40
4.39
Timer_B – Electrical Characteristics ................ 40
4.40
4.41
USCI (UART Mode) – Electrical Characteristics .... 40
USCI (SPI Master Mode) – Electrical
Characteristics....................................... 41
4.42
USCI (SPI Slave Mode) – Electrical Characteristics 42
4.43
USCI (I2C Mode) – Electrical Characteristics ....... 45
22
4.44
Comparator_A+ – Electrical Characteristics
.......
46
22
4.47
22
4.48
Typical Characteristics – Comparator A+ ...........
12-Bit ADC Power-Supply and Input Range
Conditions – Electrical Characteristics .............
12-Bit ADC External Reference – Electrical
Characteristics.......................................
12-Bit ADC Built-In Reference – Electrical
Characteristics.......................................
48
22
4.45
4.46
23
4.49
4.50
Typical Characteristics – ADC12....................
12-Bit ADC Timing Parameters – Electrical
Characteristics.......................................
12-Bit ADC Linearity Parameters – Electrical
Characteristics ......................................
12-Bit ADC Temperature Sensor and Built-In VMID –
Electrical Characteristics ............................
12-Bit DAC Supply Specifications – Electrical
Characteristics ......................................
12-Bit DAC Linearity Parameters – Electrical
Characteristics ......................................
Typical Characteristics - 12-Bit DAC Linearity
Specifications........................................
12-Bit DAC Output Specifications – Electrical
Characteristics ......................................
12-Bit DAC Reference Input Specifications –
Electrical Characteristics ............................
12-Bit DAC Dynamic Specifications, VREF = VCC,
DAC12IR = 1 – Electrical Characteristics ...........
51
1.2
Applications ........................................... 1
1.3
Description ............................................ 1
1.4
Functional Block Diagram ............................ 2
Revision History ......................................... 5
Terminal Configurations and Functions ............ 6
.......................................... 6
3.2
Pin Attributes ......................................... 7
3.3
Bare Die Information ................................ 10
Specifications ........................................... 15
4.1
Absolute Maximum Ratings ........................ 15
4.2
ESD Ratings ........................................ 15
4.3
Recommended Operating Conditions .............. 15
4.4
Thermal Information ................................. 17
3.1
4
Typical Characteristics – Calibrated DCO
Frequency ...........................................
Wake-Up From Low-Power Modes (LPM3/4) –
Electrical Characteristics ...........................
Typical Characteristics – DCO Clock Wake-Up Time
From LPM3/4 ........................................
DCO With External Resistor ROSC – Electrical
Characteristics ......................................
Typical Characteristics - DCO With External
Resistor ROSC ......................................
Crystal Oscillator (LFXT1) Low-Frequency Modes –
Electrical Characteristics ...........................
Internal Very-Low-Power, Low-Frequency Oscillator
(VLO) – Electrical Characteristics ...................
Crystal Oscillator (LFXT1) High Frequency Modes –
Electrical Characteristics ...........................
Typical Characteristics – LFXT1 Oscillator in HF
Mode (XTS = 1) .....................................
Crystal Oscillator (XT2) – Electrical Characteristics
Features .............................................. 1
4.5
4.6
Pin Diagram
Active-Mode Supply Current Into AVCC Excluding
External Current –
Electrical Characteristics ........................... 17
Typical Characteristics – Active-Mode Supply
Current (Into DVCC + AVCC) ......................... 18
4.27
4.28
4.29
4.30
4.31
4.32
4.33
4.34
4.35
4.7
4.8
Active-Mode Current vs DCO Frequency ........... 19
Low-Power-Mode Supply Currents Into AVCC
Excluding External Current – Electrical
Characteristics ...................................... 20
4.9
4.10
Typical Characteristics – LPM4 Current ............
Schmitt-Trigger Inputs (Ports P1 Through P6, and
RST/NMI, JTAG, XIN, and XT2IN) – Electrical
Characteristics ......................................
Inputs (Ports P1 and P2) – Electrical
Characteristics.......................................
Leakage Current (Ports P1 Through P6) – Electrical
Characteristics.......................................
Standard Inputs - RST/NMI – Electrical
Characteristics.......................................
Outputs (Ports P1 Through P6) – Electrical
Characteristics.......................................
Output Frequency (Ports P1 Through P6) –
Electrical Characteristics ............................
21
Typical Characteristics – Outputs ...................
POR/Brownout Reset (BOR) – Electrical
Characteristics ......................................
Typical Characteristics - POR/Brownout Reset
(BOR)................................................
SVS (Supply Voltage Supervisor/Monitor) Electrical Characteristics ............................
24
4.51
25
4.52
26
4.53
27
4.54
4.11
4.12
4.13
4.14
4.15
4.16
4.17
4.18
4.19
23
4.20
Typical Characteristics - SVS ....................... 28
4.21
Main DCO Characteristics
4.22
4.23
4.24
4.25
4.26
..........................
DCO Frequency – Electrical Characteristics ........
Calibrated DCO Frequencies (Tolerance at
Calibration) – Electrical Characteristics .............
Calibrated DCO Frequencies (Tolerance Over
Temperature) – Electrical Characteristics...........
Calibrated DCO Frequencies (Tolerance Over
Supply Voltage VCC) – Electrical Characteristics ...
Calibrated DCO Frequencies (Overall Tolerance) –
Electrical Characteristics ............................
29
29
30
31
4.55
4.56
4.57
4.58
32
32
......................................................
33
34
34
34
35
36
36
37
38
39
49
50
51
53
53
54
54
55
56
57
58
59
4.59
Flash Memory – Electrical Characteristics .......... 60
4.60
4.61
RAM – Electrical Characteristics .................... 61
JTAG and Spy-Bi-Wire Interface – Electrical
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Table of Contents
3
MSP430F2619S-HT
SLAS697E – MARCH 2010 – REVISED NOVEMBER 2016
www.ti.com
Characteristics....................................... 61
4.62
5
.................................................
5.2
Instruction Set .......................................
5.3
Operating Modes ....................................
5.4
Interrupt Vector Addresses..........................
5.5
Special Function Registers ..........................
5.6
Memory Organization ...............................
5.7
Bootstrap Loader (BSL) .............................
5.8
Flash Memory .......................................
5.9
Peripherals ..........................................
5.10 DMA Controller ......................................
5.11 Oscillator and System Clock ........................
5.12 Brownout, Supply Voltage Supervisor (SVS) .......
5.13 Digital I/O ............................................
5.14 WDT+ Watchdog Timer .............................
5.15 Hardware Multiplier .................................
5.16 USCI .................................................
5.17 Timer_A3 ............................................
5.18 Timer_B7 ............................................
5.19 Comparator_A+ .....................................
5.20 ADC12 ...............................................
5.21 DAC12 ...............................................
5.22 Peripheral File Map .................................
Applications, Implementation, and Layout........
6.1
P1.0 to P1.7, Input/Output With Schmitt Trigger ....
6.2
6.3
4
6.5
Detailed Description ................................... 63
5.1
6
6.4
JTAG Fuse – Electrical Characteristics ............. 62
CPU
63
63
64
6.7
65
6.8
66
68
6.9
68
68
6.10
69
69
6.11
69
6.12
70
70
6.13
70
70
6.14
70
6.15
71
72
7
82
83
84
85
86
87
88
89
90
91
92
JTAG Fuse Check Mode ............................ 93
Device and Documentation Support ............... 94
73
7.1
Development Tool Support.......................... 94
73
7.2
Receiving Notification of Documentation Updates .. 94
73
7.3
Community Resources .............................. 94
73
7.4
Trademarks.......................................... 94
78
7.5
Electrostatic Discharge Caution ..................... 94
7.6
Glossary ............................................. 94
78
P2.0 to P2.4, P2.6, and P2.7, Input/Output With
Schmitt Trigger ...................................... 79
P2.5, Input/Output With Schmitt Trigger and
External ROSC for DCO .............................. 81
Table of Contents
6.6
Port P3 Pin Schematic: P3.0 to P3.7, Input/Output
With Schmitt Trigger ................................
Port P4 Pin Schematic: P4.0 to P4.7, Input/Output
With Schmitt Trigger ................................
Port P5 Pin Schematic: P5.0 to P5.7, Input/Output
With Schmitt Trigger ................................
Port P6 Pin Schematic: P6.0 to P6.4, Input/Output
With Schmitt Trigger ................................
Port P6 Pin Schematic: P6.5 and P6.6, Input/Output
With Schmitt Trigger ................................
Port P6 Pin Schematic: P6.7, Input/Output With
Schmitt Trigger ......................................
Port P7 Pin Schematic: P7.0 to P7.7, Input/Output
With Schmitt Trigger ................................
Port P8 Pin Schematic: P8.0 to P8.5, Input/Output
With Schmitt Trigger ................................
Port P8 Pin Schematic: P8.6, Input/Output With
Schmitt Trigger ......................................
Port P8 Pin Schematic: P8.7, Input/Output With
Schmitt Trigger ......................................
JTAG Pins: TMS, TCK, TDI/TCLK, TDO/TDI,
Input/Output With Schmitt Trigger ..................
8
Mechanical, Packaging, and Orderable
Information .............................................. 95
8.1
Packaging Information
..............................
95
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SLAS697E – MARCH 2010 – REVISED NOVEMBER 2016
2 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (October 2013) to Revision E
•
•
•
•
Page
Added Specifications section, ESD Ratings table, Thermal Information table, Detailed Description section,
Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ......... 2
Changed ORDERING INFORMATION table to Device Information table..................................................... 2
Added 64-pin KGD device ........................................................................................................... 2
Added new bond pad coordinates table for 80-pin KGD device .............................................................. 13
Changes from Revision C (April 2013) to Revision D
•
•
•
Page
Added bullet under Supports Extreme Temperature Applications ............................................................. 1
Deleted Ordering Information table note (2) referencing package information ............................................... 2
Changed Bare Die Information section ........................................................................................... 10
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Revision History
5
MSP430F2619S-HT
SLAS697E – MARCH 2010 – REVISED NOVEMBER 2016
www.ti.com
3 Terminal Configurations and Functions
AVCC
DVSS1
AVSS
P6.2/A2
P6.1/A1
P6.0/A0
RST/NMI
TCK
TMS
TDI/TCLK
TDO/TDI
XT2IN
XT2OUT
P5.7/TBOUTH/SVSOUT
P5.6/ACLK
P5.5/SMCLK
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
Pin Diagram
64
3.1
P6.6/A6/DAC0
5
44
P5.0/UCB1STE/UCA1CLK
P6.7/A7/DAC1/SVSIN
6
43
P4.7/TBCLK
VREF+
7
42
P4.6/TB6
XIN
8
41
P4.5/TB5
XOUT
9
40
P4.4/TB4
VeREF+/DAC0
10
39
P4.3/TB3
VREF±/VeREF±
11
38
P4.2/TB2
P1.0/TACLK/CAOUT
12
37
P4.1/TB1
P1.1/TA0
13
36
P4.0/TB0
P1.2/TA1
14
35
P3.7/UCA1RXD/UCA1SOMI
P1.3/TA2
15
34
P3.6/UCA1TXD/UCA1SIMO
P1.4/SMCLK
16
33
P3.5/UCA0RXD/UCA0SOMI
P3.4/UCA0TXD/UCA0SIMO
P3.3/UCB0CLK/UCA0STE
P3.2/UCB0SOMI/UCB0SCL
P3.1/UCB0SIMO/UCB0SDA
P3.0/UCB0STE/UCA0CLK
P2.7/TA0/CA7
P2.6/ADC12CLK/DMAE0/CA6
P2.5/Rosc/CA5
P2.4/CA1/TA2
P2.3/CA0/TA1
P2.2/CAOUT/TA0/CA4
P2.1/TAINCLK/CA3
P2.0/ACLK/CA2
P1.7/TA2
P1.6/TA1
P1.5/TA0
32
P5.1/UCB1SIMO/UCB1SDA
31
45
30
4
29
P6.5/A5/DAC1
28
P5.2/UCB1SOMI/UCB1SCL
27
46
26
3
25
P6.4/A4
24
P5.3/UCB1CLK/UCA1STE
23
47
22
2
21
P6.3/A3
20
P5.4/MCLK
19
48
18
1
17
DVCC1
Not to scale
Figure 3-1. 64-Pin PM Package (Top View)
6
Terminal Configurations and Functions
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3.2
SLAS697E – MARCH 2010 – REVISED NOVEMBER 2016
Pin Attributes
Table 3-1. Pin Attributes (64-PM Package)
PIN
NAME
PM
I/O
DESCRIPTION
AVCC
64
Analog supply voltage, positive terminal. Supplies only the analog portion of
ADC12 and DAC12.
AVSS
62
Analog supply voltage, negative terminal. Supplies only the analog portion of
ADC12 and DAC12.
DVCC1
1
Digital supply voltage, positive terminal. Supplies all digital parts.
DVSS1
63
Digital supply voltage, negative terminal. Supplies all digital parts.
P1.0/TACLK/CAOUT
12
I/O
General-purpose digital I/O pin/Timer_A, clock signal TACLK
input/Comparator_A output
P1.1/TA0
13
I/O
General-purpose digital I/O pin/Timer_A, capture: CCI0A input, compare:
Out0 output/BSL transmit
P1.2/TA1
14
I/O
General-purpose digital I/O pin/Timer_A, capture: CCI1A input, compare:
Out1 output
P1.3/TA2
15
I/O
General-purpose digital I/O pin/Timer_A, capture: CCI2A input, compare:
Out2 output
P1.4/SMCLK
16
I/O
General-purpose digital I/O pin/SMCLK signal output
P1.5/TA0
17
I/O
General-purpose digital I/O pin/Timer_A, compare: Out0 output
P1.6/TA1
18
I/O
General-purpose digital I/O pin/Timer_A, compare: Out1 output
P1.7/TA2
19
I/O
General-purpose digital I/O pin/Timer_A, compare: Out2 output
P2.0/ACLK/CA2
20
I/O
General-purpose digital I/O pin/ACLK output/Comparator_A input
P2.1/TAINCLK/CA3
21
I/O
General-purpose digital I/O pin/Timer_A, clock signal at INCLK
P2.2/CAOUT/TA0/CA4
22
I/O
General-purpose digital I/O pin/Timer_A, capture: CCI0B
input/Comparator_A output/BSL receive/Comparator_A input
P2.3/CA0/TA1
23
I/O
General-purpose digital I/O pin/Timer_A, compare: Out1
output/Comparator_A input
P2.4/CA1/TA2
24
I/O
General-purpose digital I/O pin/Timer_A, compare: Out2
output/Comparator_A input
P2.5/Rosc/CA5
25
I/O
General-purpose digital I/O pin/input for external resistor defining the DCO
nominal frequency/Comparator_A input
P2.6/ADC12CLK/DMAE0/CA6
26
I/O
General-purpose digital I/O pin/conversion clock – 12-bit ADC/DMA channel
0 external trigger/Comparator_A input
P2.7/TA0/CA7
27
I/O
General-purpose digital I/O pin/Timer_A, compare: Out0
output/Comparator_A input
P3.0/UCB0STE/UCA0CLK
28
I/O
General-purpose digital I/O pin/USCI B0 slave transmit enable/USCI A0
clock input/output
P3.1/UCB0SIMO/UCB0SDA
29
I/O
General-purpose digital I/O pin/USCI B0 slave in/master out in SPI mode,
SDA I2C data in I2C mode
P3.2/UCB0SOMI/UCB0SCL
30
I/O
General-purpose digital I/O pin/USCI B0 slave out/master in in SPI mode,
SCL I2C clock in I2C mode
P3.3/UCB0CLK/UCA0STE
31
I/O
General-purpose digital I/O/USCI B0 clock input/output, USCI A0 slave
transmit enable
P3.4/UCA0TXD/UCA0SIMO
32
I/O
General-purpose digital I/O pin/USCIA transmit data output in UART mode,
slave data in/master out in SPI mode
P3.5/UCA0RXD/UCA0SOMI
33
I/O
General-purpose digital I/O pin/USCI A0 receive data input in UART mode,
slave data out/master in in SPI mode
P3.6/UCA1TXD/UCA1SIMO
34
I/O
General-purpose digital I/O pin/USCI A1 transmit data output in UART
mode, slave data in/master out in SPI mode
P3.7/UCA1RXD/UCA1SOMI
35
I/O
General-purpose digital I/O pin/USCIA1 receive data input in UART mode,
slave data out/master in in SPI mode
P4.0/TB0
36
I/O
General-purpose digital I/O pin/Timer_B, capture: CCI0A/B input, compare:
Out0 output
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Table 3-1. Pin Attributes (64-PM Package) (continued)
PIN
NAME
PM
I/O
DESCRIPTION
P4.1/TB1
37
I/O
General-purpose digital I/O pin/Timer_B, capture: CCI1A/B input, compare:
Out1 output
P4.2/TB2
38
I/O
General-purpose digital I/O pin/Timer_B, capture: CCI2A/B input, compare:
Out2 output
P4.3/TB3
39
I/O
General-purpose digital I/O pin/Timer_B, capture: CCI3A/B input, compare:
Out3 output
P4.4/TB4
40
I/O
General-purpose digital I/O pin/Timer_B, capture: CCI4A/B input, compare:
Out4 output
P4.5/TB5
41
I/O
General-purpose digital I/O pin/Timer_B, capture: CCI5A/B input, compare:
Out5 output
P4.6/TB6
42
I/O
General-purpose digital I/O pin/Timer_B, capture: CCI6A input, compare:
Out6 output
P4.7/TBCLK
43
I/O
General-purpose digital I/O pin/Timer_B, clock signal TBCLK input
P5.0/UCB1STE/UCA1CLK
44
I/O
General-purpose digital I/O pin/USCI B1 slave transmit enable/USCI A1
clock input/output
P5.1/UCB1SIMO/UCB1SDA
45
I/O
General-purpose digital I/O pin/USCI B1slave in/master out in SPI mode,
SDA I2C data in I2C mode
P5.2/UCB1SOMI/UCB1SCL
46
I/O
General-purpose digital I/O pin/USCI B1slave out/master in in SPI mode,
SCL I2C clock in I2C mode
P5.3/UCB1CLK/UCA1STE
47
I/O
General-purpose digital I/O/USCI B1 clock input/output, USCI A1 slave
transmit enable
P5.4/MCLK
48
I/O
General-purpose digital I/O pin/main system clock MCLK output
P5.5/SMCLK
49
I/O
General-purpose digital I/O pin/submain system clock SMCLK output
P5.6/ACLK
50
I/O
General-purpose digital I/O pin/auxiliary clock ACLK output
P5.7/TBOUTH/SVSOUT
51
I/O
General-purpose digital I/O pin/switch all PWM digital output ports to high
impedance -- Timer_B TB0 to TB6/SVS comparator output
P6.0/A0
59
I/O
General-purpose digital I/O pin/analog input A0 – 12-bit ADC
P6.1/A1
60
I/O
General-purpose digital I/O pin/analog input A1 – 12-bit ADC
P6.2/A2
61
I/O
General-purpose digital I/O pin/analog input A2 – 12-bit ADC
P6.3/A3
2
I/O
General-purpose digital I/O pin/analog input A3 – 12-bit ADC
P6.4/A4
3
I/O
General-purpose digital I/O pin/analog input A4 – 12-bit ADC
P6.5/A5/DAC1
4
I/O
General-purpose digital I/O pin/analog input A5 – 12-bit ADC/DAC12.1
output
P6.6/A6/DAC0
5
I/O
General-purpose digital I/O pin/analog input A6 – 12-bit ADC/DAC12.0
output
P6.7/A7/DAC1/SVSIN
6
I/O
General-purpose digital I/O pin/analog input a7 – 12-bit ADC/DAC12.1
output/SVS input
P7.0
NC
I/O
General-purpose digital I/O pin
P7.1
NC
I/O
General-purpose digital I/O pin
P7.2
NC
I/O
General-purpose digital I/O pin
P7.3
NC
I/O
General-purpose digital I/O pin
P7.4
NC
I/O
General-purpose digital I/O pin
P7.5
NC
I/O
General-purpose digital I/O pin
P7.6
NC
I/O
General-purpose digital I/O pin
P7.7
NC
I/O
General-purpose digital I/O pin
P8.0
NC
I/O
General-purpose digital I/O pin
P8.1
NC
I/O
General-purpose digital I/O pin
P8.2
NC
I/O
General-purpose digital I/O pin
P8.3
NC
I/O
General-purpose digital I/O pin
P8.4
NC
I/O
General-purpose digital I/O pin
P8.5
NC
I/O
General-purpose digital I/O pin
8
Terminal Configurations and Functions
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SLAS697E – MARCH 2010 – REVISED NOVEMBER 2016
Table 3-1. Pin Attributes (64-PM Package) (continued)
PIN
NAME
PM
I/O
DESCRIPTION
P8.6/XT2OUT
NC
O
General-purpose digital I/O pin/Output terminal of crystal oscillator XT2
P8.7/XT2IN
NC
I
General-purpose digital I/O pin/Input port for crystal oscillator XT2. Only
standard crystals can be connected.
XT2OUT
52
O
Output terminal of crystal oscillator XT2
XT2IN
53
I
Input port for crystal oscillator XT2
RST/NMI
58
I
Reset input, nonmaskable interrupt input port, or bootstrap loader start (in
flash devices)
TCK
57
I
Test clock (JTAG). TCK is the clock input port for device programming test
and bootstrap loader start.
TDI/TCLK
55
I
Test data input or test clock input. The device protection fuse is connected
to TDI/TCLK.
TDO/TDI
54
I/O
TMS
56
I
Test mode select. TMS is used as an input port for device programming and
test.
VeREF+/DAC0
10
I
Input for an external reference voltage/DAC12.0 output
VREF+
7
O
Output of positive terminal of the reference voltage in the ADC12
VREF–/VeREF–
11
I
Negative terminal for the reference voltage for both sources, the internal
reference voltage, or an external applied reference voltage
XIN
8
I
Input port for crystal oscillator XT1. Standard or watch crystals can be
connected.
XOUT
9
O
Output port for crystal oscillator XT1. Standard or watch crystals can be
connected.
Test data output port. TDO/TDI data output or programming data input
terminal.
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Terminal Configurations and Functions
9
MSP430F2619S-HT
SLAS697E – MARCH 2010 – REVISED NOVEMBER 2016
3.3
www.ti.com
Bare Die Information
DIE THICKNESS
BACKSIDE FINISH
BACKSIDE
POTENTIAL
BOND PAD METALLIZATION
COMPOSITION
BOND PAD THICKNESS
10.5 mils
Silicon with backgrind
Floating
TiN/AlCu.5%
800 nm
10
Terminal Configurations and Functions
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SLAS697E – MARCH 2010 – REVISED NOVEMBER 2016
Table 3-2. Bond Pad Coordinates in Microns (64-Pin MSP430F2619S64KGD1)
PAD NUMBER
X MIN
Y MIN
X MAX
AVCC
DESCRIPTION
1
90.65
4729.1
165.65
4804.1
DVCC1
2
90.65
4586.85
165.65
4661.85
P6.3/A3
3
87.4
4440.3
162.4
4515.3
P6.4/A4
4
87.4
4282.65
162.4
4357.65
P6.5/A5/DAC1
5
87.4
4125.05
162.4
4200.05
P6.6/A6/DAC0
6
87.4
3943.9
162.4
4018.9
P6.7/A7/DAC1/SVSIN
7
87.4
3762.75
162.4
3837.75
VREF+
8
92.95
3524.75
167.95
3599.75
XIN
9
87.4
3346.6
162.4
3421.6
XOUT
10
87.4
2472.4
162.4
2547.4
VeREF+/DAC0
11
92.95
2251
167.95
2326
VREF-/VeREF-
12
92.95
2082.5
167.95
2157.5
P1.0/TACLK/CAOUT
13
87.4
1866.2
162.4
1941.2
N/C
14
87.4
1730.6
162.4
1805.6
N/C
15
87.4
1595
162.4
1670
N/C
16
87.4
1459.4
162.4
1534.4
N/C
17
87.4
1323.8
162.4
1398.8
P1.1/TA0
18
87.4
1188.2
162.4
1263.2
P1.2/TA1
19
87.4
1052.6
162.4
1127.6
P1.3/TA2
20
87.4
807.7
162.4
882.7
P1.4/SMCLK
21
87.4
672.1
162.4
747.1
P1.5/TA0
22
559.1
87.4
634.1
162.4
P1.6/TA1
23
694.7
87.4
769.7
162.4
P1.7/TA2
24
830.3
87.4
905.3
162.4
P2.0/ACLK/CA2
25
1234.9
87.4
1309.9
162.4
P2.1/TAINCLK/CA3
26
1370.5
87.4
1445.5
162.4
P2.2/CAOUT/TA0/CA4
27
1506.1
87.4
1581.1
162.4
N/C
28
1641.7
87.4
1716.7
162.4
N/C
29
1777.3
87.4
1852.3
162.4
N/C
30
1912.9
87.4
1987.9
162.4
N/C
31
2053
87.4
2128
162.4
P2.3/CA0/TA1
32
2193.1
87.4
2268.1
162.4
P2.4/CA1/TA2
33
2328.7
87.4
2403.7
162.4
P2.5/ROSC/CA5
34
2464.3
87.4
2539.3
162.4
P2.6/ADC12CLK/DMAE0/CA6
35
2671.1
87.4
2746.1
162.4
P2.7/TA0/CA7
36
2807.15
87.4
2882.15
162.4
P3.0/UCB0STE/UCA0CLK
37
3585.9
87.4
3660.9
162.4
P3.1/UCB0SIMO/UCB0SDA
38
3721.5
87.4
3796.5
162.4
P3.2/UCB0SOMI/UCB0SCL
39
3861.6
87.4
3936.6
162.4
P3.3/UCB0CLK/UCA0STE
40
4001.7
87.4
4076.7
162.4
P3.4/UCA0TXD/UCA0SIMO
41
4137.3
87.4
4212.3
162.4
P3.5/UCA0RXD/UCA0SOMI
42
4887.6
669.65
4962.6
744.65
P3.6/UCA1TXD/UCA1SIMO
43
4887.6
805.25
4962.6
880.25
P3.7/UCA1RXD/UCA1SOMI
44
4887.6
940.85
4962.6
1015.85
N/C
45
4887.6
1076.45
4962.6
1151.45
N/C
46
4887.6
1212.05
4962.6
1287.05
P4.0/TB0
47
4887.6
1352.15
4962.6
1427.15
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MSP430F2619S-HT
SLAS697E – MARCH 2010 – REVISED NOVEMBER 2016
www.ti.com
Table 3-2. Bond Pad Coordinates in Microns (64-Pin MSP430F2619S64KGD1) (continued)
PAD NUMBER
X MIN
Y MIN
X MAX
Y MAX
P4.1/TB1
DESCRIPTION
48
4887.6
1492.25
4962.6
1567.25
P4.2/TB2
49
4887.6
1627.85
4962.6
1702.85
P4.3/TB3
50
4887.6
2533.55
4962.6
2608.55
P4.4/TB4
51
4887.6
2669.15
4962.6
2744.15
P4.5/TB5
52
4887.6
2804.75
4962.6
2879.75
N/C
53
4884.35
2953.25
4959.35
3028.25
N/C
54
4887.6
3060.45
4962.6
3135.45
P4.6/TB6
55
4887.6
3153.45
4962.6
3228.45
P4.7/TBCLK
56
4887.6
3289.05
4962.6
3364.05
P5.0/UCB1STE/UCA1CLK
57
4887.6
3424.65
4962.6
3499.65
P5.1/UCB1SIMO/UCB1SDA
58
4887.6
3560.25
4962.6
3635.25
P5.2/UCB1SOMI/UCB1SCL
59
4887.6
3700.35
4962.6
3775.35
P5.3/UCB1CLK/UCA1STE
60
4887.6
3840.45
4962.6
3915.45
P5.4/MCLK
61
4887.6
3997.05
4962.6
4072.05
P5.5/SMCLK
62
4237.65
4887.6
4312.65
4962.6
P5.6/ACLK
63
4102.05
4887.6
4177.05
4962.6
P5.7/TBOUTH/SVSOUT
64
3966.45
4887.6
4041.45
4962.6
N/C
65
3830.85
4887.6
3905.85
4962.6
N/C
66
3547.7
4887.6
3622.7
4962.6
N/C
67
3412.1
4887.6
3487.1
4962.6
N/C
68
3276.5
4887.6
3351.5
4962.6
XT2OUT
69
3140.9
4887.6
3215.9
4962.6
XT2IN
70
2992.85
4887.6
3067.85
4962.6
TDO/TDI
71
2844.6
4887.6
2919.6
4962.6
TDI/TCLK
72
2448
4887.6
2523
4962.6
TMS
73
2152.25
4887.6
2227.25
4962.6
TCK
74
1568.55
4887.6
1643.55
4962.6
RST/NMI
75
1431.85
4887.6
1506.85
4962.6
P6.0/A0
76
1230.75
4887.6
1305.75
4962.6
P6.1/A1
77
1077.9
4887.6
1152.9
4962.6
P6.2/A2
78
923.95
4887.6
998.95
4962.6
AVSS
79
821.05
4887.95
896.05
4962.95
AVSS
80
674.95
4887.6
749.95
4962.6
DVSS1
81
499.2
4887.6
574.2
4962.6
AVCC
82
337.85
4884.35
412.85
4959.35
12
Terminal Configurations and Functions
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SLAS697E – MARCH 2010 – REVISED NOVEMBER 2016
Table 3-3. Bond Pad Coordinates in Microns (80-Pin MSP430F2619SKGD1)
DESCRIPTION
PAD NUMBER
X MIN
Y MIN
X MAX
AVCC
1
90.65
4729.1
165.65
4804.1
DVCC1
2
90.65
4586.85
165.65
4661.85
P6.3/A3
3
87.4
4440.3
162.4
4515.3
P6.4/A4
4
87.4
4282.65
162.4
4357.65
P6.5/A5/DAC1
5
87.4
4125.05
162.4
4200.05
P6.6/A6/DAC0
6
87.4
3943.9
162.4
4018.9
P6.7/A7/DAC1/SVSIN
7
87.4
3762.75
162.4
3837.75
VREF+
8
92.95
3524.75
167.95
3599.75
XIN
9
87.4
3346.6
162.4
3421.6
XOUT
10
87.4
2472.4
162.4
2547.4
VeREF+/DAC0
11
92.95
2251
167.95
2326
VREF-/VeREF-
12
92.95
2082.5
167.95
2157.5
P1.0/TACLK/CAOUT
13
87.4
1866.2
162.4
1941.2
P1.1/TA0
14
87.4
1730.6
162.4
1805.6
P1.2/TA1
15
87.4
1595
162.4
1670
P1.3/TA2
16
87.4
1459.4
162.4
1534.4
P1.4/SMCLK
17
87.4
1323.8
162.4
1398.8
P1.5/TA0
18
87.4
1188.2
162.4
1263.2
P1.6/TA1
19
87.4
1052.6
162.4
1127.6
P1.7/TA2
20
87.4
807.7
162.4
882.7
P2.0/ACLK/CA2
21
87.4
672.1
162.4
747.1
P2.1/TAINCLK/CA3
22
559.1
87.4
634.1
162.4
P2.2/CAOUT/TA0/CA4
23
694.7
87.4
769.7
162.4
P2.3/CA0/TA1
24
830.3
87.4
905.3
162.4
P2.4/CA1/TA2
25
1234.9
87.4
1309.9
162.4
P2.5/Rosc/CA5
26
1370.5
87.4
1445.5
162.4
P2.6/ADC12CLK/DMAE0/CA6
27
1506.1
87.4
1581.1
162.4
P2.7/TA0/CA7
28
1641.7
87.4
1716.7
162.4
P3.0/UCB0STE/UCA0CLK
29
1777.3
87.4
1852.3
162.4
P3.1/UCB0SIMO/UCB0SDA
30
1912.9
87.4
1987.9
162.4
P3.2/UCBOSOMI/UCB0SCL
31
2053
87.4
2128
162.4
P3.3/UCB0CLK/UCA0STE
32
2193.1
87.4
2268.1
162.4
P3.4/UCA0TXD/UCA0SIMO
33
2328.7
87.4
2403.7
162.4
P3.5/UCA0RXD/UCA0SOMI
34
2464.3
87.4
2539.3
162.4
P3.6/UCA1TXD/UCA1SIMO
35
2671.1
87.4
2746.1
162.4
P3.7/UCA1RXD/UCA1SOMI
36
2807.15
87.4
2882.15
162.4
P4.0/TB0
37
3585.9
87.4
3660.9
162.4
P4.1/TB1
38
3721.5
87.4
3796.5
162.4
P4.2/TB2
39
3861.6
87.4
3936.6
162.4
P4.3/TB3
40
4001.7
87.4
4076.7
162.4
P4.4/TB4
41
4137.3
87.4
4212.3
162.4
P4.5/TB5
42
4887.6
669.65
4962.6
744.65
P4.6/TB6
43
4887.6
805.25
4962.6
880.25
P4.7/TBCLK
44
4887.6
940.85
4962.6
1015.85
P5.0/UCB1STE/UCA1CLK
45
4887.6
1076.45
4962.6
1151.45
P5.1/UCB1SIMO/UCB1SDA
46
4887.6
1212.05
4962.6
1287.05
P5.2/UCB1SOMI/UCB1SCL
47
4887.6
1352.15
4962.6
1427.15
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MSP430F2619S-HT
SLAS697E – MARCH 2010 – REVISED NOVEMBER 2016
www.ti.com
Table 3-3. Bond Pad Coordinates in Microns (80-Pin MSP430F2619SKGD1) (continued)
DESCRIPTION
PAD NUMBER
X MIN
Y MIN
X MAX
Y MAX
P5.3/UCB1CLK/UCA1STE
48
4887.6
1492.25
4962.6
1567.25
P5.4/MCLK
49
4887.6
1627.85
4962.6
1702.85
P5.5/SMCLK
50
4887.6
2533.55
4962.6
2608.55
P5.6/ACLK
51
4887.6
2669.15
4962.6
2744.15
P5.7/TBOUTH/SVSOUT
52
4887.6
2804.75
4962.6
2879.75
DVCC2
53
4884.35
2953.25
4959.35
3028.25
DVSS2
54
4887.6
3060.45
4962.6
3135.45
P7.0
55
4887.6
3153.45
4962.6
3228.45
P7.1
56
4887.6
3289.05
4962.6
3364.05
P7.2
57
4887.6
3424.65
4962.6
3499.65
P7.3
58
4887.6
3560.25
4962.6
3635.25
P7.4
59
4887.6
3700.35
4962.6
3775.35
P7.5
60
4887.6
3840.45
4962.6
3915.45
P7.6
61
4887.6
3997.05
4962.6
4072.05
P7.7
62
4237.65
4887.6
4312.65
4962.6
P8.0
63
4102.05
4887.6
4177.05
4962.6
P8.1
64
3966.45
4887.6
4041.45
4962.6
P8.2
65
3830.85
4887.6
3905.85
4962.6
P8.3
66
3547.7
4887.6
3622.7
4962.6
P8.4
67
3412.1
4887.6
3487.1
4962.6
P8.5
68
3276.5
4887.6
3351.5
4962.6
P8.6/XT2OUT
69
3140.9
4887.6
3215.9
4962.6
P8.7/XT2IN
70
2992.85
4887.6
3067.85
4962.6
TDO/TDI
71
2844.6
4887.6
2919.6
4962.6
TDI/TCLK
72
2448
4887.6
2523
4962.6
TMS
73
2152.25
4887.6
2227.25
4962.6
TCK
74
1568.55
4887.6
1643.55
4962.6
RST/NMI
75
1431.85
4887.6
1506.85
4962.6
P6.0/A0
76
1230.75
4887.6
1305.75
4962.6
P6.1/A1
77
1077.9
4887.6
1152.9
4962.6
P6.2/A2
78
923.95
4887.6
998.95
4962.6
AVSS
79
821.05
4887.95
896.05
4962.95
AVSS
80
674.95
4887.6
749.95
4962.6
DVSS1
81
499.2
4887.6
574.2
4962.6
AVCC
82
337.85
4884.35
412.85
4959.35
14
Terminal Configurations and Functions
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SLAS697E – MARCH 2010 – REVISED NOVEMBER 2016
4 Specifications
Absolute Maximum Ratings (1)
4.1
MIN
MAX
–0.3
4.1
–0.3
VCC + 0.3
–2
2
Storage temperature (unprogrammed device (3))
–55
150
Storage temperature (programmed device (3))
–55
150
Voltage applied at VCC to VSS
Voltage applied to any pin
(2)
Diode current at any device terminal
Tstg
(1)
(2)
(3)
UNIT
V
V
mA
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages referenced to VSS. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage is
applied to the TEST pin when blowing the JTAG fuse.
Higher temperature may be applied during board soldering process according to the current JEDEC J-STD-020 specification with peak
reflow temperatures not higher than classified on the device label on the shipping boxes or reels.
4.2
ESD Ratings
MAX
V(ESD)
(1)
(2)
4.3
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS001 (1)
±4000
Charged-device model (CDM), per JESD22-C101 (2)
±750
Recommended Operating Conditions (1) (2)
Supply voltage during program execution
VCC
Supply voltage during flash memory
programming
AVCC = DVCC = VCC (3)
VSS
Supply voltage
AVSS = DVSS = VSS
TA
Operating free-air temperature range
Processor frequency ƒSYSTEM
(Maximum MCLK frequency) (1) (2)
(see Figure 4-1)
(2)
(3)
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
MIN
(1)
UNIT
NOM
MAX
1.8
3.6
2.2
3.6
0
UNIT
V
V
–55
150
VCC = 2.2 V, duty cycle = 50% ±10%
DC
10
VCC = 2.7 V, duty cycle = 50% ±10%
DC
12
VCC ≥ 3.3 V, duty cycle = 50% ±10%
DC
16
°C
MHz
The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse width of the
specified maximum frequency.
Modules might have a different maximum input clock specification. Refer to the specification of the respective module in this data sheet.
It is recommended to power AVCC and DVCC from the same source. A maximum difference of 0.3 V between AVCC and DVCC can be
tolerated during power-up.
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Legend:
System Frequency −MHz
16 MHz
Supply voltage range,
during flash memory
programming
12 MHz
Supply voltage range,
during program execution
7.5 MHz
4.15 MHz
1.8 V
2.2 V
2.7 V
3.3 V 3.6 V
Supply Voltage −V
NOTE: Minimum processor frequency is defined by system clock. Flash program or erase operations require a minimum VCC
of 2.2 V.
NOTE: Minimum processor frequency is defined by system clock. Flash program or erase operations require a minimum VCC
of 2.2 V.
Figure 4-1. Operating Area
Estimated Life (Hours)
1.E+09
1.E+07
Wirebond Life
1.E+05
Electromigration Fail Mode
1.E+03
85
95
105
115
125
135
145
155
Continuous TJ (oC)
(1)
(2)
(3)
(4)
Wirebond Life = Time at temperature with or without bias.
Electromigration Fail Mode = Time at temperature with bias.
Silicon operating life design goal is 10 years at 105˚C junction temperature (does not include package interconnect life).
The predicted operating lifetime vs. junction temperature is based on reliability modeling and available qualification data.
Figure 4-2. Device Life Curve
16
Specifications
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4.4
SLAS697E – MARCH 2010 – REVISED NOVEMBER 2016
Thermal Information
MSP430F2619S-HT
THERMAL METRIC (1)
PM (QFP)
UNIT
64 PINS
RθJA
Junction-to-ambient thermal resistance
48.7
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
9.9
°C/W
RθJB
Junction-to-board thermal resistance
22.4
°C/W
ψJT
Junction-to-top characterization parameter
0.4
°C/W
ψJB
Junction-to-board characterization parameter
21.9
°C/W
(1)
4.5
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Active-Mode Supply Current Into AVCC Excluding External Current –
Electrical Characteristics (1) (2)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
IAM,
IAM,
IAM,
IAM,
1MHz
1MHz
4kHz
100kHz
TEST CONDITIONS
ƒDCO = ƒMCLK = ƒSMCLK = 1 MHz,
ƒACLK = 32,768 Hz,
Program executes in flash,
Active-mode (AM)
BCSCTL1 = CALBC1_1 MHZ,
current (1 MHz)
DCOCTL = CALDCO_1 MHZ,
CPUOFF = 0, SCG0 = 0,
SCG1 = 0, OSCOFF = 0
ƒDCO = ƒMCLK = ƒSMCLK = 1 MHz,
ƒACLK = 32,768 Hz,
Program executes in RAM,
Active-mode (AM)
BCSCTL1 = CALBC1_1 MHZ,
current (1 MHz)
DCOCTL = CALDCO_1 MHZ,
CPUOFF = 0, SCG0 = 0,
SCG1 = 0, OSCOFF = 0
ƒMCLK = ƒSMCLK = ƒACLK = 32,768 Hz/8
= 4,096 Hz, ƒDCO = 0 Hz,
Program executes in flash,
Active-mode (AM)
SELMx = 11, SELS = 1,
current (4 kHz)
DIVMx = DIVSx = DIVAx = 11,
CPUOFF = 0, SCG0 = 1,
SCG1 = 0, OSCOFF = 0
TYP MAX
365
395
TA = 105°C, VCC = 2.2 V
375
420
TA = 150°C, VCC = 2.2 V
640
TA = –55°C to 85°C,
VCC = 3 V
515
560
TA = 105°C, VCC = 3 V
525
595
TA = 150°C, VCC = 3 V
700
TA = –55°C to 85°C, VCC = 2.2
V
330
370
TA = 105°C, VCC = 2.2 V
340
390
TA = 150°C, VCC = 2.2 V
660
TA = –55°C to 85°C,
VCC = 3 V
460
495
TA = 105°C, VCC = 3 V
470
520
TA = 150°C, VCC = 3 V
710
TA = –55°C to 85°C,
VCC = 2.2 V
2.1
9
TA = 105°C, VCC = 2.2 V
15
31
3
11
TA = 105°C, VCC = 3 V
19
32
TA = –55°C to 85°C,
VCC = 2.2 V
67
86
80
99
TA = –55°C to 85°C,
VCC = 3 V
TA = 105°C, VCC = 2.2 V
ƒMCLK = ƒSMCLK = ƒDCO(0, 0) ≉ 100 kHz,
Active-mode (AM) ƒACLK = 0 Hz, Program executes in flash, TA = 150°C, VCC = 2.2 V
current (100 kHz) RSELx = 0, DCOx = 0, CPUOFF = 0,
TA = –55°C to 85°C, VCC = 3 V
SCG0 = 0, SCG1 = 0, OSCOFF = 1
TA = 105°C, VCC = 3 V
TA = 150°C, VCC = 3 V
(1)
(2)
MIN
TA = –55°C to 85°C,
VCC = 2.2 V
UNIT
μA
μA
190
μA
μA
84
107
99
128
240
All inputs are tied to 0 V or VCC. Outputs do not source or sink any current.
The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external
load capacitance is chosen to closely match the required 9 pF.
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4.6
Typical Characteristics – Active-Mode Supply Current (Into DVCC + AVCC)
Figure 4-3. Active-Mode Current vs VCC, TA = 25°C
18
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Specifications
Figure 4-4. Active-Mode Current vs DCO Frequency
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4.7
SLAS697E – MARCH 2010 – REVISED NOVEMBER 2016
Active-Mode Current vs DCO Frequency
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
Active-mode current supply
Active-mode current supply
Active-mode current supply
TEST CONDITIONS
ƒSMCLK = ƒDCO = 1 MHz
ƒSMCLK = ƒDCO = 12 MHz
ƒSMCLK = ƒDCO = 16 MHz
MIN
TYP
MAX
TA = –55°C, VCC = 2.2 V
0.35
TA = –40°C, VCC = 2.2 V
0.30
TA = 25°C, VCC = 2.2 V
0.36
TA = 125°C, VCC = 2.2 V
0.38
TA = 150°C, VCC = 2.2 V
0.42
TA = –55°C, VCC = 3 V
0.50
TA = –40°C, VCC = 3 V
0.49
TA = 25°C, VCC = 3 V
0.51
TA = 125°C, VCC = 3 V
0.55
TA = 150°C, VCC = 3 V
0.60
TA = –55°C, VCC = 2.2 V
3.71
TA = –40°C, VCC = 2.2 V
3.73
TA = 25°C, VCC = 2.2 V
3.79
TA = 125°C, VCC = 2.2 V
4.45
TA = 150°C, VCC = 2.2 V
4.60
TA = –55°C, VCC = 3 V
5.47
TA = –40°C, VCC = 3 V
5.49
TA = 25°C, VCC = 3 V
5.54
TA = 125°C, VCC = 3 V
5.68
TA = 150°C, VCC = 3 V
5.77
TA = –55°C, VCC = 2.2 V
5.46
TA = –40°C, VCC = 2.2 V
5.58
TA = 25°C, VCC = 2.2 V
5.89
TA = 125°C, VCC = 2.2 V
6.03
TA = 150°C, VCC = 2.2 V
6.20
TA = –55°C, VCC = 3 V
7.14
TA = –40°C, VCC = 3 V
7.14
TA = 25°C, VCC = 3 V
7.21
TA = 125°C, VCC = 3 V
7.429
TA = 150°C, VCC = 3 V
7.54
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UNIT
mA
mA
mA
19
MSP430F2619S-HT
SLAS697E – MARCH 2010 – REVISED NOVEMBER 2016
4.8
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Low-Power-Mode Supply Currents Into AVCC Excluding External Current – Electrical
Characteristics (1) (2)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
ILPM0,
1MHz
Low-power mode 0
(LPM0) current (3)
TEST CONDITIONS
ƒMCLK = 0 MHz,
ƒSMCLK = ƒDCO = 1 MHz,
ƒACLK = 32,768 Hz,
BCSCTL1 = CALBC1_1 MHZ,
DCOCTL = CALDCO_1 MHZ,
CPUOFF = 1, SCG0 = 0, SCG1 = 0,
OSCOFF = 0
MIN
TA = –55°C to 85°C,
VCC = 2.2 V
68
83
TA = 105°C, VCC = 2.2 V
83
98
TA = 150°C, VCC = 2.2 V
210
TA = –55°C to 85°C,
VCC = 3 V
ILPM0,
100kHz
Low-power mode 0
(LPM0) current (3)
Low-power mode 2
(LPM2) current (4)
ILPM2
ILPM3,LFXT1
ILPM3,VLO
Low-power mode 3
(LPM3) current (4)
Low-power mode 3
current, (LPM3) (4)
ƒMCLK = ƒSMCLK = 0 MHz, ƒDCO = 1
MHz,
ƒACLK = 32,768 Hz,
BCSCTL1 = CALBC1_1 MHZ,
DCOCTL = CALDCO_1 MHZ,
CPUOFF = 1, SCG0 = 0, SCG1 = 1,
OSCOFF = 0
105
TA = 105°C, VCC = 3 V
100
125
TA = 150°C, VCC = 3 V
240
ƒDCO = ƒMCLK = ƒSMCLK = 0 MHz,
ƒACLK = 32,768 Hz,
CPUOFF = 1, SCG0 = 1, SCG1 = 1,
OSCOFF = 0
ƒDCO = ƒMCLK = ƒSMCLK = 0 MHz,
ƒACLK from internal LF oscillator (VLO),
CPUOFF = 1, SCG0 = 1, SCG1 = 1,
OSCOFF = 0
37
49
TA = 105°C, VCC = 2.2 V
50
62
TA = 150°C, VCC = 2.2 V
160
40
55
TA = 105°C, VCC = 3 V
57
73
TA = 150°C, VCC = 3 V
185
TA = –55°C to 85°C,
VCC = 2.2 V
23
33
TA = 105°C, VCC = 2.2 V
35
46
TA = 150°C, VCC = 2.2 V
148
(3)
(4)
20
μA
25
36
TA = 105°C, VCC = 3 V
40
55
TA = 150°C, VCC = 3 V
168
TA = –55°C, VCC = 2.2 V
0.8
1.2
TA = 25°C, VCC = 2.2 V
1
1.3
TA = 85°C, VCC = 2.2 V
4.6
7
TA = 105°C, VCC = 2.2 V
14
24
TA = –55°C, VCC = 3 V
0.9
1.3
TA = 25°C, VCC = 3 V
1.1
1.5
TA = 85°C, VCC = 3 V
5.5
8
TA = 105°C, VCC = 3 V
17
30
TA = –55°C, VCC = 2.2 V
0.4
1
TA = 25°C, VCC = 2.2 V
0.5
1
TA = 85°C, VCC = 2.2 V
4.3
6.5
TA = 105°C, VCC = 2.2 V
14
24
1TA = 50°C, VCC = 2.2 V
125
TA = –55°C, VCC = 3 V
0.6
1.2
TA = 25°C, VCC = 3 V
0.6
1.2
TA = 85°C, VCC = 3 V
(1)
(2)
μA
TA = –55°C to 85°C,
VCC = 3 V
TA = –55°C to 85°C,
VCC = 3 V
UNIT
μA
87
TA = –55°C to 85°C,
VCC = 2.2 V
ƒMCLK = 0 MHz,
ƒSMCLK = ƒDCO(0, 0) ≉ 100 kHz,
ƒACLK = 0 Hz,
RSELx = 0, DCOx = 0,
CPUOFF = 1, SCG0 = 0, SCG1 = 0,
OSCOFF = 1
TYP MAX
5
7.5
TA = 105°C, VCC = 3 V
16.5
29.5
TA = 150°C, VCC = 3 V
130
μA
μA
All inputs are tied to 0 V or VCC. Outputs do not source or sink any current.
The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF.
The internal and external load capacitance is chosen to closely match the required 9 pF.
Current for brownout and WDT clocked by SMCLK included.
Current for brownout and WDT clocked by ACLK included.
Specifications
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Low-Power-Mode Supply Currents Into AVCC Excluding External Current – Electrical
Characteristics(1)(2) (continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
ILPM4
(5)
ƒDCO = ƒMCLK = ƒSMCLK = 0 MHz,
ƒACLK = 0 Hz,
CPUOFF = 1, SCG0 = 1, SCG1 = 1,
OSCOFF = 1
MIN
TYP MAX
TA = –55°C, VCC = 2.2 V
0.1
0.5
TA = 25°C, VCC = 2.2 V
0.1
0.5
TA = 85°C, VCC = 2.2 V
4
6
TA = 105°C, VCC = 2.2 V
13
23
TA = 150°C, VCC = 2.2 V
125
TA = –55°C, VCC = 3 V
0.2
0.5
TA = 25°C, VCC = 3 V
0.2
0.5
TA = 85°C, VCC = 3 V
4.7
7
TA = 105°C, VCC = 3 V
14
24
TA = 150°C, VCC = 3 V
146
UNIT
μA
Current for brownout included.
Typical Characteristics – LPM4 Current
ILPM4 - Low-Power Mode Current - mA
4.9
Low-power mode 4
(LPM4) current (5)
TEST CONDITIONS
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
–40
VCC = 3.6 V
VCC = 30 V
VCC = 2.2 V
VCC = 1.8 V
–20
0
20
40
60
80
100
120
TA - Temperature - °C
Figure 4-5. ILPM4 -- LPM4 Current vs Temperature
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4.10 Schmitt-Trigger Inputs (Ports P1 Through P6, and RST/NMI, JTAG, XIN, and
XT2IN) (1) – Electrical Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VIT+
TEST CONDITIONS
Positive-going input threshold voltage
VIT–
Negative-going input threshold voltage
TYP
MAX
0.75 x VCC
VCC = 2.2 V
1.00
1.65
VCC = 3 V
1.35
2.25
0.25 x VCC
0.55 x VCC
VCC = 2.2 V
0.55
1.20
VCC = 3 V
0.75
1.65
VCC = 2.2 V
0.2
1
VCC = 3 V
0.3
1
20
Vhys
Input voltage hysteresis (VIT+ – VIT–)
RPull
Pullup/pulldown resistor
For pullup: VIN = VSS
For pulldown: VIN = VCC
CI
Input capacitance
VIN = VSS or VCC
(1)
MIN
0.45 x VCC
35
50
5
UNIT
V
V
V
kΩ
pF
XIN and XT2IN in bypass mode only.
4.11 Inputs (Ports P1 and P2) – Electrical Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
t(int)
(1)
TEST CONDITIONS
MIN
Port P1, P2: P1.x to P2.x, External trigger pulse
width to set interrupt flag (1), VCC = 2.2 V or 3 V
External interrupt timing
MAX
20
UNIT
ns
An external signal sets the interrupt flag every time the minimum interrupt pulse width t(int) is met. It may be set even with trigger signals
shorter than t(int).
4.12 Leakage Current (Ports P1 Through P6) – Electrical Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
Ilkg(Px.x)
(1)
(2)
High-impedance leakage current
TEST CONDITIONS
See
(1)
and
MIN
TYP
(2)
, VCC = 2.2 V or 3 V
MAX
±250
UNIT
nA
The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.
The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor is
disabled.
4.13 Standard Inputs - RST/NMI – Electrical Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
MIN
MAX
VIL
Low-level input voltage
PARAMETER
VCC = 2.2 V or 3 V
VSS
VSS + 0.6
V
VIH
High-level input voltage
VCC = 2.2 V or 3 V
0.8 x VCC
VCC
V
22
Specifications
TEST CONDITIONS
UNIT
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4.14 Outputs (Ports P1 Through P6) – Electrical Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH(max) = –1.5 mA
VOH
High-level output voltage
(1)
, VCC = 2.2 V
VCC – 0.25
VCC
VCC – 0.6
VCC
IOH(max) = –1.5 mA (1), VCC = 3 V
VCC – 0.25
VCC
VCC – 0.6
VCC
IOL(max) = 1.5 mA , VCC = 2.2 V
VSS
VSS+0.25
IOL(max) = 6 mA (2), VCC = 2.2 V
VSS
VSS+0.6
IOL(max) = 1.5 mA (1), VCC = 3 V
VSS
VSS+0.25
IOL(max) = 6 mA (2), VCC = 3 V
VSS
VSS+0.6
(1)
(1)
(2)
Low-level output voltage
MAX
IOH(max) = –6 mA (2), VCC = 2.2 V
IOH(max) = –6 mA (2), VCC = 3 V
VOL
MIN
UNIT
V
V
The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed ±12 mA to hold the maximum voltage drop
specified.
The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed ±48 mA to hold the maximum voltage drop
specified.
4.15 Output Frequency (Ports P1 Through P6) – Electrical Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
ƒPx.y
Port output frequency
(with load)
P1.4/SMCLK, CL = 20 pF, RL = 1 kΩ (1) (2)
ƒPort_CLK
Clock output
frequency
P2.0/ACLK/CA2, P1.4/SMCLK,
CL = 20 pF (2)
t(Xdc)
Duty cycle of output
frequency
MIN
MAX
DC
10
VCC = 3 V
DC
12
VCC = 2.2 V
DC
12
VCC = 3 V
DC
16
P5.6/ACLK, CL = 20 pF, LF mode
30%
50%
70%
P5.6/ACLK, CL = 20 pF, XT1 mode
40%
50%
60%
P5.4/MCLK, CL = 20 pF, XT1 mode
40%
60%
50% – 15
ns
50% + 15
50%
ns
P5.4/MCLK, CL = 20 pF, DCO
P1.4/SMCLK, CL = 20 pF, XT2 mode
P1.4/SMCLK, CL = 20 pF, DCO
(1)
(2)
TYP
VCC = 2.2 V
40%
60%
50% – 15
ns
50% + 15
ns
UNIT
MHz
MHz
A resistive divider with 2 times 0.5 kΩ between VCC and VSS is used as load. The output is connected to the center tap of the divider.
The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.
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4.16 Typical Characteristics – Outputs
50.0
TA = 25°C
20.0
I OL − Typical Low-Level Output Current − mA
I OL − Typical Low-Level Output Current − mA
25.0
TA = 85°C
15.0
10.0
5.0
0.0
0.0
0.5
1.0
1.5
2.0
TA = 25°C
40.0
TA = 85°C
30.0
20.0
10.0
0.0
0.0
2.5
0.5
VOL − Low-Level Output Voltage − V
Figure 4-6.
−5.0
−10.0
−15.0
TA = 85°C
TA = 25°C
−25.0
0.0
2.0
2.5
3.0
3.5
0.5
1.0
1.5
2.0
2.5
−10.0
−20.0
−30.0
TA = 85°C
−40.0
−50.0
0.0
TA = 25°C
0.5
VOH − High-Level Output Voltage − V
Figure 4-8.
24
1.5
0.0
I OH − Typical High-Level Output Current − mA
I OH − Typical High-Level Output Current − mA
0.0
−20.0
1.0
VOL − Low-Level Output Voltage − V
Figure 4-7.
Specifications
1.0
1.5
2.0
2.5
3.0
3.5
VOH − High-Level Output Voltage − V
Figure 4-9.
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4.17 POR/Brownout Reset (BOR) – Electrical Characteristics (1) (2)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC(start)
See Figure 4-10
dVCC/dt ≤ 3 V/s
V(B_IT–)
See Figure 4-10 through Figure 4-12
dVCC/dt ≤ 3 V/s
Vhys(B_IT–)
See Figure 4-10
dVCC/dt ≤ 3 V/s
td(BOR)
See Figure 4-10
t(reset)
Pulse length needed at RST/NMI pin to
accepted reset internally
(1)
(2)
VCC = 2.2 V or 3 V
MIN
TYP
MAX
UNIT
0.7 ×
V(B_IT–)
70
130
V
1.71
V
210
mV
2000
μs
2
μs
The current consumption of the brownout module is already included in the ICC current consumption data. The voltage level V(B_IT–) +
Vhys(B_IT– ) is ≤ 1.8 V.
During power up, the CPU begins code execution following a period of td(BOR) after VCC = V(B_IT–) + Vhys(B_IT–). The default DCO settings
must not be changed until VCC ≥ VCC(min), where VCC(min) is the minimum supply voltage for the desired operating frequency.
VCC
Vhys(B_IT−)
V(B_IT−)
VCC(start)
1
0
t d(BOR)
Figure 4-10. POR/Brownout Reset (BOR) vs Supply Voltage
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4.18 Typical Characteristics - POR/Brownout Reset (BOR)
VCC
3V
VCC(drop) − V
2
t pw
1.5
1
VCC(drop)
0.5
0
0.001
1
1000
1 ns
tpw − Pulse Width − ms
1 ns
tpw − Pulse Width − ms
Figure 4-11. VCC(drop) Level With a Square Voltage Drop to Generate a POR/Brownout Signal
VCC
VCC(drop) − V
2
t pw
3V
1.5
1
VCC(drop)
0.5
0
0.001
tf = tr
1
1000
tf
tr
tpw − Pulse Width − ms
tpw − Pulse Width − ms
Figure 4-12. VCC(drop) Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal
26
Specifications
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4.19 SVS (Supply Voltage Supervisor/Monitor) - Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
t(SVSR)
TEST CONDITIONS
MIN
dVCC/dt > 30 V/ms (see Figure 4-13)
5
2000
SVSON, switch from VLD = 0 to VLD ≠ 0, VCC = 3 V
tsettle
VLD ≠ 0 (see
V(SVSstart)
VLD ≠ 0, VCC/dt ≤ 3 V/s (see Figure 4-13)
20
)
VCC/dt ≤ 3 V/s (see Figure 4-13)
VCC/dt ≤ 3 V/s (see Figure 4-13),
External voltage applied on A7
VCC/dt ≤ 3 V/s (see Figure 4-13 and
Figure 4-14)
V(SVS_IT-)
VCC/dt ≤ 3 V/s (see Figure 4-13 and
Figure 4-14),
External voltage applied on A7
70
μs
1.7
V
120
210
mV
V(SVS_IT-) ×
0.016
VLD = 15
4.4
20
VLD = 1
1.8
1.9
2.05
VLD = 2
1.94
2.1
2.25
VLD = 3
2.05
2.2
2.37
VLD = 4
2.14
2.3
2.48
VLD = 5
2.24
2.4
2.6
VLD = 6
2.33
2.5
2.71
VLD = 7
2.46
2.65
2.86
VLD = 8
2.58
2.8
3
VLD = 9
2.69
2.9
3.13
VLD = 10
2.83
3.05
3.29
VLD = 11
2.94
3.2
3.42
VLD = 12
3.11
3.35
3.61 (2)
VLD = 13
3.24
3.5
3.76 (2)
VLD = 14
3.43
3.7 (2)
3.99 (2)
VLD = 15
1.1
1.2
1.3
10
15
VLD ≠ 0, VCC = 2.2 V/3 V
μs
1.55
V(SVS_IT-) ×
0.004
VLD = 2 to 14
UNIT
μs
12
Vhys(SVS_IT-)
(2)
(3)
150
(1)
VLD = 1
(1)
MAX
150
dVCC/dt ≤ 30 V/ms
td(SVSon)
ICC(SVS) (3)
TYP
V
mV
V
μA
tsettle is the settling time that the comparator o/p needs to have a stable level after VLD is switched VLD ≠ 0 to a different VLD value
between 2 and 15. The overdrive is assumed to be > 50 mV.
The recommended operating voltage range is limited to 3.6 V.
The current consumption of the SVS module is not included in the ICC current consumption data.
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4.20 Typical Characteristics - SVS
Software sets VLD > 0:
SVS is active
AVCC
Vhys(SVS_IT-)
V(SVS_IT-)
V(SVSstart)
Vhys(B_IT-)
V(B_IT-)
VCC(start)
Brownout
Region
Brownout
1
0
SVS out
td(BOR)
td(BOR)
SVS circuit is active from VLD > VCC < V(B_IT-)
1
0
td(SVSon)
td(SVSR)
Set POR
1
undefined
0
Figure 4-13. SVS Reset (SVSR) vs Supply Voltage
VCC
tpw
3V
2
Rectangular Drop
VCC(min)
1.5
VCC(min) - V
Triangular Drop
1
1 ns
1 ns
VCC
0.5
tpw
3V
0
1
10
100
1000
tpw - Pulse Width - ms
VCC(min)
tf = tr
tf
tr
Figure 4-14. VCC(min): Square Voltage Drop and Triangle Voltage Drop to Generate an SVS Signal (VLD = 1)
28
Specifications
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4.21 Main DCO Characteristics
•
•
•
All ranges selected by RSELx overlap with RSELx + 1: RSELx = 0 overlaps RSELx = 1, ... RSELx = 14
overlaps RSELx = 15.
DCO control bits DCOx have a step size as defined by parameter SDCO.
Modulation control bits MODx select how often ƒDCO(RSEL,DCO+1) is used within the period of 32
DCOCLK cycles. The frequency ƒDCO(RSEL,DCO) is used for the remaining cycles. The frequency is an
average equal to:
32 f DCO(RSEL,DCO) f DCO(RSEL,DCO ) 1)
f average +
MOD f DCO(RSEL,DCO) ) (32 * MOD) f DCO(RSEL,DCO ) 1)
(1)
4.22 DCO Frequency – Electrical Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VCC
TEST CONDITIONS
Supply voltage range
MIN
TYP
MAX
RSELx < 14
1.8
3.6
RSELx = 14
2.2
3.6
RSELx = 15
UNIT
V
3.0
3.6
0.06
0.14
MHz
ƒDCO(0,0)
DCO frequency (0, 0)
RSELx = 0, DCOx = 0,
MODx = 0, VCC = 2.2 V or 3 V
ƒDCO(0,3)
DCO frequency (0, 3)
RSELx = 0, DCOx = 3,
MODx = 0, VCC = 2.2 V or 3 V
0.07
0.17
MHz
ƒDCO(1,3)
DCO frequency (1, 3)
RSELx = 1, DCOx = 3,
MODx = 0, VCC = 2.2 V or 3 V
0.10
0.20
MHz
ƒDCO(2,3)
DCO frequency (2, 3)
RSELx = 2, DCOx = 3,
MODx = 0, VCC = 2.2 V or 3 V
0.14
0.28
MHz
ƒDCO(3,3)
DCO frequency (3, 3)
RSELx = 3, DCOx = 3,
MODx = 0, VCC = 2.2 V or 3 V
0.20
0.40
MHz
ƒDCO(4,3)
DCO frequency (4, 3)
RSELx = 4, DCOx = 3,
MODx = 0, VCC = 2.2 V or 3 V
0.28
0.54
MHz
ƒDCO(5,3)
DCO frequency (5, 3)
RSELx = 5, DCOx = 3,
MODx = 0, VCC = 2.2 V or 3 V
0.39
0.77
MHz
ƒDCO(6,3)
DCO frequency (6, 3)
RSELx = 6, DCOx = 3,
MODx = 0, VCC = 2.2 V or 3 V
0.54
1.06
MHz
ƒDCO(7,3)
DCO frequency (7, 3)
RSELx = 7, DCOx = 3,
MODx = 0, VCC = 2.2 V or 3 V
0.80
1.50
MHz
ƒDCO(8,3)
DCO frequency (8, 3)
RSELx = 8, DCOx = 3,
MODx = 0, VCC = 2.2 V or 3 V
1.10
2.10
MHz
ƒDCO(9,3)
DCO frequency (9, 3)
RSELx = 9, DCOx = 3,
MODx = 0, VCC = 2.2 V or 3 V
1.60
3.00
MHz
ƒDCO(10,3)
DCO frequency (10, 3)
RSELx = 10, DCOx = 3,
MODx = 0, VCC = 2.2 V or 3 V
2.50
4.30
MHz
ƒDCO(11,3)
DCO frequency (11, 3)
RSELx = 11, DCOx = 3,
MODx = 0, VCC = 2.2 V or 3 V
3.00
5.50
MHz
ƒDCO(12,3)
DCO frequency (12, 3)
RSELx = 12, DCOx = 3,
MODx = 0, VCC = 2.2 V or 3 V
4.30
7.30
M Hz
ƒDCO(13,3)
DCO frequency (13, 3)
RSELx = 13, DCOx = 3,
MODx = 0, VCC = 2.2 V or 3 V
6.00
9.60
MHz
ƒDCO(14,3)
DCO frequency (14, 3)
RSELx = 14, DCOx = 3,
MODx = 0, VCC = 2.2 V or 3 V
8.60
13.9
MHz
ƒDCO(15,3)
DCO frequency (15, 3)
RSELx = 15, DCOx = 3,
MODx = 0, VCC = 2.2 V or 3 V
12.0
18.5
MHz
ƒDCO(15,7)
DCO frequency (15, 7)
RSELx = 15, DCOx = 7,
MODx = 0, VCC = 2.2 V or 3 V
16.0
26.0
MHz
SRSEL
Frequency step between range
RSEL and RSEL+1
SRSEL = ƒDCO(RSEL+1,DCO)/ƒDCO(RSEL,DCO), VCC =
2.2 V or 3 V
1.55
ratio
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DCO Frequency – Electrical Characteristics (continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
Frequency step between tap
DCO and DCO+1
SDCO
Duty cycle
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SDCO = ƒDCO(RSEL,DCO+1)/ƒDCO(RSEL,DCO), VCC =
2.2 V or 3 V
1.05
1.08
1.12
ratio
Measured at P1.4/SMCLK, VCC = 2.2 V or 3 V
40%
50%
60%
4.23 Calibrated DCO Frequencies (Tolerance at Calibration) – Electrical Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Frequency tolerance at calibration
TA = 25°C, VCC = 3 V
–1%
±0.2%
1%
ƒCAL(1
0.990
1
1.010
MHz
MHz)
1-MHz calibration value
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
Gating time: 5 ms
TA = 25°C, VCC = 3 V
MHz)
8-MHz calibration value
BCSCTL1 = CALBC1_8MHZ,
DCOCTL = CALDCO_8MHZ,
Gating time: 5 ms
TA = 25°C, VCC = 3 V
7.920
8
8.080
MHz
ƒCAL(12 MHz)
12-MHz calibration value
BCSCTL1 = CALBC1_12MHZ,
DCOCTL = CALDCO_12MHZ,
Gating time: 5 ms
TA = 25°C, VCC = 3 V
11.88
12
12.12
MHz
ƒCAL(16 MHz)
16-MHz calibration value
BCSCTL1 = CALBC1_16MHZ,
DCOCTL = CALDCO_16MHZ,
Gating time: 2 ms
TA = 25°C, VCC = 3 V
15.84
16
16.16
MHz
ƒCAL(8
30
Specifications
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4.24 Calibrated DCO Frequencies (Tolerance Over Temperature) – Electrical Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
1-MHz tolerance over temperature
TA = 0°C to 85°C, VCC = 3 V
–2.5%
±0.5%
2.5%
8-MHz tolerance over temperature
TA = 0°C to 85°C, VCC = 3 V
–2.5%
±1.0%
2.5%
12-MHz tolerance over temperature
TA = 0°C to 85°C, VCC = 3 V
–2.5%
±1.0%
2.5%
16-MHz tolerance over temperature
TA = 0°C to 85°C, VCC = 3 V
–3.0%
±2.0%
3.0%
BCSCTL1 = CALBC1_1MHz,
DCOCTL = CALDCO_1MHZ,
Gating time: 5 ms
TA = 0°C to 85°C
VCC = 2.2 V
0.970
1
1.030
ƒCAL(1MHz)
VCC = 3 V
0.975
1
1.025
VCC = 3.6 V
0.970
1
1.030
BCSCTL1 = CALBC1_8MHZ,
DCOCTL = CALDCO_8MHZ,
Gating time: 5 ms
TA = 0°C to 85°C
VCC = 2.2 V
7.760
8
8.400
VCC = 3 V
7.800
8
8.200
VCC = 3.6 V
7.600
8
8.240
BCSCTL1 = CALBC1_12MHZ,
DCOCTL = CALDCO_12MHZ,
Gating time: 5 ms
TA = 0°C to 85°C
VCC = 2.2 V
11.70
12
12.30
VCC = 3 V
11.70
12
12.30
VCC = 3.6 V
11.70
12
12.30
BCSCTL1 = CALBC1_16MHZ,
DCOCTL = CALDCO_16MHZ,
Gating time: 2 ms
TA = 0°C to 85°C
VCC = 3 V
15.52
16
16.48
VCC = 3.6 V
15.00
16
16.48
ƒCAL(8MHz)
ƒCAL(12MHz)
ƒCAL(16MHz)
1-MHz calibration value
8-MHz calibration value
12-MHz calibration value
16-MHz calibration value
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MHz
MHz
MHz
MHz
Specifications
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4.25 Calibrated DCO Frequencies (Tolerance Over Supply Voltage VCC) – Electrical
Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
MIN
TYP
MAX
1-MHz tolerance over VCC
PARAMETER
TA = 25°C, VCC = 1.8 V to 3.6 V
TEST CONDITIONS
–3%
±2%
3%
8-MHz tolerance overVCC
TA = 25°C, VCC = 1.8 V to 3.6 V
–3%
±2%
3%
12-MHz tolerance over VCC
TA = 25°C, VCC = 2.2 V to 3.6 V
–3%
±2%
3%
16-MHz tolerance over VCC
TA = 25°C, VCC = 3 V to 3.6 V
–6%
±2%
3%
UNIT
ƒCAL(1MHz)
1-MHz
calibration value
BCSCTL1 = CALBC1_1MHZ, DCOCTL = CALDCO_1MHZ,
Gating time: 5 ms, TA = 25°C, VCC = 1.8 V to 3.6 V
0.970
1
1.030
MHz
ƒCAL(8MHz)
8-MHz
calibration value
BCSCTL1 = CALBC1_8MHZ, DCOCTL = CALDCO_8MHZ,
Gating time: 5 ms, TA = 25°C, VCC = 1.8 V to 3.6 V
7.760
8
8.240
MHz
ƒCAL(12MHz)
12-MHz
calibration value
BCSCTL1 = CALBC1_12MHZ, DCOCTL = CALDCO_12MHZ,
Gating time: 5 ms, TA = 25°C, VCC = 2.2 V to 3.6 V
11.64
12
12.36
MHz
ƒCAL(16MHz)
16-MHz
calibration value
BCSCTL1 = CALBC1_16MHZ, DCOCTL = CALDCO_16MHZ,
Gating time: 2 ms, TA = 25°C, VCC = 3 V to 3.6 V
15.00
16
16.48
MHz
4.26 Calibrated DCO Frequencies (Overall Tolerance) – Electrical Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
MIN
TYP
MAX
TA = –55°C to 150°C, VCC = 1.8 V to 3.6 V
–5%
±2%
5%
8-MHz tolerance
over temperature
TA = –55°C to 150°C, VCC = 1.8 V to 3.6 V
–5%
±2%
5%
12-MHz tolerance
over temperature
TA = –55°C to 150°C, VCC = 2.2 V to 3.6 V
–5%
±2%
5%
16-MHz tolerance
over temperature
TA = –55°C to 150°C, VCC = 3 V to 3.6 V
–6%
±3%
6%
1-MHz tolerance
over temperature
TEST CONDITIONS
UNIT
ƒCAL(1MHz)
1-MHz
calibration value
BCSCTL1 = CALBC1_1MHZ, DCOCTL = CALDCO_1MHZ,
Gating time: 5 ms, TA = –55°C to 150°C, VCC = 1.8 V to 3.6 V
.950
1
1.050
MHz
ƒCAL(8MHz)
8-MHz
calibration value
BCSCTL1 = CALBC1_8MHZ, DCOCTL = CALDCO_8MHZ,
Gating time: 5 ms, TA = –55°C to 150°C, VCC = 1.8 V to 3.6 V
7.6
8
8.4
MHz
ƒCAL(12MHz)
12-MHz
calibration value
BCSCTL1 = CALBC1_12MHZ, DCOCTL = CALDCO_12MHZ,
Gating time: 5 ms, TA = –55°C to 150°C, VCC = 2.2 V to 3.6 V
11.4
12
12.6
MHz
ƒCAL(16MHz)
16-MHz
calibration value
BCSCTL1 = CALBC1_16MHZ, DCOCTL = CALDCO_16MHZ,
Gating time: 2 ms, TA = –55°C to 150°C, VCC = 3 V to 3.6 V
15.00
16
17.00
MHz
32
Specifications
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4.27 Typical Characteristics – Calibrated DCO Frequency
8.20
1.02
TA = 105°C
8.15
8.10
Frequency - MHz
Frequency - MHz
1.01
TA = 105°C
TA = 85°C
1
TA = 25°C
2
3
2.5
3.5
7.80
1.5
4
TA = –40°C
2
2.5
3
3.5
4
VCC - Supply Voltage - V
Figure 4-16. Calibrated 8-MHz DCO Frequency vs VCC
VCC - Supply Voltage - V
Figure 4-15. Calibrated 1-MHz DCO Frequency vs VCC
12.2
16.1
12.1
16
TA = –40°C
TA = –40°C
Frequency - MHz
Frequency - MHz
7.95
7.85
TA = –40°C
TA = 25°C
12
TA = 85°C
11.9
TA = 105°C
11.8
11.7
1.5
8
TA = 85°C
TA = 25°C
7.90
0.99
0.98
1.5
8.05
2
2.5
3
15.9
TA = 25°C
TA = 85°C
15.8
TA = 105°C
15.7
3.5
VCC - Supply Voltage - V
Figure 4-17. Calibrated 12-MHz DCO Frequency vs VCC
4
15.6
1.5
2
2.5
3
3.5
4
VCC - Supply Voltage - V
Figure 4-18. Calibrated 16-MHz DCO Frequency vs VCC
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4.28 Wake-Up From Low-Power Modes (LPM3/4) – Electrical Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
tDCO,LPM3/4
tCPU,LPM3/4
(1)
(2)
TEST CONDITIONS
DCO clock wake-up time
from LPM3/4 (1)
MIN
TYP
MAX
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
VCC = 2.2 V or 3 V
2
BCSCTL1 = CALBC1_8MHZ,
DCOCTL = CALDCO_8MHZ,
VCC = 2.2 V or 3 V
1.5
UNIT
μs
BCSCTL1 = CALBC1_12MHZ,
DCOCTL = CALDCO_12MHZ,
VCC = 3 V
1
BCSCTL1 = CALBC1_16MHZ,
DCOCTL = CALDCO_16MHZ,
VCC = 3 V
1
1/ƒMCLK +
tClock,LPM3/4
CPU wake-up time from LPM3/4 (2)
The DCO clock wake-up time is measured from the edge of an external wake-up signal (for example, port interrupt) to the first clock
edge observable externally on a clock pin (MCLK or SMCLK).
Parameter applicable only if DCOCLK is used for MCLK.
4.29 Typical Characteristics – DCO Clock Wake-Up Time From LPM3/4
DCO Wake Time − us
10.00
RSELx = 0...11
RSELx = 12...15
1.00
0.10
0.10
1.00
10.00
DCO Frequency − MHz
Figure 4-19. Clock Wake-Up Time From LPM3 vs DCO Frequency
4.30 DCO With External Resistor ROSC – Electrical Characteristics (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TYP
VCC = 2.2 V
1.8
UNIT
ƒDCO,ROSC
DCO output frequency with ROSC
DCOR = 1, RSELx = 4, DCOx = 3,
MODx = 0, TA = 25°C
Dt
Temperature drift
DCOR = 1, RSELx = 4, DCOx = 3, MODx = 0,
VCC = 2.2 V or 3 V
±0.1
%/°C
DV
Drift with VCC
DCOR = 1, RSELx = 4, DCOx = 3, MODx = 0,
VCC = 2.2 V or 3 V
10
%/V
(1)
34
VCC = 3 V
1.95
MHz
ROSC = 100 kΩ. Metal film resistor, type 0257. 0.6 watt with 1% tolerance and TK = ±50 ppm/°C
Specifications
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4.31 Typical Characteristics - DCO With External Resistor ROSC
10.00
DCO Frequency − MHz
DCO Frequency − MHz
10.00
1.00
0.10
RSELx = 4
0.01
10.00
100.00
1000.00
10000.00
ROSC − External Resistor − k
Figure 4-20. DCO Frequency vs ROSC,
VCC = 2.2 V, TA = 25°C
1.00
0.10
RSELx = 4
0.01
10.00
100.00
1000.00
10000.00
ROSC − External Resistor − k
Figure 4-21. DCO Frequency vs ROSC,
VCC = 3.0 V, TA = 25°C
2.000
1.800
ROSC = 100k
DCO Frequency - MHz
1.600
1.400
1.200
1.000
ROSC = 270k
0.800
0.600
0.400
ROSC = 1M
0.200
0.000
-75
-25
25
75
125
TA - Temperature - °C
Figure 4-22. DCO Frequency vs Temperature,
VCC = 3.0 V
175
Figure 4-23. DCO Frequency vs VCC,
TA = 25°C
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4.32 Crystal Oscillator (LFXT1) Low-Frequency Modes – Electrical Characteristics (1) (2)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
ƒLFXT1,LF
LFXT1 oscillator crystal
frequency, LF mode 0, 1
XTS = 0, LFXT1Sx = 0 or 1, VCC = 1.8 V to 3.6 V
ƒLFXT1,LF,logic
LFXT1 oscillator logiclevel square-wave input
frequency, LF mode
XTS = 0, LFXT1Sx = 3, VCC = 1.8 V to 3.6 V
OALF
Oscillation allowance for
LF crystals
200
1
XCAPx = 1
5.5
XCAPx = 2
8.5
XCAPx = 3
11
LF mode
ƒFault,LF
Oscillator fault frequency
threshold, LF mode (4)
XTS = 0, LFXT1Sx = 3 (5), VCC = 2.2 V or 3 V
(2)
(3)
(4)
(5)
50,000
Hz
kΩ
XCAPx = 0
Duty cycle
Hz
32,768
XTS = 0, LFXT1Sx = 0;ƒLFXT1,LF = 32,768 kHz,
CL,eff = 12 pF
XTS = 0, Measured at P1.4/ACLK,
ƒLFXT1,LF = 32,768 Hz, VCC = 2.2 V or 3 V
(1)
10,000
500
XTS = 0
MAX UNIT
32,768
XTS = 0, LFXT1Sx = 0; ƒLFXT1,LF = 32,768 kHz,
CL,eff = 6 pF
Integrated effective load
capacitance,
LF mode (3)
CL,eff
TYP
30%
pF
50%
70%
10
10,000
Hz
To
•
•
•
•
•
•
•
improve EMI on the LFXT1 oscillator the following guidelines should be observed:
Keep as short of a trace as possible between the device and the crystal.
Design a good ground plane around the oscillator pins.
Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other documentation. This
signal is no longer required for the serial programming adapter.
LFXT1 in 32-KHz mode is specified to function only between –55°C to 105°C. This module is know to fail above 110°C. For further info
contact TI support.
Includes parasitic bond and package capacitance (approximately 2 pF per pin). Since the PCB adds additional capacitance it is
recommended to verify the correct load by measuring the ACLK frequency. For a correct setup the effective load capacitance should
always match the specification of the used crystal.
Frequencies below the MIN specification set the fault flag, frequencies above the MAX specification do not set the fault flag.
Frequencies in between might set the flag.
Measured with logic-level input frequency, but also applies to operation with crystals.
4.33 Internal Very-Low-Power, Low-Frequency Oscillator (VLO) – Electrical Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
ƒVLO
VLO frequency
dƒVLO/dT
VLO frequency temperature drift
dƒVLO/dVCC
(1)
(2)
36
VLO frequency supply voltage drift
TEST CONDITIONS
MIN
TA = –55°C to 85°C, VCC = 2.2 V or 3 V
4
TYP MAX
12
TA = 150°C, VCC = 2.2 V or 3 V
20
22
See
(1)
0.5
See
(2)
4
, VCC = 2.2 V or 3 V
, TA = 25°C, VCC = 1.8 V to 3.6V
0.8
UNIT
kHz
%/°C
%/V
Calculated using the box method:
S Version: (MAX(–55 to 150°C) – MIN(–55 to 150°C))/MIN(–55 to 150°C)/(150°C – (–55°C))
Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8V to 3.6 V))/MIN(1.8 V to 3.6 V)/(3.6 V – 1.8 V)
Specifications
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4.34 Crystal Oscillator (LFXT1) High Frequency Modes – Electrical Characteristics (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ƒLFXT1,HF0
LFXT1 oscillator crystal frequency,
HF mode 0
XTS = 1, LFXT1Sx = 0, VCC = 1.8 V to 3.6 V
0.4
1
MHz
ƒLFXT1,HF1
LFXT1 oscillator lcrystal frequency,
HF mode 1
XTS = 1, LFXT1Sx = 1, VCC = 1.8 V to 3.6 V
1
4
MHz
VCC = 1.8 V to 3.6 V
2
10
ƒLFXT1,HF2
LFXT1 oscillator crystal frequency,
HF mode 2
XTS = 1, LFXT1Sx = 2
VCC = 2.2 V to 3.6 V
2
12
VCC = 3 V to 3.6 V
2
16
VCC = 1.8 V to 3.6 V
0.4
10
VCC = 2.2 V to 3.6 V
0.4
12
VCC = 3 V to 3.6 V
0.4
16
ƒLFXT1,HF,logic
OAHF
CL,eff
Duty cycle
ƒFault,HF
(1)
(2)
(3)
(4)
(5)
LFXT1 oscillator logic-level
square-wave input frequency,
HF mode
XTS = 1, LFXT1Sx = 3
Oscillation allowance for HF crystals
(see Figure 4-24 and Figure 4-25)
Integrated effective load capacitance,
HF mode (2)
HF mode
Oscillator fault frequency, HF mode (4)
XTS = 0, LFXT1Sx = 0;
ƒLFXT1,HF = 1 MHz, CL,eff = 15 pF
2700
XTS = 0, LFXT1Sx = 1
ƒLFXT1,HF = 4 MHz, CL,eff = 15 pF
800
XTS = 0, LFXT1Sx = 2
ƒLFXT1,HF = 16 MHz, CL,eff = 15 pF
300
XTS = 1 (3)
1
pF
40%
50%
60%
XTS = 1, Measured at P1.4/ACLK,
ƒLFXT1,HF = 16 MHz, VCC = 3 V
40%
50%
60%
30
MHz
Ω
XTS = 1, Measured at P1.4/ACLK,
ƒLFXT1,HF = 10 MHz, VCC = 3 V
XTS = 1, LFXT1Sx = 3 (5), VCC = 2.2 V or 3 V
MHz
300
kHz
To
•
•
•
•
•
•
•
improve EMI on the LFXT1 oscillator the following guidelines should be observed:
Keep as short of a trace as possible between the device and the crystal.
Design a good ground plane around the oscillator pins.
Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other documentation. This
signal is no longer required for the serial programming adapter.
Includes parasitic bond and package capacitance (approximately 2 pF per pin). Since the PCB adds additional capacitance it is
recommended to verify the correct load by measuring the ACLK frequency. For a correct setup the effective load capacitance should
always match the specification of the used crystal.
Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
Frequencies below the MIN specification set the fault flag, frequencies above the MAX specification do not set the fault flag.
Frequencies in between might set the flag.
Measured with logic-level input frequency, but also applies to operation with crystals
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4.35 Typical Characteristics – LFXT1 Oscillator in HF Mode (XTS = 1)
1500
XT Oscillator Supply Current - mA
1400
1300
LFXT1Sx = 2
1200
1100
1000
900
800
700
600
500
400
300
LFXT1Sx = 1
200
100
LFXT1Sx = 0
0
4
0
Figure 4-24. Oscillation Allowance vs Crystal Frequency, CL,eff =
15 pF, TA = 25°C
38
Specifications
8
12
16
20
Crystal Frequency - MHz
Figure 4-25. XT Oscillator Supply Current vs Crystal Frequency,
CL,eff = 15 pF, TA = 25°C
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4.36 Crystal Oscillator (XT2) – Electrical Characteristics (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ƒXT2
XT2 oscillator crystal frequency,
mode 0
XT2Sx = 0, VCC = 1.8 V to 3.6 V
0.4
0.9
MHz
ƒXT2
XT2 oscillator lcrystal frequency,
mode 1
XT2Sx = 1, VCC = 1.8 V to 3.6 V
1
4
MHz
VCC = 1.8 V to 3.6 V
2
10
ƒXT2
XT2 oscillator crystal frequency,
mode 2
XT2Sx = 2
VCC = 2.2 V to 3.6 V
2
12
VCC = 3 V to 3.6 V
2
16
VCC = 1.8 V to 3.6 V
0.4
10
VCC = 2.2 V to 3.6 V
0.4
12
VCC = 3 V to 3.6 V
0.4
16
ƒXT2
XT2 oscillator logic-level
square-wave input frequency,
XT2Sx = 3
Oscillation allowance
(see Figure 4-26 and Figure 4-27)
OA
CL,eff
Integrated effective load capacitance,
HF mode (2)
Duty cycle HF mode
ƒFault
(1)
(2)
(3)
(4)
(5)
Oscillator fault frequency, HF mode
(4)
XT2Sx = 0, ƒXT2 = 1 MHz; CL,eff = 15 pF
2700
XT2Sx = 1, ƒXT2 = 4MHz; CL,eff = 15 pF
800
XT2Sx = 2, ƒXT1, HF = 16 MHz; CL,eff = 15 pF
300
See
(3)
pF
Measured at P1.4/SMCLK,
ƒXT2 = 10 MHz, VCC = 2.2 V or 3 V
40%
50%
60%
Measured at P1.4/SMCLK,
ƒXT2 = 16 MHz, VCC = 2.2 V or 3 V
40%
50%
60%
XT2Sx = 3
, VCC = 2.2 V or 3 V
30
MHz
Ω
1
(5)
MHz
300
kHz
To
•
•
•
•
•
•
•
improve EMI on the LFXT1 oscillator the following guidelines should be observed:
Keep as short of a trace as possible between the device and the crystal.
Design a good ground plane around the oscillator pins.
Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other documentation. This
signal is no longer required for the serial programming adapter.
Includes parasitic bond and package capacitance (approximately 2 pF per pin). Since the PCB adds additional capacitance it is
recommended to verify the correct load by measuring the ACLK frequency. For a correct setup the effective load capacitance should
always match the specification of the used crystal.
Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
Frequencies below the MIN specification set the fault flag, frequencies above the MAX specification do not set the fault flag.
Frequencies in between might set the flag.
Measured with logic-level input frequency, but also applies to operation with crystals.
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4.37 Typical Characteristics – XT2 Oscillator
1500
1400
XT Oscillator Supply Current - mA
1300
XT2Sx = 2
1200
1100
1000
900
800
700
600
500
400
300
XT2Sx = 1
200
100
0
XT2Sx = 0
4
0
8
16
12
20
Crystal Frequency - MHz
Figure 4-27. XT2 Oscillator Supply Current vs Crystal
Frequency, CL,eff = 15 pF, TA = 25°C
Figure 4-26. Oscillation Allowance vs Crystal Frequency, CL,eff =
15 pF, TA = 25°C
4.38 Timer_A – Electrical Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
ƒTA
Timer_A clock frequency
Internal: SMCLK, ACLK,
External: TACLK, INCLK,
Duty cycle = 50% ±10%
tTA,cap
Timer_A, capture timing
TA0, TA1, TA2, VCC = 2.2 V or 3 V
MIN
MAX
VCC = 2.2 V
10
VCC = 3 V
16
20
UNIT
MHz
ns
4.39 Timer_B – Electrical Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
ƒTB
Timer_B clock frequency
Internal: SMCLK, ACLK,
External: TBCLK,
Duty cycle = 50% ±10%
tTB,cap
Timer_B, capture timing
TB0, TB1, TB2, VCC = 2.2 V or 3 V
MIN
MAX
VCC = 2.2 V
10
VCC = 3 V
16
20
UNIT
MHz
ns
4.40 USCI (UART Mode) – Electrical Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
ƒUSCI
USCI input clock frequency
Internal: SMCLK, ACLK,
External: UCLK;
Duty cycle = 50% ±10%
ƒBITCLK
BITCLK clock frequency
(equals baud rate in MBaud)
VCC = 2.2 V or 3 V
tτ
UART receive deglitch time (1)
(1)
40
MIN
TYP
MAX
UNIT
ƒSYSTEM
MHz
1
MHz
VCC = 2.2 V
50
150
600
VCC = 3 V
50
150
600
ns
Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are
correctly recognized, their width should exceed the maximum specification of the deglitch time.
Specifications
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4.41 USCI (SPI Master Mode) – Electrical Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) (see Figure 4-28
and Figure 4-29)
PARAMETER
ƒUSCI
USCI input clock frequency
tSU,MI
SOMI input data setup time
tHD,MI
SOMI input data hold time
tVALID,MO
SIMO output data valid time
(1)
TEST CONDITIONS
MIN
SMCLK, ACLK, Duty cycle = 50% ±10%
VCC= 2.2 V
110
VCC = 3 V
75
VCC = 2.2 V
0
VCC = 3 V
0
UCLK edge to SIMO valid,
CL = 20 pF
MAX
UNIT
ƒSYSTEM
MHz
ns
ns
VCC = 2.2 V
30
VCC = 3 V
20
ns
ƒUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(USCI) + tSU,SI(Slave), tSU,MI(USCI) + tVALID,SO(Slave)).
For the slave parameters tSU,SI(Slave) and tVALID,SO(Slave), see the SPI parameters of the attached slave.
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4.42 USCI (SPI Slave Mode) – Electrical Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) (see Figure 4-30
and Figure 4-31)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tSTE,LEAD
STE lead time,
STE low to clock
VCC = 2.2 V or 3 V
tSTE,LAG
STE lag time,
Last clock to STE high
VCC = 2.2 V or 3 V
tSTE,ACC
STE access time,
STE low to SOMI data out
VCC = 2.2 V or 3 V
50
ns
tSTE,DIS
STE disable time,
STE high to SOMI high
impedance
VCC = 2.2 V or 3 V
50
ns
tSU,SI
SIMO input data setup time
tHD,SI
SIMO input data hold time
tVALID,SO
SOMI output data valid time
(1)
50
ns
10
VCC = 2.2 V
20
VCC = 3 V
15
VCC = 2.2 V
10
VCC = 3 V
10
UCLK edge to SOMI valid,
CL = 20 pF
ns
ns
ns
VCC = 2.2 V
75
110
VCC = 3 V
50
75
ns
ƒUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(USCI) + tSU,SI(Slave), tSU,MI(USCI) + tVALID,SO(Slave)).
For the slave parameters tSU,SI(Slave) and tVALID,SO(Slave), see the SPI parameters of the attached slave.
1/fUCxCLK
CKPL
=0
CKPL
=1
UCLK
tLOW/HIGH tLOW/HIGH
tSU,MI
tHD,MI
SCMI
tVALID, MO
SIMO
Figure 4-28. SPI Master Mode, CKPH = 0
42
Specifications
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1/fUCxCLK
CKPL
=0
CKPL
=1
UCLK
tLOW/HIGH tLOW/HIGH
tHD,MI
tSU,MI
SCMI
tVALID, MO
SIMO
Figure 4-29. SPI Master Mode, CKPH = 1
tSTE,LAG
tSTE,LEAD
STE
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW,HIGH tLOW,HIGH
tSU,SIMO
tHD,SIMO
SIMO
tACC
tVALID,SOMI
tDIS
SOMI
Figure 4-30. SPI Slave Mode, CKPH = 0
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tSTE,LEAD
tSTE,LAG
STE
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW,HIGH tLOW,HIGH
tHD,SI
,
tSU,SI
SIMO
tACC
tVALID,SO
tDIS
SOMI
Figure 4-31. SPI Slave Mode, CKPH = 1
44
Specifications
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4.43 USCI (I2C Mode) – Electrical Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 4-32)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ƒUSCI
USCI input clock frequency
Internal: SMCLK, ACLK,
External: UCLK,
Duty cycle = 50% ± 10%
ƒSCL
SCL clock frequency
VCC = 2.2 V or 3 V
tHD,STA
Hold time (repeated) START
tSU,STA
Set-up time for a repeated START
tHD,DAT
Data hold time
VCC = 2.2 V or 3 V
0
ns
tSU,DAT
Data set-up time
VCC = 2.2 V or 3 V
250
ns
tSU,STO
Set-up time for STOP
VCC = 2.2 V or 3 V
4.0
μs
tSP
Pulse width of spikes suppressed by
input filter
VCC = 2.2 V
50
150
600
VCC = 3 V
50
100
600
ƒSYSTEM
0
ƒSCL ≤ 100 kHz, VCC = 2.2 V or 3 V
4.0
ƒSCL > 100 kHz, VCC = 2.2 V or 3 V
0.6
ƒSCL ≤ 100 kHz, VCC = 2.2 V or 3 V
4.7
ƒSCL > 100 kHz, VCC = 2.2 V or 3 V
0.6
tHD ,STA
tSU ,STA tHD ,STA
MHz
400
kHz
μs
μs
ns
tBUF
SDA
t
LOW
tHIGH
tSP
SCL
tSU ,DAT
tSU , STO
tHD ,DAT
Figure 4-32. I2C Mode Timing
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4.44 Comparator_A+ – Electrical Characteristics (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
I(DD)
CAON = 1 CARSEL = 0 CAREF =
0
VCC = 2.2 V
25
80
VCC = 3 V
45
96
CAON = 1, CARSEL = 0,
CAREF = 1/2/3 no load at P2
3/CA0/TA1
and P2.4/CA1/TA2
VCC = 2.2 V
or 3 V
30
50
I(Refladder/Refdiode)
VCC = 3 V
45
71
V(IC)
CAON =1, VCC = 2.2 V or 3 V
V(Ref025)
Voltage at 0.25 VCC node/VCC
PCA0 = 1, CARSEL = 1, CAREF = 1,
no load at P2.3/CA0/TA1
and P2.4/CA1/TA2, VCC = 2.2 V or 3 V
0.23
V(Ref050)
Voltage at 0.5 VCC node/VCC
PCA0 = 1, CARSEL = 1, CAREF = 2,
no load at P2.3/CA0/TA1
and P2.4/CA1/TA2, VCC = 2.2 V or 3 V
V(RefVT)
See Figure 4-36 and Figure 4-37
PCA0 = 1, CARSEL = 1,
CAREF = 3, no load at
P2.3/CA0/TA1
and P2.4/CA1/TA2, TA = 85°C
V(offset)
Offset voltage
See
Vhys
Input hysteresis
CAON=1, VCC = 2.2 V or 3 V
t(response)
(1)
(2)
(3)
46
μA
μA
Common-mode input voltage
Response time, low-to-high and highto-low (3)
UNIT
0
VCC - 1
V
0.24
0.25
V
0.47
0.48
0.5
V
VCC = 2.2 V
390
480
540
VCC = 3 V
400
490
550
30
mV
0
0.7
1.4
mV
(2)
, VCC = 2.2 V or 3 V
–30
TA = 25°C, Overdrive 10 mV,
Without filter: CAF = 0
VCC = 2.2 V
80
165
300
VCC = 3 V
70
120
240
TA = 25°C, Overdrive 10 mV,
Without filter: CAF = 1
VCC = 2.2 V
1.4
1.9
2.8
VCC = 3 V
0.9
1.5
2.2
mV
ns
µs
The leakage current for the Comparator_A+ terminals is identical to Ilkg(Px.x) specification.
The input offset voltage can be cancelled by using the CAEX bit to invert the Comparator_A+ inputs on successive measurements.
The two successive measurements are then summed together.
The response time is measured at P2.2/CAOUT/TA0/CA4 with an input voltage step, with Comparator_A+ already enabled (CAON = 1).
If CAON is set at the same time, a settling time of up to 300 ns is added to the response time.
Specifications
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0V
VCC
0
1
CAF
CAON
Low Pass Filter
V+
+
V-
-
0
0
1
1
To Internal
Modules
CAOUT
Set CAIFG
Flag
l » 2 ms
Figure 4-33. Block Diagram of Comparator_A Module
VCAOUT
Overdrive
V-
400 mV
t(response)
V+
Figure 4-34. Overdrive Definition
CASHORT
CA0
CA1
1
+
IOUT = 10 mA
VIN
Comparator_A+
CASHORT = 1
-
Figure 4-35. Comparator_A+ Short Resistance Test Condition
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4.45 Typical Characteristics – Comparator A+
Figure 4-36. V(RefVT) vs Temperature, VCC = 3 V
Figure 4-37. V(RefVT) vs Temperature, VCC = 2.2 V
Figure 4-38. Short Resistance vs VIN/VCC
48
Specifications
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4.46 12-Bit ADC Power-Supply and Input Range Conditions – Electrical Characteristics (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
AVCC
Analog input voltage range
IADC12
Operating supply current
into AVCC terminal (3)
MIN
AVCC and DVCC are connected together,
AVSS and DVSS are connected together,
V(AVSS) = V(DVSS) = 0 V
Analog supply voltage range
V(P6.x/Ax)
IREF+
TEST CONDITIONS
All P6.0/A0 to P6.7/A7 terminals.
Analog inputs selected in ADC12MCTLx register
and P6Sel.x = 1, 0 ≤ x ≤ 7,
V(AVSS) ≤ VP6.x/Ax ≤ V(AVCC)
(2)
ƒADC10CLK = 5 MHz,
ADC12ON = 1, REFON = 0,
SHT0 = 0, SHT1 = 0,
ADC12DIV = 0
VCC = 2.2 V
ƒADC12CLK = 5 MHz,
ADC12ON = 0,
REFON = 1, REF2_5V = 0
V
0
VAVCC
V
1
0.5
0.7
VCC = 2.2 V
0.5
0.7
VCC = 3 V
0.5
0.7
Input capacitance
Only one terminal selected at a time, P6.x/Ax, VCC =
2.2 V
RI (5)
Input MUX ON resistance
0 V ≤ VAx ≤ VAVCC, VCC = 3 V
(5)
3.6
0.8
VCC = 3 V
UNIT
2.2
0.8
CI (5)
(1)
(2)
(3)
(4)
MAX
0.65
ƒADC12CLK = 5 MHz,
ADC12ON = 0,
REFON = 1, REF2_5V = 1, VCC = 3 V
Reference supply current,
into AVCC terminal (4)
TYP
mA
mA
40
pF
2000
Ω
The leakage current is defined in the leakage current table with P6.x/Ax parameter.
The analog input voltage range must be within the selected reference voltage range VR+ to VR– for valid conversion results.
The internal reference supply current is not included in current consumption parameter IADC12.
The internal reference current is supplied via terminal VCC. Consumption is independent of the ADC10ON control bit, unless a
conversion is active. The REFON bit enables the built-in reference to settle before starting an A/D conversion.
Limits verified by design.
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4.47 12-Bit ADC External Reference – Electrical Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VeREF+
Positive external
reference voltage input
VeREF+ > VREF-/VeREF-
(1)
1.4
VAVCC
V
VREF- /VeREF+
Negative external
reference voltage input
VeREF+ > VREF-/VeREF-
(2)
0
1.2
V
(VeREF+ - VREF- / VeREF- )
Differential external
reference voltage input
VeREF+ > VREF-/VeREF-
(3)
1.4
VAVCC
V
IVeREF+
Static input current
0 V ≤ VeREF+ ≤ VAVCC, VCC = 2.2 V or 3 V
±1
µA
IVREF-/VeREF-
Static input current
0 V ≤ VeREF- ≤ VAVCC, VCC = 2.2 V or 3 V
±1
µA
(1)
(2)
(3)
50
The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced
accuracy requirements.
The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be appliedwith reduced
accuracy requirements.
The accuracy limitsminimum external differential reference voltage. Lower differential reference voltage levels may be appliedwith
reduced accuracy requirements.
Specifications
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4.48 12-Bit ADC Built-In Reference – Electrical Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Positive built-in
reference voltage
output
VREF+
REF2_5V = 1 (2.5 V)
IVREF+max ≤ IVREF+ ≤ IVREF+min
REF2_5V = 1 (1.5 V)
IVREF+max ≤ IVREF+ ≤ IVREF+min
MIN
TA = -55°C to 85°C, VCC = 3 V
2.4
2.5
2.6
TA = 150°C, VCC = 3 V
2.37
2.5
2.64
TA = -55°C to 85°C,
VCC = 2.2 V or 3 V
1.44
1.5
1.56
TA = 150°C, VCC = 2.2 V or 3 V
1.42
1.5
1.57
REF2_5V = 0, IVREF+max ≤ IVREF+ ≤ IVREF+min
AVCC(min)
AVCC minimum
voltage, positive built- REF2_5V = 1, –0.5 mA ≤ IVREF+ ≤ IVREF+min
in reference active
REF2_5V = 1, –1 mA ≤ IVREF+ ≤ IVREF+min
IVREF+
Load current out of
VREF+ terminal
IL(VREF)+ (1)
Load current
regulation, VREF+
terminal
2.8
2.9
0.01
–0.5
VCC = 3 V
0.01
–1
VCC = 3 V
±2
VCC = 3 V
±2
±2
20
IVREF+ = 100 μA → 900 μA,
CVREF+ = 5 μF, at ≉ 0.5 VREF+,
Error of conversion result ≤ 1 LSB, VCC = 3 V
CVREF+
Capacitance
at pin VREF+ (3)
REFON = 1, 0 mA ≤ IVREF+ ≤ IVREF+max, VCC = 2.2 V or 3 V
TREF+ (1)
Temperature
coefficient of built-in
reference
IVREF+ is a constant in the range of 0 mA ≤ IVREF+ ≤ 1 mA, VCC = 2.2 V
or 3 V
Settling time of
internal reference
voltage (4)
(see Figure 4-39)
IVREF+ = 0.5 mA, CVREF+ = 10 μF,
VREF+ = 1.5 V, VAVCC = 2.2 V
(1)
(2)
(3)
(4)
mA
LSB
IVREF+ = 500 μA ± 100 μA,
Analog input voltage VAx ≉ 1.25 V,
REF2_5V = 1, VCC = 3 V
Load current
regulation, VREF+
terminal
tREFON
V
V
VCC = 3 V
IVREF+ = 500 μA ± 100 μA,
Analog input voltage VAx ≉ 0.75 V,
REF2_5V = 0
UNIT
2.2
IDL(VREF)+ (2)
(1)
TYP MAX
5
10
ns
µF
±100
17
ppm/°
C
ms
Limits characterized.
Limits verified by design.
The internal buffer operational amplifier and the accuracy specifications require an external capacitor. All INL and DNL tests use two
capacitors between pins VREF+ and AVSS and VREF-/VeREF- and AVSS: 10 μF tantalum and 100 nF ceramic.
The condition is that the error in a conversion started after tREFON or tRefBuf is less than ±0.5 LSB.
4.49 Typical Characteristics – ADC12
CVREF+
100 mF
tREFON » .6 6 x CVREF+ [m s ] w ith CVREF+ in mF
10 mF
1mF
0
10 m s
1 ms
100 m s
tREFON
Figure 4-39. Typical Settling Time of Internal Reference tREFON vs External Capacitor on VREF+
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From
Power
Supply
DVCC
+
DVSS
10 mF
100 nF
AVCC
+
-
MSP430F2619
AVSS
10 mF
Apply External Reference [VeREF+]
or Use Internal Reference [VREF+]
100 nF
VREF+ or VeREF+
+
10 mF
Apply
External
Reference
100 nF
VREF-/VeREF-
+
10 mF
100 nF
Figure 4-40. Supply Voltage and Reference Voltage Design VREF-/VeREF- External Supply
From
Power
Supply
DVCC
+
DVSS
10 mF
100 nF
AVCC
+
-
MSP430F2619
AVSS
10 mF
Apply External Reference [VeREF+]
or Use Internal Reference [VREF+]
100 nF
VREF+ or VeREF+
+
10 mF
100 nF
Reference Is Internally
Switched to AVSS
VREF-/VeREF-
Figure 4-41. Supply Voltage and Reference Voltage Design VREF-/VeREF- = AVSS, Internally Connected
52
Specifications
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4.50 12-Bit ADC Timing Parameters – Electrical Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
ƒADC12CLK
ADC12 input clock
frequency
For specified performance of ADC12 linearity parameters,
VCC = 2.2 V or 3 V
ƒADC12OSC
ADC12 built-in oscillator
frequency
ADC12DIV = 0,
ƒADC12CLK = ƒADC12OSC , VCC = 2.2 V or 3 V
tCONVERT
tADC12ON
tSample (1)
(1)
(2)
(3)
Conversion time
(1)
ADC12 built-in oscillator, CVREF+ ≥ 5 μF,
ƒADC12OSC = 3.7 MHz to 6.3 MHz, VCC = 2.2 V or 3 V
External ƒADC12CLK from ACLK, MCLK, or SMCLK:
ADC12SSEL ≠ 0
Turn-on settling time of
the ADC
See (2)
Sampling time
RS = 400 Ω, RI = 1000 Ω, CI = 30 pF,
τ = [RS + RI] x CI (3)
MIN
TYP
MAX
UNIT
0.45
5
6.3
MHz
3.7
5
6.3
MHz
2.06
3.51
μs
13 x ADC12DIV
x 1/ƒADC12CLK
100
VCC = 3 V
1220
VCC = 2.2 V
1400
ns
ns
Limits verified by design.
The condition is that the error in a conversion started after tADC12ON is less than ±0.5 LSB. The reference and input signal are already
settled.
Approximately ten Tau (τ) are needed to get an error of less than ±0.5 LSB: tSample = ln(2n+1) x (RS + RI) x CI+ 800 ns where n = ADC
resolution = 12, RS = external source resistance.
4.51 12-Bit ADC Linearity Parameters – Electrical Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
1.4 V ≤ (VeREF+ - VREF-/VeREF-) min ≤ 1.6 V, VCC = 2.2 V or 3 V
EI
Integral linearity error
ED
Differential linearity error
(VeREF+ - VREF-/VeREF-)min ≤ (VeREF+ - VREF-/VeREF-),
CVREF+ = 10 μF (tantalum) and 100 nF (ceramic),
VCC = 2.2 V or 3 V
EO
Offset error
(VeREF+ - VREF-/VeREF-)min ≤ (VeREF+ - VREF-/VeREF-),
Internal impedance of source RS < 100 Ω,
CVREF+ = 10 μF (tantalum) and 100 nF (ceramic),
VCC = 2.2 V or 3 V
EG
Gain error
ET
Total unadjusted error
MAX
±2
1.6 V < (VeREF+ - VREF-/VeREF-) min ≤ VAVCC, VCC = 2.2 V or 3 V
±1.7
UNIT
LSB
±1
LSB
±2
±4
LSB
(VeREF+ - VREF-/VeREF-)min ≤ (VeREF+ - VREF-/VeREF-),
CVREF+ = 10 μF (tantalum) and 100 nF (ceramic),
VCC = 2.2 V or 3 V
±1.1
±2
LSB
(VeREF+ - VREF-/VeREF-)min ≤ (VeREF+ - VREF-/VeREF-),
CVREF+ = 10 μF (tantalum) and 100 nF (ceramic),
VCC = 2.2 V or 3 V
±2
±5
LSB
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4.52 12-Bit ADC Temperature Sensor and Built-In VMID – Electrical Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
VCC = 2.2 V
40
120
VCC = 3 V
60
160
UNIT
ISENSOR
Operating supply current into
AVCC terminal (1)
REFON = 0, INCH = 0Ah,
ADC12ON = 1, TA = 25°C,
VCC = 2.2 V
VSensor (2)
Sensor output voltage (3)
ADC12ON = 1, INCH = 0Ah,
TA = 0°C,
VCC = 2.2 V or 3 V
986
mV
ADC12ON = 1, INCH = 0Ah, VCC = 2.2 V or 3
V
3.55
mV/°C
TCSENSOR (2)
ADC12ON = 1, INCH = 0Ah,
Error of conversion result ≤ 1 LSB,
VCC = 2.2 V or 3 V
tSensor(sample) (2)
Sample time required
if channel 10 is selected
IVMID
Current into divider
at channel 11 (5)
ADC12ON = 1, INCH = 0Bh
VMID
AVCC divider at channel 11
ADC12ON = 1, INCH = 0Bh,
VMID is ≉ 0.5 × VAVCC
VCC = 2.2 V
1.1
VCC = 3 V
1.5 1.5 ±0.04
Sample time required
if channel 11 is selected
ADC12ON = 1, INCH = 0Bh,
Error of conversion result ≤ 1
LSB
VCC = 2.2 V
1400
tVMID(sample)
VCC = 3 V
1220
(1)
(2)
(3)
(4)
(5)
(6)
(4)
(6)
30
μA
μs
VCC = 2.2 V
NA
VCC = 3 V
NA
1.1±0.04
μA
V
ns
The sensor current ISENSOR is consumed if (ADC12ON = 1 and REFON = 1) or (ADC12ON = 1 and INCH = 0Ah and sample signal is
high). When REFON = 1, ISENSOR is included in IREF+. When REFON = 0, ISENSOR applies during conversion of the temperature sensor
input (INCH = 0Ah).
Limits characterized.
The temperature sensor offset can be as much as ±20°C. A single-point calibration is recommended to minimize the offset error of the
built-in temperature sensor.
The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time tSENSOR(on).
No additional current is needed. The VMID is used during sampling.
The on-time tVMID(on) is included in the sampling time tVMID(sample); no additional on time is needed.
4.53 12-Bit DAC Supply Specifications – Electrical Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
AVCC
Supply voltage range
TEST CONDITIONS
DAC12AMPx = 2, DAC12IR = 0,
DAC12_xDAT = 0x0800,
VCC = 2.2 V or 3 V
Supply current,
single DAC channel (1) (2)
IDD
PSSR
(1)
(2)
(3)
(4)
54
Power-supply rejection
ratio (3) (4)
MIN
AVCC = DVCC, AVSS = DVSS = 0 V
TYP
2.2
MAX
3.6
TA = -55°C to 85°C
50
110
TA = 105°C
69
150
DAC12AMPx = 2, DAC12IR = 1, DAC12_xDAT = 0x0800,
VeREF+ = VREF+ = AVCC, VCC = 2.2 V or 3 V
50
130
DAC12AMPx = 5, DAC12IR = 1, DAC12_xDAT = 0x0800,
VeREF+ = VREF+ = AVCC, VCC = 2.2 V or 3 V
200
440
DAC12AMPx = 7, DAC12IR = 1, DAC12_xDAT = 0x0800,
VeREF+ = VREF+ = AVCC, VCC = 2.2 V or 3 V
700
1500
DAC12_xDAT = 800h, VREF = 1.5 V,
ΔAVCC = 100 mV, VCC = 2.2 V or 3 V
70
DAC12_xDAT = 800h, VREF = 1.5 V or 2.5 V,
ΔAVCC = 100 mV, VCC = 2.2 V or 3 V
70
UNIT
V
μA
dB
No load at the output pin, DAC12_0 or DAC12_1, assuming that the control bits for the shared pins are set properly.
Current into reference terminals not included. If DAC12IR = 1 current flows through the input divider; see Section 4.57.
PSRR = 20 × log{ΔAVCC/ΔVDAC12_xOUT}
VREF is applied externally. The internal reference is not used.
Specifications
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4.54 12-Bit DAC Linearity Parameters – Electrical Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Resolution
12-bit monotonic
Integral nonlinearity (1)
INL
DNL
MIN
Differential nonlinearity
(1)
Offset voltage without
calibration (1) (2)
EO
Offset voltage with
calibration (1) (2)
dE(O)/dT
Offset error temperature
coefficient (1)
EG
Gain error (1)
dE(G)/dT
Gain temperature
coefficient (1)
tOffset_Cal
Time for offset calibration (3)
TYP
bits
±2
±8
VREF = 2.5 V, DAC12AMPx = 7,
DAC12IR = 1, VCC = 2.2 V or 3 V
±2
±8
VREF = 1.5 V, DAC12AMPx = 7,
DAC12IR = 1, VCC = 2.2 V or 3 V
±0.4
±1
VREF = 2.5 V, DAC12AMPx = 7,
DAC12IR = 1, VCC = 2.2 V or 3 V
±0.4
±1
VREF = 1.5 V, DAC12AMPx = 7,
DAC12IR = 1, VCC = 2.2 V or 3 V
±21
VREF = 2.5 V, DAC12AMPx = 7,
DAC12IR = 1, VCC = 2.2 V or 3 V
±21
LSB
LSB
LSB
VREF = 1.5 V, DAC12AMPx = 7,
DAC12IR = 1, VCC = 2.2 V or 3 V
±3.5
VREF = 2.5 V, DAC12AMPx = 7,
DAC12IR = 1, VCC = 2.2 V or 3 V
±3.5
30
µV/°C
VREF = 1.5 V, VCC = 2.2 V or 3 V
±3.5
VREF = 2.5 V, VCC = 2.2 V or 3 V
±3.5
LSB
ppm of
FSR/°C
10
100
DAC12AMPx = 3, 5, VCC = 2.2 V or 3 V
32
DAC12AMPx = 4, 6, 7, VCC = 2.2 V or 3 V
(2)
(3)
UNIT
12
VREF = 1.5 V, DAC12AMPx = 7,
DAC12IR = 1, VCC = 2.2 V or 3 V
DAC12AMPx = 2, VCC = 2.2 V or 3 V
(1)
MAX
LSB
6
Parameters calculated from the best-fit curve from 0x0A to 0xFFF. The best-fit curve method is used to deliver coefficients “a” and “b” of
the first-order equation: y = a + b × x. VDAC12_xOUT = EO + (1 + EG) × (VeREF+/4095) × DAC12_xDAT, DAC12IR = 1.
The offset calibration works on the output operational amplifier. Offset calibration is triggered setting bit DAC12CALON.
The offset calibration can be done if DAC12AMPx = {2, 3, 4, 5, 6, 7}. The output operational amplifier is switched off with
DAC12AMPx={0, 1}.The DAC12 module should be configured prior to initiating calibration. Port activity during calibration may affect
accuracy and is not recommended.
DAC V OUT
DAC Output
V R+
R Load =
Ideal transfer
function
AV CC
2
Offset Error
C Load = 100pF
Gain Error
Positive
Negative
DAC Code
Figure 4-42. Linearity Test Load Conditions and Gain/Offset Definition
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4.55 Typical Characteristics - 12-Bit DAC Linearity Specifications
Figure 4-43. Typical INL Error vs Digital Input Data
Figure 4-44. Typical DNL Error vs Digital Input Data
56
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4.56 12-Bit DAC Output Specifications – Electrical Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Output voltage range (1)
(see Figure 4-45)
VO
IL(DAC12)
Max DAC12 load current
RO/P(DAC12)
Output resistance
(see Figure 4-45)
0.005
No Load, VeREF+ = AVCC, DAC12_xDAT = 0FFFh,
DAC12IR = 1, DAC12AMPx = 7VCC = 2.2 V or 3 V
AVCC 0.05
AVCC
0
0.1
AVCC 0.13
AVCC
VCC = 2.2 V
VCC = 3 V
UNIT
V
VCC = 2.2 V or 3 V
100
–0.5
0.5
–1
1
RLoad = 3 kΩ, VO/P(DAC12) = 0 V, DAC12AMPx = 7,
DAC12_xDAT = 0h, VCC = 2.2 V or 3 V
150
250
RLoad = 3 kΩ, VO/P(DAC12) = 0 V, DAC12AMPx = 7,
DAC12_xDAT = 0FFFh, VCC = 2.2 V or 3 V
150
250
1
4
RLoad = 3 kΩ, 0.3 V ≤ VO/P(DAC12) ≤ AVCC - 0.3 V,
DAC12AMPx = 7, VCC = 2.2 V or 3 V
(1)
MAX
0
RLoad = 3 kΩ, VeREF+ = AVCC, DAC12_xDAT = 0FFFh,
DAC12IR = 1, DAC12AMPx = 7, VCC = 2.2 V or 3 V
Max DAC12 load
capacitance
TYP
No Load, VeREF+ = AVCC, DAC12_xDAT = 0h,
DAC12IR = 1, DAC12AMPx = 7VCC = 2.2 V or 3 V
RLoad = 3 kΩ, VeREF+ = AVCC, DAC12_xDAT = 0h,
DAC12IR = 1, DAC12AMPx = 7, VCC = 2.2 V or 3 V
CL(DAC12)
MIN
pF
mA
Ω
Data is valid after the offset calibration of the output amplifier.
Figure 4-45. DAC12_x Output Resistance Tests
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4.57 12-Bit DAC Reference Input Specifications – Electrical Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
Reference input voltage
range
VeREF+
Ri(VREF+),
Ri(VeREF+)
Reference input
resistance
TEST CONDITIONS
TYP
MAX
, VCC = 2.2 V or 3 V
AVCC/3
AVCC + 0.2
DAC12IR = 1 (3) (4), VCC = 2.2 V or 3 V
AVCC
AVCC + 0.2
DAC12IR = 0
MIN
(1) (2)
DAC12_0 IR = DAC12_1 IR = 0,
VCC = 2.2 V or 3 V
20
DAC12_0 IR = 1, DAC12_1 IR = 0,
VCC = 2.2 V or 3 V
40
48
56
20
24
28
58
V
MΩ
DAC12_0 IR = 0, DAC12_1 IR = 1,
VCC = 2.2 V or 3 V
kΩ
DAC12_0 IR = 0, DAC12_1 IR = 1
DAC12_0 SREFx = DAC12_1 SREFx (5),
VCC = 2.2 V or 3 V
(1)
(2)
(3)
(4)
(5)
UNIT
For a full-scale output, the reference input voltage can be as high as 1/3 of the maximum output voltage swing (AVCC).
The maximum voltage applied at reference input voltage terminal VeREF+ = [AVCC - VE(O)] / [3 x (1 + EG)].
For a full-scale output, the reference input voltage can be as high as the maximum output voltage swing (AVCC).
The maximum voltage applied at reference input voltage terminal VeREF+ = [AVCC - VE(O)] / (1 + EG).
When DAC12IR = 1 and DAC12SREFx = 0 or 1 for both channels, the reference input resistive dividers for each DAC are in parallel
reducing the reference input resistance.
Specifications
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4.58 12-Bit DAC Dynamic Specifications, VREF = VCC, DAC12IR = 1 – Electrical Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
tON
TEST CONDITIONS
DAC12_xDAT = 800h,
ErrorV(O) < ±0.5 LSB (1)
(see Figure 4-46), VCC =
2.2 V or 3 V
SR
tS(FS)
tS(C-C)
SR
DAC12_xDAT =
80h → F7Fh → 80h, VCC
= 2.2 V or 3 V
Settling time, full scale
DAC12_xDAT =
3F8h → 408h → 3F8h,
VCC = 2.2 V or 3 V
Settling time, code to
code
Slew rate
DAC12_xDAT =
80h → F7Fh → 80h, VCC
= 2.2 V or 3 V
(2)
DAC12_xDAT =
80h → F7Fh → 80h, VCC
= 2.2 V or 3 V
Glitch energy, full scale
BW-3dB
3-dB bandwidth,
VDC = 1.5 V,
VAC = 0.1 VPP
(see Figure 4-48)
Channel-to-channel
crosstalk (3)
(see Figure 4-49)
(1)
(2)
(3)
MIN
TYP
MAX
DAC12AMPx = 0 → {2, 3, 4}
60
120
DAC12AMPx = 0 → {5, 6}
15
30
6
12
DAC12AMPx = 0 → 7
DAC12AMPx = 2
100
200
DAC12AMPx = 3, 5
40
80
DAC12AMPx = 4, 6, 7
15
30
DAC12AMPx = 2
5
DAC12AMPx = 3, 5
2
DAC12AMPx = 4, 6, 7
1
DAC12AMPx = 2
0.05
0.12
DAC12AMPx = 3, 5
0.35
0.7
1.5
2.7
DAC12AMPx = 4, 6, 7
DAC12AMPx = 2
600
DAC12AMPx = 3, 5
150
DAC12AMPx = 4, 6, 7
UNIT
μs
μs
μs
V/μs
nV-s
30
DAC12AMPx = {2, 3, 4}, DAC12SREFx = 2,
DAC12IR = 1, DAC12_xDAT = 800h, VCC = 2.2 V or 3 V
40
DAC12AMPx = {5, 6}, DAC12SREFx = 2,
DAC12IR = 1, DAC12_xDAT = 800h, VCC = 2.2 V or 3 V
180
DAC12AMPx = 7, DAC12SREFx = 2,
DAC12IR = 1, DAC12_xDAT = 800h, VCC = 2.2 V or 3 V
550
kHz
DAC12_0DAT = 800h, No load,
DAC12_1DAT = 80h ↔ F7Fh, RLoad = 3 kΩ,
ƒDAC12_1OUT = 10 kHz, Duty cycle = 50%, VCC = 2.2 V or 3 V
–80
DAC12_0DAT = 80h ↔ F7Fh, RLoad = 3 kΩ,
DAC12_1DAT = 800h, No load,
ƒDAC12_0OUT = 10 kHz, Duty cycle = 50%, VCC = 2.2 V or 3 V
–80
dB
RLoad and CLoad are connected to AVSS (not AVCC/2) in Figure 4-46.
Slew rate applies to output voltage steps ≥ 200 mV.
RLOAD = 3 kΩ, CLOAD = 100 pF
Conversion 1
V OUT
DAC Output
I Load
R Load = 3 k W
Glitch
Energy
Conversion 2
Conversion 3
+/- 1/2 LSB
AV CC
2
R O/P(DAC12.x)
+/- 1/2 LSB
C Load = 100pF
tsettleLH
tsettleHL
Figure 4-46. Settling Time and Glitch Energy Testing
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Conversion 1
Conversion 2
Conversion 3
V OUT
90%
90%
10%
10%
tSRLH
tSRHL
Figure 4-47. Slew Rate Testing
I Load
Ve REF+
R Load = 3 k W
AV CC
DAC12_x
2
DACx
AC
C Load = 100pF
DC
Figure 4-48. Test Conditions for 3-dB Bandwidth Specification
R Load
I Load
AV CC
DAC12_0
DAC12_xDAT
2
DAC0
080h
7F7h
080h
7F7h
080h
V OUT
C Load = 100pF
VREF+
V DAC12_yOUT
R Load
I Load
AV CC
DAC12_1
V DAC12_xOUT
2
DAC1
fToggle
C Load = 100pF
Figure 4-49. Crosstalk Test Conditions
4.59 Flash Memory – Electrical Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
VCC(PGM/ERASE)
Program and erase supply voltage
2.2
ƒFTG
Flash timing generator frequency
IPGM
Supply current from VCC during program
VCC = 2.2 or 3.6 V
3
IERASE
Supply current from VCC during erase
VCC = 2.2 or 3.6 V
3
tCPT
Cumulative program time
See
tCMErase
Cumulative mass erase time
VCC = 2.2 or 3.6 V
257
(1)
, VCC = 2.2 or 3.6 V
20
104
Program/Erase endurance
tRetention
tWord
tBlock,
0
tBlock, 1-63
(1)
(2)
60
Data retention duration
TJ = 25°C
MAX
UNIT
3.6
V
476
kHz
5
mA
7
mA
10
ms
ms
105
100
cycles
years
Word or byte program time
See
(2)
35
tFTG
Block program time for 1st byte or word
See (2)
30
tFTG
Block program time for each additional byte or
word
See (2)
21
tFTG
The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming
methods: individual word/byte write and block write modes.
These values are hardwired into the Flash Controller's state machine (tFTG = 1/ƒFTG).
Specifications
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Flash Memory – Electrical Characteristics (continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
tBlock,
End
tMass Erase
tSeg
TEST CONDITIONS
TYP
MAX
UNIT
See (2)
6
tFTG
Mass erase time
See (2)
10593
tFTG
(2)
4819
tFTG
Segment erase time
Erase
MIN
Block program end-sequence wait time
See
30
25
Time - (Yrs)
20
15
10
5
0
85
90
95
100
105
110
115
120
125
130
135
140
145
150
MAX
UNIT
Junction Temperature - T J (C)
Figure 4-50. Flash Data Retention vs Junction Temperature
4.60 RAM – Electrical Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
V(RAMh)
(1)
RAM retention supply voltage
TEST CONDITIONS
(1)
MIN
CPU halted
1.6
V
This parameter defines the minimum supply voltage VCC when the data in RAM remains unchanged. No program execution should
happen during this supply voltage condition.
4.61 JTAG and Spy-Bi-Wire Interface – Electrical Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
ƒTCK
TCK input frequency
See
(1)
RInternal
Internal pulldown resistance on TEST
See
(2)
(1)
(2)
, VCC = 2.2 V or 3 V
MIN
TYP
MAX
VCC = 2.2 V
0
5
VCC = 3 V
0
10
25
60
90
UNIT
MHz
kΩ
ƒTCK may be restricted to meet the timing requirements of the module selected.
TMS, TDI/TCLK, and TCK pullup resistors are implemented in all versions.
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4.62 JTAG Fuse (1) – Electrical Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC(FB)
Supply voltage during fuse-blow condition
VFB
Voltage level on TEST for fuse blow
IFB
Supply current into TEST during fuse blow
tFB
Time to blow fuse
(1)
62
TA = 25°C
MIN
MAX
2.5
6
UNIT
V
7
V
100
mA
1
ms
Once the fuse is blown, no further access to the MSP430 JTAG/Test and emulation features is possible. The JTAG block is switched to
bypass mode.
Specifications
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5 Detailed Description
5.1
CPU
The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All
operations, other than program-flow instructions, are performed as register operations in conjunction with
seven addressing modes for source operand and four addressing modes for destination operand.
The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-toregister operation execution time is one cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and
constant generator respectively. The remaining registers are general-purpose registers.
Peripherals are connected to the CPU using data, address, and control buses, and can be handled with all
instructions.
5.2
Instruction Set
The instruction set consists of 51 instructions with three formats and seven address modes. Each
instruction can operate on word and byte data. Table 5-1 shows examples of the three types of instruction
formats; the address modes are listed in Table 5-2.
Program Counter
PC/R0
Stack Pointer
SP/R1
Status Register
Constant Generator
SR/CG1/R2
CG2/R3
General-Purpose Register
R4
General-Purpose Register
R5
General-Purpose Register
R6
General-Purpose Register
R7
General-Purpose Register
R8
General-Purpose Register
R9
General-Purpose Register
R10
General-Purpose Register
R11
General-Purpose Register
R12
General-Purpose Register
R13
General-Purpose Register
R14
General-Purpose Register
R15
Table 5-1. Instruction Word Formats
Dual operands, source-destination
For example, ADD R4,R5
R4 + R5 → R5
Single operands, destination only
For example, CALL R8
PC → (TOS), R8 → PC
Relative jump, un/conditional
For example, JNE
Jump-on-equal bit = 0
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Table 5-2. Address Mode Descriptions
(1)
(2)
5.3
ADDRESS MODE
S (1)
D (2)
SYNTAX
EXAMPLE
Register
•
•
MOV Rs,Rd
MOV R10,R11
R10 → R11
Indexed
•
•
MOV X(Rn),Y(Rm)
MOV 2(R5),6(R6)
M(2+R5) → M(6+R6)
Symbolic (PC relative)
•
•
MOV EDE,TONI
Absolute
•
•
MOV &MEM,&TCDAT
Indirect
•
MOV @Rn,Y(Rm)
MOV @R10,Tab(R6)
M(R10) → M(Tab+R6)
Indirect autoincrement
•
MOV @Rn+,Rm
MOV @R10+,R11
M(R10) → R11
R10 + 2 → R10
Immediate
•
MOV #X,TONI
MOV #45,TONI
#45 → M(TONI)
OPERATION
M(EDE) → M(TONI)
M(MEM) → M(TCDAT)
S = source
D = destination
Operating Modes
The MSP430 has one active mode and five software selectable low-power modes of operation. An
interrupt event can wake up the device from any of the five low-power modes, service the request and
restore back to the low-power mode on return from the interrupt program.
The following six operating modes can be configured by software:
• Active mode ( AM)
– All clocks are active.
• Low-power mode 0 (LPM0)
– CPU is disabled.
– ACLK and SMCLK remain active. MCLK is disabled.
• Low-power mode 1 (LPM1)
– CPU is disabled.
– ACLK and SMCLK remain active. MCLK is disabled.
– DCO’s DC generator is disabled if DCO not used in active mode.
• Low-power mode 2 (LPM2)
– CPU is disabled.
– MCLK and SMCLK are disabled.
– DCO's dc-generator remains enabled.
– ACLK remains active
• Low-power mode 3 (LPM3)
– CPU is disabled.
– MCLK and SMCLK are disabled.
– DCO's dc-generator is disabled.
– ACLK remains active.
• Low-power mode 4 (LPM4)
– CPU is disabled.
– ACLK is disabled.
– MCLK and SMCLK are disabled.
– DCO's dc-generator is disabled.
– Crystal oscillator is stopped.
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Interrupt Vector Addresses
The interrupt vectors and the power-up starting address are located in the address range of
0FFFF–0FFC0h. The vector contains the 16-bit address of the appropriate interrupt handler instruction
sequence.
If the reset vector (located at address 0FFFEh) contains 0FFFFh (for example, flash is not programmed),
the CPU goes into LPM4 immediately after power up.
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
SYSTEM
INTERRUPT
WORD ADDRESS
PRIORITY
Reset
0x0FFFE
31, highest
NMIIFG
OFIFG
ACCVIFG (2) (3)
(non)-maskable,
(non)-maskable,
(non)-maskable
0x0FFFC
30
Timer_B7
TBCCR0 CCIFG (4)
maskable
0x0FFFA
29
Timer_B7
TBCCR1 and TBCCR2
CCIFGs, TBIFG (2) (4)
maskable
0x0FFF8
28
INTERRUPT SOURCE
INTERRUPT FLAG
Power up
External reset
Watchdog
Flash key violation
PC out-of-range (1)
PORIFG
RSTIFG
WDTIFG
KEYV
NMI
Oscillator fault
Flash memory access violation
(2)
Comparator_A+
CAIFG
maskable
0x0FFF6
27
Watchdog timer+
WDTIFG
maskable
0x0FFF4
26
Timer_A3
TACCR0 CCIFG (4)
maskable
0x0FFF2
25
Timer_A3
TACCR1 CCIFG,
TACCR2 CCIFG,
TAIFG (2) (4)
maskable
0x0FFF0
24
USCI_A0/USCI_B0 receive
USCI_B0 I2C status
UCA0RXIFG, UCB0RXIFG (2) (5)
maskable
0x0FFEE
23
USCI_A0/USCI_B0 transmit
USCI_B0 I2C receive/transmit
UCA0TXIFG, UCB0TXIFG (2) (6)
maskable
0x0FFEC
22
ADC12
ADC12IFG (4)
maskable
0x0FFEA
21
0x0FFE8
20
I/O port P2 (eight flags)
P2IFG.0 to P2IFG.7 (2) (4)
maskable
0x0FFE6
19
I/O port P1 (eight flags)
P1IFG.0 to P1IFG.7 (2) (4)
maskable
0x0FFE4
18
USCI_A0/USCI_B1 receive
USCI_B1 I2C status
UCA1RXIFG, UCB1RXIFG (2) (5)
maskable
0x0FFE2
17
USCI_A1/USCI_B1 transmit
USCI_B1 I2C receive/transmit
UCA1TXIFG, UCB1TXIFG (2) (6)
maskable
0x0FFE0
16
DMA
DMA0IFG, DMA1IFG,
DMA2IFG (2) (4)
maskable
0x0FFDE
15
DAC12
DAC12_0IFG,
DAC12_1IFG (2) (4)
maskable
0x0FFDC
14
Reserved (7) (8)
Reserved
0x0FFDA to 0x0FFC0
13 to 0, lowest
A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0x00000 – 0x001FF)
or from within unused address range.
Multiple source flags
(non)-maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot.
Interrupt flags are located in the module.
In SPI mode: UCB0RXIFG. In I2C mode: UCALIFG, UCNACKIFG, ICSTTIFG, UCSTPIFG.
In UART/SPI mode: UCB0TXIFG. In I2C mode: UCB0RXIFG, UCB0TXIFG.
The address 0x0FFBE is used as bootstrap loader security key (BSLSKEY). A 0x0AA55 at this location disables the BSL completely. A
zero disables the erasure of the flash if an invalid password is supplied.
The interrupt vectors at addresses 0x0FFDC to 0x0FFC0 are not used in this device and can be used for regular program code if
necessary.
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Special Function Registers
Most interrupt and module enable bits are collected into the lowest address space. Special function
register bits not allocated to a functional purpose are not physically present in the device. Simple software
access is provided with this arrangement.
5.5.1
Interrupt Enable 1 and 2
Address
7
6
00h
5
4
1
0
ACCVIE
NMIIE
3
2
OFIE
WDTIE
rw-0
rw-0
rw-0
rw-0
WDTIE:
Watchdog Timer interrupt enable. Inactive if watchdog mode is selected. Active if Watchdog
Timer is configured in interval timer mode.
OFIE:
Oscillator fault enable
NMIIE:
(Non)maskable interrupt enable
ACCVIE:
Flash access violation interrupt enable
Address
7
6
5
01h
4
3
2
1
0
UCB0TXIE
UCB0RXIE
UCA0TXIE
UCA0RXIE
rw-0
rw-0
rw-0
rw-0
UCA0RXIE USCI_A0 receive-interrupt enable
UCA0TXIE USCI_A0 transmit-interrupt enable
UCB0RXIE USCI_B0 receive-interrupt enable
UCB0TXIE USCI_B0 transmit-interrupt enable
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Interrupt Flag Register 1 and 2
Address
7
6
5
02h
4
3
2
1
0
NMIIFG
RSTIFG
PORIFG
OFIFG
WDTIFG
rw-0
rw-(0)
rw-(1)
rw-1
rw-(0)
WDTIFG: Set on Watchdog Timer overflow (in watchdog mode) or security key violation.
Reset on VCC power-up or a reset condition at RST/NMI pin in reset mode.
OFIFG:
Flag set on oscillator fault7
RSTIFG:
External reset interrupt flag. Set on a reset condition at RST/NMI pin in reset mode. Reset on
VCC power up.
PORIFG:
Power-On Reset interrupt flag. Set on VCC power up.
NMIIFG:
Set via RST/NMI-pin
Address
7
6
5
4
03h
UCA0RXIFG
USCI_A0 receive-interrupt flag
UCA0TXIFG
USCI_A0 transmit-interrupt flag
UCB0RXIFG
USCI_B0 receive-interrupt flag
UCB0TXIFG
USCI_B0 transmit-interrupt flag
3
2
1
0
UCB0
TXIFG
UCB0
RXIFG
UCA0
TXIFG
UCA0
RXIFG
rw-1
rw-0
rw-1
rw-0
xxx
Legend:
rw:
Bit can be read and written.
rw-0, 1:
Bit can be read and written. It is Reset or Set by PUC.
rw-(0), (1):
Bit can be read and written. It is Reset or Set by POR.
SFR bit is not present in device.
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Memory Organization
MSP430F2619
Memory
Main: interrupt vector
Main: code memory
Size
Flash
Flash
120 kB Flash
0x0FFFF – 0x0FFC0
0x0FFFF – 0x02100
RAM (total)
Size
4 kB
0x020FF -- 0x01100
Extended
Size
2 kB
0x020FF -- 0x01900
Mirrored
Size
2 kB
0x018FF -- 0x01100
Information memory
Size
Flash
256 Byte
0x010FF – 0x01000
Boot memory
Size
ROM
1 kB
0x0FFF – 0x0C00
Size
2 kB
0x009FF – 0x0200
16-bit
8-bit
8-bit SFR
0x001FF – 0x00100
0x000FF – 0x00010
0x0000F – 0x00000
RAM (mirrored at 18FFh to 01100h)
Peripherals
5.7
Bootstrap Loader (BSL)
The MSP430 bootstrap loader (BSL) enables users to program the flash memory or RAM using a UART
serial interface. Access to the MSP430 memory via the BSL is protected by user-defined password. For
complete description of the features of the BSL and its implementation, see Features of the MSP430
Bootstrap Loader (SLAA089).
5.8
BSL Function
PM Package Pins
Data Transmit
13 - P1.1
Data Receive
22 - P2.2
Flash Memory
The flash memory can be programmed via the JTAG port, the bootstrap loader or in-system by the CPU.
The CPU can perform single-byte and single-word writes to the flash memory. Features of the flash
memory include:
• Flash memory has n segments of main memory and four segments of information memory (A to D) of
64 bytes each. Each segment in main memory is 512 bytes in size.
• Segments 0 to n may be erased in one step, or each segment may be individually erased.
• Segments A to D can be erased individually, or as a group with segments 0–n.
Segments A to D are also called information memory.
• Segment A contains calibration data. After reset segment A is protected against programming and
erasing. It can be unlocked but care should be taken not to erase this segment if the device-specific
calibration data is required.
• Flash content integrity check with marginal read modes.
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Peripherals
Peripherals are connected to the CPU through data, address, and control busses and can be handled
using all instructions. For complete module descriptions, refer to MSP430x2xx Family User's Guide
(SLAU144).
5.10 DMA Controller
The DMA controller allows movement of data from one memory address to another without CPU
intervention. For example, the DMA controller can be used to move data from the ADC12
conversionmemory to RAM. Using the DMA controller can increase the throughput of peripheral modules.
The DMA controller reduces system power consumption by allowing the CPU to remain in sleep mode
without having to awaken to move data to or from a peripheral.
5.11 Oscillator and System Clock
The clock system is supported by the basic clock module that includes support for a 32768-Hz watch
crystal oscillator, an internal very low power, low frequency oscillator and an internal digitally-controlled
oscillator (DCO). The basic clock module is designed to meet the requirements of both low system cost
and low-power consumption. The internal DCO provides a fast turn-on clock source and stabilizes in less
than 1 μs. The basic clock module provides the following clock signals:
• Auxiliary clock (ACLK), sourced either from a 32768-Hz watch crystal or the internal LF oscillator for
–55°C to 105°C operation. For > 105°C, use external clock source.
• Main clock (MCLK), the system clock used by the CPU
• Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules
The DCO settings to calibrate the DCO output frequency are stored in the information memory segment A.
Table 5-3. Tags Used by the TLV Structure
NAME
ADDRESS
VALUE
DESCRIPTION
TAG_DCO_30
0x10F6
0x01
DCO frequency calibration at VCC = 3 V and TA = 25°C at
calibration
TAG_ADC12_1
0x10DA
0x08
ADC12_1 calibration tag
TAG_EMPTY
--
0xFE
Identifier for empty areas
Table 5-4. Labels Used by the ADC Calibration Structure
LABEL
CONDITION AT CALIBRATION/DESCRIPTION
SIZE
ADDRESS
OFFSET
CAL_ADC_25T85
INCHx = 0x1010; REF2_5 = 1, TA = 125°C
word
0x000E
CAL_ADC_25T30
INCHx = 0x1010; REF2_5 = 1, TA = 30°C
word
0x000C
CAL_ADC_25VREF_FACTOR
REF2_5 = 1,TA = 30°C
word
0x000A
CAL_ADC_15T85
INCHx = 0x1010; REF2_5 = 0, TA = 125°C
word
0x0008
CAL_ADC_15T30
INCHx = 0x1010; REF2_5 = 0, TA = 30°C
word
0x0006
REF2_5 = 0,TA = 30°C
word
0x0004
External VREF = 1.5 V, ƒADC12CLK = 5 MHz
word
0x0002
External VREF = 1.5 , ƒADC12CLK = 5 MHz
word
0x0000
CAL_ADC_15VREF_FACTOR
CAL_ADC_OFFSET
CAL_ADC_GAIN_FACTOR
CAL_BC1_1MHZ
--
byte
0x0007
CAL_DCO_1MHZ
--
byte
0x0006
CAL_BC1_8MHZ
--
byte
0x0005
CAL_DCO_8MHZ
--
byte
0x0004
CAL_BC1_12MHZ
--
byte
0x0003
CAL_DCO_12MHZ
--
byte
0x0002
CAL_BC1_16MHZ
--
byte
0x0001
CAL_DCO_16MHZ
--
byte
0x0000
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5.12 Brownout, Supply Voltage Supervisor (SVS)
The brownout circuit is implemented to provide the proper internal reset signal to the device during power
on and power off. The SVS circuitry detects if the supply voltage drops below a user selectable level and
supports both supply voltage supervision (the device is automatically reset) and supply voltage monitoring
(SVM) (the device is not automatically reset).
The CPU begins code execution after the brownout circuit releases the device reset. However, VCC may
not have ramped to VCC(min) at that time. The user must ensure that the default DCO settings are not
changed until VCC reaches VCC(min). If desired, the SVS circuit can be used to determine when VCC
reaches VCC(min).
5.13 Digital I/O
There are six 8-bit I/O ports implemented – ports P1 through P6:
• All individual I/O bits are independently programmable.
• Any combination of input, output, and interrupt condition is possible.
• Edge-selectable interrupt input capability for all the eight bits of port P1 and P2.
• Read/write access to port-control registers is supported by all instructions.
• Each I/O has an individually programmable pullup/pulldown resistor.
5.14 WDT+ Watchdog Timer
The primary function of the watchdog timer (WDT+) module is to perform a controlled system restart after
a software problem occurs. If the selected time interval expires, a system reset is generated. If the
watchdog function is not needed in an application, the module can be disabled or configured as an interval
timer and can generate interrupts at selected time intervals.
5.15 Hardware Multiplier
The multiplication operation is supported by a dedicated peripheral module. The module performs 16 × 16,
16 × 8, 8 × 16, and 8 × 8 bit operations. The module is capable of supporting signed and unsigned
multiplication as well as signed and unsigned multiply and accumulate operations. The result of an
operation can be accessed immediately after the operands have been loaded into the peripheral registers.
No additional clock cycles are required.
5.16 USCI
The universal serial communication interface (USCI) module is used for serial data communication. The
USCI module supports synchronous communication protocols like SPI (3 or 4 pin), I2C and asynchronous
communication protocols like UART, enhanced UART with automatic baud-rate detection (LIN), and IrDA.
USCI_A0 provides support for SPI (3 or 4 pin), UART, enhanced UART and IrDA.
USCI_B0 provides support for SPI (3 or 4 pin) and I2C.
70
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5.17 Timer_A3
Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the
capture/compare registers.
Table 5-5. TIMER_A3 Signal Connections
INPUT PIN
NO.
DEVICE
INPUT
SIGNAL
MODULE
INPUT
NAME
12 - P1.0
TACLK
TACLK
ACLK
ACLK
SMCLK
SMCLK
21 - P2.1
TAINCLK
INCLK
13 - P1.1
TA0
CCI0A
22 - P2.2
TA0
CCI0B
DVSS
GND
14 - P1.2
MODULE
BLOCK
MODULE U
SIGNAL
Timer
NA
OUTPUT
PIN NO.
13 - P1.1
CCR0
TA0
17 - P1.5
27 - P2.7
DVCC
VCC
TA1
CCI1A
14 - P1.2
CAOUT
(internal)
CCI1B
18 - P1.6
DVSS
GND
23 - P2.3
DVCC
VCC
CCR1
TA1
ADC12
(internal)
DAC12_0
(internal)
DAC12_1
(internal)
15 - P1.3
TA2
CCI2A
ACLK
(internal)
CCI2B
DVSS
GND
DVCC
VCC
15 - P1.3
CCR2
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TA2
19 - P1.7
24 - P2.4
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5.18 Timer_B7
Timer_B7 is a 16-bit timer/counter with three capture/compare registers. Timer_B7 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_B7 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the
capture/compare registers.
Timer_B7 Signal Connections
INPUT PIN
NO.
DEVICE
INPUT
SIGNAL
MODULE
INPUT
NAME
43 - P4.7
TBCLK
TBCLK
ACLK
ACLK
SMCLK
SMCLK
43 - P4.7
TBCLK
INCLK
36 - P4.0
TB0
CCI0A
36 - P4.0
TB0
CCI0B
DVSS
GND
DVCC
VCC
37 - P4.1
TB1
CCI1A
37 - P4.1
TB1
CCI1B
DVSS
GND
MODULE
BLOCK
MODULE
OUTPUT
SIGNAL
Timer
NA
36 - P4.0
CCR0
TB0
ADC12
(internal)
37 - P4.1
CCR1
TB1
ADC12
(internal)
DVCC
VCC
38 - P4.2
TB2
CCI2A
38 - P4.2
38 - P4.2
TB2
CCI2B
DAC_0
(internal)
DVSS
GND
CCR2
DVCC
VCC
39 - P4.3
TB3
CCI3A
39 - P4.3
TB3
CCI3B
DVSS
GND
40 - P4.4
40 - P4.4
41 - P4.5
41 - P4.5
42 - P4.6
72
OUTPUT
PIN NO.
Detailed Description
DVCC
VCC
TB4
CCI4A
TB4
CCI4B
DVSS
GND
DVCC
VCC
TB5
CCI5A
TB5
CCI5B
DVSS
GND
DVCC
VCC
TB6
CCI6A
ACLK (internal)
CCI6B
DVSS
GND
DVCC
VCC
TB2
DAC_1
(internal)
39 - P4.3
CCR3
TB3
40 - P4.4
CCR4
TB4
41 - P4.5
CCR5
TB5
42 - P4.6
CCR6
TB6
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5.19 Comparator_A+
The primary function of the comparator_A+ module is to support precision slope analog-to-digital
conversions, battery-voltage supervision, and monitoring of external analog signals.
5.20 ADC12
The ADC12 module supports fast 12-bit analog-to-digital conversions. The module implements a 12-bit
SAR core, sample select control, reference generator, and a 16-word conversion-and-control buffer. The
conversion-and-control buffer allows up to 16 independent ADC samples to be converted and stored
without any CPU intervention.
5.21 DAC12
The DAC12 module is a 12-bit, R-ladder, voltage-output digital-to-analog converter (DAC). The DAC12
may be used in 8-bit or 12-bit mode and may be used in conjunction with the DMA controller. When
multiple DAC12 modules are present, they may be grouped together for synchronous operation.
5.22 Peripheral File Map
DMA
DMA channel 2 transfer size
DMA2SZ
0x01F2
DMA channel 2 destination address
DMA2DA
0x01EE
DMA channel 2 source address
DMA2SA
0x01EA
DMA channel 2 control
DMA2CTL
0x01E8
DMA channel 1 transfer size
DMA1SZ
0x01E6
DMA channel 1 destination address
DMA1DA
0x01E2
DMA channel 1 source address
DMA1SA
0x01DE
DMA channel 1 control
DMA1CTL
0x01DC
DMA channel 0 transfer size
DMA0SZ
0x01DA
DMA channel 0 destination address
DMA0DA
0x01D6
DMA channel 0 source address
DMA0SA
0x01D2
DMA channel 0 control
DMA0CTL
0x01D0
DMAIV
0x0126
DMA module control 1
DMACTL1
0x0124
DMA module control 0
DMACTL0
0x0122
DAC12_1 data
DAC12_1DAT
0x01CA
DAC12_1 control
DAC12_1CTL
0x01C2
DAC12_0 data
DAC12_0DAT
0x01C8
DAC12_0 control
DMA module interrupt vector word
DAC12
ADC12
DAC12_0CTL
0x01C0
Interrupt-vector-word register
ADC12IV
0x01A8
Interrupt-enable register
ADC12IE
0x01A6
Interrupt-flag register
ADC12IFG
0x01A4
Control register 1
ADC12CTL1
0x01A2
Control register 0
ADC12CTL0
0x01A0
Conversion memory 15
ADC12MEM15
0x015E
Conversion memory 14
ADC12MEM14
0x015C
Conversion memory 13
ADC12MEM13
0x015A
Conversion memory 12
ADC12MEM12
0x0158
Conversion memory 11
ADC12MEM11
0x0156
Conversion memory 10
ADC12MEM10
0x0154
Conversion memory 9
ADC12MEM9
0x0152
Conversion memory 8
ADC12MEM8
0x0150
Conversion memory 7
ADC12MEM7
0x014E
Conversion memory 6
ADC12MEM6
0x014C
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ADC12
Timer_B7
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Conversion memory 5
ADC12MEM5
0x014A
Conversion memory 4
ADC12MEM4
0x0148
Conversion memory 3
ADC12MEM3
0x0146
Conversion memory 2
ADC12MEM2
0x0144
Conversion memory 1
ADC12MEM1
0x0142
Conversion 0
ADC12MEM0
0x0140
ADC memory-control register15
ADC12MCTL15
0x008F
ADC memory-control register14
ADC12MCTL14
0x008E
ADC memory-control register13
ADC12MCTL13
0x008D
ADC memory-control register12
ADC12MCTL12
0x008C
ADC memory-control register11
ADC12MCTL11
0x008B
ADC memory-control register10
ADC12MCTL10
0x008A
ADC memory-control register9
ADC12MCTL9
0x0089
ADC memory-control register8
ADC12MCTL8
0x0088
ADC memory-control register7
ADC12MCTL7
0x0087
ADC memory-control register6
ADC12MCTL6
0x0086
ADC memory-control register5
ADC12MCTL5
0x0085
ADC memory-control register4
ADC12MCTL4
0x0084
ADC memory-control register3
ADC12MCTL3
0x0083
ADC memory-control register2
ADC12MCTL2
0x0082
ADC memory-control register1
ADC12MCTL1
0x0081
ADC memory-control register0
ADC12MCTL0
0x0080
Capture/compare register _ 6
TBCCR6
0x019E
Capture/compare register 5
TBCCR5
0x019C
Capture/compare register 4
TBCCR4
0x019A
Capture/compare register 3
TBCCR3
0x0198
Capture/compare register 2
TBCCR2
0x0196
Capture/compare register 1
TBCCR1
0x0194
Capture/compare register 0
TBCCR0
0x0192
Timer_B register
TBR
0x0190
Capture/compare control 6
TBCCTL6
0x018E
Capture/compare control 5
TBCCTL5
0x018C
Capture/compare control 4
TBCCTL4
0x018A
Capture/compare control 3
TBCCTL3
0x0188
Capture/compare control 2
TBCCTL2
0x0186
Capture/compare control 1
TBCCTL1
0x0184
Capture/compare control 0
TBCCTL0
0x0182
Timer_B control
Timer_B interrupt vector
74
Detailed Description
TBCTL
0x0180
TBIV
0x011E
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Timer_A3
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Capture/compare register 2
TACCR2
0x0176
Capture/compare register 1
TACCR1
0x0174
Capture/compare register 0
TACCR0
0x0172
Timer_A register
TAR
0x016E
Reserved
0x016C
Reserved
0x016A
Reserved
TACCTL2
0x0166
Capture/compare control 1
TACCTL1
0x0164
Capture/compare control 0
TACCTL0
0x0162
TACTL
0x0160
TAIV
0x012E
Timer_A interrupt vector
Sum extend
SUMEXT
0x013E
Result high word
RESHI
0x013C
Result low word
RESLO
0x013A
Second operand
Multiply signed +accumulate/operand1
Multiply+accumulate/operand1
Multiply signed/operand1
Multiply unsigned/operand1
Flash
0x0168
Capture/compare control 2
Timer_A control
Hardware Multiplier
0x0170
Reserved
OP2
0x0138
MACS
0x0136
MAC
0x0134
MPYS
0x0132
MPY
0x0130
Flash control 4
FCTL4
0x01BE
Flash control 3
FCTL3
0x012C
Flash control 2
FCTL2
0x012A
Flash control 1
FCTL1
0x0128
WDTCTL
0x0120
Watchdog
Watchdog/timer control
USCI A0/B0
USCI A0 auto baud rate control
UCA0ABCTL
0x005D
USCI A0 transmit buffer
UCA0TXBUF
0x0067
USCI A0 receive buffer
UCA0RXBUF
0x0066
USCI A0 status
UCA0STAT
0x0065
USCI A0 modulation control
UCA0MCTL
0x0064
USCI A0 baud rate control 1
UCA0BR1
0x0063
USCI A0 baud rate control 0
UCA0BR0
0x0062
USCI A0 control 1
UCA0CTL1
0x0061
USCI A0 control 0
UCA0CTL0
0x0060
USCI A0 IrDA receive control
UCA0IRRCTL
0x005F
USCI A0 IrDA transmit control
UCA0IRTCLT
0x005E
USCI B0 transmit buffer
UCB0TXBUF
0x006F
USCI B0 receive buffer
UCB0RXBUF
0x006E
USCI B0 status
UCB0STAT
0x006D
USCI B0 I2C interrupt enable
UCB0CIE
0x006C
USCI B0 baud rate control 1
UCB0BR1
0x006B
USCI B0 baud rate control 0
UCB0BR0
0x006A
USCI B0 control 1
UCB0CTL1
0x0069
USCI B0 control 0
UCB0CTL0
0x0068
USCI B0 I2C slave address
UCB0SA
0x011A
USCI B0 I2C own address
UCB0OA
0x0118
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USCI A1/B1
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USCI A1 auto baud rate control
UCA1ABCTL
0x00CD
USCI A1 transmit buffer
UCA1TXBUF
0x00D7
USCI A1 receive buffer
UCA1RXBUF
0x00D6
USCI A1 status
UCA1STAT
0x00D5
USCI A1 modulation control
UCA1MCTL
0x00D4
USCI A1 baud rate control 1
UCA1BR1
0x00D3
USCI A1 baud rate control 0
UCA1BR0
0x00D2
USCI A1 control 1
UCA1CTL1
0x00D1
USCI A1 control 0
UCA1CTL0
0x00D0
USCI A1 IrDA receive control
UCA1IRRCTL
0x00CF
USCI A1 IrDA transmit control
UCA1IRTCLT
0x00CE
USCI B1 transmit buffer
UCB1TXBUF
0x00DF
USCI B1 receive buffer
UCB1RXBUF
0x00DE
UCB1STAT
0x00DD
USCI B1 I2C Interrupt enable
UCB1CIE
0x00DC
USCI B1 baud rate control 1
UCB1BR1
0x00DB
USCI B1 baud rate control 0
UCB1BR0
0x00DA
USCI B1 control 1
UCB1CTL1
0x00D9
USCI B1 control 0
UCB1CTL0
0x00D8
USCI B1 status
USCI B1 I2C slave address
UCB1SA
0x017E
USCI B1 I2C own address
UCB1OA
0x017C
UC1IE
0x0006
USCI A1/B1 interrupt enable
USCI A1/B1 interrupt flag
Comparator_A+
Basic Clock
UC1IFG
0x0007
CAPD
0x005B
Comparator_A control2
CACTL2
0x005A
Comparator_A control1
CACTL1
0x0059
Basic clock system control3
BCSCTL3
0x0053
Basic clock system control2
BCSCTL2
0x0058
Basic clock system control1
BCSCTL1
0x0057
Comparator_A port disable
DCO clock frequency control
DCOCTL
0x0056
Brownout, SVS
SVS control register (reset by brownout signal)
SVSCTL
0x0055
Port P6
Port P6 resistor enable
P6REN
0x0013
Port P6 selection
P6SEL
0x0037
Port P6 direction
P6DIR
0x0036
Port P6 output
P6OUT
0x0035
P6IN
0x0034
Port P5 resistor enable
P5REN
0x0012
Port P5 selection
P5SEL
0x0033
Port P5 direction
P5DIR
0x0032
Port P5 output
P5OUT
0x0031
Port P6 input
Port P5
Port P5 input
Port P4
P5IN
0x0030
Port P4 selection
P4SEL
0x001F
Port P4 resistor enable
P4REN
0x0011
Port P4 direction
P4DIR
0x001E
Port P4 output
P4OUT
0x001D
P4IN
0x001C
Port P4 input
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Port P3
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Port P3 resistor enable
P3REN
0x0010
Port P3 selection
P3SEL
0x001B
Port P3 direction
P3DIR
0x001A
Port P3 output
P3OUT
0x0019
Port P3 input
Port P2
P3IN
0x0018
Port P2 resistor enable
P2REN
0x002F
Port P2 selection
P2SEL
0x002E
P2IE
0x002D
P2IES
0x002C
Port P2 interrupt flag
P2IFG
0x002B
Port P2 direction
P2DIR
0x002A
Port P2 output
P2OUT
0x0029
Port P2 interrupt enable
Port P2 interrupt-edge select
Port P2 input
Port P1
P2IN
0x0028
Port P1 resistor enable
P1REN
0x0027
Port P1 selection
P1SEL
0x0026
P1IE
0x0025
Port P1 interrupt-edge select
P1IES
0x0024
Port P1 interrupt flag
P1IFG
0x0023
Port P1 direction
P1DIR
0x0022
Port P1 output
Port P1 interrupt enable
Special Functions
P1OUT
0x0021
Port P1 input
P1IN
0x0020
SFR interrupt flag2
IFG2
0x0003
SFR interrupt flag1
IFG1
0x0002
SFR interrupt enable2
IE2
0x0001
SFR interrupt enable1
IE1
0x0000
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6 Applications, Implementation, and Layout
6.1
P1.0 to P1.7, Input/Output With Schmitt Trigger
Pad Logic
P1REN.x
P1DIR.x
0
0
Module X OUT
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
P1OUT.x
DVSS
P1.0/TACLK/CAOUT
P1.1/TA0
P1.2/TA1
P1.3/TA2
P1.4/SMCLK
P1.5/TA0
P1.6/TA1
P1.7/TA2
P1SEL.x
P1IN.x
EN
Module X IN
D
P1IE.x
EN
P1IRQ.x
Q
Set
P1IFG.x
P1SEL.x
P1IES.x
Interrupt
Edge Select
Figure 6-1. Port P1 (P1.0 to P1.7) Pin Schematic
Table 6-1. Port P1 (P1.0 to P1.7) Pin Functions
PIN NAME (P1.X)
X
CONTROL BITS/SIGNALS
FUNCTION
P1.0
P1.0/TACLK/ADC10CLK
0
1
I: 0; O: 1
0
0
1
ADC10CLK
1
1
I: 0; O: 1
0
Timer_A3.CCI0A
0
1
Timer_A3.TA0
1
1
I: 0; O: 1
0
Timer_A3.CCI0A
0
1
Timer_A3.TA0
1
1
I: 0; O: 1
0
Timer_A3.CCI0A
0
1
Timer_A3.TA0
1
1
I: 0; O: 1
0
1
1
I: 0; O: 1
0
1
1
I: 0; O: 1
0
P1.2 (I/O)
P1.2/TA1
2
P1.3 I/O
P1.3/TA2
3
P1.4/SMCLK
4
P1.5/TA0
5
P1.6/TA1
P1.7/TA2
78
6
7
P1SEL.x
Timer_A3.TACLK
P1.1 (I/O)
P1.1/TA0
P1DIR.x
P1.4 (I/O)
SMCLK
P1.5 (I/O)
Timer_A3.TA0
P1.6 (I/O)
Timer_A3.TA1
P1.7 (I/O)
Timer_A3.TA2
Applications, Implementation, and Layout
1
1
I: 0; O: 1
0
1
1
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6.2
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P2.0 to P2.4, P2.6, and P2.7, Input/Output With Schmitt Trigger
Pad Logic
To
Comparator_A
From
Comparator_A
CAPD.x
P2REN.x
P2DIR.x
0
0
Module X OUT
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
P2OUT.x
DVSS
Bus
Keeper
EN
P2SEL.x
P2IN.x
EN
P2.0/ACLK/CA2
P2.1/TAINCLK/CA3
P2.2/CAOUT/TA0/CA4
P2.3/CA0/TA1
P2.4/CA1/TA2
P2.6/ADC12CLK/
DMAE0/CA6
P2.7/TA0/CA7
D
Module X IN
P2IE.x
EN
P2IRQ.x
Q
Set
P2IFG.x
P2SEL.x
P2IES.x
Interrupt
Edge Select
Figure 6-2. Port P2.0, P2.3, P2.4, P2.6 and P2.7 Pin Schematic
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Table 6-2. Port P2.0, P2.3, P2.4, P2.6 and P2.7 Pin Functions
Pin Name (P2.X)
P2.0/ACLK/CA2
P2.1/TAINCLK/CA3
P2.2/CAOUT/TA0/CA4
P2.3/CA0/TA1
P2.4/CA1/TA2
P2.6/ADC12CLK/
DMAE0/CA6
P2.7/TA0/CA7
(1)
80
X
0
1
2
3
4
6
7
FUNCTION
CONTROL BITS/SIGNALS (1)
CAPD.x
P2DIR.x
P2SEL.x
P2.0 (I/O)
0
I: 0; O: 1
0
ACLK
0
1
1
CA2
1
X
X
P2.2 (I/O)
0
I: 0; O: 1
0
Timer_A3.INCLK
0
0
1
DVSS
0
1
1
CA3
1
X
X
P2.2 (I/O)
0
I: 0; O: 1
0
CAOUT
0
1
1
Timer_A3.CCI0B
0
0
1
CA4
1
X
X
P2.3 (I/O)
0
I: 0; O: 1
0
Timer_A3.TA1
0
1
1
CA0
1
X
X
P2.4 (I/O)
0
I: 0; O: 1
0
Timer_A3.TA2
0
1
X
CA1
1
X
1
P2.6 (I/O)
0
I: 0; O: 1
0
ADC12CLK
0
1
1
DMAE0
0
0
1
CA6
1
X
X
P2.7 (I/O)
0
I: 0; O: 1
0
Timer_A3.TA0
0
1
1
CA7
1
X
X
X: Don't care
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6.3
SLAS697E – MARCH 2010 – REVISED NOVEMBER 2016
P2.5, Input/Output With Schmitt Trigger and External ROSC for DCO
Pad Logic
To Comparator
From Comparator
CAPD.5
To DCO
in DCO
DCOR
P2REN.5
P2DIR.5
0
P2OUT.5
0
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
Module X OUT
DVSS
P2.5/ROSC/CA5
Bus
Keeper
EN
P2SEL.x
P2IN.5
EN
Module X IN
D
P2IE.5
P2IRQ.5
EN
Q
Set
P2IFG.5
P2SEL.5
Interrupt
Edge Select
P2IES.5
Figure 6-3. Port P2 (P2.5) Pin Schematic
Table 6-3. Port P2 (P2.5) Pin Functions
PIN NAME (P2.X)
P2.5/ROSC /CA5
(1)
(2)
X
5
FUNCTION
CONTROL BITS/SIGNALS (1)
CAPD
DCOR
P2DIR.5
P2.5 (I/O)
0
0
I: 0; O: 1
P2SEL.5
0
ROSC (2)
0
1
X
X
DVSS
0
0
1
1
ROSC
1 or selected
0
X
X
X: Don't care
If ROSC is used it is connected to an external resistor.
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6.4
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Port P3 Pin Schematic: P3.0 to P3.7, Input/Output With Schmitt Trigger
Pad Logic
P3REN.x
P3DIR.x
Module
direction
P3OUT.x
Module X OUT
0
DVSS
0
DVCC
1
1
Direction
0: Input
1: Output
1
0
1
P3.0/UCB0STE/UCA0CLK
P3.1/UCB0SIMO/UCB0SDA
P3.2/UCB0SOMI/UCB0SCL
P3.3/UCB0CLK/UCA0STE
P3.4/UCA0TXD/UCA0SIMO
P3.5/UCA0RXD/UCA0SOMI
P3.6/UCA1TXD/UCA1SIMO
P3.7/UCA1RXD/UCA1SOMI
P3SEL.x
P3IN.x
EN
Module X IN
D
Figure 6-4. Port P3 (P3.0) Pin Schematic
Table 6-4. Port P3 (P3.0) Pin Functions
PIN NAME (P3.X)
P3.0/UCB0STE/UCA0CLK
X
0
P3.1/UCB0SIMO/UCB0SDA
1
P3.2/UCB0SOMI/UCB0SCL
2
P3.3/UCB0CLK/UCA0STE
3
P3.4/UCA0TXD/UCA0SIMO
4
P3.5/UCA0RXD/UCA0SOMI
5
P3.6/UCA1TXD/UCA1SIMO
6
P3.7/UCA1RXD/UCA1SOMI
7
(1)
(2)
(3)
(4)
82
CONTROL BITS/SIGNALS (1)
FUNCTION
P3.0 (I/O)
UCB0STE/UCA0CLK (2) (3)
P3.1 (I/O)
UCB0SIMO/UCB0SDA (2) (4)
P3.2 (I/O
UCB0SOMI/UCB0SCL (2) (4)
P3.3 (I/O)
UCB0CLK/UCA0STE
(2)
P3.4 (I/O)
UCA0TXD/UCA0SIMO (2)
P3.5 (I/O)
UCA0RXD/UCA0SOMI (2)
P3.6 (I/O)
UCA1TXD/UCA1SIMO (2)
P3.7 (I/O)
UCA1RXD/UCA1SOMI (2)
P3DIR.x
P3SEL.x
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
X: Don’t care
The pin direction is controlled by the USCI module.
UCA0CLK function takes precedence over UCB0STE function. If the pin is required as UCA0CLK input or output, USCI A0/B0 is forced
to 3-wire SPI mode if 4-wire SPI mode is selected.
In case the I2C functionality is selected the output drives only the logical 0 to VSS level.
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6.5
SLAS697E – MARCH 2010 – REVISED NOVEMBER 2016
Port P4 Pin Schematic: P4.0 to P4.7, Input/Output With Schmitt Trigger
Pad Logic
P4REN.x
P4DIR.x
0
P4OUT.x
0
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
Module X OUT
DVSS
P4.0/TB0
P4.1/TB1
P4.2/TB2
P4.3/TB3
P4.4/TB4
P4.5/TB5
P4.6/TB6
P4.7/TBCLK
P4SEL.x
P4IN.x
EN
Module X IN
D
Figure 6-5. Port P4 (P4.0 to P4.7) Pin Schematic
Table 6-5. Port P4 (P4.0 to P4.7) Pin Functions
PIN NAME (P4.X)
X
FUNCTION
P4.0 (I/O)
P4.0/TB0
0
1
I: 0; O: 1
0
0
1
Timer_B7.TB0
1
1
I: 0; O: 1
0
Timer_B7.CCI1A and Timer_B7.CCI1B
0
1
Timer_B7.TB1
1
1
I: 0; O: 1
0
Timer_B7.CCI2A and Timer_B7.CCI2B
0
1
Timer_B7.TB2
1
1
I: 0; O: 1
0
Timer_B7.CCI3A and Timer_B7.CCI3B
0
1
Timer_B7.TB3
1
1
I: 0; O: 1
0
0
1
P4.2 (I/O)
P4.2/TB2
2
P4.3 (I/O)
P4.3/TB3
3
P4.4 (I/O)
P4.4/TB4
4
Timer_B7.CCI4A and Timer_B7.CCI4B
Timer_B7.TB4
P4.5 (I/O)
P4.5/TB5
5
Timer_B7.CCI5A and Timer_B7.CCI5B
Timer_B7.TB5
P4.6 (I/O)
P4.6/TB6
6
Timer_B7.CCI6A and Timer_B7.CCI6B
Timer_B7.TB6
P4.7/TBCLK
7
P4SEL.x
Timer_B7.CCI0A and Timer_B7.CCI0B
P4.1 (I/O)
P4.1/TB1
CONTROL BITS/SIGNALS
P4DIR.x
P4.7 (I/O)
Timer_B7.TBCLK
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1
1
I: 0; O: 1
0
0
1
1
1
I: 0; O: 1
0
0
1
1
1
I: 0; O: 1
0
1
1
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6.6
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Port P5 Pin Schematic: P5.0 to P5.7, Input/Output With Schmitt Trigger
Pad Logic
P5REN.x
P5DIR.x
0
Module
Direction
1
P5OUT.x
0
Module X OUT
DVSS
0
DVCC
1
1
Direction
0: Input
1: Output
1
P5.0/UCB1STE/UCA1CLK
P5.1/UCB1SIMO/UCB1SDA
P5.2/UCB1SOMI/UCB1SCL
P5.3/UCB1CLK/UCA1STE
P5.4/MCLK
P5.5/SMCLK
P5.6/ACLK
P5.7/TBOUTH/SVSOUT
P5SEL.x
P5IN.x
EN
Module X IN
D
Figure 6-6. Port P5 (P5.0 to P5.7) Pin Schematics
Table 6-6. Port P5 (P5.0 to P5.7) Pin Functions
PIN NAME (P5.X)
P5.0/UCB1STE/UCA1CLK
X
0
P5.1/UCB1SIMO/UCB1SDA
1
P5.2/UCB1SOMI/UCB1SCL
2
P5.3/UCB1CLK/UCA1STE
3
P5.4/MCLK
4
P5.5/SMCLK
5
P5.6/ACLK
6
P5.7/TBOUTH/SVSOUT
7
(1)
(2)
(3)
(4)
84
CONTROL BITS/SIGNALS (1)
FUNCTION
P5.0 (I/O)
UCB1STE/UCA1CLK (2) (3)
P5.1 (I/O)
UCB1SIMO/UCB1SDA (2) (4)
P5.2 (I/O)
UCB1SOMI/UCB1SCL (2) (4)
P5.3 (I/O)
UCB1CLK/UCA1STE
(2)
P5DIR.x
P5SEL.x
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
1
1
I: 0; O: 1
0
1
1
I: 0; O: 1
0
1
1
P5.7 (I/O)
I: 0; O: 1
0
TBOUTH
0
1
SVSOUT
1
1
P5.0 (I/O)
MCLK
P5.1 (I/O)
SMCLK
P5.2 (I/O)
ACLK
X: Don’t care
The pin direction is controlled by the USCI module.
UCA1CLK function takes precedence over UCB1STE function. If the pin is required as UCA1CLK input or output USCI A1/B1 will be
forced to 3-wire SPI mode if 4-wire SPI mode is selected.
In case the I2C functionality is selected the output drives only the logical 0 to VSS level.
Applications, Implementation, and Layout
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6.7
SLAS697E – MARCH 2010 – REVISED NOVEMBER 2016
Port P6 Pin Schematic: P6.0 to P6.4, Input/Output With Schmitt Trigger
Pad Logic
ADC12 Ax
P6REN.x
P6DIR.x
0
P6OUT.x
0
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
Module X OUT
DVSS
P6.0/A0
P6.1/A1
P6.2/A2
P6.3/A3
P6.4/A4
Bus
Keeper
EN
P6SEL.x
P6IN.x
EN
Module X IN
D
Figure 6-7. Port P6 (P6.0 to P6.4) Pin Schematic
Table 6-7. Port P6 (P6.0 to P6.4) Pin Functions
PIN NAME (P6.X)
X
P6.0/A0
0
P6.1/A1
1
P6.2/A2
2
P6.3/A3
3
P6.4/A4
4
(1)
(2)
FUNCTION
P6.0 (I/O)
A0 (2)
P6.1 (I/O)
A1
(2)
P6.2 (I/O)
A2 (2)
P6.3(I/O)
A3 (2)
P6.3 (I/O)
A4
(2)
CONTROL BITS/SIGNALS (1)
P6DIR.x
P6SEL.x
I: 0; O: 1
0
X
X
I: 0; O: 1
0
X
X
I: 0; O: 1
0
X
X
I: 0; O: 1
0
X
X
I: 0; O: 1
0
X
X
X: Don’t care
The ADC12 channel Ax is connected to AVss internally if not selected.
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6.8
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Port P6 Pin Schematic: P6.5 and P6.6, Input/Output With Schmitt Trigger
Pad Logic
DAC12_0OUT
DAC12AMP > 0
ADC12 Ax
ADC12 Ax
P6REN.x
P6DIR.x
0
P6OUT.x
0
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
Module X OUT
DVSS
P6.5/A5/DAC1
P6.6/A6/DAC0
Bus
Keeper
EN
P6SEL.x
P6IN.x
EN
Module X IN
D
Figure 6-8. Port P6 (P6.5 to P6.6) Pin Schematic
Table 6-8. Port P6 (P6.5 to P6.6) Pin Functions
CONTROL BITS/SIGNALS (1)
PIN NAME (P6.X)
X
FUNCTION
P6.5 (I/O)
P6.5/A5/DAC1
5
(1)
(2)
(3)
86
6
P6SEL.x
CAPD.x or
DAC12AMP > 0
I: 0; O: 1
0
0
DVSS
1
1
0
A5 (2)
X
X
1
DAC1 (DA12OPS = 1) (3)
X
X
1
P6.6 (I/O)
P6.6/A6/DAC0
P6DIR.x
I: 0; O: 1
0
0
DVSS
1
1
0
A6 (2)
X
X
1
DAC1 (DA12OPS = 0) (3)
X
X
1
X: Don’t care
The ADC12 channel Ax is connected to AVss internally if not selected.
The DAC outputs are floating if not selected.
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6.9
SLAS697E – MARCH 2010 – REVISED NOVEMBER 2016
Port P6 Pin Schematic: P6.7, Input/Output With Schmitt Trigger
Pad Logic
to SVS Mux
VLD = 15
DAC12_0OUT
DAC12AMP > 0
ADC12 A7
from ADC12
P6REN.7
P6DIR.7
0
P6OUT.7
0
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
Module X OUT
DVSS
P6.7/A7/DAC1/SVSIN
Bus
Keeper
EN
P6SEL.7
P6IN.7
EN
Module X IN
D
Figure 6-9. Port P6 (P6.7) Pin Schematic
Table 6-9. Port P6 (P6.7) Pin Functions
PIN NAME (P6.X)
X
FUNCTION
P6DIR.x
P6SEL.x
I: 0; O: 1
0
DVSS
1
1
(2)
P6.7 (I/O)
P6.7/A7/DAC1/SVSIN
(1)
(2)
(3)
7
CONTROL BITS/SIGNALS (1)
A7
X
X
DAC1 (DA12OPS = 0) (3)
X
X
SVSIN (VLD = 15)
X
X
X: Don’t care
The ADC12 channel Ax is connected to AVss internally if not selected.
The DAC outputs are floating if not selected.
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6.10 Port P7 Pin Schematic: P7.0 to P7.7, Input/Output With Schmitt Trigger
Pad Logic
P7REN.x
P7DIR.x
0
0
1
P7OUT.x
0
VSS
1
DVSS
0
DVCC
1
1
Direction
0: Input
1: Output
P7.x
P7SEL.x
P7IN.x
EN
Module X IN
D
Figure 6-10. Port P7 (P7.0 to P7.7) Pin Schematic
Table 6-10. Port P7 (P7.0 to P7.7) Pin Functions (1)
PIN NAME (P7.X)
P7.0
X
0
P7.1
1
P7.2
2
P7.3
3
P7.4
4
P7.5
5
P7.6
6
P7.7
(1)
88
7
CONTROL BITS/SIGNALS
FUNCTION
P7.0 (I/O)
Input
P7.1 (I/O)
Input
P7.2 (I/O)
Input
P7.3 (I/O)
Input
P7.4 (I/O)
Input
P7.5 (I/O)
Input
P7.6 (I/O)
Input
P7.7 (I/O)
Input
P7DIR.x
P7SEL.x
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
80-pin KGD only.
Applications, Implementation, and Layout
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SLAS697E – MARCH 2010 – REVISED NOVEMBER 2016
6.11 Port P8 Pin Schematic: P8.0 to P8.5, Input/Output With Schmitt Trigger
Pad Logic
P8REN.x
P8DIR.x
0
0
1
P8OUT.x
0
VSS
1
DVSS
0
DVCC
1
1
Direction
0: Input
1: Output
P8.0
P8.1
P8.2
P8.3
P8.4
P8.5
P8SEL.x
P8IN.x
EN
Module X IN
D
Figure 6-11. Port P8 (P8.0 to P8.5) Pin Schematic
Table 6-11. Port P8 (P8.0 to P8.5) Pin Functions (1)
PIN NAME (P8.X)
P8.0
P8.1
X
0
1
P8.2
2
P8.3
3
P8.4
P8.5
(1)
4
5
FUNCTION
P8.0 (I/O)
Input
P8.1 (I/O)
Input
P8.2 (I/O)
Input
P8.3 (I/O)
Input
P8.4 (I/O)
Input
P8.5 (I/O)
Input
CONTROL BITS/SIGNALS
P8DIR.x
P8SEL.x
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
80-pin KGD only.
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6.12 Port P8 Pin Schematic: P8.6, Input/Output With Schmitt Trigger
BCSCTL3.XT2Sx = 11
0
XT2CLK
From
P8.7/XIN
1
P8.7/XIN
XT2 off
Pad Logic
P8SEL.7
P8REN.6
P8DIR.6
0
P8OUT.6
0
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
Module X OUT
DVSS
P8.6/XOUT
Bus
Keeper
EN
P8SEL.6
P8IN.6
EN
Module X IN
D
Figure 6-12. Port P8 (P8.6) Pin Schematic
Table 6-12. Port P8 (P8.6) Pin Functions (1)
PIN NAME (P8.X)
X
CONTROL BITS/SIGNALS
FUNCTION
P8DIR.x
P8SEL.x
I: 0; O: 1
0
XOUT (default)
0
1
DVSS
1
1
P8.6 (I/O)
P8.6/XOUT
(1)
90
6
80-pin KGD only.
Applications, Implementation, and Layout
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SLAS697E – MARCH 2010 – REVISED NOVEMBER 2016
6.13 Port P8 Pin Schematic: P8.7, Input/Output With Schmitt Trigger
BCSCTL3.XT2Sx = 11
P8.6/XOUT
XT2 off
0
XT2CLK
1
P8SEL.6
Pad Logic
P8REN.7
0
P8DIR.7
0
0
Module X OUT
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
P8OUT.7
DVSS
P8.7/XIN
Bus
Keeper
EN
P8SEL.7
P8IN.7
EN
Module X IN
D
Figure 6-13. Port P8 (P8.7) Pin Schematic
Table 6-13. Port P8 (P8.7) Pin Functions (1)
PIN NAME (P8.X)
X
FUNCTION
P8DIR.x
P8SEL.x
I: 0; O: 1
0
XIN (default)
0
1
VSS
1
1
P8.7 (I/O)
P8.7/XIN
(1)
6
CONTROL BITS/SIGNALS
80-pin KGD only.
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6.14 JTAG Pins: TMS, TCK, TDI/TCLK, TDO/TDI, Input/Output With Schmitt Trigger
TDO
Controlled by JTAG
Controlled by JTAG
JTAG
TDO/TDI
Controlled
by JTAG
DVCC
DVCC
TDI
Fuse
Burn and Test
Fuse
Test
TDI/TCLK
and
DVCC
Emulation
Module
TMS
TMS
DVCC
During Programming Activity and
During Blowing of the Fuse, Pin
TDO/TDI is Used to Apply the Test
Input Data for JTAG Circuitry
TCK
TCK
Figure 6-14. JTAG Module
92
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6.15 JTAG Fuse Check Mode
MSP430 devices that have the fuse on the TEST terminal have a fuse check mode that tests the
continuity of the fuse the first time the JTAG port is accessed after a power-on reset (POR). When
activated, a fuse check current, ITF , of 1 mA at 3 V, 2.5 mA at 5 V can flow from the TEST pin to ground if
the fuse is not burned. Care must be taken to avoid accidentally activating the fuse check mode and
increasing overall system power consumption.
When the TEST pin is again taken low after a test or programming session, the fuse check mode and
sense currents are terminated.
Activation of the fuse check mode occurs with the first negative edge on the TMS pin after power up or if
TMS is being held low during power up. The second positive edge on the TMS pin deactivates the fuse
check mode. After deactivation, the fuse check mode remains inactive until another POR occurs. After
each POR the fuse check mode has the potential to be activated.
The fuse check current flows only when the fuse check mode is active and the TMS pin is in a low state
(see Figure 6-15). Therefore, the additional current flow can be prevented by holding the TMS pin high
(default condition).
Time TMS Goes Low After POR
TMS
ITF
ITEST
Figure 6-15. Fuse Check Mode Current
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7 Device and Documentation Support
7.1
Development Tool Support
All MSP430 microcontrollers include an embedded emulation module (EEM) allowing advanced debugging
and programming through easy-to-use development tools. Recommended hardware options include:
• Debugging and programming interface
– MSP-FET430UIF (USB)
– MSP-FET430PIF (parallel port)
• Debugging and programming interface with target board
– MSP-FET430U64
– MSP-FET430U80
• Standalone target board
– MSP-TS430PM64
• Production programmer
– MSP-GANG430
7.2
Receiving Notification of Documentation Updates
To receive notification of documentation updates—including silicon errata—go to the product folder for
your device on ti.com (MSP430F2619S-HT). In the upper right-hand corner, click the "Alert me" button.
This registers you to receive a weekly digest of product information that has changed (if any). For change
details, check the revision history of any revised document.
7.3
Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the
respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;
see TI's Terms of Use.
TI E2E™ Online Community The TI engineer-ro-engineer (E2E) community was created to foster
collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge,
explore ideas and help solve problems with fellow engineers.
TI Embedded Processors Wiki Established to help developers get started with Embedded Processors
from Texas Instruments and to foster innovation and growth of general knowledge about the
hardware and software surrounding these devices.
7.4
Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
7.5
Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
7.6
Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
94
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8 Mechanical, Packaging, and Orderable Information
8.1
Packaging Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and
revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Mechanical, Packaging, and Orderable Information
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PACKAGE OPTION ADDENDUM
www.ti.com
23-Dec-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
MSP430F2619S64KGD1
ACTIVE
XCEPT
KGD
0
36
TBD
Call TI
N / A for Pkg Type
-55 to 150
MSP430F2619SKGD1
ACTIVE
XCEPT
KGD
0
36
TBD
Call TI
N / A for Pkg Type
-55 to 150
MSP430F2619SPM
ACTIVE
LQFP
PM
64
160
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-55 to 150
M430F2619SPM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
23-Dec-2016
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MTQF008A – JANUARY 1995 – REVISED DECEMBER 1996
PM (S-PQFP-G64)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
0,08 M
33
48
49
32
64
17
0,13 NOM
1
16
7,50 TYP
Gage Plane
10,20
SQ
9,80
12,20
SQ
11,80
0,25
0,05 MIN
0°– 7°
0,75
0,45
1,45
1,35
Seating Plane
0,08
1,60 MAX
4040152 / C 11/96
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Falls within JEDEC MS-026
May also be thermally enhanced plastic with leads connected to the die pads.
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