DATA SHEET 512MB SDRAM S.O.DIMM EBS52UC8APSA (64M words × 64 bits, 2 bank) Description Features The EBS52UC8APSA is 64M words × 64 bits, 2 banks Synchronous Dynamic RAM Small Outline Dual In-line Memory Module (S.O.DIMM), mounted 16 pieces of 256M bits SDRAM sealed in µBGA package. This module provides high density and large quantities of memory in a small space without utilizing the surface mounting technology. Decoupling capacitors are mounted on power supply line for noise reduction. • Fully compatible with 8 bytes S.O.DIMM: JEDEC standard outline • 144-pin socket type small outline dual in line memory module (S.O.DIMM) PCB height: 31.75mm (1.25inch ) Lead pitch: 0.80mm • 3.3V power supply • Clock frequency: 133MHz (max.) • LVTTL interface • Data bus width: × 64 non-ECC • Single pulsed /RAS • 4 Banks can operates simultaneously and independently • Burst read/write operation and burst read/single write operation capability • Programmable burst length (BL): 1, 2, 4, 8, Full page • 2 variations of burst sequence Sequential Interleave • Programmable /CAS latency (CL): 2, 3 • Byte control by DQMB • Refresh cycles: 8192 refresh cycles/64ms • 2 variations of refresh Auto refresh Self refresh Note : Do not push the cover or drop the modules in order to protect from mechanical defects, which would be electrical defects. Document No. E0240E20 (Ver. 2.0) Date Published May 2002 (K) Japan URL: http://www.elpida.com Elpida Memory, Inc. 2001-2002 EBS52UC8APSA Ordering Information Part number Clock frequency MHz (max.) /CAS latency Package EBS52UC8APSA-7A EBS52UC8APSA-75 *1 EBS52UC8APSA-7AL EBS52UC8APSA-75L*1 133 133 133 133 2, 3 3 2, 3 3 144-pin S.O.DIMM Contact pad Mounted devices Gold EDS2508APSA Note: 1. 100MHz operation at /CAS latency = 2. Pin Configurations Front Side 1pin 59pin 61pin 143pin 2pin 60pin 62pin 144pin Back Side Front side Back side Pin No. Pin name Pin No. Pin name Pin No. Pin name Pin No. Pin name 1 VSS 73 NC 2 VSS 74 CLK1 3 DQ0 75 VSS 4 DQ32 76 VSS 5 DQ1 77 NC 6 DQ33 78 NC 7 DQ2 79 NC 8 DQ34 80 NC 9 DQ3 81 VDD 10 DQ35 82 VDD 11 VDD 83 DQ16 12 VDD 84 DQ48 13 DQ4 85 DQ17 14 DQ36 86 DQ49 15 DQ5 87 DQ18 16 DQ37 88 DQ50 17 DQ6 89 DQ19 18 DQ38 90 DQ51 19 DQ7 91 VSS 20 DQ39 92 VSS 21 VSS 93 DQ20 22 VSS 94 DQ52 23 DQMB0 95 DQ21 24 DQMB4 96 DQ53 25 DQMB1 97 DQ22 26 DQMB5 98 DQ54 27 VDD 99 DQ23 28 VDD 100 DQ55 29 A0 101 VDD 30 A3 102 VDD 31 A1 103 A6 32 A4 104 A7 33 A2 105 A8 34 A5 106 BA0 35 VSS 107 VSS 36 VSS 108 VSS 37 DQ8 109 A9 38 DQ40 110 BA1 39 DQ9 111 A10 (AP) 40 DQ41 112 A11 41 DQ10 113 VDD 42 DQ42 114 VDD 43 DQ11 115 DQMB2 44 DQ43 116 DQMB6 Data Sheet E0240E20 (Ver. 2.0) 2 EBS52UC8APSA Front side Back side Pin No. Pin name Pin No. Pin name Pin No. Pin name Pin No. Pin name 45 VDD 117 DQMB3 46 VDD 118 DQMB7 47 DQ12 119 VSS 48 DQ44 120 VSS 49 DQ13 121 DQ24 50 DQ45 122 DQ56 51 DQ14 123 DQ25 52 DQ46 124 DQ57 53 DQ15 125 DQ26 54 DQ47 126 DQ58 55 VSS 127 DQ27 56 VSS 128 DQ59 57 NC 129 VDD 58 NC 130 VDD 59 NC 131 DQ28 60 NC 132 DQ60 61 CLK0 133 DQ29 62 CKE0 134 DQ61 63 VDD 135 DQ30 64 VDD 136 DQ62 65 /RAS 137 DQ31 66 /CAS 138 DQ63 67 /WE 139 VSS 68 CKE1 140 VSS 69 /CS0 141 SDA 70 A12 142 SCL 71 /CS1 143 VDD 72 NC 144 VDD Pin Description Pin name Function A0 to A12 Address input Row address A0 to A12 Column address A0 to A9 BA0, BA1 Bank select address DQ0 to DQ63 Data input/output /CS0, /CS1 Chip select input /RAS Row enable (/RAS) input /CAS Column enable (/CAS) input /WE Write enable input DQMB0 to DQMB7 Byte data mask CLK0, CLK1 Clock input CKE0, CKE1 Clock enable input SDA Data input/output for serial PD SCL Clock input for serial PD VDD Primary positive power supply VSS Ground NC No connection Data Sheet E0240E20 (Ver. 2.0) 3 EBS52UC8APSA Serial PD Matrix Byte No. Function described Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments 0 Number of bytes used by module manufacturer 1 0 0 0 0 0 0 0 80H 128 bytes 1 Total SPD memory size 0 0 0 0 1 0 0 0 08H 256 bytes 2 Memory type 0 0 0 0 0 1 0 0 04H SDRAM 3 Number of row addresses bits 0 0 0 0 1 1 0 1 0DH 13 4 Number of column addresses bits 0 0 0 0 1 0 1 0 0AH 10 5 Number of banks 0 0 0 0 0 0 1 0 02H 2 6 Module data width 0 1 0 0 0 0 0 0 40H 64 7 Module data width (continued) 0 0 0 0 0 0 0 0 00H 0 Module interface signal levels 0 0 0 0 0 0 0 1 01H LVTTL 1 1 1 0 1 0 1 75H 7.5ns 1 0 1 0 1 0 0 54H 5.4ns 8 9 10 SDRAM cycle time at CL = 3 0 (highest /CAS latency) SDRAM access from Clock at CL = 3 0 (highest /CAS latency) 11 Module configuration type 0 0 0 0 0 0 0 0 00H None. 12 Refresh rate/type 1 0 0 0 0 0 1 0 82H 7.8µs 13 SDRAM width 0 0 0 0 1 0 0 0 08H ×8 14 Error checking SDRAM width 0 0 0 0 0 0 0 0 00H None. 0 0 0 0 0 0 0 1 01H 1 CLK 1 0 0 0 1 1 1 1 8FH 1,2,4,8,F 0 0 0 0 0 1 0 0 04H 4 0 0 0 0 0 1 1 0 06H 2,3 0 0 0 0 0 0 0 1 01H 0 0 0 0 0 0 0 0 1 01H 0 15 16 17 18 19 20 SDRAM device attributes: minimum clock delay for back-toback random column addresses SDRAM device attributes: Burst lengths supported SDRAM device attributes: number of banks on SDRAM device SDRAM device attributes: /CAS latency SDRAM device attributes: /CS latency SDRAM device attributes: /WE latency 21 SDRAM device attributes 0 0 0 0 0 0 0 0 00H 22 SDRAM device attributes: General 0 0 0 0 1 1 1 0 0EH 23 SDRAM cycle time at CL = 2 (2nd highest /CAS latency) (-7A/7AL) 0 1 1 1 0 1 0 1 75H 7.5ns 1 0 1 0 0 0 0 0 A0H 10ns 24 SDRAM access from Clock at CL = 2 (2nd highest /CAS latency) 0 (-7A/7AL) 1 0 1 0 1 0 0 54H 5.4ns 0 1 1 0 0 0 0 0 60H 6ns 0 0 0 0 0 0 0 0 00H 0 0 0 0 1 1 1 1 0FH 15ns 0 0 0 1 0 1 0 0 14H 20ns (-75/75L) (-75/75L) 25 to 26 27 Minimum row precharge time (-7A/7AL) (-75/75L) Data Sheet E0240E20 (Ver. 2.0) 4 EBS52UC8APSA Byte No. Function described Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments 28 Row active to row active min 0 0 0 0 1 1 1 1 0FH 15ns 29 /RAS to /CAS delay min (-7A/7AL) 0 0 0 0 1 1 1 1 0FH 15ns 0 0 0 1 0 1 0 0 14H 20ns (-75/75L) 30 Minimum /RAS pulse width 0 0 1 0 1 1 0 1 2DH 45ns 31 Density of each bank on module 0 1 0 0 0 0 0 0 40H 256MB 0 0 0 1 0 1 0 1 15H 1.5ns 0 0 0 0 1 0 0 0 08H 0.8ns Data signal input setup time 0 0 0 1 0 1 0 1 15H 1.5ns 35 Data signal input hold time 0 0 0 0 1 0 0 0 08H 0.8ns 36 to 61 Superset information 0 0 0 0 0 0 0 0 00H 62 SPD data revision code 0 0 0 1 0 0 1 0 12H 63 Checksum for Bytes 0 to 62 (-7A/7AL) 1 0 0 1 0 0 1 0 92H 1 1 0 1 0 0 1 1 D3H 32 33 34 Address and command signal input setup time Address and command signal input hold time (-75/75L) 1.2 64 to 65 Manufacturer’s JEDEC ID code 0 1 1 1 1 1 1 1 7FH Continuation code 66 Manufacturer’s JEDEC ID code 1 1 1 1 1 1 1 0 FEH Elpida Memory 67 to 71 Manufacturer’s JEDEC ID code 0 0 0 0 0 0 0 0 00H 72 Manufacturing location 0 1 1 0 0 1 0 0 64H 1 1 0 0 0 1 1 1 C7H 73 to 90 Manufacturer’s part number 91 to 92 Revision code 93 to 94 Manufacturing date 95 to 98 Assembly serial number 99 to 125 Manufacturer specific data 126 127 Reserved (Intel specification frequency) Reserved (Intel specification /CAS# latency support) Data Sheet E0240E20 (Ver. 2.0) 5 100MHz EBS52UC8APSA Block Diagram /WE /CS1 /CS0 /CS /WE DQM DQMB0 DQ0 to DQ7 N0, N1 I/O0 to I/O7 D0 DQM DQMB1 DQ8 to DQ15 N2, N3 I/O0 to I/O7 DQM DQ16 to DQ23 N4, N5 I/O0 to I/O7 /CS /WE DQM DQMB3 DQ24 to DQ31 N6, N7 I/O0 to I/O7 D3 DQM DQMB5 DQ40 to DQ47 N10, N11 I/O0 to I/O7 DQM DQMB6 DQ48 to DQ55 N12, N13 I/O0 to I/O7 /CS /WE DQM D11 I/O0 to I/O7 DQ56 to DQ63 /RAS /RAS (D0 to D15) /CAS /CAS (D0 to D15) N14, N15 I/O0 to I/O7 BA0, BA1 DQM D5 /CS /WE DQM D6 CKE (D0 to D7) CKE1 CKE (D8 to D15) D14 I/O0 to I/O7 /CS /WE DQM D7 D15 I/O0 to I/O7 SDA SCL SCL A0 U0 A1 BAx (D0 to D15) CKE0 D13 I/O0 to I/O7 Serial PD Ax (D0 to D15) A0 to A12 /CS /WE /CS /WE DQM DQMB7 D12 I/O0 to I/O7 /CS /WE D10 I/O0 to I/O7 D4 I/O0 to I/O7 /CS /WE DQM D2 N8, N9 /CS /WE DQM /CS /WE D9 I/O0 to I/O7 /CS /WE DQMB2 DQ32 to DQ39 /CS /WE DQM D1 DQM DQMB4 D8 I/O0 to I/O7 /CS /WE /CS /WE /CS /WE DQM A2 VSS CLK (D0, D1, D8, D9) CLK0 CLK (D2, D3, D10, D11) CLK (D4, D5, D12, D13) CLK1 CLK (D6, D7, D14, D15) VDD VDD (D0 to D15) C0 to C8 VSS C9 to C32 VSS (D0 to D15) Data Sheet E0240E20 (Ver. 2.0) 6 * D0 to D15 : 256M bits SDRAM U0 : 2k bits EEPROM C0 to C8 : 0.1µF C9 to C32 : 2200pF N0 to N15 : Network resistors (10Ω) SDA EBS52UC8APSA Electrical Specifications • All voltages are referenced to VSS (GND). • After power up, wait more than 100 µs and then, execute power on sequence and CBR (Auto) refresh before proper device operation is achieved. Absolute Maximum Ratings Parameter Symbol Value Unit Voltage on any pin relative to VSS VT –0.5 to VDD + 0.5 (≤ 4.6 (max.)) V Supply voltage relative to VSS VDD –0.5 to +4.6 V Short circuit output current IOS 50 mA Power dissipation PD 16 W Operating temperature TA 0 to +70 °C Storage temperature Tstg –55 to +125 °C Note 1 Notes: 1. SDRAM device specification Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. DC Operating Conditions (TA = 0 to +70°C) (SDRAM device specification) Parameter Symbol min. max. Unit Note Supply voltage VDD 3.0 3.6 V 1 VSS 0 0 V 2 Input high voltage VIH 2.0 VDD + 0.3 V 3 Input low voltage VIL −0.3 0.8 V 4 Notes: 1. 2. 3. 4. The supply voltage with all VDD pins must be on the same level. The supply voltage with all VSS pins must be on the same level. VIH (max.) = VDD + 2.0V for pulse width ≤ 3ns at VDD. VIL (min.) = VSS − 2.0V for pulse width ≤ 3ns at VSS. Data Sheet E0240E20 (Ver. 2.0) 7 EBS52UC8APSA DC Characteristics 1 (TA = 0 to +70°C, VDD = 3.3V ± 0.3V, VSS = 0V) Parameter Operating current Standby current in power down Standby current in non power down Active standby current in power down Active standby current in non power down Symbol Grade max. Unit Test condition Notes Burst length = 1 tRC = tRC (min.) 1, 2, 3 ICC1 -7A/7AL 1280 mA ICC1 -75/75L 1120 mA 48 mA CKE = VIL, tCK = 12ns 6 4 ICC2P ICC2N 320 mA CKE, /CS = VIH, tCK = 12ns ICC3P 64 mA CKE = VIL, tCK = 12ns 1, 2, 6 ICC3N 480 mA CKE, /CS = VIH, tCK = 12ns 1, 2, 4 Burst operating current ICC4 1320 mA tCK = tCK (min.), BL = 4 1, 2, 5 Refresh current ICC5 -7A/7AL 2240 mA tRC = tRC (min.) 3 ICC5 -75/75L 2000 mA 48 mA VIH ≥ VDD – 0.2V VIL ≤ 0.2V 7 16 mA Self refresh current ICC6 Self refresh current (L-version) ICC6 -XXL Notes: 1. ICC depends on output load condition when the device is selected. ICC (max.) is specified at the output open condition 2. One bank operation. 3. Input signals are changed once per one clock. 4. Input signals are changed once per two clocks. 5. Input signals are changed once per four clocks. 6. After power down mode, /CLK operating current. 7. After self refresh mode set, self refresh current. DC Characteristics 2 (TA = 0 to +70°C, VDD = 3.3V ± 0.3V, VSS = 0V) Parameter Symbol min. max. Unit Test condition Input leakage current ILI –10 10 µA 0 ≤ VIN ≤ VDD Output leakage current ILO –10 10 µA 0 ≤ VOUT ≤ VDD DQ = disable Output high voltage VOH 2.4 — V IOH = –4mA Output low voltage VOL — 0.4 V IOL = 4mA Data Sheet E0240E20 (Ver. 2.0) 8 Notes EBS52UC8APSA Pin Capacitance (TA = +25°C, VDD = 3.3V ± 0.3V) Parameter Symbol Input capacitance Data input/output capacitance Pins max. Notes Unit CI1 Address 46 pF CI2 /RAS, /CAS, /WE 50 pF CI3 CKE 60 pF CI4 /CS 30 pF CI5 CLK 32 pF CI6 DQMB 8 pF CI/O1 DQ 12 pF AC Characteristics (TA = 0 to +70°C, VDD = 3.3V ± 0.3V, VSS = 0V) (SDRAM device specification) -7A/7AL -75/75L Parameter Symbol min. max. min. max. Unit Notes System clock cycle time (CL = 2) tCK 7.5 — 10 — ns 1 (CL = 3) tCK 7.5 — 7.5 — ns CLK high pulse width tCH 2.5 — 2.5 — ns 1 CLK low pulse width tCL 2.5 — 2.5 — ns 1 Access time from CLK tAC — 5.4 — 5.4 ns 1, 2 Data-out hold time tOH 2.7 — 2.7 — ns 1, 2 CLK to Data-out low impedance tLZ 1 — 1 — ns 1, 2, 3 CLK to Data-out high impedance tHZ — 5.4 — 5.4 ns 1, 4 Input setup time tSI 1.5 — 1.5 — ns 1 Input hold time tHI 0.8 — 0.8 — ns 1 Ref/Active to Ref/Active command period tRC 60 — 67.5 — ns 1 Active to Precharge command period tRAS 45 120000 45 120000 ns 1 Active command to column command (same bank) tRCD 15 — 20 — ns 1 Precharge to active command period tRP 15 — 20 — ns 1 Write recovery or data-in to precharge lead time tDPL 15 — 15 — ns 1 Last data into active latency tDAL 2CLK + 15ns — 2CLK + 20ns — 1 Active (a) to Active (b) command period tRRD 15 — 15 — ns Transition time (rise and fall) tT 0.5 5 0.5 5 ns Refresh period (8192 refresh cycles) tREF — 64 — 64 ms Notes: 1. 2. 3. 4. AC measurement assumes tT = 0.5ns. Reference level for timing of input signals is 1.4V. Access time is measured at 1.4V. Load condition is CL = 50pF. tLZ (min.) defines the time at which the outputs achieves the low impedance state. tHZ (max.) defines the time at which the outputs achieves the high impedance state. Data Sheet E0240E20 (Ver. 2.0) 9 EBS52UC8APSA Test Conditions • Input and output timing reference levels: 1.4V • Input waveform and output load: See following figures 2.4V 0.4V DQ 2.0V 0.8V CL tT tT Input Waveform and Output Load Relationship Between Frequency and Minimum Latency (SDRAM device specification) Parameter -7A/7AL -75/75L Frequency (MHz) 133 133 tCK (ns) 7.5 7.5 Symbol CL = 2 CL = 3 Notes lRCD 2 3 1 lRC 8 9 1 lRAS 6 6 1 lRP 2 3 1 lDPL 2 2 1 lRRD 2 2 1 Self refresh exit time lSREX 1 1 2 Last data in to active command (Auto precharge, same bank) lDAL 4 5 = [lDPL + lRP] Self refresh exit to command input lSEC 8 9 = [lRC] 3 Precharge command to high impedance lHZP 2 3 Last data out to active command (auto precharge) (same bank) lAPR 1 1 Last data out to precharge (early precharge) lEP –1 –2 Column command to column command lCCD 1 1 Write command to data in latency lWCD 0 0 DQM to data in lDID 0 0 DQM to data out lDOD 2 2 CKE to CLK disable lCLE 1 1 Register set to active command lMRD 2 2 /CS to command disable lCDD 0 0 Power down exit to command input lPEC 1 1 /CAS latency Active command to column command (same bank) Active command to active command (same bank) Active command to precharge command (same bank) Precharge command to active command (same bank) Write recovery or data-in to precharge command (same bank) Active command to active command (different bank) Notes: 1. IRCD to IRRD are recommended value. 2. Be valid [DESL] or [NOP] at next command of self refresh exit. 3. Except [DESL] and [NOP] Data Sheet E0240E20 (Ver. 2.0) 10 EBS52UC8APSA Pin Functions CLK0, CLK1 (input pin): CLK is the master clock input to this pin. The other input signals are referred at CLK rising edge. /CS0, /CS1 (input pin): When /CS is Low, the command input cycle becomes valid. When /CS is High, all inputs are ignored. However, internal operations (bank active, burst operations, etc.) are held. /RAS, /CAS and /WE (input pins): Although these pin names are the same as those of conventional DRAMs, they function in a different way. These pins define operation commands (read, write, etc.) depending on the combination of their voltage levels. For details, refer to the command operation section. A0 to A12 (input pins): Row address (AX0 to AX12) is determined by A0 to A12 level at the bank active command cycle CLK rising edge. Column address (AY0 to AY9) is determined by A0 to A9 level at the read or write command cycle CLK rising edge. And this column address becomes burst access start address. A10 defines the precharge mode. When A10 = High at the precharge command cycle, all banks are precharged. But when A10 = Low at the precharge command cycle, only the bank that is selected by BA0 and BA1 (BA) is precharged. BA0 and BA1 (input pin) BA0 and BA1 are bank select signal (BA). (See Bank Select Signal Table) [Bank Select Signal Table] BA0 BA1 Bank 0 L L Bank 1 H L Bank 2 L H Bank 3 H H Remark: H: VIH. L: VIL. CKE0, CKE1 (input pin): This pin determines whether or not the next CLK is valid. If CKE is High, the next CLK rising edge is valid. If CKE is Low, the next CLK rising edge is invalid. This pin is used for power-down and clock suspend modes. DQMB0 to DQMB7 (input pins): Read operation: If DQMB is High, the output buffer becomes High-Z. If the DQMB is Low, the output buffer becomes Low-Z. Write operation: If DQMB is High, the previous data is held (the new data is not written). If DQMB is Low, the data is written. DQ0 to DQ63 (input/output pins): Data is input to and output from these pins. VDD (power supply pins): 3.3V is applied. VSS (power supply pins): Ground is connected. Detailed Operation Part Refer to the EDS2504APSA/08APSA/16APSA (E0228E). Data Sheet E0240E20 (Ver. 2.0) 11 EBS52UC8APSA Physical Outline Unit:mm 3.80 Max 1 143 20.00 Component area (front) B 23.20 3.30 32.80 4.00 Min 2R3.00 Min 3.20 Min 31.75 (Datum -A-) A 1.00 ± 0.10 4.60 2.50 67.60 ± 0.15 2.10 4.60 4.00 ± 0.10 32.80 144 23.20 2 3.70 Component area (back) 2-R2.00 2.00 Min (Datum -A-) Detail B Detail A (DATUM -A-) 2.5 R0.75 4.00 ± 0.10 2.55 Min 0.25 Max 0.60 ± 0.05 0.80 1.50 ± 0.10 ECA-TS2-0044-02 Data Sheet E0240E20 (Ver. 2.0) 12 EBS52UC8APSA CAUTION FOR HANDLING MEMORY MODULES When handling or inserting memory modules, be sure not to touch any components on the modules, such as the memory ICs, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on these components to prevent damaging them. In particular, do not push module cover or drop the modules in order to protect from mechanical defects, which would be electrical defects. When re-packing memory modules, be sure the modules are not touching each other. Modules in contact with other modules may cause excessive mechanical stress, which may damage the modules. MDE0202 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR MOS DEVICES Exposing the MOS devices to a strong electric field can cause destruction of the gate oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it, when once it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. MOS devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. MOS devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor MOS devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES No connection for CMOS devices input pins can be a cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. The unused pins must be handled in accordance with the related specifications. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Power-on does not necessarily define initial status of MOS devices. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the MOS devices with reset function have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. MOS devices are not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for MOS devices having reset function. CME0107 Data Sheet E0240E20 (Ver. 2.0) 13 EBS52UC8APSA µBGA is registered trademark of Tessera, Inc. The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Elpida Memory, Inc. Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights (including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or third parties by or arising from the use of the products or information listed in this document. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of Elpida Memory, Inc. or others. Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of the customer's equipment shall be done under the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. [Product applications] Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability. However, users are instructed to contact Elpida Memory's sales office before using the product in aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment for life support, or other such application in which especially high quality and reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk of bodily injury. [Product usage] Design your application so that the product is used within the ranges and conditions guaranteed by Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage when the product is used beyond the guaranteed ranges and conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other consequential damage due to the operation of the Elpida Memory, Inc. product. [Usage environment] This product is not designed to be resistant to electromagnetic waves or radiation. This product must be used in a non-condensing environment. If you export the products or technology described in this document that are controlled by the Foreign Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by U.S. export control regulations, or another country's export control laws or regulations, you must follow the necessary procedures in accordance with such laws or regulations. If these products/technology are sold, leased, or transferred to a third party, or a third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations. M01E0107 Data Sheet E0240E20 (Ver. 2.0) 14