Austin AS27C010A-15ECAM 1 meg uveprom uv erasable programmable read-only memory Datasheet

UVEPROM
SMJ27C010A
AS27C010A
Austin Semiconductor, Inc.
1 MEG UVEPROM
PIN ASSIGNMENT
(Top View)
UV Erasable Programmable
Read-Only Memory
32-Pin DIP (J)
(600 MIL)
AVAILABLE AS MILITARY
SPECIFICATIONS
V PP
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
• SMD 5962-89614
• MIL-STD-883
FEATURES
• Organized 131,072 x 8
• Single +5V ±10% power supply
• Operationally compatible with existing megabit EPROMs
• Industry standard 32-pin ceramic dual-in-line package
• All inputs/outputs fully TTL compatible
• 8-bit output for use in microprocessor-based systems
• Very high-speed SNAP! Pulse Programming
• Power-saving CMOS technology
• 3-state output buffers
• 400mV minimum DC noise immunity with standard
TTL loads
• Latchup immunity of 250 mA on all input and output pins
• No pullup resistors required
• Low power dissipation (Vcc = 5.5V)
3Active - 165 mW Worst Case
3Standby - 0.55 mW Worst Case (CMOS-input levels)
OPTIONS
• Timing
120ns access
150ns access
200ns access
• Package(s)
Ceramic DIP (600mils)
Pin Name
A0 - A18
DA0-DQ7
E\
G\
GND
PGM\
VCC
Vcc
PGM\
NC
A14
A13
A8
A9
A11
G\
A10
E\
DQ7
DQ6
DQ5
DQ4
DQ3
Function
Address Inputs
Inputs (programming)/Outputs
Chip Enable
Output Enable
Ground
Program
5V Supply
GENERAL DESCRIPTION
The SMJ27C010A series are 131072 by 8-bit (1048576bit), ultaviolet (UV) light erasable, electrically programmable
read-only memories (EPROMs).
These devices are fabricated using power-saving CMOS
technology for high speed and simple interface with MOS and
bipolar circuits. All inputs (including program data inputs)
can be driven by Series 54 TTL circuits without the use of
external pullup resistors. Each output can drive one Series 54
TTL circuit without external resistors.
The SMJ27C010A EPROM is offered in a ceramic
dual-in-line package (J suffix) designed for insertion in
mounting-hole rows on 15.2mm (600mil) centers.
These EPROMs operate from a single 5V supply (in the
read mode), and therefore, are ideal for use in
microprocessor-based systems. One other 13V supply is
needed for programming. All programming signals are TTL
level. These devices are programmable using the SNAP! Pulse
programming algorithm. The SNAP! Pulse programming
algorithm uses a VPP of 13V and a VCC of 6.5V for a nominal
programming time of thirteen seconds. For programming
outside the system, existing EPROM programmers can be
used. Locations can be programmed singly, in blocks, or at
random.
-12
-15
-20
No. 114
• Operating Temperature Ranges
Military (-55oC to +125oC)
M
For more products and information
please visit our web site at
www.austinsemiconductor.com
SMJ27C010A
AS27C010A
Rev. 2.1 6/05
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VPP
13V Power Supply*
*Only in program mode.
MARKING
J or ECA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
1
UVEPROM
SMJ27C010A
AS27C010A
Austin Semiconductor, Inc.
FUNCTIONAL BLOCK DIAGRAM*
EPROM 131,072 x 8
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
E\
G\
12
11
10
9
8
7
6
5
27
26
23
25
4
28
29
3
2
22
24
0
A
0
131,071
13
14
15
17
18
19
20
21
A
A
A
A
A
A
A
A
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
16
[PWR DWN]
&
EN
* This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. J package illustrated.
OPERATION
The seven modes of operation are listed in Table 1. The read mode requires a single 5V supply. All inputs are TTL level
except for VPP during programming (13V for SNAP! Pulse), and 12V on A9 for signature mode.
TABLE 1. OPERATION MODES
FUNCTION
READ
MODE*
OUTPUT
PROGRAM
SIGNATURE MODE
STANDBY PROGRAMMING VERIFY
DISABLE
INHIBIT
VIL
VIL
VIH
VIL
VIL
VIH
E\
VIL
G\
VIL
VIH
X
VIH
VIL
X
VIL
PGM\
X
X
X
VIL
VIH
X
X
VPP
VCC
VCC
VCC
VPP
VPP
VPP
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
A9
X
X
X
X
X
X
VH**
VH**
A0
X
X
X
X
X
X
VIL
VIH
DQ0-DQ7
Data Out
High-Z
High-Z
Data In
Data Out
High-Z
CODE
MFG
DEVICE
97
D6
* X can be VIL or VIH.
**VH = 12V ± 0.5V
SMJ27C010A
AS27C010A
Rev. 2.1 6/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
2
UVEPROM
SMJ27C010A
AS27C010A
Austin Semiconductor, Inc.
READ/OUTPUT DISABLE
SNAP! PULSE PROGRAMMING
When the outputs of two or more SMJ27C010As are
connected in parallel on the same bus, the output of any
particular device in the circuit can be read with no
interference from competing outputs of the other devices. To
read the output of a single device, a low level signal is applied
to the E\ and G\ pins. All other devices in the circuit should
have their outputs disabled by applying a high-level signal to
one of these pins.
The SMJ27C010A is programmed by using the SNAP! Pulse
programming algorithm as illustrated by the flow chart
(Figure 1). This algorithm programs in a nominal time of
thirteen seconds. Actual programming time varies as a
function of the programmer used.
The SNAP! Pulse programming algorithm uses an initial pulse
of 100 microseconds (µs) followed by a byte verification to
determine when the addressed byte has been successfully
programmed. Up to ten 100µs pulses per byte are provided
before a failure is recognized.
LATCHUP IMMUNITY
Latchup immunity on the SMJ27C010A is a minimum of
250mA on all inputs and outputs. This feature provides latchup
immunity beyond any potential transients at the printed
circuit board level when the devices are interfaced to
industry-standard TTL or MOS logic devices. The input/
output layout approach controls latchup without
compromising performance or packing density.
The programming mode is achieved when V PP = 13V,
VCC= 6.5V, E\ = VIL, and G\ = VIH. Data is presented in
parallel (eight bits) on pins DQ0 through DQ7. Once addresses
and data are stable, PGM\ is pulsed low.
More than one device can be programmed when the devices
are connected in parallel. Locations can be programmed in
any order. When the SNAP! Pulse programming routine is
complete, all bits are verified with VCC = VPP = 5V ± 10%.
POWER DOWN
Active ICC supply current can be reduced from 30mA to 500µA
by applying a high TTL input on E\ and to 100µA by applying a
high CMOS input on E\. In this mode all outputs are in the
high-impedance state.
PROGRAM INHIBIT
Programming can be inhibited by maintaining high level
inputs on the E\ or the PGM\ pins.
ERASURE
Before programming, the SMJ27C010A EPROM is erased
by exposing the chip through the transparent lid to a highintensity ultraviolet light (wavelength 2537 Å). The
recommended minimum exposure dose (UV intensity x
exposure time) is 15-W . s/cm 2 . A typical 12-mW/cm 2,
filterless UV lamp erases the device in 21 minutes. The lamp
should be located about 2.5cm above the chip during erasure.
After erasure, all bits are in the high state. It should be noted
that normal ambient light contains the correct wavelength for
erasure; therefore, when using the SMJ27C010A, the window
should be covered with an opaque label. After erasure (all
bits in logic high state), logic lows are programmed into the
desired locations. A programmed low can be erased only by
ultraviolet light.
PROGRAM VERIFY
Programmed bits can be verified with VPP = 13V when
G\ = VIL, and E\ = VIL, and PGM\ = VIH.
SIGNATURE MODE
The signature mode provides access to a binary code
identifying the manufacturer and type. This mode is activated
when A9 (pin 26) is forced to 12V. Two identifier bytes are
accessed by toggling A0. All other addresses must be held
low. The signature code for these devices is 97D6. A0 low
selects the manufacturer’s code 97 (Hex), and A0 high
selects the device code D6 (Hex), as shown in Table 2.
TABLE 2. SIGNATURE MODES
IDENTIFIER*
PINS
DQ4
DQ3
A0
DQ7
DQ6
DQ5
DQ2
DQ1
DQ0
HEX
MANUFACTURER CODE
VIL
1
0
0
1
0
1
1
1
97
DEVICE CODE
VIH
1
1
0
1
0
1
1
0
D6
* E\ = G\ = VIL, A1 - A8 = VIL, A9 = VH, A10 - A16 = VIL, VPP = VCC.
SMJ27C010A
AS27C010A
Rev. 2.1 6/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
3
UVEPROM
SMJ27C010A
AS27C010A
Austin Semiconductor, Inc.
FIGURE 1. SNAP! PULSE PROGRAMMING FLOW CHART
START
Address = First Location
VCC = 6.5V ± 0.25V, VPP = 13V ± 0.25V
Program
Mode
Program One Pulse = tW = 100µs
Last
Address?
Increment Address
No
Yes
Address = First Location
X=0
Program One Pulse = tW = 100µs
No
Verify
One
Byte
Increment
Address
Fail
X = X+1
Interactive
Mode
Pass
No
X = 10?
Last
Address?
Yes
Yes
Device Failed
VCC = VPP = 5V ± 0.5V
Compare
All Bytes
to Original
Data
Fail
Final
Verification
Pass
Device Passed
SMJ27C010A
AS27C010A
Rev. 2.1 6/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
4
UVEPROM
Austin Semiconductor, Inc.
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage Range, VCC**...........................-0.6V to +7.0V
Supply Voltage Range, Vpp**.........................-0.6V to +14.0V
Input Voltage Range, All inputs except A9**..-0.6V to VCC+1
A9.....-0.6V to +13.5V
Output Voltage Range,
with respect to VSS**..................................-0.6V to VCC +1
Operating Free-air Temperature Range, TA....-55°C to 125°C
Storage Temperature Range, Tstg.....................-65°C to 150°C
SMJ27C010A
AS27C010A
*Stresses greater than those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the
operation section of this specification is not implied.
Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
** All voltage values are with respect to GND.
RECOMMENDED OPERATING CONDITIONS
MIN
4.5
6.25
VCC-0.6
12.75
2
1
VCC
Supply Voltage
Read Mode
SNAP! Pulse programming algorithm
VPP
Supply Voltage
Read Mode
SNAP! Pulse programming algorithm
VIH
High-level DC input voltage
VIL
Low-level DC input voltage
TA
Operating free-air temperature
2
TTL
CMOS
TTL
CMOS
NOM
5
6.5
VCC
13
VCC-0.2
-0.5
-0.5
-55
MAX
5.5
6.75
VCC+0.6
13.25
VCC+0.5
UNIT
V
V
V
V
V
VCC+0.5
0.8
GND+0.2
125
V
V
V
°C
NOTES:
1. VCC must be applied before or at the same time as VPP and removed after or at the same time as VPP. The deivce must not be inserted into or removed from
the board when VPP or VCC is applied.
2. During programming, VPP must be maintained at 13V ± 0.25V.
ELECTRICAL CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE
AND OPERATING FREE-AIR TEMPERATURE
TEST CONDITIONS
PARAMETER
VOH
High-level DC output voltage
VOL
Low-level DC output voltage
MIN
IOH = -20µA
VCC-0.2
IOH = -2.5mA
3.5
MAX
UNIT
V
IOL = 2.1mA
0.4
IOL = 20µA
0.1
V
II
Input current (leakage)
VI = 0V to 5.5V
±1
µA
IO
Output current (leakage)
VO = 0V to VCC
±1
µA
IPP1
VPP supply current
VPP = VCC = 5.5V
10
µA
IPP2
VPP supply current (during program pulse)
VPP = 13V
50
mA
VCC = 5.5V, E\=VIH
500
TTL-Input Level
ICC1
VCC supply current (standby)
ICC2
VCC supply current (active) (output open)
CMOS-Input Level VCC = 5.5V, E\=VCC±0.2V
100
µA
E\=VIL, VCC=5.5V
tcycle = minimum cycle time,
30
mA
1
outputs open
NOTES:
1. Minimum cycle time = maximum access time.
SMJ27C010A
AS27C010A
Rev. 2.1 6/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
5
UVEPROM
SMJ27C010A
AS27C010A
Austin Semiconductor, Inc.
CAPACITANCE OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE, f = 1MHz*
PARAMETER
TEST CONDITIONS
TYP**
MAX
UNIT
CI
Input capacitance
VI = 0V, f = 1MHz
4
8
pF
CO
Output capacitance
VO = 0V, f= 1 MHz
6
10
pF
* Capacitance measurements are made on sample basis only.
** All typical values are at TA = 25°C and nominal voltages.
SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES OF
OPERATING CONDITIONS 1,2
TEST
CONDITIONS
PARAMETER
ta(A)
Access time from address
ta(E)
Access time from chip enable
ten(G)
Output enable time from G\
Output disable time from G\ or E\, whichever
tdis
tv(A)
3
occurs first
Output data valid time after change of
CL = 100pF
1 Series 74
TTL Load,
Input tr < 20ns,
-15
-12
-20
MIN MAX MIN MAX MIN MAX
0
UNIT
120
150
200
ns
120
150
200
ns
55
75
75
ns
60
ns
50
0
60
0
Input tf < 20ns
0
3
address, E\, or G\, whichever occurs first
0
0
ns
NOTES:
1. For all switching characteristics, the input pulse levels are 0.4V to 2.4V. Timing measurements are made at 2V for logic high and 0.8V for logic low.
(Reference AC testing waveform)
2. Common test conditions apply for tdis except during programming.
3. Value calculated from 0.5V delta to measured output level.
SWITCHING CHARACTERISTICS FOR PROGRAMMING: V CC = 6.5V and V PP = 13V
(SNAP! Pulse), T A = 25°C 1
PARAMETER
tdis(G) Disable, Output disable time from G\
MIN
0
MAX
130
UNIT
ns
150
ns
ten(G) Enable, Output enable time from G\
NOTE: 1. For all switching characteristics, the input pulse levels are 0.4V to 2.4V. Timing measurements are made at 2V for logic high and 0.8V for logic low
(reference AC testing waveform).
TIMING REQUIREMENTS FOR PROGRAMMING
tw(PGM)
Pulse duration, program
SNAP! Pulse Programming Algorithm
MIN
TYP
MAX
UNIT
95
100
105
µs
tsu(A)
Setup Time, Address
2
µs
tsu(E)
Setup Time, E\
2
µs
tsu(G)
Setup Time, G\
2
µs
tsu(D)
Setup Time, Data
2
µs
tsu(Vpp)
Setup Time, VPP
2
µs
tsu(Vcc)
Setup Time, VCC
2
µs
th(A)
Hold time, address
0
µs
th(D)
Hold time, data
2
µs
SMJ27C010A
AS27C010A
Rev. 2.1 6/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
6
UVEPROM
Austin Semiconductor, Inc.
SMJ27C010A
AS27C010A
PARAMETER MEASUREMENT INFORMATION
2.08V
RL = 800Ω
Output Under Test
CL = 100 pF1
NOTES:
1. CL includes probe and fixture capacitance.
FIGURE 2. AC TEST OUTPUT LOAD CIRCUIT WAVEFORM
AC testing inputs are driven at 2.4V for logic high and 0.4V for logic low. Timing measurements are made
at 2V for logic high and 0.8V for logic low for both inputs and outputs.
FIGURE 3. READ-CYCLE TIMING
SMJ27C010A
AS27C010A
Rev. 2.1 6/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
7
UVEPROM
Austin Semiconductor, Inc.
SMJ27C010A
AS27C010A
FIGURE 4. PROGRAM-CYCLE TIMING (SNAP! PULSE PROGRAMMING)
* tdis(G) and ten(G) are characteristics of the device but must be accommodated by the programmer.
** 13V VPP and 6.5V VCC for SNAP! Pulse programming.
SMJ27C010A
AS27C010A
Rev. 2.1 6/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
8
UVEPROM
SMJ27C010A
AS27C010A
Austin Semiconductor, Inc.
MECHANICAL DEFINITION*
ASI Case #114 (Package Designator J or ECA)
SMD 5962-89614, Case Outline X
D
A
L
L1
b
e
b1
Pin 1
E
b2
E1
SMD Specifications
SYMBOL
A
b
b1
b2
D
E
e
E1
L1
L
MIN
--0.014
0.045
0.008
--0.510
MAX
0.225
0.026
0.065
0.018
1.680
0.620
0.100 BSC
0.600 BSC
0.125
0.015
0.200
0.070
NOTE: These dimensions are per the SMD. ASI's package dimensional limits
may differ, but they will be within the SMD limits.
*All measurements are in inches.
SMJ27C010A
AS27C010A
Rev. 2.1 6/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
9
UVEPROM
Austin Semiconductor, Inc.
SMJ27C010A
AS27C010A
ORDERING INFORMATION
EXAMPLE: SMJ27C010A-12JM
Device Number Speed ns
Package
Type
Process
SMJ27C010A
-12
J
*
SMJ27C010A
-15
J
*
SMJ27C010A
-20
J
*
EXAMPLE: AS27C010A-15ECAM
Device Number Speed ns
Process
AS27C010A
-12
ECA
*
AS27C010A
-15
ECA
*
AS27C010A
-20
ECA
*
*AVAILABLE PROCESSES
M = Extended Temperature Range
SMJ27C010A
AS27C010A
Rev. 2.1 6/05
Package
Type
-55oC to +125oC
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
10
UVEPROM
Austin Semiconductor, Inc.
SMJ27C010A
AS27C010A
ASI TO DSCC PART NUMBER
CROSS REFERENCE*
ASI Package Designator ECA
TI Part #**
AS27C010A-12ECAM
AS27C010A-15ECAM
AS27C010A-20ECAM
SMD Part #
5962-8961420QYA
5962-8961419QYA
5962-8961417QYA
ASI Package Designator J
TI Part #**
SMJ27C010A-12JM
SMJ27C010A-15JM
SMJ27C010A-20JM
SMD Part #
5962-8961420QXA
5962-8961419QXA
5962-8961417QXA
* ASI part number is for reference only. Orders received referencing the SMD part number will be processed per the SMD.
** Parts are listed on SMD under the old Texas Instruments part number. ASI purchased this product line in November of 1999.
SMJ27C010A
AS27C010A
Rev. 2.1 6/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
11
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