Data Sheet No. PD60225 revA IRMCK203 High Performance Sensorless Motion Control IC Features Product Summary ! Max Clock input ! ! ! ! ! ! ! ! ! ! ! ! ! Complete Sensorless control IC for Permanent Magnet AC motors No phase voltage feedback sensing required Sinusoidal current waveform with Synchronously Rotating Frame closed loop current control High starting torque and smooth speed ramping Direct interface to IR2175 current sensing high voltage IC Auto Retry at startup with configurable starting torque Versatile loss minimization Space Vector PWM Serial communication interface (RS232C, RS422, SPI) 2 I C serial interface to 1k bit serial EEPROM for parameter storage for stand alone operation Phase loss/Overcurrent/Overvoltage protection 7-bit discrete I/O for sequencing and status monitor Integrated brake IGBT control for dc bus voltage limitation TM ServoDesigner tool for easy operation Parallel interface for microcontroller expansion Sensorless control computation time Speed operating range (typical) 33.3 MHz 10 µsec max 5% to 100% Speed control resolution 15 bit full range Adjustable current limit at start-up 15 bit full range Programmable retry on start-up max 16 trials Over current, speed, phase loss, dc bus fault protection PWM carrier frequency 16 bit/33MHz IR2175 Current feedback data resolution 10bit Inverter leg current sensing (optional) 12bit RS232C speed Optional RS422 communication Max SPI Clock up to 57.6 Kbps up to 1 Mbps 8 MHz Package: QFP80 Description IRMCK203 is a high performance digital motion control IC for Sensorless AC permanent magnet motor application. Control is based on closed loop vector control for sinusoidal Back EMF motors. With IRMCK203, the users can readily build a high performance Sensorless drive system without any programming effort and minimum start-up time. Built-in unique start-up and ramping algorithm enables wide application. This IC is versatile enough that the users can configure and optimize system performance according to the needs of each application. With International Rectifier iMOTION products including high voltage ICs such as IR2175 current sensing IC and IRAM series of Intelligent IGBT module in combination with IRMCK203, the end result is a fully optimized system with reduced electronics component counts. This simplifies the design for low cost Sensorless drive modules. IRMCK203 can be easily adapted to various permanent magnet motors through ServoDesignerTM tool, which is the fully configurable graphic user interface tool. This document is the property of International Rectifier and may not be copied or distributed without expressed consent. IRMCK203 Overview IRMCK203 is a new International Rectifier integrated circuit device designed for one-chip solution for complete closed loop current and velocity control of a high performance Sensorless drive for PM motors. Unlike a traditional microcontroller or DSP, IRMCK203 does not require any programming to complete complex Sensorless algorithm development. Combined with International Rectifier's high voltage gate drive and current sensing IC, the user can implement complete speed control of PM motors with minimum component count and virtually no design effort. In addition to Sensorless closed loop speed control operation, features such as Start-up retry, Phase Loss detection, Low Loss PWM, Regeneration Braking control and various drive protections are all implemented inside IRMCK203. Analog and digital I/Os can also be configured. Host communication logic contains Asynchronous Communication Interface for RS232C or RS422 communication interface, a fast slave SPI interface and an 8 bit wide Host Parallel Interface. All communication ports have the same access capability to the host register set. The users can write to, and read from the predefined registers to configure and monitor the drive through these communication ports. IRMCK203 Main functions • • • • • • • • • • • • • • • • • • • Complete closed loop current control based on Synchronously Rotating Frame Field Orientation (using Rotor Angle Observer) Closed loop velocity control based on estimated speed Configurable parameters (PI controller gains, PI output limit range, current feedback scaling, PWM carrier frequency) provide adaptation to various PM motors Built-in Sensorless control logic for start-up, ramping, and running conditions Auto Retry (programmable) on start-up with configurable torque current limit Analog reference input (can be used for speed reference) RS232C/RS422 reference input Full dynamic braking control for DC bus voltage limitation Cycle-by-cycle on/off Control for Brake IGBT Loss minimization Space Vector PWM with deadtime insertion Build-in two IR2175 current sensing IC interfaces Phase Loss, Overcurrent (GATEKILL input), Overvoltage, Undervoltage, Overspeed protection Low cost serial 12bit A/D interface with multiplexer and sample/hold circuit Optional Inverter Leg (low side) current sensing in lieu of IR2175 IC 4 channel analog output (PWM) Local EEPROM for startup initialization of internal data/parameters through host register interface AT24C01A, 128X8 Versatile host communication interface RS232C or RS422 host interface Fast SPI slave host interface with multi-drop capability Parallel Host interface (total 12 pins) Multiplexed data/address bus Address Enable RD/WR Discrete I/Os for Standalone mode operation STARTSTOP (Input) ESTOP (Input) This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 2 IRMCK203 DIR (Input) FLTCLR (Input) FAULT (Output) SYNC (Output) REDLED (Output) GREENLED (Output) This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 3 IRMCK203 Table of Contents Overview........................................................................................................................................................................... 2 IRMCK203 Main functions .............................................................................................................................................. 2 IRMCK203 Block Diagrams............................................................................................................................................. 7 Basic Block Diagram .................................................................................................................................................... 7 Input/Output of IRMCK203.......................................................................................................................................... 8 Application Connections............................................................................................................................................. 12 IC Crystal Clock Circuitry .......................................................................................................................................... 13 PLL Clock Circuitry.................................................................................................................................................... 14 Low Pass Filter............................................................................................................................................................ 14 Implementing the Low Pass Filter Shield ............................................................................................................... 15 Cp Rp and Cs Component Values........................................................................................................................... 15 PLL Reset.................................................................................................................................................................... 15 DC Electrical Characteristics and Operating Conditions ................................................................................................ 16 Absolute Maximum Ratings........................................................................................................................................ 16 Recommended Operating Conditions ......................................................................................................................... 16 DC Characteristics ...................................................................................................................................................... 17 Common Quiescent and Leakage Current .................................................................................................................. 17 Input Characteristics – Non Schmitt Inputs ................................................................................................................ 17 Input Characteristics – Schmitt Inputs ........................................................................................................................ 17 Output Characteristics................................................................................................................................................. 17 Output Characteristics OSC2CLK .............................................................................................................................. 18 Pin and I/O Characteristic Table ................................................................................................................................. 19 Power Consumption .................................................................................................................................................... 21 AC Electrical Characteristics and Operating Conditions ................................................................................................ 22 System Level AC Characteristics................................................................................................................................ 22 Sync Pulse to Sync Pulse Timing............................................................................................................................ 22 FAULT and REDLED Response to GATEKILL ................................................................................................... 23 Host Interface AC Characteristics............................................................................................................................... 24 SPI Timing .............................................................................................................................................................. 24 Host Parallel Timing ................................................................................................................................................... 25 Host Parallel Read Cycle......................................................................................................................................... 25 Host Parallel Write Cycle........................................................................................................................................ 26 Discrete I/O Electrical Characteristics ........................................................................................................................ 27 Motion Peripheral Electrical Characteristics............................................................................................................... 28 PWM Electrical Characteristics .............................................................................................................................. 28 IR2175 Interface ..................................................................................................................................................... 28 Analog Interface Electrical Characteristics................................................................................................................. 29 ADC Timing............................................................................................................................................................ 29 PLL Interface Electrical Characteristics...................................................................................................................... 30 Appendix A Host Register Map .................................................................................................................................. 31 Register Access ........................................................................................................................................................... 31 Host Parallel Access................................................................................................................................................ 31 SPI Register Access ................................................................................................................................................ 31 RS-232 Register Access.......................................................................................................................................... 31 Write Register Definitions .......................................................................................................................................... 36 PwmConfig Register Group (Write Registers) ....................................................................................................... 36 CurrentFeedbackConfig Register Group (Write Registers) .................................................................................... 37 SystemControl Register Group (Write Registers)................................................................................................... 38 TorqueLoopConfig Register Group (Write Registers)............................................................................................ 38 VelocityControl Register Group (Write Registers)................................................................................................. 39 This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 4 IRMCK203 FaultControl Register Group (Write Registers) ...................................................................................................... 40 SystemConfig Register Group (Write Registers).................................................................................................... 41 EepromControl Registers (Write Registers)............................................................................................................ 42 ClosedLoopAngleEstimator Registers (Write Registers)........................................................................................ 43 OpenLoopAngleEstimator Registers (Write Registers) .......................................................................................... 44 StartupAngleEstimator Registers (Write Registers)................................................................................................ 44 StartupRetrial Registers (Write Registers) .............................................................................................................. 45 PhaseLossDetect Registers (Write Registers) ......................................................................................................... 47 D/AConverter Registers (Write Registers) ............................................................................................................. 47 Factory Test Register (Write Register) ................................................................................................................... 48 Read Register Definitions ........................................................................................................................................... 49 SystemStatus Register Group (Read Registers) ...................................................................................................... 49 DcBusVoltage Register Group (Read Registers) .................................................................................................... 49 FocDiagnosticData Register Group (Read Registers)............................................................................................. 50 FaultStatus Register Group (Read Registers).......................................................................................................... 51 VelocityStatus Register Group (Read Registers) .................................................................................................... 52 CurrentFeedbackOffset Register Group (Read Registers) ...................................................................................... 53 EepromStatus Registers (Read Registers)............................................................................................................... 53 FOCDiagnosticDataSupplement Register Group (Read Registers) ........................................................................ 54 ProductIdentification Registers (Read Registers) ................................................................................................... 55 Factory Register (Read Register) ............................................................................................................................ 55 Appendix B Package ................................................................................................................................................... 56 This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 5 IRMCK203 Table of Figures Figure 1: IRMCS2031 Simplified Blocks......................................................................................................................... 7 Figure 2: Input/Output of IRMCK203 .............................................................................................................................. 8 Figure 3: Application Connection of IRMCK203........................................................................................................... 12 Figure 4: Oscillator Circuit ............................................................................................................................................. 13 Figure 5: PLL Low Pass Filter Shielding........................................................................................................................ 14 Figure 6: System Level SYNC To SYNC Timing .......................................................................................................... 22 Figure 7: FAULT and REDLED Response to GATEKILL............................................................................................ 23 Figure 8: SPI Timing....................................................................................................................................................... 24 Figure 9: Host Parallel Read Cycle ................................................................................................................................. 25 Figure 10: Host Parallel Write Cycle .............................................................................................................................. 26 Figure 11: Discrete I/O Timing....................................................................................................................................... 27 Figure 12: PWM Timing................................................................................................................................................. 28 Figure 13: IR2175 Interface............................................................................................................................................ 28 Figure 14: Top Level ADC Timing ................................................................................................................................ 29 Table of Tables Table 1: Typical Values for the Clock Circuit ................................................................................................................ 13 Table 2: PLL Test Pin Assignments................................................................................................................................ 14 Table 3: PLL Low Pass Filter Values ............................................................................................................................. 15 Table 4: Absolute Maximum Ratings ............................................................................................................................. 16 Table 5: Recommended Operating Conditions ............................................................................................................... 16 Table 6: DC Characteristics ............................................................................................................................................ 17 Table 7: Non Schmitt Input Characteristics .................................................................................................................... 17 Table 8: Schmitt Input Characteristics ............................................................................................................................ 17 Table 9: Output Characteristics....................................................................................................................................... 17 Table 10: Output Characteristics OSC2CLK .................................................................................................................. 18 Table 11: Pin and I/O Characteristics ............................................................................................................................. 21 Table 12: IRMCK203 Power Consumption.................................................................................................................... 21 Table 13: System Level SYNC to SYNC Timing........................................................................................................... 22 Table 14: FAULT and REDLED Response to GATEKILL ........................................................................................... 23 Table 15: SPI Timing ...................................................................................................................................................... 24 Table 16: Host Parallel Read Cycle Timing.................................................................................................................... 25 Table 17: Host Parallel Write Cycle Timing................................................................................................................... 26 This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 6 IRMCK203 IRMCK203 Block Diagrams Basic Block Diagram Figure 1 shows the basic block diagram of the IRMCK203 surrounded by International Rectifiers’ ICs. Host communications are provided over SPI, RS-232C or Host parallel ports. Two current sensing ICs (IR2175) and a three phase high voltage gate drive typically implement the high voltage / current interface between the IRMCK203 IC and motor. The IRMCK203 can operate in a “stand-alone” mode without the host controller. utilized to load motor-specific parameters into the IC. A serial EEPROM would be AC Power Analog Monitor IRMCS2031 EEPROM Analog Speed Reference IRMCK203 select A/D interface 4 channel D/A Host Controller SPI Interface Parallel Interface RAMP + + Host Register Interface jθ - - e + Space Vector PWM FAULT Monitoring Registers e 2/3 DC bus feedback Plug-N-DriveTM IGBT module IRAMY20UP60A Rotor Angle/ speed Estimator jθ MUX Dead time - Configuration Registers A/D BRAKE IR2136 RS232C or RS422 DC bus dynamic brake control Period/Duty counters IR2175 Period/Duty counters IR2175 Motor Figure 1: IRMCS2031 Simplified Blocks Configurable parameters are provided to tailor design to various applications (motor and load). These configurable parameters can be modified via the host register interface through the communication interface. In the IRMCK203 product, a design spread sheet is provided to aid the user for ease of drive start-up, the spread sheet will input high level application data such as motor name plate information, max speed, current limit, speed and current regulator bandwidth, base on this information the program will generate the required configurable parameters. Detail on Drive commissioning is described in the IRMCK203 Application Developer’s Guide. All logic and algorithms are pre-programmed, and the user does not need to make any effort to develop code, alleviating the tedious design process. If needed, the user can configure the drive to tailor the control per specific This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 7 IRMCK203 needs to meet the required specification. This configuration can be easily done by accessing the host register interface through the communication interface. Input/Output of IRMCK203 The I/O signals are shown in Figure 2. The interface signals are divided into sub-groups. assignment, please refer to appendix (Pin definition). For detailed pin OSC1CLK Crystal OSC2CLK PWMUH BYPASSMODE PWMUL PWMVH PLLTEST XPD PWMVL PWMWH CHGO PWMWL AVDD LPVSS BRAKE FLTCLROUT VSSHC GATEKILL PLL Clock Control SPI Interface SPICLK SPIMISO IFB[0-1] SPIMOSI SPICSN DAC[0-3] RS232C Interface Parallel Interface TX RX BAUDSEL IRMCK203 PWM gate signal Interface IR2175 Interface D/A Interface (PWM output) ADCLK ADOUT ADCONVST HPD[0-7] HPOEN ADMUX[0-2] HPWEN HPCSN RESSAMPLE A/D Interface HPA Discrete I/O STARTSTOP ESTOP FLTCLR SYNC FAULT DIR RESETN Serial EEPROM System Reset SCA SCL LED/Status REDLED GREENLED Figure 2: Input/Output of IRMCK203 This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 8 IRMCK203 Host Interface Group SPICLK I SPIMISO SPIMOSI SPICSN HPOEN O I I I Low (L) / High (H) True Asserted Positive edge sensitive L L HPWEN I L I/O - HPA I H HPCSN TX RX I O I L - BAUDSEL[1:0] I H SYNC O L CLK1XOUT O - Signal HPD [7:0] Input (I) / Output (O) Function SPI clock Master input and slave output Master output and slave input SPI chip select Parallel data output enable Parallel data write cycle identification Parallel data Parallel data address cycle identification Chip select RS-232 data out RS-232 data in RS-232 baud rate: 00 = 19.3K bps; 01 = 38.4K bps 10 = 57.6K bps; 11 = 1.031250M bps Start of PWM cycle 33.333 MHz output of PLL. This signal has no phase relationship with the OSC1CLK or OSC2CLK inputs. Discrete I/O Group Input (I) / Output (O) Low (L) / High (H) True Asserted STARTSTOP I H DIR I H FAULTCLR I H ESTOP I H PWEN SYNC FAULT O O O H H H Signal Function Start / Stop command edge sensitive Forward/Reverse Direction command, level sensitive Fault Clear Emergency Stop, state sensitive PWM enable/disable state SYNC pulse Fault state This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 9 IRMCK203 Motion Peripheral Group Signal Input (I) / Output (O) PWMUH PWMUL PWMVH PWHVL PWMWH PWMWL BRAKE O O O O O O O GATEKILL I IFB0 IFB1 I I Low (L) / High (H) True Asserted - L Varies, Based on Write Register 0x0C Bit 7 - Function PWM phase U high side PWM phase U low side PWM phase V high side PWM phase V low side PWM phase W high side PWM phase W low side IGBT gate When asserted, negates all six PWM signals, host writeable Channel 0 (phase V) Channel 1 (phase W) Analog Interface Group Signal Input (I) / Output (O) ADCLK O ADOUT DAC [3:0] ADCONVST I O O RESSAMPLE O ADMUX0 ADMUX1 O O Low (L) / High (H) True Asserted Negative Edge Sensitive L H H Function Clock to ADS7818 Serial data from ADS7818 Diagnostic DAC Conversion start to ADS7818 Sample/hold control signal channel 0 A/D converter Analog input MUX select Analog input MUX select PLL Interface Group XPD RESETN I I Low (L) / High (H) True Asserted L L BYPASSCLK I H BYPASSMODE I H OSC1CLK OSC2CLK I I - PLLTEST I H I/O I/O - Signal CHGO LPVSS Input (I) / Output (O) Function PLL reset Digital logic reset Internal test pin – force to logic low Internal test pin – force to logic low 33.33 MHz crystal input 33.33 MHz crystal input Internal test pin – force to logic low Low pass filter Low pass filter ground This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 10 IRMCK203 Miscellaneous Group Signal Input (I) / Output (O) SCA I/O SCL O GREENLED REDLED O O Low (L) / High (H) True Asserted Positive Edge Sensitive H H Function EEPROM data EEPROM clock LED signal LED signal Power Supply Group Signal LVDD AVCC MVDD VSSHC Function IC Logic +3.3V power supply IC Analog +3.3V power supply IC Phase +3.3V Lock Loop power supply IC Phase Lock Loop power supply return This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 11 IRMCK203 Application Connections Typical application connection is shown in Figure 3. In order to complete a Sensorless drive control, all necessary components are shown in connection to IRMCK203. Although this is a typical hardware configuration, users can customize the design without the effort of modifying code. OSC1CLK 33MHz Crystal System Clock OSC2CLK SPI Interface TX RX MAX232A To PC PWMUH PWMUL PWMVH PWMVL PWMWH PWMWL BRAKE SPICLK SPIMISO SPIMOSI SPICSN Gate Drive & IGBTs GATEKILL FAULTCLR BAUDSEL[1:0] Optional microcontroller 8051 uP HPD[0-7] HPOEN,HPWEN DIR ESTOP FLTCLR SYNC FAULT LED Serial EEPROM Bi-Color LED AT24C01A SCA SCL IRMCK203 Digital Control IC PO Isolator STARTSTOP Discrete I/O switches Motor Phase Shunt 5V IFB0 HPCSN,HPA IR2175 IFB1 Isolator Motor Current Sensing Motor Phase Shunt 5V PO IR2175 Analog Speed Reference ADCLK ADOUT ADCONVST DC bus voltage ADS7818 4051 REDLED GREENLED ADMUX0 2-leg shunt current sensing (optional) ADMUX1 ADMUX2 RESSAMPLE DAC0 DAC1 Analog Output DAC2 DAC3 CHGO BYPASSCLK BYPASSMODE PLLTEST PLL Low Pass FIlter LPVSS Figure 3: Application Connection of IRMCK203 This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 12 IRMCK203 IC Crystal Clock Circuitry The clock input to the IC is a 33.33 MHz crystal oscillator. required to terminate the crystal to the IC. Two shunt capacitors and a possibly a series resistor is The values of the R/C will vary based on actual PCB attributes, and some empirical analysis may be required to get the PLL to start oscillating. Once oscillating, verify that the signal waveform at the OSC1CLK and OSC2CLK pins are sinusoidal rather than trapezoidal. Refer to Table 1 for suggested R/C values. Most low-cost crystals can be used in this application. An example is a Citizen Part number CM309B33.333MABJT available from Digi-Key under part number 300-4160-1-ND. OSC1CLK IRMCK203 C1 XTAL R2 OSC2CLK R1 C2 Figure 4: Oscillator Circuit Component XTAL C1 C2 R1 R2 Value 33.33 5 5 0 3.9K Units MHz pF pF Ω Ω Table 1: Typical Values for the Clock Circuit This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 13 IRMCK203 PLL Clock Circuitry The IRMCK203 contains a PLL that creates a 2X and 4X clock from the input 33.33 MHz input clock pin. are a number of pins on the IC allocated for factory testing purposes that need to be connected to VSS. Table 2 shows required PCB signal connections for these pins. Pin Number 1 7 There PCB Connection VSS VSS Table 2: PLL Test Pin Assignments Low Pass Filter The low pass filter for this PLL resides between the CHGO and LPVSS pins. required to implement this filter: Cp, Rp and Cs. Three passive components are Figure 5 shows how to place these components around the IC. A shield should be placed below Rp, Cp and Cs made out of copper etch. S h ie ld e d b y L P V S S CHGO Rp IR M C K 2 0 3 Cs Cp LPVSS Figure 5: PLL Low Pass Filter Shielding This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 14 IRMCK203 Implementing the Low Pass Filter Shield Make all connections between CHGO, Rp, Cp, Cs and LPVSS as short as possible. Create the underlining shield by “copper filling” a larger area in the signal plane of the PCB. Connect this shield to the LPVSS pin of the IC. Do not connect this shield to signal ground (VSS). Cp Rp and Cs Component Values For a typical FR4 PCB, the values of the passive components are shown in Table 3. Component Rp Cp Cs Value 3.9K 1000 Not Installed Units Ω pF - Table 3: PLL Low Pass Filter Values PLL Reset There are two reset pins on the IC, XPD and RESETN both low true. XPD holds the PLL circuitry in reset when low. Upon XPD going high, the PLL circuitry begins to lock onto the 33.33 MHz clock input. The PLL circuit may take up to 1 msec to become stable. RESETN asserted low holds the internal DSP logic in reset. Upon RESETN going high, the IC digital logic becomes active. RESET should be held low during and at least 1 ms after XPD goes high false to hold the internal logic in reset while the PLL becomes stable. This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 15 IRMCK203 DC Electrical Characteristics and Operating Conditions Absolute Maximum Ratings Note: VSS = 0 Volt PARAMETER SYMBOL LIMITS NOTE VSS-0.3 to 4.0 UNIT S V Power Supply Voltage Input Voltage VDD VI VSS-0.3 to VDD+0.5 V Input Voltage VI VSS-0.3 to 7 V Non 5 Volt Tolerant Pins (Table 11) Only on 5 Volt Tolerant Pins (Table 11) Output Voltage Output Current per Pin Storage Temperature VO IOUT VSS-0.3 to VDD+0.5 +/- 30 V mA Tstg -65 to 150 °C Table 4: Absolute Maximum Ratings Recommended Operating Conditions Note: VSS = 0 Volt PARAMETER Power Supply Voltage Input Voltage SYMBOL VDD MIN 3.0 TYP 3.3 MAX 3.6 UNITS V NOTE VI VSS - VDD V Input Voltage VI VSS - 5.5 V Ambient Temperature Ta -40 - 85 Non 5 Volt Tolerant Pins (Table 11) Only on 5 Volt Tolerant Pins (Table 11) Note 2 °C Table 5: Recommended Operating Conditions Notes: 2. The ambient temperature range is recommended for Tj= -40 to 125 °C This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 16 IRMCK203 DC Characteristics Common Quiescent and Leakage Current PARAMETER Quiescent Current SYMBOL IDDS Input Leakage Current ILI CONDITIONS VI=VDD or VSS VDD=MAX IOH=IOL=0 Ta=Tj=85°C VDD=MAX VIH=VDD VIL=VSS MIN - TYP - MAX .35 UNITS uA -1 - 1 uA Table 6: DC Characteristics Input Characteristics – Non Schmitt Inputs PARAMETER High Level Input Voltage Low Level Input Voltage SYMBOL VIH1 CONDITIONS VDD=MAX MIN 2.0 TYP - MAX - UNITS V VIL1 VDD=MIN - - 0.8 V Table 7: Non Schmitt Input Characteristics Input Characteristics – Schmitt Inputs PARAMETER High Level Input Voltage Low Level Input Voltage Hysteresis Voltage SYMBOL VT1+ CONDITIONS VDD=MAX MIN 1.1 TYP - MAX 2.4 UNITS V VT1- VDD=MIN 0.6 - 1.8 V VH1 VDD=MIN 0.1 - - V Table 8: Schmitt Input Characteristics Output Characteristics PARAMETER High Level Output Voltage Low Level Output Voltage SYMBOL VOH3 VOL3 CONDITIONS VDD=MIN IOH=-12mA VDD=MIN IOH = 12mA MIN VDD - 0.4 TYP - MAX - UNITS V - - VSS + 0.4 V Table 9: Output Characteristics This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 17 IRMCK203 Output Characteristics OSC2CLK PARAMETER High Level Output Voltage Low Level Output Voltage SYMBOL LVOH LVOL CONDITIONS VDD=MIN IOH=-530uA VDD=MIN IOH = 730uA MIN VDD - 0.4 TYP - MAX - UNITS V - - VSS + 0.4 V Table 10: Output Characteristics OSC2CLK This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 18 IRMCK203 Pin and I/O Characteristic Table Pin Number Pin Name 1 BYPASSMODE 2 3 4 5 6 7 FLTCLROUT OSC1CLK LVDD OSC2CLK VSS PLLTEST 8 9 10 11 12 13 14 15 XPD VSSHC MVDD VSSHC AVDD CHGO LPVSS DIR 16 RESETN 17 18 19 20 21 22 23 24 25 26 27 28 29 30 SPICSN REDLED GREENLED VSS PWMWL PWMWH PWMVL LVDD PWMVH PWMUL VSS PWMUH BRAKE BAUDSEL0 31 GATEKILL 32 33 34 35 36 37 38 39 40 IFB1 IFB2 LVDD CLK1XOUT VSS SPIMOSI SPIMISO SPICLK TX INTERNAL IC RESISTOR TERMINATION 40K-240K Pull Down 20K-120K Pull Down 20K – 120K Pull Down 20K -120K Pull Up 20K – 120K Pull Down 20K -120K Pull Up Pin Type I 5.50 VOLT TOLERANT INPUT - INPUT DC CHARACTERISTIC TABLE Table 8 OUTPUT DC CHARACTERISTIC TABLE - O I P O P I - Table 7 - Table 9 Table 7 Table 10 - I P P P P O P I YES Table 7 Table 8 - I - Table 8 - I O O P O O O P O O P O O I YES Table 8 Table 8 Table 9 Table 9 Table 9 Table 9 Table 9 Table 9 Table 9 Table 9 Table 9 I - Table 8 - I I P O P I O I O YES YES YES YES - Table 8 Table 8 - Table 9 Table 8 Table 8 - Table 9 Table 9 This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 19 IRMCK203 Pin Number Pin Name 41 42 RX BAUDSEL1 43 44 45 46 47 48 49 50 51 52 53 54 LVDD ADMUX0 VSS ADMUX1 ADMUX2 RESSAMPLE ADCONVST ADCLK ADOUT SYNC FAULT STARTSTOP 55 ESTOP 56 FLTCLR 57 58 59 60 61 62 63 64 LVDD PWMEN DAC3 VSS DAC2 DAC1 DAC0 HPD0 65 HPD1 66 HPD2 67 68 VDD HPD3 69 HPD4 70 71 VSS HPD5 72 HPD6 73 HPD7 74 75 76 77 HPOEN HPWEN HPA HPCSN INTERNAL IC RESISTOR TERMINATION 20K -120K Pull Up 20K -120K Pull Down 20K -120K Pull Down 20K -120K Pull Down 20K -120K Pull Down 20K -120K Pull Down 20K -120K Pull Down 20K -120K Pull Down 20K -120K Pull Down 20K -120K Pull Down 20K -120K Pull Down 20K -120K Pull Down Pin Type I I 5.50 VOLT TOLERANT INPUT YES YES INPUT DC CHARACTERISTIC TABLE Table 8 Table 8 OUTPUT DC CHARACTERISTIC TABLE - P O P O O O O O I O O I YES YES Table 8 Table 8 Table 9 Table 9 Table 9 Table 9 Table 9 Table 9 Table 9 Table 9 - I YES Table 8 - I YES Table 8 - P O O P O O O B - Table 7 Table 9 Table 9 Table 9 Table 9 Table 9 Table 9 B - Table 7 Table 9 B - Table 7 Table 9 P B - Table 7 Table 9 B - Table 7 Table 9 P B - Table 7 Table 9 B - Table 7 Table 9 B - Table 7 Table 9 I I I I YES YES YES YES Table 8 Table 8 Table 8 Table 8 - This document is the property of International Rectifier and may not be copied or distributed without expressed consent. - 20 IRMCK203 Pin Number 78 79 80 Pin Name VSS SCL SDA INTERNAL IC RESISTOR TERMINATION 20K -120K Pull Up Pin Type P O B 5.50 VOLT TOLERANT INPUT - INPUT DC CHARACTERISTIC TABLE Table 7 OUTPUT DC CHARACTERISTIC TABLE Table 9 Table 9 Table 11: Pin and I/O Characteristics Power Consumption PARAMETER PTotal SYMBOL PTOTAL CONDITIONS VDD=3.3V MIN - TYP 1.2 MAX - UNITS WATT Table 12: IRMCK203 Power Consumption This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 21 IRMCK203 AC Electrical Characteristics and Operating Conditions System Level AC Characteristics Sync Pulse to Sync Pulse Timing t5 SYNC Current Feedback sampling Angle Estimation t1 t2 t3 Closed loop current control t4 Space Vector PWM Figure 6: System Level SYNC To SYNC Timing SYMBOL t1 t2 t3 t4 t5 DESCRIPTION Current Feedback Sample Delay Using IR2175 for current feedback Using Leg Shunts for current feedback (optional) Rotor Angle Estimation Time Current and velocity control Space Vector PWM calculation time Total SYNC to SYNC minimum time TIME (µsec) 4.3 2.0 4.9 3.1 2.3 14.6 (max) Table 13: System Level SYNC to SYNC Timing This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 22 IRMCK203 FAULT and REDLED Response to GATEKILL t5 GATEKILL t3 t1 FAULT t2 REDLED t4 FLTCLR Figure 7: FAULT and REDLED Response to GATEKILL SYMBOL t1 t2 t3 t4 t5 DESCRIPTION FAULT Response to GATEKILL REDLED Response to GATEKILL FAULT Response to FLTCLR REDLED Response to FLTCLR GATEKILL Pulse Width MIN TYP 640 640 UNITS ns ns 190 190 ns ns ns 485 Table 14: FAULT and REDLED Response to GATEKILL This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 23 IRMCK203 Host Interface AC Characteristics SPI Timing tSCLK SCLK tCSS CS tMOSIS MOSI MISO tMISO tMISOZ Figure 8: SPI Timing SYMBOL fSCLK tSCLK tCSS tMOSIS tMISO tMIOZ DESCRIPTION SPI Clock Frequency SPI Clock Period CS to SCLK high Setup MOSI to SCLK low Setup SCLK to MISO Valid CS to MISO High Impedance MIN 125 20 20 73 15 MAX 8 35 UNITS MHz ns ns ns ns ns Table 15: SPI Timing This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 24 IRMCK203 Host Parallel Timing Host Parallel Read Cycle tHPCSN HPCSN HPWEN tHPWENS HPA tHPAS tHPA tAHPD HPD[7:0] VALID tHPZD tHPOENS tHPDZ tHPOEN HPOEN Figure 9: Host Parallel Read Cycle SYMBOL DESCRIPTION tHPCSN tHPWENS tHPAS tAHPD THPZD tHPDZ tHPOENS tHPOEN HPCSN Period HPWENS Setup HPA Setup HPD[7:0] Access HPD[7:0] Active HPD[7:0] High Impedance HPOEN Setup HPOEN Period MIN 70 40 40 60 0 0 40 70 MAX 105 9 6 UNIT S ns ns ns ns ns ns ns ns NOTE Note 3 Note 3 Table 16: Host Parallel Read Cycle Timing Note: 3. HPOEN, HPWEN must be stable before the high to low transition of HPCSN. This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 25 IRMCK203 Host Parallel Write Cycle tHPCSN HPCSN tHPWENS tHPWEN HPWEN tHPAS tHPA tHPD[7:0] HPD[7:0] tHPD[7:0]S tHPOEN HPOEN tHPOENS Figure 10: Host Parallel Write Cycle SYMBOL tHPCSN tHPWENS tHPWEN tHPAS tHPA tHPD[7:0] tHPOENS tHPOEN DESCRIPTION HPCSN Period HPWENS Setup HPWEN Period HPA Setup HPA Period HPD[7:0] Setup HPOEN Setup HPOEN Period MIN 70 40 70 -10 70 -10 40 70 MAX UNITS ns ns ns ns ns ns ns ns NOTE Note 4 Table 17: Host Parallel Write Cycle Timing Note: 4. HPOEN must be asserted high while HPCSN low during a Host Parallel Write Cycle. This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 26 IRMCK203 Discrete I/O Electrical Characteristics START/STOP FLTCLR tL Figure 11: Discrete I/O Timing SYMBOL tL DESCRIPTION Pulse Width STARTSTOP Pulse Width FLTCLR MIN 100 1 MAX UNITS ns us Table 15: Discrete I/O Timing This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 27 IRMCK203 Motion Peripheral Electrical Characteristics PWM Electrical Characteristics tDEADTIMERESOLUTION tDEADTIMERESOLUTION SYNC PWMUH PWMUL PWMVH PWMVL PWMWH PWMWL Figure 12: PWM Timing SYMBOL tDEADTIMERESOLUTION DESCRIPTION Deadtime Insertion Logic Resolution 30 UNITS ns Table 16: PWM Timing IR2175 Interface tIFB tIFBH IFB0 IFB1 tIFBL Figure 13: IR2175 Interface SYMBOL fIFB tIFB tIBH tIFBH DESCRIPTION Current Feedback Input Frequency Current Feedback Period Current Feedback High Pulse Width Current Feedback Low Pulse Width MIN 95 10.52 500 ns 500 ns MAX 165 6.06 10 us 10 us UNITS kHz us Table 17: IR2175 Interface This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 28 Analog Interface Electrical Characteristics ADC Timing System Level Timing The IRMCK203 contains logic to drive an ADC Converter, Analog MUX and associated Sample and Hold circuits. Figure 14 shows the system level timing of these elements. The IRMCK203 is specifically designed to interface to the Burr-Brown ADS7818 ADC. As such, all interface signals between the ADC and IRMCK203 are guaranteed to meet worst case timing specifications over the IRMCK203 and ADS7818 specified operation environment. For interfacing to other ADCs, please contact International Rectifier for detailed specifications. Also refer to the Application Developers Guide for a detailed description of ADC, MUX and Sample and Hold signal system level protocol. RESSAMPLE ADCONVST t2 tMUX[2:0] t1 ADMUX0 ADMUX1 ADMUX2 ADCLK t3 tADCLK tCLKDLY Figure 14: Top Level ADC Timing SYMBOL tMUX[2:0] t1 t2 t3 tADCLK tCLKDLY DESCRIPTION ADCONVST to MUX[2:0] ADCONVST Low Period ADCONVST High Period ADCONVST to ADCLK Falling ADCLK Period ADCLK STALL Period TYP 22 1.44 630 60 127.5 210 Table 18: Top Level ADC Timing This document is the property of International Rectifier and may not be copied or distributed without expressed consent. UNITS ns us ns ns ns ns PLL Interface Electrical Characteristics PARAMETER Current Consumption Current Consumption Peak jitter Cycle jitter Lock-up Time PLL Reset Period SYMBOL IDDS CONDITIONS Static MIN - TYP - MAX 170 UNITS uA IDD Dynamic - 5 - MA Tpj Tcj Tlock Trst Recommended operating condition -500 10 - 1000 +500 1 - ps ps ms Ns Table 20: PLL Electrical Characteristics This document is the property of International Rectifier and may not be copied or distributed without expressed consent. IRMCK203 Appendix A Host Register Map Register Access A host computer controls the IRMCK203 using its slave-mode Full-Duplex SPI port, a standard RS-232 port or a 8-bit parallel port for connection to a microprocessor. All interfaces are always active and can be used interchangeably, although not simultaneously. Control/status registers are mapped into a 128-byte address space. Host Parallel Access The IRMCK203 contains an address register that is updated with the Host Register address when HPA = 1. After each subsequent data byte is either read or written, the internal address register is incremented. The diagram below shows that Data Bytes 0 to N would access register locations initially specified by the Address Byte. The Address Byte with the HPA signal can be asserted at any time. Address Byte Data Byte 0 HPA = 1 HPA = 0 ……………. Data Byte N HPA = 0 HPA = 0 Host Parallel Data Transfer Format SPI Register Access When configured as an SPI device read only and read/write operations are performed using the following transfer format: Command Byte Data Byte 0 ……………. Data Byte N Data Transfer Format 7 6 Read Only 5 Bit Position 4 3 2 1 0 Register Map Starting Address Command Byte Format Data transfers begin at the address specified in the command byte and proceed sequentially until the SPI transfer completes. As in the Host Parallel Access, the internal address register is incremented after each SPI byte is transferred. Note that accesses are read/write unless the “read only” bit is set. RS-232 Register Access The IRMCK203 includes an RS-232 interface channel that provides a direct connection to the host PC. The software interface combines a basic "register map" control method with a simple communication protocol to accommodate potential communication errors. This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 31 IRMCK203 RS-232 Register Write Access A Register write operation consists of a command/address byte, byte count, register data and checksum. When the IRMCK203 receives the register data, it validates the checksum, writes the register data, and transmits and acknowledgement to the host. Command / Address Byte Byte Count 1-6 bytes of register data Checksum Register Write Operation Command Acknowledgement Byte Checksum Register Write Acknowledgement 7 6 5 1=Read/ 0=Write Bit Position 4 3 2 1 0 1 0 Register Map Starting Address Command/Address Byte Format 7 1=Error/ 0=OK 6 5 Bit Position 4 3 2 Register Map Starting Address Command Acknowledgement Byte Format The following example shows a command sequence sent from the host to the IRMCK203 requesting a two-byte register write operation: 0x2F Write operation beginning at offset 0x2F 0x02 Byte count of register data is 2 0x00 Data byte 1 0x04 Data byte 2 0x35 Checksum (sum of preceding bytes, overflow discarded) A good reply from the IRMCK203 would appear as follows: 0x2F Write completed OK at offset 0x2F 0x2F Checksum An error reply to the command would have the following format: 0xAF Write at offset 0x2F completed in error 0xAF Checksum This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 32 IRMCK203 RS-232 Register Read Access A register read operation consists of a command/address byte, byte count and checksum. When the IRMCK203 receives the command, it validates the checksum and transmits the register data to the host. Command / Address Byte Byte Count Checksum Register Read Operation Command Acknowledgement Byte Register Data (Byte Count bytes) Checksum Register Read Acknowledgement (transfer OK) Command Acknowledgement Byte Checksum Register Read Acknowledgement (error) The following example shows a command sequence sent from the host to the IRMCK203 requesting four bytes of read register data: 0xA0 Read operation beginning at offset 0x20 (high-order bit selects read operation) 0x04 Requested data byte count is 4 0xA4 Checksum A good reply from the IRMCK203 might appear as follows: 0x20 Read completed OK at offset 0x20 0x11 Data byte 1 0x22 Data byte 2 0x33 Data byte 3 0x44 Data byte 4 0xCA Checksum An error reply to the command would have the following format: 0xA0 Read at offset 0x20 completed in error 0xA0 Checksum RS-232 Timeout The IRMCK203 receiver includes a timer that automatically terminates transfers from the host to the IRMCK203 after a period of 32 msec. RS-232 Transfer Examples The following example shows a normal exchange executing a register write access. This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 33 IRMCK203 The example below shows a normal register read access exchange. The following example shows a register write request that is repeated by the host due to a negative acknowledgement from the IRMCK203. In the final example, the host repeats a register read access request when it receives no response to its first attempt. This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 34 IRMCK203 This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 35 IRMCK203 Write Register Definitions PwmConfig Register Group (Write Registers) Byte Offset 7 Gatekill Sns (W) 0xC 5 SPARE Gate SnsL (W) Gate SnsU (W) SyncSns 2 1 0 BrakeSns SD (W) SPARE PwmPeriod (LSBs) (W) 0xD 0xE Bit Position 4 3 6 TwoPhs Pwm (W) TwoPhs Type (W) PwmConfig (W) PwmPeriod (MSBs) (W) 0xF PwmDeadTm (W) 0x44 ModScl (LSBs) (W) 0x45 ModScl (MSBs) (W) 0x51 PwmGuardBand (W) PwmConfig Write Register Map Field Name SD BrakeSns Access (R/W) W W SyncSns W GateSnsU W GateSnsL W GatekillSns W PwmPeriod W PwmConfig W TwoPhsType W TwoPhsPwm W Field Description Shutdown control output to IR2137. Logic Sense for BRAKE signal output to gate driver IC. 0 = Active low, 1 = active high. Logic Sense for PWM SYNC signal output to microprocessor. 0 = Active low, 1 = active high. Upper IGBT gate sense. 1 = active high gate control, 0 = active low gate control. Lower IGBT gate sense. 1 = active high gate control, 0 = active low gate control. GATEKILL signal sense. 1 = active high GATEKILL, 0 = active low GATEKILL. PWM Carrier period. Actual PWM carrier period is 2 * (PwmPeriod + 1) * (System Clock Period). PWM Configuration. 0 = Asymmetrical center aligned PWM, 1 = Symmetrical Center aligned PWM. Used only for two-phase PWM modulation mode: 0 = Type 1 2-phase PWM 1 = Type 2 2-phase PWM Selects PWM modulation mode: 0 = Enable 3-phase space vector PWM modulation 1 = Enable 2-phase space vector PWM modulation This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 36 IRMCK203 Field Name PwmDeadTm Access (R/W) W Field Description Gate drive dead time in units of system clock cycles (e.g., 30 ns with 33 MHz clock). Space vector modulator scale factor. This register, which depends on the PWM carrier frequency, should be set as follows: W ModScl = PwmPeriod * sqrt(3) * 4096 / 2355 where PwmPeriod is the value in the PwmConfig write register group’s PwmPeriod register. W This parameter provides a guard band (scaling: 1 = 30nsec) such that PWM switching will not migrate into the current feedback sampling instant (Sync Pulse region). This guard band is provided to improve feedback noise. The parameter only applies to the 3phase Space Vector modulation scheme. Please do not modify this parameter without consulting a motor drive FAE. PwmConfig Write Register Field Definitions ModScl PwmGuardBand CurrentFeedbackConfig Register Group (Write Registers) Byte Offset 7 6 5 Bit Position 4 3 0x15 IfbkScl (LSB) (W) 0x16 IfbkScl (MSB) (W) 0x7D OffsetCalDelay (W) 2 1 0 CurrentFeedbackConfig Write Register Map Field Name IfbkScl IfbOffsVOffse tCal Delay Access (R/W) Field Description Rotating frame Iq component and Id component current feedback scale factor. Constant used to scale current measurements before they are used in the field orientation calculation. This is a 15-bit fixedpoint signed number with 10 fractional bits that ranges from –16 to + 16 + 1023 / 1024. This parameter specifies the delay time (1 = 1 sec) to restart current W offset measurement after a stop command is issued. Only applies if Leg Shunt current feedback is selected.12-bit signed value for V phase current feedback offset. When the IfbOffsEnb bit in the SystemControl write register group is "0" this value is automatically added to each current measurement in hardware. CurrentFeedbackConfig Write Register Field Definitions W This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 37 IRMCK203 SystemControl Register Group (Write Registers) Byte Offset 7 6 5 Bit Position 4 3 SPARE 0x17 2 1 0 HostEstop StartCmd Rotation SystemControl Write Register Map Field Name Rotation Access (R/W) W Field Description Direction of motor rotation: 0 = Reverse motor rotation; 1 = Forward motor rotation. W Start/Stop bit. Setting this bit to 1 issues a start command. Setting this bit to 0 stops the motor. W Emergency coast stop will take place when this bit is set to one. SystemControl Write Register Field Definitions StartCmd HostEstop TorqueLoopConfig Register Group (Write Registers) Byte Offset 7 6 5 Bit Position 4 3 2 0x1A KpIreg – Current Loop Proportional Gain (LSBs) (W) 0x1B KpIreg – Current Loop Proportional Gain (MSBs) (W) 0x1C KxIreg – Current Loop Integral Gain (LSBs) (W) 0x1D KxIreg – Current Loop Integral Gain (MSBs) (W) 0x22 VqLim – Quadrature Current Output Limit (LSBs) (W) 0x23 VqLim – Quadrature Current Output Limit (MSBs) (W) 0x26 VdLim – Direct Current Output Limit (LSBs) (W) 0x27 VdLim – Direct Current Output Limit (MSBs) (W) 1 0 TorqueLoopConfig Write Register Map This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 38 IRMCK203 Field Name KpIreg Access (R/W) W KxIreg W VqLim VdLim W W Field Description 15-bit signed current loop PI controller proportional gain. Scaled with 14 fractional bits for an effective range of 0 – 1. 15-bit signed current loop PI controller integral gain. Scaled with 19 fractional bits for an effective range of 0 - .03125. 16-bit Quadrature current PI controller voltage output limit. 16-bit Direct current PI controller voltage output limit. TorqueLoopConfig Write Register Field Definitions VelocityControl Register Group (Write Registers) Byte Offset 7 6 5 Bit Position 4 3 2 0x32 KpSreg – Velocity loop proportional gain (LSBs) (W) 0x33 KpSreg – Velocity loop proportional gain (MSBs) (W) 0x34 KxSreg – Velocity loop integral gain (LSBs) (W) 0x35 KxSreg – Velocity loop integral gain (MSBs) (W) 0x36 MotorLim – Velocity loop Output Positive Limit (LSBs) (W) 0x37 MotorLim – Velocity loop Output Positive Limit (MSBs) (W) 0x38 RegenLim – – Velocity loop Output Negative Limit (LSBs) 0x39 RegenLim – – Velocity loop Output Negative Limit (MSBs) 0x3A SpdScl – Speed Scale Factor (LSBs) 0x3B SpdScl – Speed Scale Factor (MSBs) 0x3C TargetSpd – Setpoint/target speed (LSBs) 0x3D TargetSpd – Setpoint/target speed (MSBs) 0x3E AccelRate 0x3F DecelRate 0x7A MinSpd 1 This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 0 39 IRMCK203 Byte Offset 7 6 Bit Position 4 3 5 0x18 StartLim (LSBs) 0x19 StartLim (MSBs) 2 1 0 VelocityControl Write Register Map Field Name KpSreg Access (R/W) W KxSreg W MotorLim W RegenLim W SpdScl W TargetSpd W AccelRate DecelRate MinSpd W W W StartLim W Field Description 15-bit velocity loop proportional gain, in fixed point with 5 fractional bits. Range = 0 - 512. 15-bit velocity loop integral gain, in fixed point with 13 fractional bits. Range = 0 - 2. Motoring torque current limit (4095 = rated motor current).16-bit speed PI controller output positive limit. Regeneration torque current limit (4095 = rated motor current)16-bit speed PI controller output negative limit (2’s complement).. Motor Speed Scale factor. Spd value (in the VelocityStatus read register group) is maintained in SPEED units of SpdScl * (Encoder counts / Velocity Loop Execution) or SpdScl * (RATE * Encoder counts / PWM period). The user should set SpdScl = (64 * 16384) * 60 * PWMFREQ / (RATE * Max RPM * Encoder counts/revolution), which will result in a Spd value ranging ±16384 corresponding to ± Max RPM. Velocity loop speed setpoint in SPEED units, which are determined by the user via the SpdScl register setting. Positive speedAcceleration rate limit. Negative speedDeceleration rate limit. Minimum speed protection. This parameter sets the minimum reference speed. Drive start-up current limit. (4095 = rated motor current). VelocityControl Write Register Field Definitions FaultControl Register Group (Write Registers) Byte Offset 7 0x42 6 Bit Position 4 3 5 2 1 0 FltClr DcBusM Enb SPARE FaultControl Write Register Map This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 40 IRMCK203 Field Name Access (R/W) DcBusMEnb W FltClr W Field Description DC Bus monitor enable. 1 = Monitor DC bus voltage and generate appropriate brake signal control and disable PWM output when voltage fault conditions occur. GatekillFlt and OvrSpdFlt faults cannot be disabled. DC bus voltage thresholds are as follows: Overvoltage – 410V Brake On – 380V Brake Off – 360V Nominal – 310V Undervoltage off – 140V Undervoltage – 120V This bit clears all active fault conditions. The user should monitor the FaultStatus read register group to determine fault status and set this bit to “1” to clear any faults that have occurred. A fault condition automatically clears the PwmEnbW and FocEnbW bits in the SystemControl write register group. Note that this bit also directly controls the output 2137 FLTCLR pin. After clearing a fault, the user must explicitly set this bit to “0” to re-enable fault processing. FaultControl Write Register Field Definitions SystemConfig Register Group (Write Registers) Byte Offset 0x50 7 6 5 ExtCtrl AdcIfbEnb Ramp Stop Bit Position 4 3 2 1 0 SPARE SystemConfig Write Register Map Field Name RampStop AdcIfbEnb ExtCtrl Access (R/W) Field Description Selects the stopping mode: 0 - Configure for Coast stopping 1 - Configure for Ramp stopping W Selects the current feedback mode: 0 - Selects IR2175 current feedback 1 - Selects Leg-Shunt current feedback Setting this bit to “1” enables direct control of basic motor operation W via the external User Interface pins. When this bit is “1”, the FocEnbW and PwmEnbW bits in the SystemControl write register group are ignored. SystemConfig Write Register Field Definitions W This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 41 IRMCK203 EepromControl Registers (Write Registers) At power up, the write registers can be optionally initialized with values stored in EEPROM. The EepromControl write register group and EepromStatus read register group are used to read and write these EEPROM values. Since the EeAddrW write register (which selects the EEPROM offset to read or write) does not require initialization at power up, the location corresponding to that register in EEPROM (at offset 0x5D) is used to store a register map version code. At power on, the IRMCK203 initializes the write registers from EEPROM only if the version code stored at this offset in EEPROM matches its internal register map version code (which can be read from the RegMapVer field of the EepromStatus read register group). To enable write register initialization at power up, write the appropriate register map version code to EEPROM at offset 0x5D. To disable write register initialization at power up, write a zero (or any non-matching version code) to offset 0x5D of the EEPROM. Byte Offset 7 6 Bit Position 4 3 5 SPARE 0x5C 0x5D EeAddrW / RegMapVersCode (W) 0x5E EeDataW (W) 2 1 0 EeWrite EeRead EeRst EepromControl Write Register Map Field Name EeRst Access (R/W) W EeRead W EeWrite W EeAddrW W EeDataW W Field Description Self-clearing EEPROM reset. Writing a "1" to this bit resets the I2C EEPROM interface. Self-clearing I2c EEPROM Read. Writing a "1" to this bit initiates an EEPROM read from the byte located at EEPROM address EeAddrW. After setting this bit the user should poll the EeBusy bit in the EepromStatus read register group to determine when the read completes and then read the data from EeDataR in the EepromStatus read register group. Self-clearing EEPROM Write. Writing a "1" to this bit initiates an EEPROM write from the data byte in EeDataW to the EEPROM address EeAddrW . EEPROM Address Register. Contains the address for the next EEPROM read or write operation. EEPROM Data Register. Contains the data for the next EEPROM write operation. EepromControl Write Register Field Definitions This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 42 IRMCK203 ClosedLoopAngleEstimator Registers (Write Registers) Byte Offset 7 6 5 Bit Position 4 3 0x60 IScl (LSBs) (W) 0x61 IScl (MSBs (W) 0x62 FlxBInit (LSBs) (W) 0x63 FlxBInit (MSBs) (W) 0x6A PllKp (LSBs) (W) 0x6B SPARE 0 PllKp (MSBs (W) SPARE PllKi (MSBs (W) 0x6E VoltScl (LSBs) (W) 0x6F VoltScl (MSBs (W) 0x70 Rs (LSBs) (W) 0x71 Rs (MSBs (W) 0x72 Ld (LSBs) (W) 0x73 Ld (MSBs (W) 0x74 AtanTau (LSBs) (W) 0x75 AtanTau (MSBs (W) 0x76 FlxTau (LSBs) (W) 0x77 1 PllKi (LSBs) (W) 0x6C 0x6D 2 SPARE FlxTau (MSBs) (W) ClosedLoopAngleEstimator Write Register Map This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 43 IRMCK203 Field Name IScl FlxBInit PllKp PllKi VoltScl Rs Ld AtanTau FlxTau Access Field Description (R/W) W Current scaler for motor flux calculation. W Initialization value of Beta flux at start. W Flux phase lock loop proportional gain. W Flux phase lock loop integral gain. W Voltage scaler for motor flux calculation. W Motor per phase resistance including cable (@25C). W Motor per phase inductance. W Rotor angle estimator phase compensation gain. W Rotor angle estimator flux model time constant. ClosedLoopAngleEstimator Write Register Field Definitions OpenLoopAngleEstimator Registers (Write Registers) Byte Offset 7 6 5 Bit Position 4 3 0x66 KTorque (LSBs) (W) 0x67 KTorque (MSBs (W) 0x5F VFGain (W) 2 1 0 OpenLoopAngleEstimator Write Register Map Field Name KTorque VFGain Access Field Description (R/W) W Motor mechanical model torque constant. W Open-Loop Volts/Hz Flux gain. (for diagnostic use only). OpenLoopAngleEstimator Write Register Field Definitions StartupAngleEstimator Registers (Write Registers) Byte Offset 7 6 5 0x68 2 1 0 ParkI (W) 0x64 0x65 Bit Position 4 3 SPARE Zero SpdFlt Disable Use2xFrq Scale PhsLosFlt Disable DiagnosticCtrl (W) WeThr (LSBs) (W) This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 44 IRMCK203 Byte Offset 7 6 5 Bit Position 4 3 0x69 WeThr (MSBs (W) 0x78 ParkTm (W) 2 1 0 StartupAngleEstimator Write Register Map Field Name ParkI DiagnosticCtrl Access (R/W) W W Field Description DC current injection level during motor parking (start-up mode). 1 (0001) – Enable Parking diagnostic 2 (0010) – Enable start-up diagnostic 5 (0101) – Enable current regulator diagnostic 9 (1001) – Enable volts Hertz diagnostic W Enable/disable phase loss fault: 0 = Enable Phase Loss Fault; 1 = Disable Phase Loss Fault W Selects speed scaling: 0 - Norminal speed scale 1 - Reduce speed feedback scaling by half Please do not modify this parameter without consulting motor control FAEs W Zero speed fault enable/disable: 0 - Enbale Zero Speed Fault 1 - Disable Zero Speed Fault W Frequency threshold level (switch over from open-loop to closedloop mode). W Time duration of parking mode. 255 = 4 sec StartupAngleEstimator Write Register Field Definitions PhsLosFlt Disable Use2xFrqScale ZeroSpdFlt Disable WeThr ParkTm StartupRetrial Registers (Write Registers) Byte Offset 7 6 5 Bit Position 4 3 0x1E RetryTm (LSBs) 0x1F RetryTm (MSBs) 0x79 ParkTmRet 0x7B FlxThrL 0x7C FlxThrH 2 1 This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 0 45 IRMCK203 Byte Offset 7 6 5 Bit Position 4 3 0x7E NumRetries 0x7F ParkIRet 2 1 0 StartupRetrial Write Register Map Field Name Access (R/W) RetryTm W ParkTmRet W FlxThrL W FlxThrH W NumRetries W ParkIRet W Field Description This parameter provides the adjustment to the sampling instant for determination of start failure. The sampling instant starts when Closed_Loop = 1. Scaling 1 count = 1.966 msec. Please do not modify this parameter without consulting a motor drive FAE. During motor start-up, dc current is injected to the motor for maximization of startup torque per ampere rating. ParkTm controls the duration of dc current injection. However, users are able to use a longer duration after two or more restarts by setting this parameter (ParkTmRet scaling 255 = 4 secs.). This is done to increase the chance of a successful start-up.Start-up failure may be caused by increased shaft friction. After first start-up retry, the parking time can be increased to improve parking performance. The low flux threshold level for determining a successful startup (scaling: 129 = 100% flux). Please do not modify this parameter without consulting a motor drive FAE.The low flux threshold level for determining a successful startup. The upper flux threshold level for determining a successful startup (scaling: 64 = 100% flux). Please do not modify this parameter without consulting a motor drive FAE.The high flux threshold level for determining start-up failure. If start-up fails, the user can program start-up retrial. This parameter determines the number of start-up retries. A value of zero will disable startup retrial. The maximum number of retries is 15. During motor start-up, dc current is injected to the motor for maximization of startup torque per ampere rating. Users are able to use a higher level of dc current injection (ParkIRet scaling 255 = Motor Rated Amp * 0.866) after two or more restarts. This is done to increase the chance of a successful start-up.Start-up failure may be caused by increased shaft friction. After first start-up retry, the parking current can be increased to improve parking performance. StartupRetrial Write Register Field Definitions This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 46 IRMCK203 PhaseLossDetect Registers (Write Registers) Byte Offset 7 6 5 Bit Position 4 3 0x79 ParkTmRet 0x28 AdjPark1 0x29 AdjPark2 0x2A RetryTm 2 1 0 PhaseLossDetect Write Register Map Field Name AdjPark1 Access (R/W) W Field Description Anticipated W-phase motor current gain scaler used during initial stage of Phase Loss detection. W Anticipated W-phase motor current gain scaler used during final stage of Phase Loss detection. W Phase Loss detection current error thershold. PhaseLossDetect Write Register Field Definitions AdjPark2 PhsLosThr D/AConverter Registers (Write Registers) Byte Offset 7 0x4F 6 5 Bit Position 4 3 2 1 0 DacSel D/AConverter Write Register Map This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 47 IRMCK203 Field Name DacSel Access (R/W) W Field Description Selects D/A converter diagnostic outputs 0 - 3. A value of 0 selects: Data 0 = Alpha fluxFlux Data 1 = Electrical Rotor angle Data 2 = Alpha voltageTorque current Data 3 = Closed loop/open loop status (0 = open, 1 = closed) A value of 1 selects: Data 0 = Alpha currentDC bus voltage Data 1 = Torque current feedbackAlpha voltage Data 2 = IQ refTorque current reference Data 3 = Motor speed A value of 2 selects: Data 0 = Q-axis command voltage Data 1 = D-axis command voltage Data 2 = Alpha current Data 3 = Beta current A value of 3 selects: Data 0 = Flux magnitude Data 1 = Current error at parking Data 2 = Parking diagnostic flag Data 3 = W-phase current D/AConverter Write Register Field Definitions Factory Test Register (Write Register) Byte Offset 7 6 5 Bit Position 4 3 2 1 0 Test 0x58 Factory Write Register Map Field Name Test Access (R/W) W Field Description Reserved for factory use. Data written to this register could be read from a read register at location 0x58. Factory Write Register Field Definitions This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 48 IRMCK203 Read Register Definitions SystemStatus Register Group (Read Registers) Byte Offset 0x7 7 6 5 Bit Position 4 3 2 1 0 StartStop FwdRev ESTOP PwrID ExtCtrlR Foc EnbR Pwm EnbR SystemStatus Read Register Map Field Name PwmEnbR FocEnbR ExtCtrlR Access (R/W) R R R PwrID ESTOP FwdRev R R R StartStop R Field Description PWM Enable bit status. FOC Enable bit status. Reflects the status of the ExtCtrl bit in the System Configuration write register (address 0x50). Power ID. 0 = 3 kW, 1 = 2 kW, 2 = 500 W. User Interface emergency stop signal (1 – emergency stop) User Interface “FWD/REVDIR" digital input status. 1 - Forward rotation request 0 - Reverse rotation request User Interface “START/STOP" digital input status. 1 - Start 0 - Stop SystemStatus Read Register Field Definitions DcBusVoltage Register Group (Read Registers) Byte Offset 7 6 5 2 1 0 DcBusVolts (LSBs) 0xA 0xB Bit Position 4 3 SPARE Brake DcBusVolts (MSBs) DcBusVoltage Read Register Map This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 49 IRMCK203 Field Name DcBusVolts Access (R/W) R Brake R Field Description DC Bus Voltage. Data range is 0 - 4095, which corresponds to a DC bus voltage between 0 and 500 volts. Brake signal status. 1 = Brake signal active. DcBusVoltage Read Register Field Definitions FocDiagnosticData Register Group (Read Registers) Byte Offset 7 6 Bit Position 4 3 5 1 0 RotatorAngle (LSB) 0xC 0xD 2 SPARE Parking Done Start_ Fail Closed_ Loop RotatorAngle (MSB) 0xE Id – Synchronous Frame Direct Current (LSBs) 0xF Id – Synchronous Frame Direct Current (MSBs) 0x10 Iq – Synchronous Frame Quadrature Current (LSBs) 0x11 Iq – Synchronous Frame Quadrature Current (MSBs) 0x12 IqRef_C – Synchronous Frame Quadrature Current command (LSB) 0x13 IqRef_C – Synchronous Frame Quadrature Current command (MSB) 0x14 Flx_Alpha – Estimated Motor Flux (LSB) 0x15 Flx_Alpha – Estimated Motor Flux (MSB) 0x16 I_Alpha – Alpha Frame Current (LSB) 0x17 I_Alpha – Alpha Frame Current (MSB) 0x18 V_Alpha – Alpha Frame Voltage (LSB) 0x19 V_Alpha – Alpha Frame Voltage (MSB) FocDiagnosticData Read Register Map This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 50 IRMCK203 Field Name Access (R/W) Field Description Estimated rotor angle (electrical), which is used for synchronous frame to stationary frame transformation. The scaling is 4096 = 2PI. The range is 0 – 4095. This is a drive control status flag which indicates that the drive has R switched from open-loop to closed-loop operation. The switch over is done during drive start-up (initial speed ramping) This is a drive control status flag indicating that the drive has failed to R start due to various reasons (for instance: shaft jam). The start-stop sequencer uses this bit and parameter NumRetry to determine whether a start-up retry should be activated. This is a status flag indicating that the drive has finished obtaining the R initial rotor angle (parking) for motor startup. During drive start-up, the first start-up stage is parking stage. Synchronous or rotating frame direct and quadrature current values R in 2’s complement representation. The full scale current values range from –16384 to 16383. (Scaling: 4095 = rated motor current) Synchronous or rotating frame quadrature current command values R in 2’s complement representation. The full scale current values range from –16384 to 16383. R Estimated motor flux value. Scaling is 5000 = rated motor flux. Stationary frame current. Scaling is platform dependent (current R shunt resistor). Drive commissioning tool (Spreadsheet) provides the scaling of I_Alpha (AiBi scale). Stationary frame Alpha voltage. This voltage is constructed by dc bus R voltage and modulation index in the Stationary frame. The scaling is platform dependent. FocDiagnosticData Read Register Field Definitions RotatorAnlge R Closed_Loop Start_Fail Parking Done Id, Iq IqRef_C Flx_Alpha I_Alpha V_Alpha FaultStatus Register Group (Read Registers) The Fault Status register records fault conditions that occur during drive operation. When any of these fault conditions occur, the PWM output is automatically disabled. The user should monitor this register continuously for fault conditions. A fault condition can be cleared by writing a “1” to the FaultClr bit in the FaultControl write register group. (This does not automatically re-enable PWM output.) Byte Offset 0x1E 7 6 5 PhsLoss Flt RetryFlt ZeroSpd Flt Bit Position 4 3 ExecTm Flt OvrSpdFlt 2 1 0 OvFlt LvFlt GatekillFlt FaultStatus Read Register Map Field Name GatekillFlt LvFlt Access (R/W) R R Field Description Filtered and latched version of IR2137 FAULT output. DC bus low voltage fault. This fault occurs if the DC bus drops below 120V. This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 51 IRMCK203 Field Name OvFlt Access (R/W) R OvrSpdFlt R ExecTmFlt ZeroSpdFlt R R RetryFlt R PhsLossFlt R Field Description DC bus overvoltage fault. This fault occurs if the DC bus voltage exceeds 410V. Over speed fault. This fault occurs whenever the motor reaches the positive or negative limits. The user should use the scale factor in the SpdScl field of the VelocityControl write register group to scale the motor speed so that it falls between -16384 and +16383 with these limits as the over speed condition. Execution time fault. Zero Speed fault. When speed is less than MinSpd/2 (half minimum speed) for a continuous period of 2 4 seconds, the zero speed fault will be set. Start-up retry fault. After a certain number (determined by parameter NumRetries) of start-up failures, this fault will be set. Phase loss fault. Drive to motor phase connection may be loose. FaultStatus Read Register Field Definitions VelocityStatus Register Group (Read Registers) Byte Offset 7 6 5 Bit Position 4 3 0x26 Spd (LSBs) 0x27 Spd (MSBs) 2 1 0 VelocityStatus Read Register Map Field Name Spd Access (R/W) R Field Description Current motor speed in SPEED units. (See the description of SpdScl in the VelocityControl write register group.) VelocityStatus Read Register Field Definitions This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 52 IRMCK203 CurrentFeedbackOffset Register Group (Read Registers) Byte Offset 7 6 5 Bit Position 4 3 2 1 0 IfbVOffs (LSBs) (R) 0x30 IfbWOffs (LSBs) (R) 0x31 IfbVOffs (MSBs) (R) IfbWOffs (MSBs) (R) 0x32 CurrentFeedbackOffset Read Register Map Field Name Access (R/W) Field Description Current feedback offset values from the last IFB Offset calculation. These values are automatically applied to each current feedback measurement value whenever the IfbOffsEnb bit in the SystemControl write register group is set. CurrentFeedbackOffset Read Register Field Definitions IfbVOffs, IfbWOffs R EepromStatus Registers (Read Registers) Byte Offset 7 6 5 Bit Position 4 3 2 1 SPARE 0x38 0x39 EdDataR (R) 0x3A EeAddrR (R) 0 EeBusy EepromStatus Read Register Map Field Name EeBusy Access (R/W) R Field Description I2C EEPROM Interface busy bit. The user should wait for this bit to clear before initiating EEPROM read or write operations. This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 53 IRMCK203 Field Name EeDataR Access (R/W) R EeAddrR R Field Description EEPROM Data Register. Contains the data from the last EEPROM read operation. Note that writing to the EeRst field in the EepromControl write register group invalidates this register. EEPROM Address read register shows the value stored in EEPROM at the offset of the EeAddrW write register (0x5D). Since this address in the EEPROM contains the BPIRMCK203 register map version, the user can read this field to determine whether or not the write registers were initialized at power on. EepromStatus Read Register Field Definitions FOCDiagnosticDataSupplement Register Group (Read Registers) Byte Offset 7 6 5 2 1 0 ElecAngR (LSBs) (R) 0x3C 0x3D Bit Position 4 3 SPARE ElecAngR (MSBs) (R) 0x3E SpdRef (LSBs) (R) 0x3F SpdRef (MSBs) (R) 0x40 SpdErr (LSBs) (R) 0x41 SpdErr (MSBs) (R) 0x42 IqRefR (LSBs) (R) 0x43 IqRefR (MSBs) (R) FOCDiagnosticDataSupplement Read Register Map Field Name ElecAngR SpdRef SpdErr IqRefR Access Field Description (R/W) R Electrical angle. R Speed PI controller reference input. R Speed PI controller error. R Speed PI controller output. FOCDiagnosticDataSupplement Read Register Field Definitions This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 54 IRMCK203 ProductIdentification Registers (Read Registers) Byte Offset 7 6 Bit Position 4 3 5 0x7C ProductID (R) 0x7D RegMapVerID (R) 0x7E RevCodeID (LSBs) (R) 0x7F RevCodeID (MSBs) (R) 2 1 0 ProductIdentification Read Register Map Field Name ProductID RegMapVerID RevCodeID Access (R/W) R R R Field Description Product identification code. Current register map version code. IRMCK203 Revision Code. Revision code format is “XX.XX”, where each “X” is a 4-bit hexadecimal number. ProductIdentification Read Register Field Definitions Factory Register (Read Register) Byte Offset 7 6 5 Bit Position 4 3 2 1 0 Test (R) 0x58 Factory Read Register Map Field Name Test Access (R/W) R Field Description Data value resulting from a write to write register 0x58. factory use only. Factory Read Register Field Definitions This document is the property of International Rectifier and may not be copied or distributed without expressed consent. Used for 55 IRMCK203 Appendix B Package This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 56 IRMCK203 IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, Tel: (310) 252-7105 Data and specifications subject to change without notice. 4/13/2004 http://www.irf.com Sales Offices, Agents and Distributors in Major Cities Throughout the World. This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 57