LINER LTC2391CUK-16 16-bit, 250ksps sar adc with 94db snr Datasheet

LTC2391-16
16-Bit, 250ksps SAR ADC
with 94dB SNR
Features
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Description
250ksps Throughput Rate
±2LSB INL (Max)
Guaranteed 16-Bit No Missing Codes
94dB SNR (Typ) at fIN = 20kHz
Guaranteed Operation to 125°C
Single 5V Supply
1.8V to 5V I/O Voltages
95mW Power Dissipation
±4.096V Differential Input Range
Internal Reference (20ppm/°C Max)
No Pipeline Delay, No Cycle Latency
Parallel and Serial Interface
Internal Conversion Clock
48-Pin 7mm × 7mm LQFP and QFN Packages
The LTC®2391-16 is a low noise, high speed 16-bit successive approximation register (SAR) ADC. Operating
from a single 5V supply, the LTC2391-16 supports a large
±4.096V fully differential input range, making it ideal for
high performance applications which require maximum
dynamic range. The LTC2391-16 achieves ±2LSB INL max,
no missing codes at 16-bits and 94dB SNR (typ).
The LTC2391-16 includes a precision internal reference
with a guaranteed 0.5% initial accuracy and a ±20ppm/°C
(max) temperature coefficient. Fast 250ksps throughput
with no cycle latency in both parallel and serial interface
modes makes the LTC2391-16 ideally suited for a wide
variety of high speed applications. An internal oscillator
sets the conversion time, easing external timing considerations. The LTC2391-16 dissipates only 95mW at 250ksps,
while both nap and sleep power-down modes are provided
to further reduce power during inactive periods.
Applications
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Medical Imaging
High Speed Data Acquisition
Digital Signal Processing
Industrial Process Control
Instrumentation
ATE
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
5V
5V
16k Point FFT fS = 250ksps,
fIN = 20kHz
1.8V TO 5V
0
ANALOG INPUT
0V TO 4.096V
LT6350
10µF
AVP
249Ω
0.1µF
4.7µF
DVP
OVP
IN+
2200pF
249Ω
SINGLE-ENDEDTO-DIFFERENTIAL
DRIVER
0.1µF
LTC2391-16
IN–
VCM REFIN REFOUT CNVST PD RESET GND OGND
–40
PARALLEL
OR
16 BIT
SERIAL
INTERFACE
SER/PAR
BYTESWAP
OB/2C
CS
RD
BUSY
239116 TA01
10µF
1µF
SAMPLE CLOCK
SNR = 94dB
THD –103dB
SINAD = 93.5dB
SFDR = 104dB
–20
AMPLITUDE (dBFS)
10µF
–60
–80
–100
–120
–140
–160
–180
0
25
75
50
FREQUENCY (kHz)
100
125
239116 G08
239116f
LTC2391-16
Absolute Maximum Ratings (Notes 1, 2)
Supply Voltage (VAVP , VDVP , VOVP)...........................6.0V
Analog Input Voltage (Note 3)
IN+, IN–, REFIN, CNVST... (GND – 0.3V) to (VAVP + 0.3V)
Digital Input Voltage......... (GND – 0.3V) to (VOVP + 0.3V)
Digital Output Voltage...... (GND – 0.3V) to (VOVP + 0.3V)
Power Dissipation................................................500mW
Operating Temperature Range
LTC2391C................................................. 0°C to 70°C
LTC2391I.............................................. –40°C to 85°C
LTC2391H........................................... –40°C to 125°C
Storage Temperature Range.................... –65°C to 150°C
Pin Configuration
TOP VIEW
GND 1
AVP 2
DVP 3
SER/PAR 4
GND 5
OB/2C 6
GND 7
BYTESWAP 8
D0 9
D1 10
D2 11
D3 12
36 VCM
35 GND
34 CNVST
33 PD
32 RESET
31 CS
30 RD
29 BUSY
28 D15
27 D14
26 D13
25 D12
GND 1
AVP 2
DVP 3
SER/PAR 4
GND 5
OB/2C 6
GND 7
BYTESWAP 8
D0 9
D1 10
D2 11
D3 12
36
35
34
33
32
31
30
29
28
27
26
25
VCM
GND
CNVST
PD
RESET
CS
RD
BUSY
D15
D14
D13
D12
D4 13
D5 14
D6 15
D7 16
OGND 17
OVP 18
DVP 19
GND 20
D8 21
D9/SDIN 22
D10/SDOUT 23
D11/SCLK 24
D4 13
D5 14
D6 15
D7 16
OGND 17
OVP 18
DVP 19
GND 20
D8 21
D9/SDIN 22
D10/SDOUT 23
D11/SCLK 24
49
GND
48
47
46
45
44
43
42
41
40
39
38
37
48 GND
47 AVP
46 AVP
45 AVP
44 GND
43 IN+
42 IN–
41 GND
40 AVP
39 REFSENSE
38 REFIN
37 REFOUT
GND
AVP
AVP
AVP
GND
IN+
IN–
GND
AVP
REFSENSE
REFIN
REFOUT
TOP VIEW
UK PACKAGE
48-LEAD (7mm s 7mm) PLASTIC QFN
LX PACKAGE
48-LEAD (7mm s 7mm) PLASTIC LQFP
TJMAX = 125°C, θJA = 29°C/W
EXPOSED PAD (PIN 49) IS GND, MUST BE SOLDERED TO PCB
TJMAX = 125°C, θJA = 55°C/W
Order Information
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC2391CUK-16#PBF
LTC2391CUK-16#TRPBF
LTC2391UK-16
48-Lead 7mm × 7mm Plastic QFN
0°C to 70°C
LTC2391IUK-16#PBF
LTC2391IUK-16#TRPBF
LTC2391UK-16
48-Lead 7mm × 7mm Plastic QFN
–40°C to 85°C
LEAD FREE FINISH
TRAY
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC2391CLX-16#PBF
LTC2391CLX-16#PBF
LTC2391LX-16
48-Lead 7mm × 7mm Plastic LQFP
0°C to 70°C
LTC2391ILX-16#PBF
LTC2391ILX-16#PBF
LTC2391LX-16
48-Lead 7mm × 7mm Plastic LQFP
–40°C to 85°C
LTC2391HLX-16#PBF
LTC2391HLX-16#PBF
LTC2391LX-16
48-Lead 7mm × 7mm Plastic LQFP
–40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
239116f
LTC2391-16
ANALOG INPUT The l denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
VIN
+
Absolute Input Range (IN+)
MIN
(Note 5)
l
VIN–
Absolute Input Range (IN–)
(Note 5)
l
VIN+ – VIN–
Input Differential Voltage Range
VIN = VIN+ – VIN–
VCM
IIN
CIN
Analog Input Capacitance
CMRR
Input Common Mode Rejection Ratio
TYP
MAX
UNITS
–0.05
AVP
V
–0.05
AVP
V
l
–VREF
VREF
V
Common Mode Input Range
l
VREF/2 – 0.05
Analog Input Leakage Current
l
Sample Mode
Hold Mode
VREF/2
VREF/2 + 0.05
V
±1
µA
45
5
pF
pF
70
dB
converter characteristics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
MIN
UNITS
l
16
Bits
No Missing Codes
l
16
Bits
INL
Integral Linearity Error
DNL
Differential Linearity Error
Bipolar Zero Error
0.3
(Note 6)
(Note 7)
l
–2
l
–1
l
–7
Bipolar Zero Error Drift
FSE
MAX
Resolution
Transition Noise
BZE
TYP
Bipolar Full-Scale Error
±1
LSBRMS
2
LSB
1
LSB
7
1
External Reference
Internal Reference (Note 7)
LSB
ppm/°C
0.14
0.1
l
Bipolar Full-Scale Error Drift
±10
%
%
ppm/°C
dynamic accuracy The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. AIN = –1dBFS (Notes 4, 8)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
SINAD
Signal-to-(Noise + Distortion) Ratio
fIN = 20kHz
l
90.5
93.5
dB
SNR
Signal-to-Noise Ratio
fIN = 20kHz
l
91
94
dB
THD
Total Harmonic Distortion
fIN = 20kHz, First 5 Harmonics
l
SFDR
Spurious-Free Dynamic Range
fIN = 20kHz
–103
–94
dB
104
dB
–3dB Input Bandwidth
50
MHz
Aperture Delay
0.5
Aperture Jitter
7
psRMS
60
ns
Transient Response
Full-Scale Step
ns
239116f
LTC2391-16
INTERNAL REFERENCE CHARACTERISTICS The l denotes the specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. (Note 4)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VREF Output Voltage
IOUT = 0
4.076
4.096
4.116
V
VREF Output Tempco
IOUT = 0 (I-, H-Grades) (Note 11)
±10
±20
VREF Output Impedance
–0.1mA ≤ IOUT ≤ 0.1mA
l
ppm/°C
2.6
External Reference Voltage
2.5
REFIN Input Impedance
4.096
kΩ
AVP – 0.5
V
85
kΩ
VREF Line Regulation
AVP = 4.75V to 5.25V
0.3
mV/V
VCM Output Voltage
IOUT = 0
2.08
V
DIGITAL INPUTS AND DIGITAL OUTPUTS The l denotes the specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
VIH
High Level Input Voltage
CONDITIONS
l
VIL
Low Level Input Voltage
l
IIN
Digital Input Current
CIN
Digital Input Capacitance
VOH
High Level Output Voltage
IO = –500µA
l
VOL
Low Level Output Voltage
IO = 500µA
l
IOZ
Hi-Z Output Leakage Current
VOUT = 0V to OVP
l
ISOURCE
Output Source Current
VOUT = 0V
–10
mA
ISINK
Output Sink Current
VOUT = OVP
10
mA
VIN = 0V to OVP
MIN
l
TYP
MAX
0.8 • OVP
UNITS
V
–10
0.5
V
10
µA
5
pF
OVP – 0.2
V
–10
0.2
V
10
µA
power requirements The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
VAVP , VDVP
Supply Voltage
VOVP
Supply Voltage
IDD
Supply Current
Power Down Mode
250ksps Sample Rate with Nap Mode
Conversion Done and All Digital Inputs Tied to OVP
PD
Power Dissipation
Power Down Mode
250ksps Sample Rate with Nap Mode
Conversion Done and All Digital Inputs Tied to OVP
l
MIN
TYP
MAX
UNITS
4.75
5
5.25
V
5.25
V
19
35
25
250
mA
µA
95
175
125
1250
mW
µW
1.71
l
l
239116f
LTC2391-16
timing characteristics
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
MAX
UNITS
fSMPL
Sampling Frequency
l
250
ksps
tCONV
Conversion Time
l
2500
ns
tACQ
Acquisition Time
l
1485
ns
t4
CNVST Low Time
l
20
l
250
t5
CNVST High Time
t6
CNVST↓ to BUSY Delay
t7
RESET Pulse Width
CONDITIONS
MIN
CL = 15pF
ns
ns
15
l
(Note 9)
TYP
ns
l
5
ns
t8
SCLK Period
l
12.5
ns
t9
SCLK High Time
l
4
ns
t10
SCLK Low Time
l
4
ns
tr , tf
SCLK Rise and Fall Times
t11
SDIN Setup Time
l
2
t12
SDIN Hold Time
l
1
l
2
(Note 10)
1
CL = 15pF
t13
SDOUT Delay After SCLK↑
t14
SDOUT Delay After CS↓
l
t15
CS↓ to SCLK Setup Time
l
µs
ns
ns
8
ns
8
ns
20
ns
t16
Data Valid to BUSY↓
l
1
ns
t17
Data Access Time after RD↓ or BYTESWAP↑
l
10
ns
t18
Bus Relinquish Time
l
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground.
Note 3: When these pin voltages are taken below ground or above
AVP, DVP or OVP, they will be clamped by internal diodes. This product can
handle input currents up to 100mA below ground or above AVP, DVP or
OVP without latchup.
Note 4: AVP = DVP = OVP = 5V, fSMPL = 250ksps, external reference equal
to 4.096V unless otherwise noted.
Note 5: Recommended operating conditions.
Note 6: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
tWIDTH
0.5V
tDELAY
ns
Note 7: Bipolar zero error is the offset voltage measured from –0.5LSB
when the output code flickers between 0000 0000 0000 0000 and 1111
1111 1111 1111. Bipolar full-scale error is the worst-case of –FS or +FS
untrimmed deviation from ideal first and last code transitions and includes
the effect of offset error.
Note 8: All specifications in dB are referred to a full-scale ±4.096V input
with a 4.096V reference voltage.
Note 9: t13 of 8ns maximum allows a shift clock frequency up to
2 • (t13 + tSETUP) for falling edge capture with 50% duty cycle and up to
80MHz for rising capture. tSETUP is the set-up time of the receiving logic.
Note 10: Guaranteed by design.
Note 11: Temperature coefficient is calculated by dividing the maximum
change in output voltage by the specified temperature range.
4V
4V
0.5V
10
tDELAY
50%
50%
4V
0.5V
239116F01
Figure 1. Voltage Levels for Timing Specifications
239116f
LTC2391-16
Typical Performance Characteristics TA = 25°C, fSMPL = 250ksps, unless otherwise noted.
Integral Nonlinearity
vs Output Code
Differential Nonlinearity
vs Output Code
DC Histogram
(External Reference)
2000000
1.5
2.0
1.5
1800000
1.0
1600000
0.5
0
–0.5
1400000
0.5
COUNTS
DNL ERROR (LSB)
INL ERROR (LSB)
1.0
0
–0.5
–2.0
200000
0
16384
32768
49152
65536
–1.5
0
16384
32768
49152
OUTPUT CODE
DC Histogram
(Internal Reference)
4.0970
1600000
4.0965
1200000
1000000
800000
600000
400000
32766
32768
CODE
32770
32772
200000
Offset Error vs Temperature
1.0
TC = 4ppm/°C
0.8
OFFSET ERROR (LSB)
1800000
REFERENCE OUTPUT (V)
4.0975
1400000
32764
239116 G03
Internal Reference Output
vs Temperature
2000000
0
0
65536
239116 G02
239116 G01
COUNTS
800000
400000
–1.0
OUTPUT CODE
4.0960
4.0955
4.0950
4.0945
4.0940
4.0935
0.6
0.4
0.2
4.0930
32764
32766
32768
CODE
32770
4.0925
–55 –35 –15
32772
0
8
–20
6
–4
–40
–60
–80
–100
–120
–80
–100
–120
–6
–140
–8
–160
–160
5 25 45 65 85 105 125
TEMPERATURE (°C)
239116 G07
–180
0
25
75
50
FREQUENCY (kHz)
100
SNR = 93.4dB
THD –98.7dB
SINAD = 92.3dB
SFDR = 106.6dB
–60
–140
–10
–55 –35 –15
16k Point FFT fS = 250ksps,
fIN = 100kHz
–20
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
–2
0
SNR = 94dB
THD –103dB
SINAD = 93.5dB
SFDR = 104dB
–40
0
239116 G06
16k Point FFT fS = 250ksps,
fIN = 20kHz
10
2
5 25 45 65 85 105 125
TEMPERATURE (°C)
239116 G05
Full-Scale Error vs Temperature
4
0
–55 –35 –15
5 25 45 65 85 105 125
TEMPERATURE (°C)
239116 G04
FULL-SCALE ERROR (LSB)
1000000
600000
–1.0
–1.5
1200000
125
239116 G08
–180
0
25
75
50
FREQUENCY (kHz)
100
125
239116 G09
239116f
LTC2391-16
Typical Performance Characteristics TA = 25°C, fSMPL = 250ksps, unless otherwise noted.
THD, Harmonics
vs Input Frequency
SNR, SINAD vs Input Frequency
–70
SNR
–75
SINAD
THD, HARMONICS (dBFS)
SNR, SINAD (dBFS)
94
92
90
88
86
84
–80
95
–85
–90
–95
THD
–100
3RD
–105
94
SINAD
2ND
–115
0
25
50
75
INPUT FREQUENCY (kHz)
–120
100
0
50
25
75
INPUT FREQUENCY (kHz)
30
94.5
3RD
2ND
POWER SUPPLY CURRENT (mA)
SNR
THD
SINAD
94.0
93.5
–115
5 25 45 65 85 105 125
TEMPERATURE (°C)
93.0
–40
–30
–20
–10
10
5
1
10
100
SAMPLING FREQUENCY (kHz)
1000
239116 G15
Power-Down Current
vs Temperature
90
80
POWER-DOWN CURRENT (µA)
AVP
14
12
10
8
DVP
4
2
15
239116 G14
18
6
20
INPUT LEVEL (dB)
Supply Current vs Temperature
16
25
0
0.1
0
239116 G13
POWER SUPPLY CURRENT (mA)
–120
–55 –35 –15
Supply Current vs Sampling
Frequency
95.0
SNR, SINAD (dBFS)
–110
239116 G12
SNR, SINAD vs Input Level
–95
–100
5 25 45 65 85 105 125
TEMPERATURE (°C)
239116 G11
THD, Harmonics at fIN = 20kHz
vs Temperature
–105
92
–55 –35 –15
100
239116 G10
THD, HARMONICS (dBFS)
SNR
93
–110
82
80
96
SNR, SINAD (dBFS)
96
SNR, SINAD at fIN = 20kHz
vs Temperature
60
50
40
30
20
10
0VP
0
–55 –35 –15
70
5 25 45 65 85 105 125
TEMPERATURE (°C)
239116 G16
DVP
AVP
0VP
0
–55 –35 –15 5 25 45 65 85 105 125
TEMPERATURE (°C)
239116 G17
239116f
LTC2391-16
Pin Functions
GND (Pins 1, 5, 7, 20, 35, 41, 44, 48, Exposed Pad Pin
49): Ground. All GND pins must be connected to a solid
ground plane.
AVP (Pins 2, 40, 45, 46, 47): 5V Analog Power Supply.
The range of AVP is 4.75V to 5.25V. Bypass AVP to GND
with a good quality 0.1µF and a 10µF ceramic capacitor
in parallel.
DVP (Pins 3, 19): 5V Digital Power Supply. The range of
DVP is 4.75V to 5.25V. Bypass DVP to GND with a good
quality 0.1µF and a 10µF ceramic capacitor in parallel.
SER/PAR (Pin 4): Serial/Parallel Selection Input. This pin
controls the digital interface. A logic high on this pin selects the serial interface and a logic low selects the parallel
interface. In the serial mode the non-active digital outputs
are high impedance.
OB/2C (Pin 6): Offset Binary/Two’s Complement Input.
When OB/2C is high, the digital output is offset binary.
When low, the MSB is inverted resulting in two’s complement output.
BYTESWAP (Pin 8): BYTESWAP Input. With BYTESWAP
low, data will be output with Pin 28 (D15) being the
MSB and Pin 9 (D0) being the LSB. With BYTESWAP
high, the upper eight bits and the lower eight bits will
be switched. The MSB is output on Pin 16 and Bit 8 is
output on Pin 9. Bit 7 is output on Pin 28 and the LSB is
output on Pin 21.
D0 (Pin 9): Data Bit 0. When SER/PAR = 0 this pin is Bit 0
of the parallel port data output bus.
D1 (Pin 10): Data Bit 1. When SER/PAR = 0 this pin is
Bit 1 of the parallel port data output bus.
D2 (Pin 11): Data Bit 2. When SER/PAR = 0 this pin is
Bit 2 of the parallel port data output bus.
D3 (Pin 12): Data Bit 3. When SER/PAR = 0 this pin is
Bit 3 of the parallel port data output bus.
D4 (Pin 13): Data Bit 4. When SER/PAR = 0 this pin is
Bit 4 of the parallel port data output bus.
D5 (Pin 14): Data Bit 5. When SER/PAR = 0 this pin is
Bit 5 of the parallel port data output bus.
D6 (Pin 15): Data Bit 6. When SER/PAR = 0 this pin is
Bit 6 of the parallel port data output bus.
D7 (Pin 16): Data Bit 7. When SER/PAR = 0 this pin is
Bit 7 of the parallel port data output bus.
OGND (Pin 17): Digital Ground for the Input/Output
Interface.
OVP (Pin 18): Digital Power Supply for the Input/Output
Interface. The range for OVP is 1.8V to 5V. Bypass OVP
to OGND with a good quality 4.7µF ceramic capacitor
close to the pin.
D8 (Pin 21): Data Bit 8. When SER/PAR = 0 this pin is
Bit 8 of the parallel port data output bus.
D9/SDIN (Pin 22): Data Bit 9/Serial Data Input. When
SER/PAR = 0 this pin is Bit 9 of the parallel port data
output bus. When SER/PAR = 1, (serial mode) this is
the serial data input. SDIN can be used as a data input to
daisy-chain two or more conversion results into a single
SDOUT line. The digital data level on SDIN is output on
SDOUT with a delay of 16 SCLK periods after the start of
the read sequence.
D10/SDOUT (Pin 23): Data Bit 10/Serial Data Ouput. When
SER/PAR = 0 this pin is Bit 10 of the parallel port data
output bus. When SER/PAR = 1, (serial mode) this is the
serial data output. The conversion result can be clocked
out serially on this pin synchronized to SCLK. The data
is clocked out MSB first on the rising edge of SCLK and
is valid on the falling edge of SCLK. The data format is
determined by the logic level of OB/2C.
D11/SCLK (Pin 24): Data Bit 11/Serial Clock Input. When
SER/PAR = 0 this pin is Bit 11 of the parallel port data
output bus. When SER/PAR = 1, (serial mode) this is the
serial clock input.
D12 (Pin 25): Data Bit 12. When SER/PAR = 0 this pin is
Bit 12 of the parallel port data output bus.
D13 (Pin 26): Data Bit 13. When SER/PAR = 0 this pin is
Bit 13 of the parallel port data output bus.
D14 (Pin 27): Data Bit 14. When SER/PAR = 0 this pin is
Bit 14 of the parallel port data output bus.
D15 (Pin 28): Data Bit 15. When SER/PAR = 0 this pin is
Bit 15 of the parallel port data output bus. The data format
is determined by the logic level of OB/2C.
239116f
LTC2391-16
Pin Functions
BUSY (Pin 29): Busy Output. A low-to-high transition occurs when a conversion is started. It stays high until the
conversion is complete. The falling edge of BUSY can be
used as the data-ready clock signal.
RD (Pin 30): Read Data Input. When CS and RD are both
low, the parallel and serial output bus is enabled.
CS (Pin 31): Chip Select. When CS and RD are both low,
the parallel and serial output bus is enabled. CS is also
used to gate the external shift clock.
RESET (Pin 32): Reset Input. When high the LTC2391-16
is reset, and if this occurs during a conversion, the conversion is halted and the data bus is put into Hi-Z mode.
PD (Pin 33): Power-Down Input. When high, the
LTC2391-16 is powered down and subsequent conversion
requests are ignored. Before entering power shutdown,
the digital output data should be read.
CNVST (Pin 34): Conversion Start Input. A falling edge
on CNVST puts the internal sample-and-hold into the hold
mode and starts a conversion. CNVST is independent of
CS.
VCM (Pin 36): Common Mode Analog Output. Typically
the output voltage is 2.048V. Bypass to GND with a 10µF
capacitor.
REFOUT (Pin 37): Internal Reference Output. Nominal
output voltage is 4.096V. Connect this pin to REFIN if using the internal reference. If an external reference is used
connect REFOUT to ground.
REFIN (Pin 38): Reference Input. An external reference
can be applied to REFIN if a more accurate reference is
required. If an external reference is used tie REFOUT to
ground.
REFSENSE (Pin 39): Reference Input Sense. Leave
REFSENSE open when using the internal reference. If
an external reference is used connect REFSENSE to the
ground pin of the external reference.
IN–, IN+ (Pin 42, Pin 43): Differential Analog Inputs.
IN+ – (IN–) can range up to ±VREF .
239116f
LTC2391-16
FUNCTIONAL Block Diagram
AVP DVP OVP
LTC2391-16
16-BIT OR
TWO BYTE
SDIN
IN+
16-BIT SAMPLING ADC
IN–
16-BIT
SDOUT
PARALLEL/
SERIAL
INTERFACE
SCLK
CS
1x BUFFER
RD
REFIN
SER/PAR
BYTESWAP
REFOUT
VCM
OB/2C
4.096V
REFERENCE
BUSY
CONTROL LOGIC
REFSENSE
CNVST
PD
RESET
GND OGND
239116BD
TIMING DiagramS
Conversion Timing Using the Parallel Interface
CS, RD = 0
CNVST
ACQUIRE
BUSY
CONVERT
D[15:0]
PREVIOUS CONVERSION
CURRENT CONVERSION
239116 TD01
Conversion Timing Using the Serial Interface
CS, RD = 0
CNVST
ACQUIRE
BUSY
CONVERT
SCLK
D14 D12 D10 D8 D6 D4 D2 D0
SDOUT
239116 TD02
D15 D13 D11 D9 D7 D5 D3 D1
239116f
10
LTC2391-16
OVERVIEW
The LTC2391-16 is a low noise, high speed 16-bit successive approximation register (SAR) ADC. Operating
from a single 5V supply, the LTC2391-16 supports a
large ±4.096V fully differential input range, making it ideal
for high performance applications which require a wide
dynamic range. The LTC2391-16 achieves ±2LSB INL max,
no missing codes at 16 bits and 94dB SNR (typ).
The LTC2391-16 includes a precision internal reference with
a guaranteed 0.5% initial accuracy and a ±20ppm/°C (max)
temperature coefficient. Fast 250ksps throughput with no
cycle latency in both parallel and serial interface modes
makes the LTC2391-16 ideally suited for a wide variety
of high speed applications. An internal oscillator sets the
conversion time, easing external timing considerations.
The LTC2391-16 dissipates only 95mW at 250ksps, while
both nap and sleep power-down modes are provided to
further reduce power during inactive periods.
CONVERTER OPERATION
The LTC2391-16 operates in two phases. During the acquisition phase, the charge redistribution capacitor D/A
converter (CDAC) is connected to the IN+ and IN– pins
to sample the differential analog input voltage. A falling
edge on the CNVST pin initiates a conversion. During the
conversion phase, the 16-bit CDAC is sequenced through a
successive approximation algorithm, effectively comparing
the sampled input with binary-weighted fractions of the
reference voltage (e.g., VREF/2, VREF/4 … VREF/65536)
using the differential comparator. At the end of conversion,
the CDAC output approximates the sampled analog input.
The ADC control logic then prepares the 16-bit digital
output code for parallel or serial transfer.
OUTPUT CODE (TWO’S COMPLEMENT)
Applications Information
011...111
000...001
000...000
111...111
111...110
100...001
FSR = +FS – –FS
1LSB = FSR/65536
100...000
–FSR/2
–1 0V 1
FSR/2 – 1LSB
LSB
LSB
INPUT VOLTAGE (V)
239116 F02
Figure 2. LTC2391-16 Two’s Complement Transfer Function
ANALOG INPUT
The analog inputs of the LTC2391-16 are fully differential
in order to maximize the signal swing that can be digitized.
The analog inputs can be modeled by the equivalent circuit
shown in Figure 3. The diodes at the input provide ESD protection. The analog inputs should not exceed the supply or
go below ground. In the acquisition phase, each input sees
approximately 40pF (CIN) from the sampling CDAC in series
with 50Ω (RIN) from the on-resistance of the sampling
switch. Any unwanted signal that is common to both
inputs will be reduced by the common mode rejection of
the ADC. The inputs draw only one small current spike
while charging the CIN capacitors during acquisition.
During conversion, the analog inputs draw only a small
leakage current.
AVP
RIN
IN+
CIN
BIAS
VOLTAGE
AVP
TRANSFER FUNCTION
The LTC2391-16 digitizes the full-scale voltage of 2 • VREF
into 216 levels, resulting in an LSB size of 125µV when VREF
= 4.096V. The ideal transfer function for two’s complement
is shown in Figure 2. The OB/2C pin selects either offset
binary or two’s complement format.
BIPOLAR
ZERO
011...110
IN–
RIN
CIN
239116 F03
Figure 3. The Equivalent Circuit for the
Differential Analog Input of the LTC2391-16
239116f
11
LTC2391-16
Applications Information
INPUT DRIVE CIRCUITS
A low impedance source can directly drive the high impedance inputs of the LTC2391-16 without gain error. A high
impedance source should be buffered to minimize settling
time during acquisition and to optimize the distortion
performance of the ADC.
For best performance, a buffer amplifier should be used
to drive the analog inputs of the LTC2391-16. The amplifier provides low output impedance to allow for fast
settling of the analog signal during the acquisition phase.
It also provides isolation between the signal source and
the ADC inputs which draw a small current spike during
acquisition.
Input Filtering
The noise and distortion of the buffer amplifier and other
circuitry must be considered since they add to the ADC
noise and distortion. Noisy input circuitry should be filtered
prior to the analog inputs to minimize noise. A simple
1‑pole RC filter is sufficient for many applications.
Large filter RC time constants slow down the settling at
the analog inputs. It is important that the overall RC time
constants be short enough to allow the analog inputs to
completely settle to 16-bit resolution within the acquisition time (tACQ).
High quality capacitors and resistors should be used in the
RC filter since these components can add distortion. NPO
and silver mica type dielectric capacitors have excellent
linearity. Carbon surface mount resistors can generate
distortion from self heating and from damage that may
occur during soldering. Metal film surface mount resistors
are much less susceptible to both problems.
Single-to-Differential Conversion
For single-ended input signals, a single-ended-to-differential conversion circuit must be used to produce a differential signal at the ADC inputs. The LT6350 ADC driver is
recommended for performing a single-ended-to-differential
conversion, as shown in Figure 4a. Its low noise and good
DC linearity allows the LTC2391-16 to meet full data sheet
specifications. An alternative solution using two op amps
is shown in Figure 4b. Using two LT®1806 op amps, the
circuit achieves 94dB signal-to-noise ratio (SNR). For a
20kHz input signal, the input of the LTC2391-16 has been
bandwidth limited to about 25kHz.
ADC REFERENCE
A low noise, low temperature drift reference is critical to
achieving the full data sheet performance of the ADC. The
LTC2391-16 provides an excellent internal reference with
a ±20ppm/°C (max) temperature coefficient. For better
accuracy, an external reference can be used.
The high speed, low noise internal reference buffer is used
for both internal and external reference applications. It
cannot be bypassed.
ANALOG
INPUT
0V TO 4.096V
+
LT1806
–
249Ω
301Ω
249Ω
ANALOG INPUT
0V TO 4.096V
IN+
2200pF
LT6350
249Ω
301Ω
LTC2391-16
Figure 4a. Recommended Single-Ended-to-Differential
Conversion Circuit Using the LT6350 ADC Driver
0.013µF
LTC2391-16
IN–
239116 F04b
–
IN–
SINGLE-ENDEDTO-DIFFERENTIAL
DRIVER
249Ω
IN+
239116 F04a
COMMON
MODE
VOLTAGE
LT1806
+
Figure 4b. Alternative Single-Ended-to-Differential
Conversion Circuit Using Two LT1806 Op Amps
239116f
12
LTC2391-16
Applications Information
Internal Reference
DYNAMIC PERFORMANCE
To use the internal reference, simply tie the REFOUT and
REFIN pins together. This connects the 4.096V output of
the internal reference to the input of the internal reference
buffer. The output impedance of the internal reference is
approximately 2.6kΩ and the input impedance of the internal reference buffer is about 85kΩ. It is recommended
that this node be bypassed to ground with a 1µF or larger
capacitor to filter the output noise of the internal reference.
The REFSENSE pin should be left floating when using the
internal reference.
Fast fourier transform (FFT) techniques are used to test
the ADC’s frequency response, distortion and noise at the
rated throughput. By applying a low distortion sine wave
and analyzing the digital output using an FFT algorithm,
the ADC’s spectral content can be examined for frequencies outside the fundamental. The LTC2391-16 provides
guaranteed tested limits for both AC distortion and noise
measurements.
External Reference
An external reference can be used with the LTC2391‑16
when even higher performance is required. The
LT1790‑4.096 offers 0.05% (max) initial accuracy and
10ppm/°C (max) temperature coefficient. When using an
external reference, connect the reference output to the
REFIN pin and connect the REFOUT pin to ground. The
REFSENSE pin should be connected to the ground of the
external reference.
0
The signal-to-noise and distortion ratio (SINAD) is the
ratio between the RMS amplitude of the fundamental input
frequency and the RMS amplitude of all other frequency
components at the A/D output. The output is band-limited
to frequencies from above DC and below half the sampling
frequency. Figure 5 shows that the LTC2391-16 achieves
a typical SINAD of 93.5dB at a 250ksps sampling rate
with a 20kHz input.
SNR = 94dB
THD –103dB
SINAD = 93.5dB
SFDR = 104dB
–20
–40
AMPLITUDE (dBFS)
Signal-to-Noise and Distortion Ratio (SINAD)
–60
–80
–100
–120
–140
–160
–180
0
25
75
50
FREQUENCY (kHz)
100
125
239116 G08
Figure 5. 16k Point FFT of the LTC2391-16, fS = 250ksps, fIN = 20kHz
239116f
13
LTC2391-16
Applications Information
Signal-to-Noise Ratio (SNR)
Power Supply Sequencing
The signal-to-noise ratio (SNR) is the ratio between the
RMS amplitude of the fundamental input frequency and
the RMS amplitude of all other frequency components
except the first five harmonics and DC. Figure 5 shows
that the LTC2391-16 achieves a typical SNR of 94dB at a
250kHz sampling rate with a 20kHz input.
The LTC2391-16 does not have any specific power supply sequencing requirements. Care should be taken to
observe the maximum voltage relationships described in
the Absolute Maximum Ratings section. The LTC2391‑16
has a power-on reset (POR) circuit. With the POR, the
result of the first conversion is valid after power has
been applied to the ADC. The LTC2391-16 will reset itself
if the power supply voltage drops below 2.5V. Once the
supply voltage is brought back to its nominal value, the
POR will reinitialize the ADC and it will be ready to start
a new conversion.
Total Harmonic Distortion (THD)
Total harmonic distortion (THD) is the ratio of the RMS sum
of all harmonics of the input signal to the fundamental itself.
The out-of-band harmonics alias into the frequency band
between DC and half the sampling frequency (fSMPL/2).
THD is expressed as:
THD = 20 log
V22 + V32 + V42...VN2
V1
where V1 is the RMS amplitude of the fundamental frequency and V2 through VN are the amplitudes of the second
through Nth harmonics.
Nap Mode
The LTC2391-16 can be put into the nap mode after a
conversion has been completed to reduce the power
consumption between conversions. In this mode some
of the circuitry on the device is turned off. Nap mode is
enabled by keeping CNVST low between conversions. When
the next conversion is requested, bring CNVST high and
hold for at least 250ns, then start the next conversion by
bringing CNVST low. See Figure 6.
POWER CONSIDERATIONS
Power Shutdown Mode
The LTC2391-16 provides three sets of power supply
pins: the analog 5V power supply (AVP), the digital 5V
power supply (DVP) and the digital input/output interface
power supply (OVP). The flexible OVP supply allows the
LTC2391‑16 to communicate with any digital logic operating
between 1.8V and 5V, including 2.5V and 3.3V systems.
When PD is tied high, the LTC2391-16 enters power shutdown and subsequent requests for conversion are ignored.
Before entering power shutdown, the digital output data
needs to be read. However, if a request for power shutdown
(PD = high) occurs during a conversion, the conversion
will finish and then the device will power down. The data
t5
CNVST
tCONV
tACQ
BUSY
NAP
NAP MODE
239116 F06
Figure 6. Nap Mode Timing for the LTC2391-16
239116f
14
LTC2391-16
Applications Information
from that conversion can be read after PD = low is applied. In this mode, power consumption drops to a typical
value of 175µW from 95mW. This mode can be used if the
LTC2391-16 is inactive for a long period of time and the
user wants to minimize the power dissipation.
Recovery from Power Shutdown Mode
Once the PD pin is returned to a low level, ending the
power shutdown request, the internal circuitry will begin
to power up. If the internal reference is used, the 2.6kΩ
output impedance with the 1µF bypass capacitor on the
REFIN/REFOUT pins will be the main time constant for
the power-on recovery time. If an external reference is
used, typically allow 5ms for recovery before initiating a
new conversion.
Power Dissipation vs Sampling Frequency
The power dissipation of the LTC2391-16 will decrease
as the sampling frequency is reduced when nap mode
is activated. See Figure 7. In nap mode, a portion of the
circuitry on the LTC2391-16 is turned off after a conversion
has been completed. Increasing the time allowed between
conversions lowers the average power.
POWER SUPPLY CURRENT (mA)
30
25
20
The LTC2391-16 conversion is controlled by CNVST. A
falling edge on CNVST will start a conversion. CS and RD
control the digital interface on the LTC2391-16. When
either CS or RD is high, the digital outputs are high
impedance.
CNVST Timing
The LTC2391-16 conversion is controlled by CNVST. A
falling edge on CNVST will start a conversion. Once a
conversion has been initiated, it cannot be restarted until
the conversion is complete. For optimum performance
CNVST should be a clean low jitter signal. Converter status
is indicated by the BUSY output which remains high while
the conversion is in progress. To ensure no errors occur
in the digitized results return the rising edge either within
40ns from the start of the conversion or wait until after
the conversion has been completed. The CNVST timing
needed to take advantage of the reduced power mode of
operation is described in the Nap Mode section.
Internal Conversion Clock
The LTC2391-16 has an internal clock that is trimmed
to achieve a maximum conversion time of 2500ns. No
external adjustments are required and with a maximum
acquisition time of 1485ns, a throughput performance of
250ksps is guaranteed.
DIGITAL INTERFACE
15
The LTC2391-16 allows both parallel and serial digital
interfaces. The flexible OVP supply allows the LTC2391-16
to communicate with any digital logic operating between
1.8V and 5V, including 2.5V and 3.3V systems.
10
5
0
0.1
TIMING AND CONTROL
1
10
100
SAMPLING FREQUENCY (kHz)
1000
239116 G15
Figure 7. Power Dissipation of the LTC2391-16
Decreases with Decreasing Sampling Frequency
239116f
15
LTC2391-16
Applications Information
Parallel Modes
The parallel output data interface is active when the
SER/PAR pin is tied low and when both CS and RD are low.
The output data can be read as a 16-bit word as shown
in Figures 8, 9 and 10 or it can be read as two 8-bit bytes
by using the BYTESWAP pin. As shown in Figure 11, with
the BYTESWAP pin low, the first eight MSBs are output on
the D15 to D8 pins and the eight LSBs are output on the
D7 to DO pins. When BYTESWAP is taken high, the eight
LSBs now are output on the D15 to D8 pins and the eight
MSBs are output on the D7 to D0 pins.
Serial Modes
The serial output data interface is active when the
SER/PAR pin is tied high and when both CS and RD are
low. The serial output data will be clocked out on the
SDOUT pin when an external clock is applied to the SCLK
pin. Clocking out the data after the conversion will yield
the best performance. With a shift clock frequency of at
least 15MHz, a 250ksps throughput is achieved. The serial
output data changes state on the rising edge of SCLK and
can be captured on the falling edge of SCLK. D15 remains
valid till the first rising edge of shift clock after the first
falling edge of shift clock. The non-active digital outputs
are high impedance when operating in the serial mode.
CS = RD = 0
The SDIN input pin is used to daisy-chain multiple converters. This is useful for applications where hardware
constraints may limit the number of lines needed to
interface to a large number of converters. For example,
if two devices are cascaded, the MSB of the first device
will appear at the output after 17 SCLK cycles. The first
MSB is clocked in on the falling edge of the first SCLK.
See Figure 12.
Data Format
When OB/2C is high, the digital output is offset binary.
When low, the MSB is inverted resulting in two’s complement output. This pin is active in both the parallel and
serial modes of operation.
Reset
When the RESET pin is high, the LTC2391-16 is reset, and
if this occurs during a conversion, the conversion is halted
and the data bus is put into Hi-Z mode. In reset, requests
for new conversions are ignored. Once RESET returns low,
the LTC2391-16 is ready to start a new conversion after
the acquisition time has been met. See Figure 13.
t4
CNVST
BUSY
tCONV
t6
DATA BUS D[15:0]
PREVIOUS CONVERSION
t16
NEW
239116 F08
Figure 8. Read the Parallel Data Continuously.
The Data Bus is Always Driven and Can’t Be Shared
239116f
16
LTC2391-16
Applications Information
CS
RD
BUSY
Hi-Z
DATA BUS D[15:0]
Hi-Z
CURRENT
CONVERSION
239116 F09
t18
t17
Figure 9. Read the Parallel Data After the Conversion
CS = 0
t4
CNVST, RD
BUSY
tCONV
t6
DATA BUS D[15:0]
Hi-Z
Hi-Z
PREVIOUS
CONVERSION
239116 F09
t17
t18
Figure 10. Read the Parallel Data During the Conversion
8-BIT INTERFACE
CS, RD
BYTESWAP
D[15:8]
Hi-Z
HIGH BYTE
t17
Hi-Z
LOW BYTE
t17
239116 F11
t18
Figure 11. 8-Bit Parallel Interface Using the BYTESWAP Pin
239116f
17
LTC2391-16
Applications Information
RD = 0
SCLK STARTS LOW
t15
CS
BUSY
t8
t9
SCLK
t10
1
2
4
3
15
16
17
18
t13
SDOUT
(ADC 2)
Hi-Z
D14
D15
t14
SDIN
(ADC 2)
D13
D1
D0
X15
X14
t12
t11
X15
X14
X13
X1
X0
SCLK STARTS HIGH
RD = 0
CS
BUSY
t10
SCLK
t8
1
t9
2
3
4
15
16
17
18
t13
SDOUT
(ADC 2)
Hi-Z
D15
t14
SDIN
(ADC 2)
D14
D13
D1
D0
X15
X14
t12
t11
X15
X14
X13
X1
X0
CNVST IN
CS IN
RD IN
SCLK IN
LTC2391-16
LTC2391-16
CNVST
CS
RD
SCLK
SDIN SDOUT
CNVST
CS
RD
SCLK
SDIN SDOUT
ADC 1
ADC 2
DATA OUT
239116 F12
Figure 12. Serial Interface with External Clock. Read After
the Conversion. Daisy-Chain Multiple Converters
239116f
18
LTC2391-16
Applications Information
t7
RESET
tACQ
CVNST
DATA BUS D[15:0]
Hi-Z
239116 F13
Figure 13. RESET Pin Timing
239116f
19
LTC2391-16
Applications Information
BOARD LAYOUT
Recommended Layout
To obtain the best performance from the LTC2391-16, a
printed circuit board (PCB) is recommended. Layout for
the printed circuit board should ensure the digital and
analog signal lines are separated as much as possible.
In particular, care should be taken not to run any digital
clocks or signals alongside analog signals or underneath
the ADC.
The following is an example of a recommended PCB layout.
A single solid ground plane is used. Bypass capacitors to
the supplies are placed as close as possible to the supply
pins. Low impedance common returns for these bypass
capacitors are essential to the low noise operation of the
ADC. The analog input traces are screened by ground.
For more details and information refer to DC1500A, the
evaluation kit for the LTC2391-16
Partial Schematic of Demoboard
CNVST
34
39
CNVST
R2
249Ω
1%
43
C54
OPT
REFIN
LTC2391-16
44
C55
OPT
IN–
VCM OB/2C
36
C53
10µF
GND SER/PAR RESET PD
5
6
C31
0.1µF
C30
10µF
5V
47
46
37
REFOUT
BUSY
D15
D14
D13
D12
D11/SCLK
D10/SDOUT
D9/SDIN
D8
D7
D6
D5
D4
D3
D2
D1
D0
BYTESWAP
GND
IN+
C2
2200pF
1206 NPO
R3
249Ω
1%
38
REFSENSE
C36
1µF
45
40
4
32
C29
0.1µF
R24
1.0Ω
BUSY
D15
D14
D13
D12
D11/SCLK
D10/SDOUT
D9/SDIN
D8
D7
D6
D5
D4
D3
D2
D1
D0
CS RD
31 30
C28
10µF
3.3V
2
AVP/AVL AVP AVP AVP AVP
33
29
28
27
26
25
24
23
22
21
16
15
14
13
12
11
10
9
8
7
19
3
C40
4.7µF
18
DVP DVP/DVL OVP
LTC2391-16
GND GND GND GND GND GND OGND
48
44
41
35
20
1
17
239116 TA02
239116f
20
LTC2391-16
Applications Information
Partial Top Silkscreen
Partial Layer 1 Component Side
Partial Layer 2 Ground Plane
239116f
21
LTC2391-16
Package Description
UK Package
48-Lead Plastic QFN (7mm × 7mm)
(Reference LTC DWG # 05-08-1704)
0.70 p0.05
5.15 p 0.05
5.50 REF
6.10 p0.05 7.50 p0.05
(4 SIDES)
5.15 p 0.05
PACKAGE OUTLINE
0.25 p0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
7.00 p 0.10
(4 SIDES)
0.75 p 0.05
R = 0.10
TYP
R = 0.115
TYP
47 48
0.40 p 0.10
PIN 1 TOP MARK
(SEE NOTE 6)
1
2
PIN 1
CHAMFER
C = 0.35
5.50 REF
(4-SIDES)
5.15 p 0.10
5.15 p 0.10
0.200 REF
0.00 – 0.05
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WKKD-2)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
(UK48) QFN 0406 REV C
0.25 p 0.05
0.50 BSC
BOTTOM VIEW—EXPOSED PAD
239116f
22
LTC2391-16
Package Description
LX Package
48-Lead Plastic LQFP (7mm × 7mm)
(Reference LTC DWG # 05-08-1760 Rev Ø)
7.15 – 7.25
9.00 BSC
5.50 REF
7.00 BSC
48
0.50 BSC
1
2
48
SEE NOTE: 4
1
2
9.00 BSC
5.50 REF
7.00 BSC
7.15 – 7.25
0.20 – 0.30
A
A
PACKAGE OUTLINE
C0.30 – 0.50
1.30 MIN
RECOMMENDED SOLDER PAD LAYOUT
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
1.60
1.35 – 1.45 MAX
11° – 13°
R0.08 – 0.20
GAUGE PLANE
0.25
0° – 7°
11° – 13°
0.09 – 0.20
1.00 REF
0.50
BSC
0.17 – 0.27
0.05 – 0.15
LX48 LQFP 0907 REVØ
0.45 – 0.75
SECTION A – A
NOTE:
1. PACKAGE DIMENSIONS CONFORM TO JEDEC #MS-026 PACKAGE OUTLINE
2. DIMENSIONS ARE IN MILLIMETERS
3. DIMENSIONS OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.25mm ON ANY SIDE, IF PRESENT
4. PIN-1 INDENTIFIER IS A MOLDED INDENTATION, 0.50mm DIAMETER
5. DRAWING IS NOT TO SCALE
239116f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
23
LTC2391-16
Typical Application
ADC Driver: Single-Ended Input to Differential Output
5V
249Ω
0.1µF
VIN
0V to 4V
+
–
+IN1
SHDN
+
–
V+
5V
OUT2
AIN–
LT6350
+IN2
– IN1
–
+
2200pF
AIN+
V–
OUT1
249Ω
0.1µF
499Ω
2V
LTC2391-16
239116 TA03
0.1µF
–5V
Related Parts
PART NUMBER
LTC1411
DESCRIPTION
14-Bit 2.5Msps Parallel ADC
LTC1609
16-Bit 200ksps Serial ADC
LTC1864
LTC1864L
LTC1865
LTC1865L
LTC1867
16-Bit 250ksps Serial ADC
16-Bit 150ksps Serial ADC
16-Bit 250ksps Serial ADC
16-Bit 150ksps Serial ADC
16-Bit, 200ksps 8-Channel ADC
LTC2355-14/LTC2356-14
LTC2392-16
14-Bit, 3.5Msps Serial ADCs
16-Bit, 500ksps Parallel/Serial ADC
LTC2393-16
16-Bit, 1Msps Parallel/Serial ADC
DACs
LTC2641
LTC2630
References
LT1236
LTC6655
Amplifiers
LT1469
LT1806/LT1807
LTC6200/LTC6200-5/
LTC6200-10
LT6350
COMMENTS
5V Supply, 1-Channel, 80dB SNR, ±1.8V Input Range,
SSOP-36 Package
5V Supply, 1-Channel, 87dB SNR, Resistor-Selectable Inputs:
±10V, ±5V, ±3.3V, 0V to 4V, 0V to 5V, 0V to 10V
5V Supply, 1-Channel, 4.3mW, MSOP-8 Package
3V Supply, 1-Channel, 1.3mW, MSOP-8 Package
5V Supply, 2-Channel, 4.3mW, MSOP-8 Package
3V Supply, 2-Channel, 1.3mW, MSOP-8 Package
5V Supply, 6.5mW, SSOP-16 Package, Pin Compatible with
LTC1863, LTC1867L
3.3V Supply, 1-Channel, 18mW, MSOP-10 Package
5V Supply, Differential Input, 94dB SNR, ±4.096V Input Range,
Pin Compatible with the LTC2393-16, LTC2391-16
5V Supply, Differential Input, 94dB SNR, ±4.096V Input Range,
Pin Compatible with the LTC2392-16, LTC2391-16
16-Bit Single Serial VOUT DACs
12-/10-/8-Bit Single VOUT DACs
±1LSB INL, ±1LSB DNL, MSOP-8 Package, 0V to 5V Output
SC70 6-Pin Package, Internal Reference, ±1LSB INL (12 Bits)
Precision Reference in SO-8 Package
0.25ppmP-P Noise, Low Drift Precision Reference
5V, 10V; 0.05% Initial Accuracy (Max); 5ppm Tempco (Max)
0.025% Initial Accuracy (Max), 2ppm Tempco (Max),
0.25ppmP-P Noise (0.1Hz to 10Hz) in MSOP-8 Package
Dual 90MHz, 22V/µs Dual Op Amps in 4mm × 4mm
DFN-12 Package
325MHz, Single/Dual Precision Op Amps in TSOT23-6,
MSOP-8 Packages
165MHz/800MHz/1.6GHz Op Amps with
Unity Gain/AV = 5/AV = 10
Low Noise Single-Ended-to-Differential ADC Driver
125mV (Max) Input Offset Voltage, Low Distortion: –96.5dB at
100kHz, 10VP-P , Settling Time: 900ns
Rail-to-Rail Input and Output, Low Distortion, –80dBc at 5MHz,
Low Voltage Noise: 3.5nV/√Hz
Low Noise Voltage: 0.95nV/√Hz (100kHz), Low Distortion:
–80dB at 1MHz, TSOT23-6 Package
Rail-to-Rail Input and Outputs, 240ns 0.01% Settling Time
239116f
24 Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
LT 0210 • PRINTED IN USA
 LINEAR TECHNOLOGY CORPORATION 2010