Quad-Channel, 12-Bit, Serial Input, 4 mA to 20 mA and Voltage Output DAC with Dynamic Power Control AD5735 Data Sheet FEATURES On-chip dynamic power control minimizes package power dissipation in current mode. This reduced power dissipation is achieved by regulating the voltage on the output driver from 7.4 V to 29.5 V using a dc-to-dc boost converter optimized for minimum on-chip power dissipation. 12-bit resolution and monotonicity Dynamic power control for thermal management Current and voltage output pins connectable to a single terminal Current output ranges: 0 mA to 20 mA, 4 mA to 20 mA, and 0 mA to 24 mA ±0.1% total unadjusted error (TUE) maximum Voltage output ranges (with 20% overrange): 0 V to 5 V, 0 V to 10 V, ±5 V, and ±10 V ±0.09% total unadjusted error (TUE) maximum User-programmable offset and gain On-chip diagnostics On-chip reference: ±10 ppm/°C maximum −40°C to +105°C temperature range The AD5735 uses a versatile 3-wire serial interface that operates at clock rates of up to 30 MHz and is compatible with standard SPI, QSPI™, MICROWIRE®, DSP, and microcontroller interface standards. The serial interface also features optional CRC-8 packet error checking, as well as a watchdog timer that monitors activity on the interface. PRODUCT HIGHLIGHTS 1. 2. 3. APPLICATIONS Dynamic power control for thermal management. 12-bit performance. Quad channel. COMPANION PRODUCTS Process control Actuator control PLCs Product Family: AD5755, AD5755-1, AD5757, AD5737 External References: ADR445, ADR02 Digital Isolators: ADuM1410, ADuM1411 Power: ADP2302, ADP2303 Additional companion products on the AD5735 product page GENERAL DESCRIPTION The AD5735 is a quad-channel voltage and current output DAC that operates with a power supply range from −26.4 V to +33 V. FUNCTIONAL BLOCK DIAGRAM AVCC 5.0V AVSS –15V AGND AVDD +15V SWx DVDD VBOOST_x 7.4V TO 29.5V DGND LDAC DC-TO-DC CONVERTER SCLK SDIN SYNC SDO CLEAR DIGITAL INTERFACE IOUT_x + FAULT ALERT GAIN REG A OFFSET REG A AD1 AD0 DAC A CURRENT AND VOLTAGE OUTPUT RANGE SCALING RSET_x +VSENSE_x VOUT_x –VSENSE_x DAC CHANNEL A REFOUT REFERENCE REFIN DAC CHANNEL B DAC CHANNEL C DAC CHANNEL D 09961-100 AD5735 NOTES 1. x = A, B, C, OR D. Figure 1. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2011–2012 Analog Devices, Inc. All rights reserved. AD5735 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Control Registers ........................................................................ 34 Applications ....................................................................................... 1 Readback Operation .................................................................. 37 General Description ......................................................................... 1 Device Features ............................................................................... 39 Product Highlights ........................................................................... 1 Fault Output ................................................................................ 39 Companion Products ....................................................................... 1 Voltage Output Short-Circuit Protection ................................ 39 Functional Block Diagram .............................................................. 1 Digital Offset and Gain Control ............................................... 39 Revision History ............................................................................... 2 Status Readback During a Write .............................................. 39 Detailed Functional Block Diagram .............................................. 3 Asynchronous Clear................................................................... 40 Specifications..................................................................................... 4 Packet Error Checking ............................................................... 40 AC Performance Characteristics ................................................ 7 Watchdog Timer ......................................................................... 40 Timing Characteristics ................................................................ 8 Alert Output ................................................................................ 40 Absolute Maximum Ratings.......................................................... 11 Internal Reference ...................................................................... 40 Thermal Resistance .................................................................... 11 External Current Setting Resistor ............................................ 40 ESD Caution ................................................................................ 11 Digital Slew Rate Control .......................................................... 41 Pin Configuration and Function Descriptions ........................... 12 Dynamic Power Control............................................................ 41 Typical Performance Characteristics ........................................... 15 DC-to-DC Converters ............................................................... 42 Voltage Outputs .......................................................................... 15 AICC Supply Requirements—Static .......................................... 43 Current Outputs ......................................................................... 19 AICC Supply Requirements—Slewing ...................................... 43 DC-to-DC Converter ................................................................. 23 Applications Information .............................................................. 45 Reference ..................................................................................... 24 Voltage and Current Output Pins on the Same Terminal ..... 45 General ......................................................................................... 25 Current Output Mode with Internal RSET ................................ 45 Terminology .................................................................................... 26 Precision Voltage Reference Selection ..................................... 45 Theory of Operation ...................................................................... 28 Driving Inductive Loads ............................................................ 46 DAC Architecture ....................................................................... 28 Transient Voltage Protection .................................................... 46 Power-On State of the AD5735 ................................................ 29 Microprocessor Interfacing ....................................................... 46 Serial Interface ............................................................................ 29 Layout Guidelines....................................................................... 46 Transfer Function ....................................................................... 29 Galvanically Isolated Interface ................................................. 47 Registers ........................................................................................... 30 Outline Dimensions ....................................................................... 48 Enabling the Output ................................................................... 31 Ordering Guide .......................................................................... 48 Data Registers ............................................................................. 32 REVISION HISTORY 5/12—Rev. A to Rev. B Changes to Figure 2 ........................................................................... 3 Changes to Power-On State of the AD5735 Section .................. 29 Changes to Readback Operation Section .................................... 37 11/11—Rev. 0 to Rev. A 7/11—Revision 0: Initial Version Added Comments to OUTPUT CHARACTERISTICS and ACCURACY, CURRENT OUTPUT Parameters in Table 1 ................................................................................................. 4 Rev. B | Page 2 of 48 Data Sheet AD5735 DETAILED FUNCTIONAL BLOCK DIAGRAM AVCC 5.0V AVSS –15V DVDD DGND LDAC CLEAR SCLK SDIN SYNC SDO AGND SWA VBOOST_A POWER-ON RESET DC-TO-DC CONVERTER DYNAMIC POWER CONTROL INPUT SHIFT REGISTER AND CONTROL FAULT STATUS REGISTER ALERT AVDD +15V 12 DAC DATA REG A + DAC INPUT REG A 12 7.4V TO 29.5V VSEN1 R2 VSEN2 R3 DAC A GAIN REG A OFFSET REG A IOUT_A RSET_A R1 WATCHDOG TIMER (SPI ACTIVITY) 30kΩ REFOUT REFIN VOUT RANGE SCALING VREF REFERENCE BUFFERS +VSENSE_A VOUT_A DAC CHANNEL A –VSENSE_A AD1 AD0 AD5735 RSET_B, RSET_C, RSET_D DAC CHANNEL D ±V SENSE_B, ±VSENSE_C, ±VSENSE_D VOUT_B, VOUT_C, VOUT_D SWB, SWC, SWD Figure 2. Rev. B | Page 3 of 48 VBOOST_B, VBOOST_C, VBOOST_D 09961-001 IOUT_B, IOUT_C, IOUT_D DAC CHANNEL B DAC CHANNEL C AD5735 Data Sheet SPECIFICATIONS AVDD = VBOOST_x = 15 V; AVSS = −15 V; DVDD = 2.7 V to 5.5 V; AVCC = 4.5 V to 5.5 V; dc-to-dc converter disabled; AGND = DGND = GNDSWx = 0 V; REFIN = 5 V; voltage outputs: RL = 1 kΩ, CL = 220 pF; current outputs: RL = 300 Ω; all specifications TMIN to TMAX, unless otherwise noted. Table 1. Parameter 1 VOLTAGE OUTPUT Output Voltage Ranges Resolution ACCURACY, VOLTAGE OUTPUT Total Unadjusted Error (TUE) TUE Long-Term Stability Relative Accuracy (INL) Differential Nonlinearity (DNL) Zero-Scale Error Zero-Scale TC 2 Bipolar Zero Error Bipolar Zero TC2 Offset Error Offset TC2 Gain Error Gain TC2 Full-Scale Error Min 0 0 −5 −10 0 0 −6 −12 12 −0.09 −0.13 −0.032 −1 −0.05 −0.08 −0.05 −0.08 −0.065 −0.09 −0.08 −0.15 −0.09 −0.13 Full-Scale TC2 OUTPUT CHARACTERISTICS, VOLTAGE OUTPUT2 Headroom Footroom Output Voltage Drift vs. Time Short-Circuit Current Resistive Load Capacitive Load Stability DC Output Impedance DC PSRR DC Crosstalk CURRENT OUTPUT Output Current Ranges Resolution Typ ±0.012 ±0.05 35 ±0.006 ±0.004 ±0.004 ±2 ±0.003 ±0.03 ±2 ±0.005 ±0.03 ±2 ±0.004 ±0.004 ±3 ±0.01 ±0.05 ±2 1 1 20 12/6 1 Max Unit 5 10 +5 +10 6 12 +6 +12 V V V V V V V V Bits +0.09 +0.13 % FSR % FSR ppm FSR % FSR LSB % FSR % FSR ppm FSR/°C % FSR % FSR ppm FSR/°C % FSR % FSR ppm FSR/°C % FSR % FSR ppm FSR/°C % FSR % FSR ppm FSR/°C 0 V to 5 V, 0 V to 10 V, ±5 V, ±10 V ranges On overranges (0 V to 6 V, 0 V to 12 V, ±6 V, ±12 V) Drift after 1000 hours, TJ = 150°C V V ppm FSR With respect to VBOOST supply With respect to the AVSS supply +0.032 +1 +0.05 +0.08 +0.05 +0.08 +0.065 +0.09 +0.08 +0.15 +0.09 +0.13 2.2 1.4 16/8 10 2 0.06 50 24 0 0 4 12 24 20 20 Rev. B | Page 4 of 48 mA kΩ nF µF Ω µV/V µV mA mA mA Bits Test Conditions/Comments Guaranteed monotonic 0 V to 5 V, 0 V to 10 V ranges On overranges (0 V to 6 V, 0 V to 12 V) ±5 V, ±10 V ranges On overranges (±6 V, ±12 V) 0 V to 5 V, 0 V to 10 V, ±5 V, ±10 V ranges On overranges (0 V to 6 V, 0 V to 12 V, ±6 V, ±12 V) 0 V to 5 V, 0 V to 10 V, ±5 V, ±10 V ranges On overranges (0 V to 6 V, 0 V to 12 V, ±6 V, ±12 V) 0 V to 5 V, 0 V to 10 V, ±5 V, ±10 V ranges On overranges (0 V to 6 V, 0 V to 12 V, ±6 V, ±12 V) Drift after 1000 hours, ¾ scale output, TJ = 150°C, AVSS = −15 V Programmable by user; defaults to 16 mA typical For specified performance External 220 pF compensation capacitor connected Data Sheet Parameter 1 ACCURACY, CURRENT OUTPUT (EXTERNAL RSET) Total Unadjusted Error (TUE) TUE Long-Term Stability Relative Accuracy (INL) Differential Nonlinearity (DNL) Offset Error Offset Error Drift2 Gain Error Gain TC2 Full-Scale Error Full-Scale TC2 DC Crosstalk ACCURACY, CURRENT OUTPUT (INTERNAL RSET) Total Unadjusted Error (TUE) 3, 4 TUE Long-Term Stability Relative Accuracy (INL) Differential Nonlinearity (DNL) Offset Error3, 4 Offset Error Drift2 Gain Error Gain TC2 Full-Scale Error3, 4 Full-Scale TC2 DC Crosstalk4 OUTPUT CHARACTERISTICS, CURRENT OUTPUT2 Current Loop Compliance Voltage AD5735 Min Typ Max Unit −0.1 ±0.019 100 ±0.006 +0.1 % FSR ppm FSR % FSR LSB % FSR ppm FSR/°C % FSR ppm FSR/°C % FSR ppm FSR/°C % FSR −0.032 −1 −0.1 −0.1 −0.1 −0.14 −0.032 −1 −0.1 −0.12 −0.14 ±0.012 ±4 ±0.004 ±3 ±0.014 ±5 0.0005 ±0.022 180 ±0.006 ±0.017 ±6 ±0.004 ±9 ±0.02 ±14 −0.011 VBOOST_x − 2.4 +0.032 +1 +0.1 +0.1 +0.1 +0.14 +0.032 +1 +0.1 +0.12 +0.14 VBOOST_x − 2.7 % FSR ppm FSR % FSR LSB % FSR ppm FSR/°C % FSR ppm FSR/°C % FSR ppm FSR/°C % FSR Resistive Load DC Output Impedance DC PSRR REFERENCE INPUT/OUTPUT Reference Input2 Reference Input Voltage DC Input Impedance Reference Output Output Voltage Reference TC2 Output Noise (0.1 Hz to 10 Hz)2 Noise Spectral Density2 Output Voltage Drift vs. Time2 Capacitive Load2 Load Current Short-Circuit Current Line Regulation2 Load Regulation2 Thermal Hysteresis2 100 0.02 Drift after 1000 hours, TJ = 150°C Guaranteed monotonic External RSET Drift after 1000 hours, TJ = 150°C Guaranteed monotonic Internal RSET V Output Current Drift vs. Time 90 140 Test Conditions/Comments Assumes ideal resistor, see External Current Setting Resistor section for more information. 1000 ppm FSR ppm FSR Ω 1 MΩ µA/V Drift after 1000 hours, ¾ scale output, TJ = 150°C External RSET Internal RSET The dc-to-dc converter has been characterized with a maximum load of 1 kΩ, chosen such that compliance is not exceeded; see Figure 51 and the DC-DC MaxV bits in Table 28 4.95 45 5 150 5.05 V MΩ For specified performance 4.995 −10 5 ±5 7 100 180 1000 9 10 3 95 160 5 5.005 +10 V ppm/°C µV p-p nV/√Hz ppm nF mA mA ppm/V ppm/mA ppm ppm TA = 25°C Rev. B | Page 5 of 48 At 10 kHz Drift after 1000 hours, TJ = 150°C See Figure 62 See Figure 63 See Figure 62 First temperature cycle Second temperature cycle AD5735 Parameter 1 DC-TO-DC CONVERTER Switch Switch On Resistance Switch Leakage Current Peak Current Limit Oscillator Oscillator Frequency Maximum Duty Cycle DIGITAL INPUTS2 Input High Voltage, VIH Input Low Voltage, VIL Input Current Pin Capacitance DIGITAL OUTPUTS2 SDO, ALERT Pins Output Low Voltage, VOL Output High Voltage, VOH High Impedance Leakage Current High Impedance Output Capacitance FAULT Pin Output Low Voltage, VOL Data Sheet Min Typ Max 0.425 10 0.8 11.5 13 14.5 AISS 2 0.8 +1 2.6 0.4 0.4 V V V 10 kΩ pull-up resistor to DVDD At 2.5 mA 10 kΩ pull-up resistor to DVDD 33 −10.8 5.5 5.5 10.5 V V V V mA 7 −8.8 7.5 mA mA 9.2 11 mA mA 1 2.7 mA mA 1 mA mW +1 2.5 3.6 9 −26.4 2.7 4.5 8.6 AICC IBOOST 5 Power Dissipation Per pin Per pin Sinking 200 µA Sourcing 200 µA −1.7 DICC V V µA pF This oscillator is divided down to provide the dc-to-dc converter switching frequency At 410 kHz dc-to-dc switching frequency JEDEC compliant V V µA pF DVDD − 0.5 −1 −11 MHz % 0.6 Output High Voltage, VOH POWER REQUIREMENTS AVDD AVSS DVDD AVCC AIDD Test Conditions/Comments Ω nA A 89.6 −1 Unit 173 Voltage output mode on all channels, outputs unloaded, over supplies Current output mode on all channels Voltage output mode on all channels, outputs unloaded, over supplies Current output mode on all channels VIH = DVDD, VIL = DGND, internal oscillator running, over supplies Outputs unloaded, over supplies Per channel, voltage output mode, outputs unloaded, over supplies Per channel, current output mode AVDD = 15 V, AVSS = −15 V, dc-to-dc converter enabled, current output mode, outputs disabled Temperature range: −40°C to +105°C; typical at +25°C. Guaranteed by design and characterization; not production tested. 3 For current outputs with internal RSET, the offset, full-scale, and TUE measurements exclude dc crosstalk. The measurements are made with all four channels enabled and loaded with the same code. 4 See the Current Output Mode with Internal RSET section for more information about dc crosstalk. 5 Efficiency plots in Figure 53 through Figure 56 include the IBOOST quiescent current. 1 2 Rev. B | Page 6 of 48 Data Sheet AD5735 AC PERFORMANCE CHARACTERISTICS AVDD = VBOOST_x = 15 V; AVSS = −15 V; DVDD = 2.7 V to 5.5 V; AVCC = 4.5 V to 5.5 V; dc-to-dc converter disabled; AGND = DGND = GNDSWx = 0 V; REFIN = 5 V; voltage outputs: RL = 2 kΩ, CL = 220 pF; current outputs: RL = 300 Ω; all specifications TMIN to TMAX, unless otherwise noted. Table 2. Parameter 1 DYNAMIC PERFORMANCE, VOLTAGE OUTPUT Output Voltage Settling Time Min Typ Max 11 Test Conditions/Comments 5 V step to ±0.03% FSR, 0 V to 5 V range 10 V step to ±0.03% FSR, 0 V to 10 V range 0 V to 10 V range Slew Rate Power-On Glitch Energy Digital-to-Analog Glitch Energy Glitch Impulse Peak Amplitude Digital Feedthrough DAC-to-DAC Crosstalk Output Noise (0.1 Hz to 10 Hz Bandwidth) Output Noise Spectral Density 1.9 150 6 25 1 2 0.01 µs µs V/µs nV-sec nV-sec mV nV-sec nV-sec LSB p-p 150 nV/√Hz AC PSRR 83 dB 18 DYNAMIC PERFORMANCE, CURRENT OUTPUT Output Current Settling Time Output Noise (0.1 Hz to 10 Hz Bandwidth) Output Noise Spectral Density 1 Unit 15 See Test Conditions/Comments µs ms 0.01 LSB p-p 0.5 nA/√Hz Guaranteed by design and characterization; not production tested. Rev. B | Page 7 of 48 0 V to 10 V range 12-bit LSB, 0 V to 10 V range Measured at 10 kHz, midscale output, 0 V to 10 V range 200 mV, 50 Hz/60 Hz sine wave superimposed on power supply voltage To 0.1% FSR, 0 mA to 24 mA range For settling times when using the dc-to-dc converter, see Figure 47, Figure 48, and Figure 49 12-bit LSB, 0 mA to 24 mA range Measured at 10 kHz, midscale output, 0 mA to 24 mA range AD5735 Data Sheet TIMING CHARACTERISTICS AVDD = VBOOST_x = 15 V; AVSS = −15 V; DVDD = 2.7 V to 5.5 V; AVCC = 4.5 V to 5.5 V; dc-to-dc converter disabled; AGND = DGND = GNDSWx = 0 V; REFIN = 5 V; voltage outputs: RL = 1 kΩ, CL = 220 pF; current outputs: RL = 300 Ω; all specifications TMIN to TMAX, unless otherwise noted. Table 3. Parameter1, 2, 3 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t194 Limit at TMIN, TMAX 33 13 13 13 13 198 5 5 20 Unit ns min ns min ns min ns min ns min ns min ns min ns min µs min 5 10 500 See Table 2 10 5 40 µs min ns min ns max µs max ns min µs max ns max 21 5 500 800 µs min µs min ns min ns min 20 5 µs min µs min Description SCLK cycle time SCLK high time SCLK low time SYNC falling edge to SCLK falling edge setup time 24th/32nd SCLK falling edge to SYNC rising edge (see Figure 76) SYNC high time Data setup time Data hold time SYNC rising edge to LDAC falling edge (all DACs updated or any channel has digital slew rate control enabled) SYNC rising edge to LDAC falling edge (single DAC updated) LDAC pulse width low LDAC falling edge to DAC output response time DAC output settling time CLEAR high time CLEAR activation time SCLK rising edge to SDO valid SYNC rising edge to DAC output response time (LDAC = 0) All DACs updated Single DAC updated LDAC falling edge to SYNC rising edge RESET pulse width SYNC high to next SYNC low (digital slew rate control enabled) All DACs updated Single DAC updated Guaranteed by design and characterization; not production tested. All input signals are specified with tRISE = tFALL = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.2 V. 3 See Figure 3, Figure 4, Figure 5, and Figure 6. 4 This specification applies if LDAC is held low during the write cycle; otherwise, see t9. 1 2 Rev. B | Page 8 of 48 Data Sheet AD5735 Timing Diagrams t1 SCLK 1 2 24 t3 t6 t2 t4 t5 SYNC t8 t7 SDIN t19 MSB LSB t10 t10 t9 LDAC t17 t12 t11 VOUT_x LDAC = 0 t12 t16 VOUT_x t13 CLEAR t14 VOUT_x 09961-002 t18 RESET Figure 3. Serial Interface Timing Diagram SCLK 1 1 24 24 t6 SYNC MSB LSB MSB LSB INPUT WORD SPECIFIES REGISTER TO BE READ NOP CONDITION MSB SDO LSB UNDEFINED t15 Figure 4. Readback Timing Diagram Rev. B | Page 9 of 48 SELECTED REGISTER DATA CLOCKED OUT 09961-003 SDIN AD5735 Data Sheet LSB 1 MSB 16 2 SCLK SDO R/W DUT_ AD1 DUT_ AD0 SDO DISABLED X X X D15 D14 D1 D0 SDO_ ENAB STATUS STATUS STATUS STATUS Figure 5. Status Readback During Write, Timing Diagram 200µA TO OUTPUT PIN IOL VOH (MIN) OR VOL (MAX) CL 50pF 200µA IOH Figure 6. Load Circuit for SDO Timing Diagrams Rev. B | Page 10 of 48 09961-005 SDIN 09961-004 SYNC Data Sheet AD5735 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Transient currents of up to 100 mA do not cause SCR latch-up. Table 4. Parameter AVDD, VBOOST_x to AGND, DGND AVSS to AGND, DGND AVDD to AVSS AVCC to AGND DVDD to DGND Digital Inputs to DGND Digital Outputs to DGND REFIN, REFOUT to AGND VOUT_x to AGND +VSENSE_x, −VSENSE_x to AGND IOUT_x to AGND SWx to AGND AGND, GNDSWx to DGND Operating Temperature Range (TA) Industrial1 Storage Temperature Range Junction Temperature (TJ max) Power Dissipation Lead Temperature Soldering 1 Rating −0.3 V to +33 V +0.3 V to −28 V −0.3 V to +60 V −0.3 V to +7 V −0.3 V to +7 V −0.3 V to DVDD + 0.3 V or +7 V (whichever is less) −0.3 V to DVDD + 0.3 V or +7 V (whichever is less) −0.3 V to AVDD + 0.3 V or +7 V (whichever is less) AVSS to VBOOST_x or 33 V if using the dc-to-dc converter AVSS to VBOOST_x or 33 V if using the dc-to-dc converter AVSS to VBOOST_x or 33 V if using the dc-to-dc converter −0.3 V to +33 V −0.3 V to +0.3 V Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE Junction-to-air thermal resistance (θJA) is specified for a JEDEC 4-layer test board. Table 5. Thermal Resistance Package Type 64-Lead LFCSP (CP-64-3) ESD CAUTION −40°C to +105°C −65°C to +150°C 125°C (TJ max − TA)/θJA JEDEC industry standard J-STD-020 Power dissipated on chip must be derated to keep the junction temperature below 125°C. Rev. B | Page 11 of 48 θJA 20 Unit °C/W AD5735 Data Sheet 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 RSET_C RSET_D REFOUT REFIN COMPLV_D –VSENSE_D +VSENSE_D COMPDCDC_D VBOOST_D VOUT_D IOUT_D AVSS COMPLV_C –VSENSE_C +VSENSE_C VOUT_C PIN CONFIGURATION AND FUNCTION DESCRIPTIONS PIN 1 INDICATOR 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 AD5735 TOP VIEW (Not to Scale) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 COMPDCDC_C IOUT_C VBOOST_C AVCC SWC GNDSWC GNDSWD SWD AVSS SWA GNDSWA GNDSWB SWB AGND VBOOST_B IOUT_B NOTES 1.THE EXPOSED PADDLE SHOULD BE CONNECTED TO THE POTENTIAL OF THE AVSS PIN, OR, ALTERNATIVELY, IT CAN BE LEFT ELECTRICALLY UNCONNECTED. IT IS RECOMMENDED THAT THE PADDLE BE THERMALLY CONNECTED TO A COPPER PLANE FOR ENHANCED THERMAL PERFORMANCE. 09961-006 POC RESET AVDD COMPLV_A –VSENSE_A +VSENSE_A COMPDCDC_A VBOOST_A VOUT_A IOUT_A AVSS COMPLV_B –VSENSE_B +VSENSE_B VOUT_B COMPDCDC_B 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 RSET_B RSET_A REFGND REFGND AD0 AD1 SYNC SCLK SDIN SDO DVDD DGND LDAC CLEAR ALERT FAULT Figure 7. Pin Configuration Table 6. Pin Function Descriptions Pin No. 1 Mnemonic RSET_B 2 RSET_A 3 4 5 6 7 REFGND REFGND AD0 AD1 SYNC 8 SCLK 9 10 11 12 13 SDIN SDO DVDD DGND LDAC 14 CLEAR Description An external, precision, low drift, 15 kΩ current setting resistor can be connected to this pin to improve the IOUT_B temperature drift performance. For more information, see the External Current Setting Resistor section. An external, precision, low drift, 15 kΩ current setting resistor can be connected to this pin to improve the IOUT_A temperature drift performance. For more information, see the External Current Setting Resistor section. Ground Reference Point for Internal Reference. Ground Reference Point for Internal Reference. Address Decode for the Device Under Test (DUT) on the Board. Address Decode for the DUT on the Board. Frame Synchronization Signal for the Serial Interface. Active low input. When SYNC is low, data is clocked into the input shift register on the falling edge of SCLK. Serial Clock Input. Data is clocked into the input shift register on the falling edge of SCLK. The serial interface operates at clock speeds of up to 30 MHz. Serial Data Input. Data must be valid on the falling edge of SCLK. Serial Data Output. Used to clock data from the serial register in readback mode (see Figure 4 and Figure 5). Digital Supply Pin. The voltage range is from 2.7 V to 5.5 V. Digital Ground. Load DAC. This active low input is used to update the DAC register and, consequently, the DAC outputs. When LDAC is tied permanently low, the addressed DAC data register is updated on the rising edge of SYNC. If LDAC is held high during the write cycle, the DAC input register is updated, but the DAC output is updated only on the falling edge of LDAC (see Figure 3). Using this mode, all analog outputs can be updated simultaneously. The LDAC pin must not be left unconnected. Active High, Edge Sensitive Input. When this pin is asserted, the output current and voltage are set to the programmed clear code bit setting. Only channels enabled to be cleared are cleared. For more information, see the Asynchronous Clear section. When CLEAR is active, the DAC output register cannot be written to. Rev. B | Page 12 of 48 Data Sheet Pin No. 15 Mnemonic ALERT 16 FAULT 17 POC 18 19 20 RESET AVDD COMPLV_A 21 −VSENSE_A 22 +VSENSE_A 23 COMPDCDC_A 24 VBOOST_A 25 26 27 28 VOUT_A IOUT_A AVSS COMPLV_B 29 −VSENSE_B 30 +VSENSE_B 31 32 VOUT_B COMPDCDC_B 33 34 IOUT_B VBOOST_B 35 36 AGND SWB 37 38 39 GNDSWB GNDSWA SWA 40 41 AVSS SWD 42 43 44 GNDSWD GNDSWC SWC AD5735 Description Active High Output. This pin is asserted when there is no SPI activity on the interface pins for a preset time. For more information, see the Alert Output section. Active Low, Open-Drain Output. This pin is asserted low when any of the following conditions is detected: open circuit in current mode; short circuit in voltage mode; PEC error; or an overtemperature condition (see the Fault Output section). Power-On Condition. This pin determines the power-on condition and is read during power-on and after a device reset. If POC = 0, the device is powered up with the voltage and current channels in tristate mode. If POC = 1, the device is powered up with a 30 kΩ pull-down resistor to ground on the voltage output channel, and the current channel is in tristate mode. Hardware Reset, Active Low Input. Positive Analog Supply Pin. The voltage range is from 9 V to 33 V. Optional Compensation Capacitor Connection for VOUT_A Output Buffer. Connecting a 220 pF capacitor between this pin and the VOUT_A pin allows the voltage output to drive up to 2 µF. Note that the addition of this capacitor reduces the bandwidth of the output amplifier, increasing the settling time. Sense Connection for the Negative Voltage Output Load Connection for VOUT_A. This pin must stay within ±3.0 V of AGND for specified operation. Sense Connection for the Positive Voltage Output Load Connection for VOUT_A. The difference in voltage between this pin and the VOUT_A pin is added directly to the headroom requirement. DC-to-DC Compensation Capacitor. Connect a 10 nF capacitor from this pin to ground. Used to regulate the feedback loop of the Channel A dc-to-dc converter. Alternatively, if using an external compensation resistor, place a resistor in series with a capacitor to ground from this pin. For more information, see the DC-to-DC Converter Compensation Capacitors section and the AICC Supply Requirements—Slewing section. Supply for Channel A Current Output Stage (see Figure 71). This pin is also the supply for the VOUT_A stage, which is regulated to 15 V by the dc-to-dc converter. To use the dc-to-dc converter, connect this pin as shown in Figure 77. Buffered Analog Output Voltage for DAC Channel A. Current Output Pin for DAC Channel A. Negative Analog Supply Pin. The voltage range is from −10.8 V to −26.4 V. Optional Compensation Capacitor Connection for VOUT_B Output Buffer. Connecting a 220 pF capacitor between this pin and the VOUT_B pin allows the voltage output to drive up to 2 µF. Note that the addition of this capacitor reduces the bandwidth of the output amplifier, increasing the settling time. Sense Connection for the Negative Voltage Output Load Connection for VOUT_B. This pin must stay within ±3.0 V of AGND for specified operation. Sense Connection for the Positive Voltage Output Load Connection for VOUT_B. The difference in voltage between this pin and the VOUT_B pin is added directly to the headroom requirement. Buffered Analog Output Voltage for DAC Channel B. DC-to-DC Compensation Capacitor. Connect a 10 nF capacitor from this pin to ground. Used to regulate the feedback loop of the Channel B dc-to-dc converter. Alternatively, if using an external compensation resistor, place a resistor in series with a capacitor to ground from this pin. For more information, see the DC-to-DC Converter Compensation Capacitors section and the AICC Supply Requirements—Slewing section. Current Output Pin for DAC Channel B. Supply for Channel B Current Output Stage (see Figure 71). This pin is also the supply for the VOUT_B stage, which is regulated to 15 V by the dc-to-dc converter. To use the dc-to-dc converter, connect this pin as shown in Figure 77. Ground Reference Point for Analog Circuitry. This pin must be connected to 0 V. Switching Output for Channel B DC-to-DC Circuitry. To use the dc-to-dc converter, connect this pin as shown in Figure 77. Ground Connection for DC-to-DC Switching Circuit. This pin should always be connected to ground. Ground Connection for DC-to-DC Switching Circuit. This pin should always be connected to ground. Switching Output for Channel A DC-to-DC Circuitry. To use the dc-to-dc converter, connect this pin as shown in Figure 77. Negative Analog Supply Pin. The voltage range is from −10.8 V to −26.4 V. Switching Output for Channel D DC-to-DC Circuitry. To use the dc-to-dc converter, connect this pin as shown in Figure 77. Ground Connection for DC-to-DC Switching Circuit. This pin should always be connected to ground. Ground Connection for DC-to-DC Switching Circuit. This pin should always be connected to ground. Switching Output for Channel C DC-to-DC Circuitry. To use the dc-to-dc converter, connect this pin as shown in Figure 77. Rev. B | Page 13 of 48 AD5735 Data Sheet Pin No. 45 46 Mnemonic AVCC VBOOST_C 47 48 IOUT_C COMPDCDC_C 49 50 VOUT_C +VSENSE_C 51 −VSENSE_C 52 COMPLV_C 53 54 55 56 AVSS IOUT_D VOUT_D VBOOST_D 57 COMPDCDC_D 58 +VSENSE_D 59 −VSENSE_D 60 COMPLV_D 61 62 REFIN REFOUT 63 RSET_D 64 RSET_C EPAD Description Supply for DC-to-DC Circuitry. The voltage range is from 4.5 V to 5.5 V. Supply for Channel C Current Output Stage (see Figure 71). This pin is also the supply for the VOUT_C stage, which is regulated to 15 V by the dc-to-dc converter. To use the dc-to-dc converter, connect this pin as shown in Figure 77. Current Output Pin for DAC Channel C. DC-to-DC Compensation Capacitor. Connect a 10 nF capacitor from this pin to ground. Used to regulate the feedback loop of the Channel C dc-to-dc converter. Alternatively, if using an external compensation resistor, place a resistor in series with a capacitor to ground from this pin. For more information, see the DC-to-DC Converter Compensation Capacitors section and the AICC Supply Requirements—Slewing section. Buffered Analog Output Voltage for DAC Channel C. Sense Connection for the Positive Voltage Output Load Connection for VOUT_C. The difference in voltage between this pin and the VOUT_C pin is added directly to the headroom requirement. Sense Connection for the Negative Voltage Output Load Connection for VOUT_C. This pin must stay within ±3.0 V of AGND for specified operation. Optional Compensation Capacitor Connection for VOUT_C Output Buffer. Connecting a 220 pF capacitor between this pin and the VOUT_C pin allows the voltage output to drive up to 2 µF. Note that the addition of this capacitor reduces the bandwidth of the output amplifier, increasing the settling time. Negative Analog Supply Pin. The voltage range is from −10.8 V to −26.4 V. Current Output Pin for DAC Channel D. Buffered Analog Output Voltage for DAC Channel D. Supply for Channel D Current Output Stage (see Figure 71). This pin is also the supply for the VOUT_D stage, which is regulated to 15 V by the dc-to-dc converter. To use the dc-to-dc converter, connect this pin as shown in Figure 77. DC-to-DC Compensation Capacitor. Connect a 10 nF capacitor from this pin to ground. Used to regulate the feedback loop of the Channel D dc-to-dc converter. Alternatively, if using an external compensation resistor, place a resistor in series with a capacitor to ground from this pin. For more information, see the DC-to-DC Converter Compensation Capacitors section and the AICC Supply Requirements—Slewing section. Sense Connection for the Positive Voltage Output Load Connection for VOUT_D. The difference in voltage between this pin and the VOUT_D pin is added directly to the headroom requirement. Sense Connection for the Negative Voltage Output Load Connection for VOUT_D. This pin must stay within ±3.0 V of AGND for specified operation. Optional Compensation Capacitor Connection for VOUT_D Output Buffer. Connecting a 220 pF capacitor between this pin and the VOUT_D pin allows the voltage output to drive up to 2 µF. Note that the addition of this capacitor reduces the bandwidth of the output amplifier, increasing the settling time. External Reference Voltage Input. Internal Reference Voltage Output. It is recommended that a 0.1 µF capacitor be placed between REFOUT and REFGND. An external, precision, low drift, 15 kΩ current setting resistor can be connected to this pin to improve the IOUT_D temperature drift performance. For more information, see the External Current Setting Resistor section. An external, precision, low drift, 15 kΩ current setting resistor can be connected to this pin to improve the IOUT_C temperature drift performance. For more information, see the External Current Setting Resistor section. Exposed Pad. The exposed paddle should be connected to the potential of the AVSS pin, or, alternatively, it can be left electrically unconnected. It is recommended that the paddle be thermally connected to a copper plane for enhanced thermal performance. Rev. B | Page 14 of 48 Data Sheet AD5735 TYPICAL PERFORMANCE CHARACTERISTICS VOLTAGE OUTPUTS 0.008 0.008 AVDD = +15V AVSS = –15V TA = 25°C 0.006 0.006 0.004 INL ERROR (%FSR) 0.002 0 –0.002 0.002 0 –0.002 AVDD = +15V AVSS = –15V OUTPUT UNLOADED –0.004 ±10V RANGE ±12V RANGE –0.004 –0.006 ±10V RANGE WITH DC-TO-DC CONVERTER 0 1000 2000 3000 4000 CODE –0.008 –40 09961-208 –0.006 –20 0 20 40 60 80 100 TEMPERATURE (°C) Figure 8. Integral Nonlinearity Error vs. DAC Code Figure 11. Integral Nonlinearity Error vs. Temperature 1.0 1.0 AVDD = +15V AVSS = –15V TA = 25°C 0.8 0.6 0.6 0.4 0.4 0.2 0 –0.2 ±10V RANGE –0.4 AVDD = +15V AVSS = –15V ALL RANGES 0.8 DNL ERROR (LSB) DNL ERROR (LSB) +5V RANGE MAX INL ±10V RANGE MAX INL ±12V RANGE MAX INL +5V RANGE MIN INL ±10V RANGE MIN INL ±12V RANGE MIN INL 09961-211 INL ERROR (%FSR) 0.004 MAX DNL 0.2 0 MIN DNL –0.2 –0.4 ±12V RANGE –0.6 –0.6 ±10V RANGE WITH DC-TO-DC CONVERTER –0.8 0 1000 2000 3000 4000 CODE –1.0 –40 09961-209 –1.0 0 20 40 60 80 100 TEMPERATURE (°C) Figure 9. Differential Nonlinearity Error vs. DAC Code Figure 12. Differential Nonlinearity Error vs. Temperature 0.02 0.06 0 –0.01 –0.02 ±10V RANGE ±12V RANGE –0.03 ±10V RANGE WITH DC-TO-DC CONVERTER –0.04 0 1000 2000 3000 CODE 4000 Figure 10. Total Unadjusted Error vs. DAC Code 0.05 +5V RANGE ±10V RANGE ±12V RANGE 0.04 0.03 AV DD = +15V AV SS = –15V OUTPUT UNLOADED 0.02 0.01 0 –0.01 –40 –20 0 20 40 60 80 TEMPERATURE (°C) Figure 13. Total Unadjusted Error vs. Temperature Rev. B | Page 15 of 48 100 09961-129 0.01 TOTAL UNADJUSTED ERROR (%FSR) AVDD = +15V AVSS = –15V TA = 25°C 09961–210 TOTAL UNADJUSTED ERROR (%FSR) –20 09961-212 –0.8 AD5735 Data Sheet 0.09 0.06 0.08 0.07 +5V RANGE ±10V RANGE ±12V RANGE 0.04 GAIN ERROR (%FSR) FULL-SCALE ERROR (%FSR) 0.05 0.03 AV DD = +15V AV SS = –15V OUTPUT UNLOADED 0.02 0.01 0.06 +5V RANGE ±10V RANGE ±12V RANGE AV DD = +15V AV SS = –15V OUTPUT UNLOADED 0.05 0.04 0.03 0.02 0.01 0 0 0 20 40 60 80 100 TEMPERATURE (°C) –0.02 –40 09961-132 –20 –20 0 20 40 60 80 100 80 100 TEMPERATURE (°C) Figure 14. Full-Scale Error vs. Temperature 09961-135 –0.01 –0.01 –40 Figure 17. Gain Error vs. Temperature 0.015 0.006 0.010 0.005 +5V RANGE ±10V RANGE ±12V RANGE –0.005 –0.010 –0.015 AV DD = +15V AV SS = –15V OUTPUT UNLOADED –0.020 –0.025 –0.030 +5V RANGE 0.004 0.003 +6V RANGE 0.002 0.001 AV DD = +15V AV SS = –15V OUTPUT UNLOADED –0.035 –20 0 20 40 60 80 100 TEMPERATURE (°C) 0 –40 09961-133 –0.040 –40 0 20 40 60 TEMPERATURE (°C) Figure 15. Offset Error vs. Temperature Figure 18. Zero-Scale Error vs. Temperature 0.010 0.006 MAX INL ±10V RANGE 0.005 0.004 0 –0.010 –0.015 INL ERROR (%FSR) –0.005 AV DD = +15V AV SS = –15V OUTPUT UNLOADED –0.020 ±12V RANGE –0.025 0.002 0V TO 5V RANGE TA = 25°C AVSS = –26.4V FOR AVDD > +26.4V AVSS = –10.8V FOR AVDD < +10.8V 0 –0.002 –0.030 –0.035 –0.004 MIN INL –0.045 –40 –20 0 20 40 60 80 TEMPERATURE (°C) 100 Figure 16. Bipolar Zero Error vs. Temperature –0.006 5 10 15 20 SUPPLY (V) 25 Figure 19. Integral Nonlinearity Error vs. Supply Rev. B | Page 16 of 48 30 09961-219 –0.040 09961-134 BIPOLAR ZERO ERROR (%FSR) –20 09961-136 0 ZERO-SCALE ERROR (%FSR) OFFSET ERROR (%FSR) 0.005 Data Sheet AD5735 1.0 12 AV DD = +15V AV SS = –15V ±10V RANGE TA = 25°C OUTPUT UNLOADED 0.8 ALL RANGES TA = 25°C AVSS = –26.4V FOR AVDD > +26.4V AVSS = –10.8V FOR AVDD < +10.8V 0.4 0.2 OUTPUT VOLTAGE (V) DNL ERROR (LSB) 0.6 8 MAX DNL 0 MIN DNL –0.2 –0.4 –0.6 4 0 –4 –8 5 10 15 20 SUPPLY (V) 25 –12 –5 09961-220 –1.0 30 10 15 Figure 23. Full-Scale Positive Step 12 0.020 0V TO 5V RANGE TA = 25°C AV SS = –26.4V FOR AV DD > +26.4V AV SS = –10.8V FOR AV DD < +10.8V 0.015 0.010 AV DD = +15V AV SS = –15V ±10V RANGE TA = 25°C OUTPUT UNLOADED 8 OUTPUT VOLTAGE (V) 0.005 MAX TUE 0 –0.005 MIN TUE –0.010 4 0 –4 –0.015 –8 5 10 15 20 25 –12 –5 09961-035 –0.025 30 SUPPLY (V) 10 15 Figure 24. Full-Scale Negative Step 0.0020 15 8mA LIMIT, CODE = 0xFFFF 16mA LIMIT, CODE = 0xFFFF 0x7FFF TO 0x8000 0x8000 TO 0x7FFF AV DD = +15V AV SS = –15V +10V RANGE TA = 25ºC 10 0.0010 5 VOLTAGE (V) 0.0005 0 –0.0005 0 –5 –10 –0.0010 AV DD = +15V AV SS = –15V ±10V RANGE TA = 25°C –16 –12 –8 –4 0 4 8 12 16 –15 20 OUTPUT CURRENT (mA) 09961-036 –0.0015 –0.0020 –20 5 TIME (µs) Figure 21. Total Unadjusted Error vs. Supply 0.0015 0 09961-038 –0.020 Figure 22. Source and Sink Capability of the Output Amplifier –20 0 1 2 3 TIME (µs) Figure 25. Digital-to-Analog Glitch Rev. B | Page 17 of 48 4 5 09961-039 TOTAL UNADJUSTED ERROR (%FSR) 5 TIME (µs) Figure 20. Differential Nonlinearity Error vs. Supply OUTPUT VOLTAGE DELTA (V) 0 09961-037 –0.8 AD5735 Data Sheet 15 60 AV DD = +15V AV SS = –15V ±10V RANGE TA = 25°C OUTPUT UNLOADED 10 40 20 0 0 –5 –20 –40 –60 POC = 1 POC = 0 –80 AV DD = +15V AV SS = –15V ±10V RANGE TA = 25°C INT_ENABLE = 1 –100 –10 –120 0 1 2 3 4 5 6 7 8 9 10 TIME (s) –140 09961-040 –15 0 AV DD = +15V AV SS = –15V 8 10 0 ±10V RANGE OUTPUT UNLOADED TA = 25°C VOUT_X PSRR (dB) –20 100 0 –100 –200 AV DD = +15V VBOOST = +15V AV SS = –15V TA = 25°C –40 –60 –80 –300 0 1 2 3 4 5 6 7 8 9 10 TIME (µs) 09961-041 –100 Figure 27. Peak-to-Peak Noise (100 kHz Bandwidth) 20 15 10 5 0 –5 –10 –25 0 25 50 75 100 TIME (µs) 125 09961-043 AV DD = +15V AV SS = –15V TA = 25°C –20 100 1k 10k 100k FREQUENCY (Hz) Figure 30. VOUT_x PSRR vs. Frequency 25 –15 –120 10 Figure 28. Voltage vs. Time on Power-Up Rev. B | Page 18 of 48 1M 10M 09961-045 VOLTAGE (µV) 6 Figure 29. Voltage vs. Time on Output Enable 200 VOLTAGE (mV) 4 TIME (µs) Figure 26. Peak-to-Peak Noise (0.1 Hz to 10 Hz Bandwidth) 300 2 09961-044 VOLTAGE (mV) VOLTAGE (µV) 5 Data Sheet AD5735 CURRENT OUTPUTS 0.008 0.008 4mA TO 20mA, INTERNAL RSET, WITH DC-TO-DC CONVERTER 4mA TO 20mA, EXTERNAL RSET, WITH DC-TO-DC CONVERTER 4mA TO 20mA, INTERNAL RSET 4mA TO 20mA, EXTERNAL RSET 0.006 0.006 INL ERROR (%FSR) 0.002 0 –0.002 0.002 0 –0.002 4mA TO 20mA RANGE MAX INL 0mA TO 24mA RANGE MAX INL 0mA TO 20mA RANGE MAX INL 4mA TO 20mA RANGE MIN INL 0mA TO 24mA RANGE MIN INL 0mA TO 20mA RANGE MIN INL AVDD = +15V AVSS = –15V/0V –0.004 AVDD = +15V AVSS = –15V TA = 25°C –0.006 –0.006 0 1000 2000 3000 4000 CODE –0.008 –40 09961-231 –0.004 –20 0 20 40 60 80 100 TEMPERATURE (°C) Figure 31. Integral Nonlinearity Error vs. DAC Code 09961-234 INL ERROR (%FSR) 0.004 0.004 Figure 34. Integral Nonlinearity Error vs. Temperature, Internal RSET 0.008 1.0 4mA TO 20mA, INTERNAL RSET, WITH DC-TO-DC CONVERTER 4mA TO 20mA, EXTERNAL RSET, WITH DC-TO-DC CONVERTER 4mA TO 20mA, INTERNAL RSET 4mA TO 20mA, EXTERNAL RSET 0.8 0.6 0.006 INL ERROR (%FSR) DNL ERROR (LSB) 0.004 0.4 0.2 0 –0.2 –0.4 0.002 0 –0.002 4mA TO 20mA RANGE MAX INL 0mA TO 24mA RANGE MAX INL 0mA TO 20mA RANGE MAX INL 4mA TO 20mA RANGE MIN INL 0mA TO 24mA RANGE MIN INL 0mA TO 20mA RANGE MIN INL AVDD = +15V AVSS = –15V/0V –20 60 –0.004 AVDD = +15V AVSS = –15V TA = 25°C –1.0 0 1000 2000 3000 4000 CODE Figure 32. Differential Nonlinearity Error vs. DAC Code 0.4 DNL ERROR (LSB) 0.6 0.02 AVDD = +15V AVSS = –15V TA = 25°C MIN DNL –0.2 –0.4 –0.6 –0.8 4mA TO 20mA, EXTERNAL RSET 4mA TO 20mA, EXTERNAL RSET, WITH DC-TO-DC CONVERTER –0.04 1000 2000 3000 CODE 4000 Figure 33. Total Unadjusted Error vs. DAC Code MAX DNL 0 –0.02 0 100 0.2 –0.01 –0.03 80 0.8 0.03 0 40 1.0 0.04 0.01 20 TEMPERATURE (°C) 4mA TO 20mA, INTERNAL RSET 4mA TO 20mA, INTERNAL RSET, WITH DC-TO-DC CONVERTER 0.05 0 Figure 35. Integral Nonlinearity Error vs. Temperature, External RSET 09961-233 TOTAL UNADJUSTED ERROR (%FSR) 0.06 –0.008 –40 09961-235 –0.006 09961-232 –0.8 –1.0 –40 AVDD = +15V AVSS = –15V/0V ALL RANGES INTERNAL AND EXTERNAL RSET –20 0 20 40 60 80 100 TEMPERATURE (°C) Figure 36. Differential Nonlinearity Error vs. Temperature Rev. B | Page 19 of 48 09961-236 –0.6 AD5735 Data Sheet 0.008 0.025 MAX INL 0.006 0.015 0.005 0 –0.005 AV DD = +15V AV SS = –15V –0.010 0.004 INL ERROR (%FSR) 0.010 4mA TO 20mA RANGE TA = 25°C AVSS = –26.4V FOR AVDD > +26.4V AVSS = –10.8V FOR AVDD < +10.8V 0.002 0 –0.002 –0.015 –0.004 –0.025 –40 –20 0 20 40 60 TEMPERATURE (°C) 80 100 –0.006 MIN INL 5 10 15 20 25 30 SUPPLY (V) 09961-240 4mA TO 20mA RANGE, INTERNAL RSET 4mA TO 20mA RANGE, EXTERNAL RSET –0.020 09961-155 TOTAL UNADJUSTED ERROR (%FSR) 0.020 Figure 40. Integral Nonlinearity Error vs. Supply, External RSET Figure 37. Total Unadjusted Error vs. Temperature 0.020 0.008 0.015 0.006 0.010 0 –0.005 AV DD = +15V AV SS = –15V –0.004 –20 0 20 40 60 TEMPERATURE (°C) 80 100 –0.006 10 15 20 25 30 Figure 41. Integral Nonlinearity Error vs. Supply, Internal RSET 1.0 0.005 ALL RANGES TA = 25°C AVSS = –26.4V FOR AVDD > +26.4V AVSS = –10.8V FOR AVDD < +10.8V 0.8 0 DNL ERROR (LSB) 0.6 –0.005 –0.010 –0.015 4mA TO 20mA RANGE, INTERNAL RSET 4mA TO 20mA RANGE, EXTERNAL RSET 0 60 20 40 TEMPERATURE (°C) MAX DNL 0.2 0 MIN DNL –0.2 –0.6 –0.020 –20 0.4 –0.4 AV DD = +15V AV SS = –15V 80 –0.8 100 09961-159 GAIN ERROR (%FSR) 5 SUPPLY (V) Figure 38. Full-Scale Error vs. Temperature –0.025 –40 MIN INL 09961-241 –0.020 –40 0 –0.002 4mA TO 20mA RANGE, INTERNAL RSET 4mA TO 20mA RANGE, EXTERNAL RSET –0.015 4mA TO 20mA RANGE TA = 25°C AVSS = –26.4V FOR AVDD > +26.4V AVSS = –10.8V FOR AVDD < +10.8V 0.002 Figure 39. Gain Error vs. Temperature –1.0 5 10 15 20 25 30 SUPPLY (V) Figure 42. Differential Nonlinearity Error vs. Supply Rev. B | Page 20 of 48 09961-242 –0.010 0.004 INL ERROR (%FSR) 0.005 09961-157 FULL-SCALE ERROR (%FSR) MAX INL Data Sheet AD5735 4 MAX TUE 0 2 –0.005 0 –0.015 –0.020 –2 –4 MIN TUE –6 AV DD = +15V AV SS = –15V TA = 25°C RLOAD = 300Ω INT_ENABLE = 1 –0.025 –8 –0.030 5 10 15 20 25 –10 09961-060 –0.035 30 SUPPLY (V) 0 1 0.05 0.04 4mA TO 20mA RANGE TA = 25°C AV SS = –26.4V FOR AV DD > +26.4V AV SS = –10.8V FOR AV DD < +10.8V 0.01 0 MIN TUE –0.01 5 10 15 20 25 09961-061 –0.02 30 SUPPLY (V) OUTPUT CURRENT (mA) AND VBOOST_x VOLTAGE (V) TOTAL UNADJUSTED ERROR (%FSR) MAX TUE 0.02 4 5 6 Figure 46. Current vs. Time on Output Enable 0.07 0.03 3 TIME (µs) Figure 43. Total Unadjusted Error vs. Supply, External RSET 0.06 2 30 25 20 IOUT_x VBOOST_x 15 10 0mA TO 24mA RANGE 1kΩ LOAD fSW = 410kHz INDUCTOR = 10µH (XAL4040-103) AV CC = 5V TA = 25°C 5 0 –0.50 –0.25 0 0.25 0.50 0.75 1.00 1.25 09961-167 –0.010 09961-063 4mA TO 20mA RANGE TA = 25°C AV SS = –26.4V FOR AV DD > +26.4V AV SS = –10.8V FOR AV DD < +10.8V CURRENT (µA) TOTAL UNADJUSTED ERROR (%FSR) 0.005 1.50 1.75 2.00 TIME (ms) Figure 44. Total Unadjusted Error vs. Supply, Internal RSET Figure 47. Output Current and VBOOST_x Settling Time with DC-to-DC Converter (See Figure 77) 6 30 AV DD = +15V AV SS = –15V TA = 25°C RLOAD = 300Ω 25 3 2 1 20 TA = –40°C TA = +25°C TA = +105°C 15 10 0mA TO 24mA RANGE 1kΩ LOAD fSW = 410kHz INDUCTOR = 10µH (XAL4040-103) AV CC = 5V 5 0 0 5 10 15 TIME (µs) 20 09961-062 CURRENT (µA) 4 Figure 45. Current vs. Time on Power-Up 0 –0.25 0 0.25 0.50 0.75 1.00 TIME (ms) 1.25 1.50 1.75 09961-168 OUTPUT CURRENT (mA) 5 Figure 48. Output Current Settling Time with DC-to-DC Converter over Temperature (See Figure 77) Rev. B | Page 21 of 48 AD5735 Data Sheet 8 30 0mA TO 24mA RANGE 1kΩ LOAD fSW = 410kHz INDUCTOR = 10µH (XAL4040-103) TA = 25°C 7 HEADROOM VOLTAGE (V) 20 AVCC = 4.5V AVCC = 5.0V AVCC = 5.5V 10 0mA TO 24mA RANGE 1kΩ LOAD fSW = 410kHz INDUCTOR = 10µH (XAL4040-103) TA = 25°C 5 0 –0.25 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 TIME (ms) 5 4 3 2 1 Figure 49. Output Current Settling Time with DC-to-DC Converter over AVCC (See Figure 77) 10 6 0 0 10 15 20 OUTPUT CURRENT (mA) Figure 51. DC-to-DC Converter Headroom vs. Output Current (See Figure 77) 0 20mA OUTPUT 10mA OUTPUT 8 –20 6 IOUT_x PSRR (dB) 4 2 0 –2 –4 AV DD = +15V VBOOST_x = +15V AV SS = –15V TA = 25°C –40 –60 –80 –6 –10 0 2 4 6 8 10 –100 0mA TO 24mA RANGE 1kΩ LOAD EXTERNA L RSET TA = 25°C 12 TIME (µs) 14 –120 10 100 1k 10k 100k FREQUENCY (Hz) Figure 50. Output Current, AC-Coupled vs. Time with DC-to-DC Converter (See Figure 77) Figure 52. IOUT_x PSRR vs. Frequency Rev. B | Page 22 of 48 1M 10M 09961-068 AV CC = 5V fSW = 410kHz INDUCTOR = 10µH (XAL4040-103) –8 09961-170 CURRENT (AC-COUPLED) (µA) 5 09961-067 15 09961-169 OUTPUT CURRENT (mA) 25 Data Sheet AD5735 DC-TO-DC CONVERTER 90 80 AV CC = 4.5V AV CC = 5V AV CC = 5.5V 85 20mA OUTPUT 70 75 70 65 0mA TO 24mA RANGE 1kΩ LOAD EXTERNAL RSET fSW = 410kHz INDUCTOR = 10µH (XAL4040-103) TA = 25°C 55 50 0 4 8 12 16 20 50 40 30 24 OUTPUT CURRENT (mA) 20 –40 09961-016 60 60 0mA TO 24mA RANGE 1kΩ LOAD EXTERNAL RSET AV CC = 5V fSW = 410kHz INDUCTOR = 10µH (XAL4040-103) –20 0 20 40 60 80 100 TEMPERATURE (°C) Figure 53. Efficiency at VBOOST_x vs. Output Current (See Figure 77) 09961-019 IOUT_x EFFICIENCY (%) VBOOST_x EFFICIENCY (%) 80 Figure 56. Output Efficiency vs. Temperature (See Figure 77) 0.6 90 20mA OUTPUT 85 SWITCH RESISTANCE (Ω) 75 70 0mA TO 24mA RANGE 1kΩ LOAD EXTERNAL RSET AV CC = 5V fSW = 410kHz INDUCTOR = 10µH (XAL4040-103) TA = 25°C 60 55 50 –40 –20 0 20 40 60 80 100 Figure 54. Efficiency at VBOOST_x vs. Temperature (See Figure 77) AV CC = 4.5V AV CC = 5V AV CC = 5.5V 50 0mA TO 24mA RANGE 1kΩ LOAD EXTERNAL RSET fSW = 410kHz INDUCTOR = 10µH (XAL4040-103) TA = 25°C 20 0 4 8 12 16 20 24 OUTPUT CURRENT (mA) 09961-018 IOUT_x EFFICIENCY (%) 60 30 0.2 0 –40 –20 0 20 40 60 80 TEMPERATURE (°C) Figure 57. Switch Resistance vs. Temperature 80 40 0.3 0.1 TEMPERATURE (°C) 70 0.4 Figure 55. Output Efficiency vs. Output Current (See Figure 77) Rev. B | Page 23 of 48 100 09961-123 65 09961-017 VBOOST_x EFFICIENCY (%) 0.5 80 AD5735 Data Sheet REFERENCE 5.0050 16 AV DD REFOUT TA = 25°C 12 10 8 6 4 2 0 5.0040 5.0035 5.0030 5.0025 5.0020 5.0015 5.0010 5.0005 0 0.2 0.4 0.6 0.8 1.0 1.2 TIME (ms) 5.0000 –40 09961-010 –2 Figure 58. REFOUT Voltage Turn-On Transient –20 0 20 40 60 80 100 TEMPERATURE (°C) 09961-163 VOLTAGE (V) 30 DEVICES SHOWN AV DD = 15V 5.0045 REFERENCE OUTPUT VOLTAGE (V) 14 Figure 61. REFOUT Voltage vs. Temperature (When the AD5735 is soldered onto a PCB, the reference shifts due to thermal shock on the package. The average output voltage shift is −4 mV. Measurement of these parts after seven days shows that the outputs typically shift back 2 mV toward their initial values. This second shift is due to the relaxation of stress incurred during soldering.) 4 5.002 REFERENCE OUTPUT VOLTAGE (V) 1 0 –1 –3 0 2 4 6 8 10 TIME (s) 09961-011 –2 5.000 4.999 4.998 4.997 4.996 4.995 0 4 6 8 10 LOAD CURRENT (mA) Figure 59. REFOUT Output Noise (0.1 Hz to 10 Hz Bandwidth) Figure 62. REFOUT Voltage vs. Load Current 150 5.00000 REFERENCE OUTPUT VOLTAGE (V) AV DD = 15V TA = 25°C 100 50 0 –50 –100 –150 0 5 10 15 TIME (ms) 20 09961-012 VOLTAGE (µV) 2 Figure 60. REFOUT Output Noise (100 kHz Bandwidth) 4.99995 TA = 25°C 4.99990 4.99985 4.99980 4.99975 4.99970 4.99965 4.99960 10 15 20 25 AV DD (V) Figure 63. REFOUT Voltage vs. AVDD Rev. B | Page 24 of 48 30 09961-015 VOLTAGE (µV) 2 AV DD = 15V TA = 25°C 5.001 09961-014 AV DD = 15V TA = 25°C 3 Data Sheet AD5735 GENERAL 450 13.4 DVDD = 5V TA = 25°C 400 13.3 350 FREQUENCY (MHz) 13.2 250 200 150 13.1 13.0 12.9 12.8 100 12.7 50 0 1 2 3 4 5 SDIN VOLTAGE (V) 12.6 –40 09961-007 0 DVDD = 5.5V –20 0 20 40 60 80 09961-020 DICC (µA) 300 100 TEMPERATURE (°C) Figure 64. DICC vs. Logic Input Voltage Figure 67. Internal Oscillator Frequency vs. Temperature 10 14.4 8 14.2 6 AIDD AISS TA = 25°C VOUT = 0V OUTPUT UNLOADED 2 0 14.0 FREQUENCY (MHz) CURRENT (mA) 4 –2 –4 13.8 13.6 13.4 –6 –8 13.2 –10 15 20 25 30 VOLTAGE (V) Figure 65. Supply Current (AIDD/AISS) vs. Supply Voltage (AVDD/|AVSS|) 7 5 4 3 2 AIDD TA = 25°C IOUT = 0mA 15 20 25 30 VOLTAGE (V) 09961-009 CURRENT (mA) 6 0 10 3.0 3.5 4.0 4.5 5.0 5.5 VOLTAGE (V) Figure 68. Internal Oscillator Frequency vs. DVDD Supply Voltage 8 1 13.0 2.5 Figure 66. Supply Current (AIDD) vs. Supply Voltage (AVDD) Rev. B | Page 25 of 48 09961-021 TA = 25°C 09961-008 –12 10 AD5735 Data Sheet TERMINOLOGY Relative Accuracy or Integral Nonlinearity (INL) Relative accuracy, or integral nonlinearity (INL), is a measure of the maximum deviation from the best fit line through the DAC transfer function. INL is expressed in percent of full-scale range (% FSR). Typical INL vs. code plots are shown in Figure 8 and Figure 31. Differential Nonlinearity (DNL) Differential nonlinearity (DNL) is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified DNL of ±1 LSB maximum ensures monotonicity. The AD5735 is guaranteed monotonic by design. Typical DNL vs. code plots are shown in Figure 9 and Figure 32. Monotonicity A DAC is monotonic if the output either increases or remains constant for increasing digital input code. The AD5735 is monotonic over its full operating temperature range. Negative Full-Scale Error or Zero-Scale Error Negative full-scale error is the error in the DAC output voltage when 0x0000 (straight binary coding) is loaded to the DAC register. Zero-Scale Temperature Coefficient (TC) Zero-scale TC is a measure of the change in zero-scale error with a change in temperature. Zero-scale TC is expressed in ppm FSR/°C. Bipolar Zero Error Bipolar zero error is the deviation of the analog output from the ideal half-scale output of 0 V when the DAC register is loaded with 0x8000 (straight binary coding). Bipolar Zero Temperature Coefficient (TC) Bipolar zero TC is a measure of the change in the bipolar zero error with a change in temperature. It is expressed in ppm FSR/°C. Offset Error In voltage output mode, offset error is the deviation of the analog output from the ideal quarter-scale output when the DAC is configured for a bipolar output range and the DAC register is loaded with 0x4000 (straight binary coding). Gain Temperature Coefficient (TC) Gain TC is a measure of the change in gain error with changes in temperature and is expressed in ppm FSR/°C. Full-Scale Error Full-scale error is a measure of the output error when full-scale code is loaded to the DAC register. Ideally, the output should be full-scale − 1 LSB. Full-scale error is expressed in % FSR. Full-Scale Temperature Coefficient (TC) Full-scale TC is a measure of the change in full-scale error with changes in temperature and is expressed in ppm FSR/°C. Total Unadjusted Error (TUE) Total unadjusted error (TUE) is a measure of the output error that includes all the error measurements: INL error, offset error, gain error, temperature, and time. TUE is expressed in % FSR. DC Crosstalk DC crosstalk is the dc change in the output level of one DAC in response to a change in the output of another DAC. It is measured with a full-scale output change on one DAC while monitoring another DAC, which is at midscale. Current Loop Compliance Voltage The current loop compliance voltage is the maximum voltage at the IOUT_x pin for which the output current is equal to the programmed value. Voltage Reference Thermal Hysteresis Voltage reference thermal hysteresis is the difference in output voltage measured at +25°C compared to the output voltage measured at +25°C after cycling the temperature from +25°C to −40°C to +105°C and back to +25°C. The hysteresis is specified for the first and second temperature cycles and is expressed in ppm. Output Voltage Settling Time Output voltage settling time is the amount of time it takes for the output to settle to a specified level for a full-scale input change. Plots of settling time are shown in Figure 23, Figure 48, and Figure 49. In current output mode, offset error is the deviation of the analog output from the ideal zero-scale output when all DAC registers are loaded with 0x0000. Slew Rate The slew rate of a device is a limitation in the rate of change of the output voltage. The output slewing speed of a voltage output DAC is usually limited by the slew rate of the amplifier used at its output. Slew rate is measured from 10% to 90% of the output signal and is given in V/µs. Offset Error Drift or Offset TC Offset error drift, or offset TC, is a measure of the change in offset error with changes in temperature and is expressed in ppm FSR/°C. Power-On Glitch Energy Power-on glitch energy is the impulse injected into the analog output when the AD5735 is powered on. It is specified as the area of the glitch in nV-sec (see Figure 28 and Figure 45). Gain Error Gain error is a measure of the span error of the DAC. It is the deviation in slope of the DAC transfer function from the ideal, expressed in % FSR. Rev. B | Page 26 of 48 Data Sheet AD5735 Digital-to-Analog Glitch Energy Digital-to-analog glitch energy is the impulse injected into the analog output when the input code in the DAC register changes state but the output voltage remains constant. It is normally specified as the area of the glitch in nV-sec and is measured when the digital input code is changed by 1 LSB at the major carry transition (~0x7FFF to 0x8000). See Figure 25. Glitch Impulse Peak Amplitude Glitch impulse peak amplitude is the peak amplitude of the impulse injected into the analog output when the input code in the DAC register changes state. It is specified as the amplitude of the glitch in mV and is measured when the digital input code is changed by 1 LSB at the major carry transition (~0x7FFF to 0x8000). See Figure 25. Digital Feedthrough Digital feedthrough is a measure of the impulse injected into the analog output of the DAC from the digital inputs of the DAC but is measured when the DAC output is not updated. It is specified in nV-sec and measured with a full-scale code change on the data bus. DAC-to-DAC Crosstalk DAC-to-DAC crosstalk is the glitch impulse transferred to the output of one DAC due to a digital code change and a subsequent output change of another DAC. DAC-to-DAC crosstalk includes both digital and analog crosstalk. It is measured by loading one DAC with a full-scale code change (all 0s to all 1s and vice versa) with LDAC low while monitoring the output of another DAC. The energy of the glitch is expressed in nV-sec. Reference Temperature Coefficient (TC) Reference TC is a measure of the change in the reference output voltage with changes in temperature. It is expressed in ppm/°C. Line Regulation Line regulation is the change in the reference output voltage due to a specified change in supply voltage. It is expressed in ppm/V. Load Regulation Load regulation is the change in the reference output voltage due to a specified change in load current. It is expressed in ppm/mA. DC-to-DC Converter Headroom DC-to-DC converter headroom is the difference between the voltage required at the current output and the voltage supplied by the dc-to-dc converter (see Figure 51). Output Efficiency Output efficiency is defined as the ratio of the power delivered to a channel’s load and the power delivered to the channel’s dc-to-dc input. The VBOOST_x quiescent current is considered part of the dc-to-dc converter’s losses. I OUT 2 × R LOAD AVCC × AI CC Efficiency at VBOOST_x The efficiency at VBOOST_x is defined as the ratio of the power delivered to a channel’s VBOOST_x supply and the power delivered to the channel’s dc-to-dc input. The VBOOST_x quiescent current is considered part of the dc-to-dc converter’s losses. Power Supply Rejection Ratio (PSRR) PSRR indicates how the output of the DAC is affected by changes in the power supply voltage. Rev. B | Page 27 of 48 I OUT × V BOOST _ x AVCC × AI CC AD5735 Data Sheet THEORY OF OPERATION The AD5735 is a quad, precision digital-to-current loop and voltage output converter designed to meet the requirements of industrial process control applications. It provides a high precision, fully integrated, low cost, single-chip solution for generating current loop and unipolar/bipolar voltage outputs. VBOOST_x R2 T2 A2 DAC ARCHITECTURE The DAC core architecture of the AD5735 consists of two matched DAC sections. A simplified circuit diagram is shown in Figure 69. The four MSBs of the 12-bit data-word are decoded to drive 15 switches, E1 to E15. Each switch connects one of 15 matched resistors either to ground or to the reference buffer output. The remaining eight bits of the data-word drive Switch S0 to Switch S7 of an 8-bit voltage mode R-2R ladder network. VOUT RSET Figure 71. Voltage-to-Current Conversion Circuitry Voltage Output Amplifier The voltage output amplifier is capable of generating both unipolar and bipolar output voltages. It is capable of driving a load of 1 kΩ in parallel with 1 µF (with an external compensation capacitor) to AGND. The source and sink capabilities of the output amplifier are shown in Figure 22. The slew rate is 1.9 V/µs with a full-scale settling time of 18 µs max (10 V step). If remote sensing of the load is not required, connect +VSENSE_x directly to VOUT_x, and connect −VSENSE_x directly to AGND. −VSENSE_x must stay within ±3.0 V of AGND for specified operation. The difference in voltage between +VSENSE_x and VOUT_x should be added directly to the headroom requirement. 2R 2R 2R 2R Driving Large Capacitive Loads S0 S1 S7 E1 E2 E15 The voltage output amplifier is capable of driving capacitive loads of up to 2 µF with the addition of a 220 pF, nonpolarized compensation capacitor on each channel. The 220 pF capacitor is connected between the COMPLV_x pin and the VOUT_x pin. FOUR MSBs DECODED INTO 15 EQUAL SEGMENTS Figure 69. DAC Ladder Structure The voltage output from the DAC core can be • Buffered and scaled to output a software selectable unipolar or bipolar voltage range (see Figure 70) Converted to a current, which is then mirrored to the supply rail so that the application sees only a current source output (see Figure 71) Care should be taken to choose an appropriate value of compensation capacitor. This capacitor, while allowing the AD5735 to drive higher capacitive loads and reduce overshoot, increases the settling time of the part and, therefore, affects the bandwidth of the system. Without the compensation capacitor, capacitive loads of up to 10 nF can be driven. Reference Buffers Both the voltage and current outputs are supplied by VBOOST_x. The current and voltage are output on separate pins and cannot be output simultaneously. The current and voltage output pins of a channel can be tied together (see the Voltage and Current Output Pins on the Same Terminal section). The AD5735 can operate with either an external or internal reference. The reference input requires a 5 V reference for specified performance. This input voltage is then buffered before it is applied to the DAC. +VSENSE_X RANGE SCALING VOUT_X VOUT_X SHORT FAULT –VSENSE_X 09961-070 12-BIT DAC IOUT_x 2R 8-BIT R-2R LADDER • T1 A1 2R 09961-069 2R 12-BIT DAC 09961-071 The current ranges available are 0 mA to 20 mA, 4 mA to 20 mA, and 0 mA to 24 mA. The voltage ranges available are 0 V to 5 V, ±5 V, 0 V to 10 V, and ±10 V. The current and voltage outputs are available on separate pins, and only one output is active at any one time. The output configuration is user-selectable via the DAC control register. On-chip dynamic power control minimizes package power dissipation in current mode (see the Dynamic Power Control section). R3 Figure 70. Voltage Output Rev. B | Page 28 of 48 Data Sheet AD5735 POWER-ON STATE OF THE AD5735 On initial power-up of the AD5735, the state of the power-on reset circuit is dependent on the power-on condition (POC) pin. • • If POC = 0, both the voltage output and current output channels power up in tristate mode. If POC = 1, the voltage output channel powers up with a 30 kΩ pull-down resistor to ground, and the current output channel powers up in tristate mode. The output ranges are not enabled, but the default output range is 0 V to 5 V, and the clear code register is loaded with all 0s. Therefore, if the user clears the part after power-up, the output is actively driven to 0 V if the channel has been enabled for clear. Simultaneous Updating of All DACs To update all DACs simultaneously, LDAC is held high while data is clocked into the DAC data register. After LDAC is taken high, only the first write to the DAC data register of each channel is valid; subsequent writes to the DAC data register are ignored, although these subsequent writes are returned if a readback is initiated. All DAC outputs are updated by taking LDAC low after SYNC is taken high. OUTPUT AMPLIFIERS VREFIN After device power on, or a device reset, it is recommended to wait 100 μs or more before writing to the device to allow time for internal calibrations to take place. LDAC SERIAL INTERFACE 12-BIT DAC VOUT_x DAC REGISTER DAC INPUT REGISTER The AD5735 is controlled by a versatile 3-wire serial interface that operates at clock rates of up to 30 MHz and is compatible with SPI, QSPI, MICROWIRE, and DSP standards. Data coding is always straight binary. OFFSET AND GAIN CALIBRATION DAC DATA REGISTER SCLK SYNC SDIN The input shift register is 24 bits wide. Data is loaded into the device MSB first as a 24-bit word under the control of the serial clock input, SCLK. Data is clocked in on the falling edge of SCLK. If packet error checking (PEC) is enabled, an additional eight bits must be written to the AD5735, creating a 32-bit serial interface (see the Packet Error Checking section). The DAC outputs can be updated in one of two ways: individual DAC updating or simultaneous updating of all DACs. INTERFACE LOGIC SDO 09961-072 Input Shift Register Figure 72. Simplified Serial Interface of the Input Loading Circuitry for One DAC Channel TRANSFER FUNCTION Table 7 shows the input code to ideal output voltage relationship for the AD5735 for straight binary data coding of the ±10 V output range. Table 7. Input Code to Ideal Output Voltage Relationship Individual DAC Updating To update an individual DAC, LDAC is held low while data is clocked into the DAC data register. The addressed DAC output is updated on the rising edge of SYNC. See Table 3 and Figure 3 for timing information. Digital Input Straight Binary Data Coding MSB LSB1 1111 1111 1111 XXXX 1111 1111 1110 XXXX 1000 0000 0000 XXXX 0000 0000 0001 XXXX 0000 0000 0000 XXXX 1 X = don’t care. Rev. B | Page 29 of 48 Analog Output VOUT +2 VREF × (2047/2048) +2 VREF × (2046/2048) 0V −2 VREF × (2047/2048) −2 VREF AD5735 Data Sheet REGISTERS Table 8, Table 9, and Table 10 provide an overview of the registers for the AD5735. Table 8. Data Registers for the AD5735 Register DAC Data Registers Gain Registers Offset Registers Clear Code Registers Description The four DAC data registers (one register per DAC channel) are used to write a DAC code to each DAC channel. The DAC data bits are D15 to D4. The four gain registers (one register per DAC channel) are used to program the gain trim on a per-channel basis. The gain data bits are D15 to D4. The four offset registers (one register per DAC channel) are used to program the offset trim on a per-channel basis. The offset data bits are D15 to D4. The four clear code registers (one register per DAC channel) are used to program the clear code on a perchannel basis. The clear code data bits are D15 to D4. Table 9. Control Registers for the AD5735 Register Main Control Register DAC Control Registers Software Register DC-to-DC Control Register Slew Rate Control Registers Description The main control register is used to configure functions for the entire part. These functions include the following: enabling status readback during a write; enabling the output on all four DAC channels simultaneously; power-on of the dc-to-dc converter on all four DAC channels simultaneously; and enabling and configuring the watchdog timer. For more information, see the Main Control Register section. The four DAC control registers (one register per DAC channel) are used to configure the following functions on a per-channel basis: output range (for example, 4 mA to 20 mA or 0 V to 10 V); selection of the internal current sense resistor or an external current sense resistor; enabling/disabling the use of a clear code; enabling/disabling overrange on a voltage channel; enabling/disabling the internal circuitry (dc-to-dc converter, DAC, and internal amplifiers); power-on/power-off of the dc-to-dc converter; and enabling/ disabling the output channel. The software register is used to perform a reset, to toggle the user bit in the status register, and, as part of the watchdog timer feature, to verify correct data communication operation. The dc-to-dc control register is used to set the control parameters for the dc-to-dc converter: maximum output voltage, phase, and switching frequency. This register is also used to select the internal compensation resistor or an external compensation resistor for the dc-to-dc converter. The four slew rate control registers (one register per DAC channel) are used to program the slew rate of the DAC output. Table 10. Readback Register for the AD5735 Register Status Register Description The status register contains any fault information, as well as a user toggle bit. Rev. B | Page 30 of 48 Data Sheet AD5735 ENABLING THE OUTPUT Reprogramming the Output Range To correctly write to and set up the part from a power-on condition, use the following sequence: When changing the range of an output, the same sequence described in the Enabling the Output section should be used. It is recommended that the range be set to 0 V (zero scale or midscale) before the output is disabled. Because the dc-to-dc switching frequency, maximum output voltage, and phase have already been selected, there is no need to reprogram these values. Figure 74 provides a flowchart of this sequence. 3. 4. 5. Perform a hardware or software reset after initial power-on. Configure the dc-to-dc converter supply block. Set the dc-to-dc switching frequency, the maximum output voltage allowed, and the dc-to-dc converter phase between channels. Configure the DAC control register on a per-channel basis. Select the output range, and enable the dc-to-dc converter block (DC_DC bit). Other control bits can also be configured. Set the INT_ENABLE bit, but do not set the OUTEN (output enable) bit. Write the required code to the DAC data register. This step implements a full internal DAC calibration. For reduced output glitch, allow at least 200 µs before performing Step 5. Write to the DAC control register again to enable the output (set the OUTEN bit). Figure 73 provides a flowchart of this sequence. CHANNEL OUTPUT IS ENABLED. STEP 1: WRITE TO CHANNEL’S DAC DATA REGISTER. SET THE OUTPUT TO 0V (ZERO OR MIDSCALE). STEP 2: WRITE TO DAC CONTROL REGISTER. DISABLE THE OUTPUT (OUTEN = 0) AND SET THE NEW OUTPUT RANGE. KEEP THE DC_DC BIT AND THE INT_ENABLE BIT SET. STEP 3: WRITE VALUE TO THE DAC DATA REGISTER. POWER ON. STEP 4: WRITE TO DAC CONTROL REGISTER. RELOAD SEQUENCE AS IN STEP 2. SET THE OUTEN BIT TO ENABLE THE OUTPUT. STEP 1: PERFORM A SOFTWARE/HARDWARE RESET. 09961-074 1. 2. Figure 74. Programming Sequence to Change the Output Range STEP 2: WRITE TO DC-TO-DC CONTROL REGISTER TO SET DC-TO-DC CLOCK FREQUENCY, PHASE, AND MAXIMUM VOLTAGE. STEP 3: WRITE TO DAC CONTROL REGISTER. SELECT THE DAC CHANNEL AND OUTPUT RANGE. SET THE DC_DC BIT AND OTHER CONTROL BITS AS REQUIRED. SET THE INT_ENABLE BIT BUT DO NOT SET THE OUTEN BIT. STEP 5: WRITE TO DAC CONTROL REGISTER. RELOAD SEQUENCE AS IN STEP 3. SET THE OUTEN BIT TO ENABLE THE OUTPUT. 09961-073 STEP 4: WRITE TO ONE OR MORE DAC DATA REGISTERS. ALLOW AT LEAST 200µs BETWEEN STEP 3 AND STEP 5 FOR REDUCED OUTPUT GLITCH. Figure 73. Programming Sequence to Correctly Enable the Output Rev. B | Page 31 of 48 AD5735 Data Sheet DATA REGISTERS DAC Data Register The input shift register is 24 bits wide. When PEC is enabled, the input shift register is 32 bits wide, with the last eight bits corresponding to the PEC code (see the Packet Error Checking section for more information about PEC). When writing to a data register, the format shown in Table 11 must be used. When writing to a DAC data register, Bit D15 to Bit D4 are the DAC data bits. Table 13 shows the register format, and Table 12 describes the functions of Bit D23 to Bit D16. Table 11. Input Shift Register for a Write Operation to a Data Register MSB D23 R/W D22 DUT_AD1 D21 DUT_AD0 D20 DREG2 D19 DREG1 D18 DREG0 D17 DAC_AD1 D16 DAC_AD0 LSB D15 to D0 Data Table 12. Descriptions of Data Register Bits[D23:D16] Bit Name R/W DUT_AD1, DUT_AD0 DREG2, DREG1, DREG0 DAC_AD1, DAC_AD0 Description This bit indicates whether the addressed register is written to or read from. 0 = write to the addressed register. 1 = read from the addressed register. Used in association with the external pins AD1 and AD0, these bits determine which AD5735 device is being addressed by the system controller. DUT_AD1 DUT_AD0 Part Addressed 0 0 Pin AD1 = 0, Pin AD0 = 0 0 1 Pin AD1 = 0, Pin AD0 = 1 1 0 Pin AD1 = 1, Pin AD0 = 0 1 1 Pin AD1 = 1, Pin AD0 = 1 These bits select the register to be written to. If a control register is selected (DREG[2:0] = 111), the CREG bits in the control register select the specific control register to be written to (see Table 20). DREG2 DREG1 DREG0 Function 0 0 0 Write to DAC data register (one DAC channel) 0 0 1 Reserved 0 1 0 Write to gain register (one DAC channel) 0 1 1 Write to gain registers (all DAC channels) 1 0 0 Write to offset register (one DAC channel) 1 0 1 Write to offset registers (all DAC channels) 1 1 0 Write to clear code register (one DAC channel) 1 1 1 Write to a control register These bits are used to specify the DAC channel. If a write to the part does not apply to a specific DAC channel, these bits are don’t care bits. DAC_AD1 DAC_AD0 DAC Channel 0 0 DAC A 0 1 DAC B 1 0 DAC C 1 1 DAC D Table 13. Programming the DAC Data Register D23 R/W 1 D22 DUT_AD1 D21 DUT_AD0 D20 0 D19 0 D18 0 X = don’t care. Rev. B | Page 32 of 48 D17 DAC_AD1 D16 DAC_AD0 D15 to D4 DAC data D3 to D0 X1 Data Sheet AD5735 Gain Register DREG[2:0] bits to 100 (see Table 16). To write the same offset code to all four DAC channels at the same time, set the DREG[2:0] bits to 101. The offset register coding is straight binary, as shown in Table 17. The default code in the offset register is 0x8000, which results in zero offset programmed to the output (for more information, see the Digital Offset and Gain Control section). The 12-bit gain register allows the user to adjust the gain of each channel in steps of 1 LSB. To write to the gain register of one DAC channel, set the DREG[2:0] bits to 010 (see Table 14). To write the same gain code to all four DAC channels at the same time, set the DREG[2:0] bits to 011. The gain register coding is straight binary, as shown in Table 15. The default code in the gain register is 0xFFFF. The maximum recommended gain trim is approximately 50% of the programmed range to maintain accuracy (for more information, see the Digital Offset and Gain Control section). Clear Code Register The 12-bit clear code register allows the user to set the clear value of each channel. To configure a channel to be cleared when the CLEAR pin is activated, set the CLR_EN bit in the DAC control register for that channel (see Table 24). To write to the clear code register, set the DREG[2:0] bits to 110 (see Table 18). The default clear code is 0x0000 (for more information, see the Asynchronous Clear section). Offset Register The 12-bit offset register allows the user to adjust the offset of each channel by −2048 LSB to +2047 LSB in steps of 1 LSB. To write to the offset register of one DAC channel, set the Table 14. Programming the Gain Register R/W 0 DUT_AD1 DUT_AD0 Device address DREG2 0 DREG1 1 DREG0 0 DAC_AD1 DAC_AD0 DAC channel address D15 to D4 Gain adjustment D3 to D0 1111 Table 15. Gain Register Bit Descriptions Gain Adjustment +4096 LSB +4095 LSB … 1 LSB 0 LSB G15 1 1 … 0 0 G14 1 1 … 0 0 G13 to G5 111111111 111111111 … 000000000 000000000 G4 1 0 … 1 0 G3 to G0 1111 1111 1111 1111 1111 Table 16. Programming the Offset Register R/W 0 DUT_AD1 DUT_AD0 Device address DREG2 1 DREG1 0 DREG0 0 DAC_AD1 DAC_AD0 DAC channel address D15 to D4 Offset adjustment D3 to D0 0000 Table 17. Offset Register Bit Descriptions Offset Adjustment +2047 LSB +2046 LSB … No Adjustment (Default) … −2047 LSB −2048 LSB OF15 1 1 … 1 … 0 0 OF14 1 1 … 0 … 0 0 OF13 1 1 … 0 … 0 0 OF12 to OF5 11111111 11111111 … 00000000 … 00000000 00000000 OF4 1 0 … 0 … 1 0 OF3 to OF0 0000 0000 0000 0000 0000 0000 0000 Table 18. Programming the Clear Code Register R/W 0 DUT_AD1 DUT_AD0 Device address DREG2 1 DREG1 1 DREG0 0 Rev. B | Page 33 of 48 DAC_AD1 DAC_AD0 DAC channel address D15 to D4 Clear code D3 to D0 0000 AD5735 Data Sheet CONTROL REGISTERS Main Control Register When writing to a control register, the format shown in Table 19 must be used. See Table 12 for information about the configuration of Bit D23 to Bit D16. The control registers are addressed by setting the DREG[2:0] bits (Bits[D20:D18] in the input shift register) to 111 and then setting the CREG[2:0] bits to select the specific control register (see Table 20). The main control register options are shown in Table 21 and Table 22. See the Device Features section for more information about the features controlled by the main control register. Table 19. Input Shift Register for a Write Operation to a Control Register MSB D23 R/W D22 DUT_AD1 D21 DUT_AD0 D20 1 D19 1 D18 1 D17 DAC_AD1 D16 DAC_AD0 D15 CREG2 D14 CREG1 D13 CREG0 LSB D12 to D0 Data Table 20. Control Register Addresses (CREG[2:0] Bits) CREG2 (D15) 0 0 0 0 1 CREG1 (D14) 0 0 1 1 0 CREG0 (D13) 0 1 0 1 0 Control Register Slew rate control register (one per channel) Main control register DAC control register (one per channel) DC-to-DC control register Software register Table 21. Programming the Main Control Register D15 0 1 D14 0 D13 1 D12 POC D11 STATREAD D10 EWD D9 WD1 D8 WD0 D7 X1 D6 ShtCctLim D5 D4 OUTEN_ALL DCDC_ALL D3 to D0 X1 X = don’t care. Table 22. Main Control Register Bit Descriptions Bit Name POC STATREAD EWD WD1, WD0 ShtCctLim OUTEN_ALL DCDC_ALL Description The POC bit determines the state of the voltage output channels during normal operation. POC = 0: the output goes to the value set by the POC hardware pin when the voltage output is not enabled (default). POC = 1: the output goes to the opposite value of the POC hardware pin when the voltage output is not enabled. Enable status readback during a write. See the Status Readback During a Write section. 0 = disable status readback (default). 1 = enable status readback. Enable the watchdog timer. See the Watchdog Timer section. 0 = disable the watchdog timer (default). 1 = enable the watchdog timer. Timeout select bits. Used to select the timeout period for the watchdog timer. WD1 WD0 Timeout Period (ms) 0 0 5 0 1 10 1 0 100 1 1 200 Programmable short-circuit limit on the VOUT_x pin in the event of a short-circuit condition. 0 = 16 mA (default). 1 = 8 mA. Setting this bit to 1 enables the output on all four DACs simultaneously. Do not use the OUTEN_ALL bit when using the OUTEN bit in the DAC control register. Setting this bit to 1 powers up the dc-to-dc converter on all four channels simultaneously. To power down the dc-to-dc converters, all channel outputs must first be disabled. Do not use the DCDC_ALL bit when using the DC_DC bit in the DAC control register. Rev. B | Page 34 of 48 Data Sheet AD5735 DAC Control Register The DAC control register is used to configure each DAC channel. The DAC control register options are shown in Table 23 and Table 24. Table 23. Programming the DAC Control Register D15 0 1 D14 1 D13 0 D12 X1 D11 X1 D10 X1 D9 X1 D8 D7 D6 INT_ENABLE CLR_EN OUTEN D5 RSET D4 DC_DC D3 OVRNG D2 R2 D1 R1 D0 R0 X = don’t care. Table 24. DAC Control Register Bit Descriptions Bit Name INT_ENABLE CLR_EN OUTEN RSET DC_DC OVRNG R2, R1, R0 Description Powers up the dc-to-dc converter, DAC, and internal amplifiers for the selected channel. This bit applies to individual channels only; it does not enable the output. After setting this bit, it is recommended that a >200 µs delay be observed before enabling the output to reduce the output enable glitch. See Figure 29 and Figure 46 for plots of this glitch. Per-channel clear enable bit. This bit specifies whether the selected channel is cleared when the CLEAR pin is activated. 0 = channel is not cleared when the part is cleared (default). 1 = channel is cleared when the part is cleared. Enables or disables the selected output channel. 0 = channel disabled (default). 1 = channel enabled. Selects the internal current sense resistor or an external current sense resistor for the selected DAC channel. 0 = external resistor selected (default). 1 = internal resistor selected. Powers up or powers down the dc-to-dc converter on the selected channel. All dc-to-dc converters can be powered up simultaneously using the DCDC_ALL bit in the main control register. To power down the dc-to-dc converter, the OUTEN and INT_ENABLE bits must also be set to 0. 0 = dc-to-dc converter is powered down (default). 1 = dc-to-dc converter is powered up. Enables 20% overrange on the voltage output channel only. No current output overrange is available. 0 = overrange disabled (default). 1 = overrange enabled. Selects the output range to be enabled. R2 R1 R0 Output Range Selected 0 0 0 0 V to 5 V voltage range (default) 0 0 1 0 V to 10 V voltage range 0 1 0 ±5 V voltage range 0 1 1 ±10 V voltage range 1 0 0 4 mA to 20 mA current range 1 0 1 0 mA to 20 mA current range 1 1 0 0 mA to 24 mA current range Rev. B | Page 35 of 48 AD5735 Data Sheet Software Register The software register allows the user to perform a software reset of the part. This register is also used to set the user toggle bit, D11, in the status register and as part of the watchdog timer feature when that feature is enabled. Bit D12 in the software register can be used to ensure that communication has not been lost between the MCU and the AD5735 and that the datapath lines are working properly (that is, SDIN, SCLK, and SYNC). When the watchdog timer feature is enabled, the user must write 0x195 to Bits[D11:D0] of the software register within the timeout period. If this command is not received within the timeout period, the ALERT pin signals a fault condition. This command is only required when the watchdog timer feature is enabled. DC-to-DC Control Register The dc-to-dc control register allows the user to configure the dc-to-dc switching frequency and phase, as well as the maximum allowable dc-to-dc output voltage. The dc-to-dc control register options are shown in Table 27 and Table 28. Table 25. Programming the Software Register D15 1 D14 0 D13 0 D12 User program D11 to D0 Reset code/SPI code Table 26. Software Register Bit Descriptions Bit Name User Program Reset Code/SPI Code Description This bit is mapped to Bit D11 of the status register. When this bit is set to 1, Bit D11 of the status register is set to 1. When this bit is set to 0, Bit D11 of the status register is also set to 0. This feature can be used to ensure that the SPI pins are working correctly by writing a known bit value to this register and then reading back Bit D11 from the status register. Option Description Reset code Writing 0x555 to Bits[D11:D0] performs a software reset of the AD5735. SPI code If the watchdog timer feature is enabled, 0x195 must be written to the software register (Bits[D11:D0]) within the programmed timeout period (see Table 22). Table 27. Programming the DC-to-DC Control Register D15 0 1 D14 1 D13 1 D12 to D7 X1 D6 DC-DC comp D5 to D4 DC-DC phase D3 to D2 DC-DC freq D1 to D0 DC-DC MaxV X = don’t care. Table 28. DC-to-DC Control Register Bit Descriptions Bit Name DC-DC Comp DC-DC Phase DC-DC Freq DC-DC MaxV Description Selects the internal compensation resistor or an external compensation resistor for the dc-to-dc converter. See the DC-to-DC Converter Compensation Capacitors section and the AICC Supply Requirements—Slewing section. 0 = selects the internal 150 kΩ compensation resistor (default). 1 = bypasses the internal compensation resistor. When this bit is set to 1, an external compensation resistor must be used; this resistor is placed at the COMPDCDC_x pin in series with the 10 nF dc-to-dc compensation capacitor to ground. Typically, a resistor of ~50 kΩ is recommended. User-programmable dc-to-dc converter phase (between channels). 00 = all dc-to-dc converters clock on the same edge (default). 01 = Channel A and Channel B clock on the same edge; Channel C and Channel D clock on the opposite edge. 10 = Channel A and Channel C clock on the same edge; Channel B and Channel D clock on the opposite edge. 11 = Channel A, Channel B, Channel C, and Channel D clock 90° out of phase from each other. Switching frequency for the dc-to-dc converter; this frequency is divided down from the internal 13 MHz oscillator (see Figure 67 and Figure 68). 00 = 250 kHz ± 10%. 01 = 410 kHz ± 10% (default). 10 = 650 kHz ± 10%. Maximum allowed VBOOST_x voltage supplied by the dc-to-dc converter. 00 = 23 V + 1 V/−1.5 V (default). 01 = 24.5 V ± 1 V. 10 = 27 V ± 1 V. 11 = 29.5 V ± 1 V. Rev. B | Page 36 of 48 Data Sheet AD5735 Slew Rate Control Register This register is used to program the slew rate control for the selected DAC channel. This feature is available on both the current and voltage outputs. The slew rate control is enabled/ disabled and programmed on a per-channel basis. See Table 29 and the Digital Slew Rate Control section for more information. READBACK OPERATION Readback mode is invoked by setting the R/W bit = 1 in the serial input register write. See Table 30 for the bits associated with a readback operation. The DUT_AD1 and DUT_AD0 bits, in association with Bits[RD4:RD0], select the register to be read (see Table 31). The remaining data bits in the write sequence are don’t care bits. During the next SPI transfer, the data that appears on the SDO output contains the data from the previously addressed register (see Figure 4). This second SPI transfer should be either a request to read another register on a third data transfer or a no operation command. The no operation command for DUT Address 00 is 0x1CE000, for other DUT addresses, Bit D22 and Bit D21 are set accordingly. Readback Example To read back the gain register of AD5735 Device 1, Channel A, implement the following sequence: 1. 2. Write 0xA80000 to the input register to configure Device Address 1 for read mode with the gain register of Channel A selected. The data bits, D15 to D0, are don’t care bits. Execute another read command or a no operation command (0x3CE000). During this command, the data from the Channel A gain register is clocked out on the SDO line. Table 29. Programming the Slew Rate Control Register D15 0 1 D14 0 D13 0 D12 SREN D11 to D7 X1 D6 to D3 SR_CLOCK D2 to D0 SR_STEP X = don’t care. Table 30. Input Shift Register for a Read Operation MSB D23 R/W 1 D22 DUT_AD1 D21 DUT_AD0 D20 RD4 D19 RD3 D18 RD2 D17 RD1 X = don’t care. Table 31. Read Addresses (Bits[RD4:RD0]) RD4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 RD3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 RD2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 RD1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 RD0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Function Read DAC A data register Read DAC B data register Read DAC C data register Read DAC D data register Read DAC A control register Read DAC B control register Read DAC C control register Read DAC D control register Read DAC A gain register Read DAC B gain register Read DAC C gain register Read DAC D gain register Read DAC A offset register Read DAC B offset register Read DAC C offset register Read DAC D offset register Read DAC A clear code register Read DAC B clear code register Read DAC C clear code register Read DAC D clear code register Read DAC A slew rate control register Read DAC B slew rate control register Read DAC C slew rate control register Read DAC D slew rate control register Read status register Read main control register Read dc-to-dc control register Rev. B | Page 37 of 48 D16 RD0 LSB D15 to D0 X1 AD5735 Data Sheet Status Register read back on the SDO pin during every write sequence. Alternatively, if the STATREAD bit is not set, the status register can be read using the normal readback operation (see the Readback Operation section). The status register is a read-only register. This register contains any fault information, as a well as a ramp active bit (Bit D9) and a user toggle bit (Bit D11). When the STATREAD bit in the main control register is set, the status register contents can be Table 32. Decoding the Status Register MSB D15 D14 D13 D12 D11 D10 DC-DCD DC-DCC DC-DCB DC-DCA User PEC toggle error D9 Ramp active D8 Over temp D7 VOUT_D fault D6 VOUT_C fault D5 VOUT_B fault D4 VOUT_A fault D3 IOUT_D fault D2 IOUT_C fault D1 IOUT_B fault LSB D0 IOUT_A fault Table 33. Status Register Bit Descriptions Bit Name DC-DCD Description In current output mode, this bit is set if the dc-to-dc converter on Channel D cannot maintain compliance, for example, if the dc-to-dc converter is reaching its VMAX voltage; in this case, the IOUT_D fault bit is also set. See the DC-to-DC Converter VMAX Functionality section for more information about the operation of this bit under this condition. In voltage output mode, this bit is set if the dc-to-dc converter on Channel D is unable to regulate to 15 V as expected. When this bit is set, it does not result in the FAULT pin going high. DC-DCC In current output mode, this bit is set if the dc-to-dc converter on Channel C cannot maintain compliance, for example, if the dc-to-dc converter is reaching its VMAX voltage; in this case, the IOUT_C fault bit is also set. See the DC-to-DC Converter VMAX Functionality section for more information about the operation of this bit under this condition. In voltage output mode, this bit is set if the dc-to-dc converter on Channel C is unable to regulate to 15 V as expected. When this bit is set, it does not result in the FAULT pin going high. DC-DCB In current output mode, this bit is set if the dc-to-dc converter on Channel B cannot maintain compliance, for example, if the dc-to-dc converter is reaching its VMAX voltage; in this case, the IOUT_B fault bit is also set. See the DC-to-DC Converter VMAX Functionality section for more information about the operation of this bit under this condition. In voltage output mode, this bit is set if the dc-to-dc converter on Channel B is unable to regulate to 15 V as expected. When this bit is set, it does not result in the FAULT pin going high. DC-DCA In current output mode, this bit is set if the dc-to-dc converter on Channel A cannot maintain compliance, for example, if the dc-to-dc converter is reaching its VMAX voltage; in this case, the IOUT_A fault bit is also set. See the DC-to-DC Converter VMAX Functionality section for more information about the operation of this bit under this condition. In voltage output mode, this bit is set if the dc-to-dc converter on Channel A is unable to regulate to 15 V as expected. When this bit is set, it does not result in the FAULT pin going high. User Toggle PEC Error Ramp Active Over Temp VOUT_D Fault VOUT_C Fault VOUT_B Fault VOUT_A Fault IOUT_D Fault IOUT_C Fault IOUT_B Fault IOUT_A Fault User toggle bit. This bit is set or cleared via the software register and can be used to verify data communications, if needed. Denotes a PEC error on the last data-word received over the SPI interface. This bit is set while any output channel is slewing (digital slew rate control is enabled on at least one channel). This bit is set if the AD5735 core temperature exceeds approximately 150°C. This bit is set if a fault is detected on the VOUT_D pin. This bit is set if a fault is detected on the VOUT_C pin. This bit is set if a fault is detected on the VOUT_B pin. This bit is set if a fault is detected on the VOUT_A pin. This bit is set if a fault is detected on the IOUT_D pin. This bit is set if a fault is detected on the IOUT_C pin. This bit is set if a fault is detected on the IOUT_B pin. This bit is set if a fault is detected on the IOUT_A pin. Rev. B | Page 38 of 48 Data Sheet AD5735 DEVICE FEATURES FAULT OUTPUT The AD5735 is equipped with a FAULT pin, an active low, open-drain output that allows several AD5735 devices to be connected together to one pull-up resistor for global fault detection. The FAULT pin is forced active by any one of the following fault conditions: • • • • DAC INPUT REGISTER DAC DATA REGISTER DAC 09961-075 GAIN (M) REGISTER OFFSET (C) REGISTER The voltage at IOUT_x attempts to rise above the compliance range due to an open-loop circuit or insufficient power supply voltage. The internal circuitry that develops the fault output avoids using a comparator with windowed limits because this requires an actual output error before the FAULT output becomes active. Instead, the signal is generated when the internal amplifier in the output stage has less than approximately 1 V of remaining drive capability. Thus, the FAULT output is activated slightly before the compliance limit is reached. A short circuit is detected on a voltage output pin. The short-circuit current is limited to 16 mA or 8 mA, which is programmable by the user. If the AD5735 is used in unipolar supply mode, a short-circuit fault may be generated if the output voltage is below 50 mV. An interface error is detected due to a PEC failure (see the Packet Error Checking section). The core temperature of the AD5735 exceeds approximately 150°C. The VOUT_x fault, IOUT_x fault, PEC error, and over temp bits of the status register are used in conjunction with the FAULT output to inform the user which fault condition caused the FAULT output to be activated. VOLTAGE OUTPUT SHORT-CIRCUIT PROTECTION Under normal operation, the voltage output sinks/sources up to 12 mA and maintains specified operation. The maximum output current or short-circuit current is programmable by the user and can be set to 16 mA or 8 mA. If a short circuit is detected, the FAULT pin goes low, and the relevant VOUT_x fault bit is set in the status register (see Table 33). DIGITAL OFFSET AND GAIN CONTROL Each DAC channel has a gain (M) register and an offset (C) register, which allow trimming out of the gain and offset errors of the entire signal chain. Data from the DAC data register is operated on by a digital multiplier and adder controlled by the contents of the gain and offset registers; the calibrated DAC data is then stored in the DAC input register (see Figure 75). Figure 75. Digital Offset and Gain Control Although Figure 75 indicates a multiplier and adder for each channel, the device has only one multiplier and one adder, which are shared by all four channels. This design has implications for the update speed when several channels are updated at once (see Table 3). When data is written to the gain (M) or offset (C) register, the output is not automatically updated. Instead, the next write to the DAC channel uses the new gain and offset values to perform a new calibration and automatically updates the channel. The output data from the calibration is routed to the DAC input register. This data is then loaded to the DAC, as described in the Serial Interface section. Both the gain register and the offset register have 12 bits of resolution. The correct order to calibrate the gain and offset is to first calibrate the gain and then calibrate the offset. The value (in decimal) that is written to the DAC input register can be calculated as follows: Code DACRegister = D × ( M + 1) 212 + C − 211 (1) where: D is the code loaded to the DAC data register of the DAC channel. M is the code in the gain register (default code = 212 − 1). C is the code in the offset register (default code = 211). STATUS READBACK DURING A WRITE The AD5735 can be configured to read back the contents of the status register during every write sequence. This feature is enabled using the STATREAD bit in the main control register. When this feature is enabled, the user can continuously monitor the status register and act quickly in the case of a fault. When status readback during a write is enabled, the contents of the 16-bit status register (see Table 33) are output on the SDO pin, as shown in Figure 5. When the AD5735 is powered up, the status readback during a write feature is disabled. When this feature is enabled, readback of registers other than the status register is not available. To read back any other register, clear the STATREAD bit before following the readback sequence (see the Readback Operation section). The STATREAD bit can be set high again after the register read. Rev. B | Page 39 of 48 AD5735 Data Sheet ASYNCHRONOUS CLEAR ignored. If status readback during a write is disabled, the user can still use the normal readback operation to monitor status register activity with PEC. CLEAR is an active high, edge sensitive input that allows the output to be cleared to a preprogrammed 12-bit code. This code is user-programmable via a per-channel 12-bit clear code register. WATCHDOG TIMER When enabled, an on-chip watchdog timer generates an alert signal if 0x195 is not written to the software register within the programmed timeout period. This feature is useful to ensure that communication has not been lost between the MCU and the AD5735 and that the datapath lines are working properly (that is, SDIN, SCLK, and SYNC). If 0x195 is not received by the software register within the timeout period, the ALERT pin signals a fault condition. The ALERT pin is active high and can be connected directly to the CLEAR pin to enable a clear in the event that communication from the MCU is lost. For a channel to be cleared, set the CLR_EN bit in the DAC control register for that channel. If the clear function on a channel is not enabled, the output remains in its current state, independent of the level of the CLEAR pin. When the CLEAR signal returns low, the relevant outputs remain cleared until a new value is programmed to them. PACKET ERROR CHECKING To verify that data has been received correctly in noisy environments, the AD5735 offers the option of packet error checking based on an 8-bit cyclic redundancy check (CRC-8). The device controlling the AD5735 should generate an 8-bit frame check sequence using the following polynomial: To enable the watchdog timer and set the timeout period (5 ms, 10 ms, 100 ms, or 200 ms), program the main control register (see Table 21 and Table 22). C(x) = x8 + x2 + x1 + 1 ALERT OUTPUT This value is added to the end of the data-word, and 32 bits are sent to the AD5735 before SYNC goes high. If the AD5735 sees a 32-bit frame, it performs the error check when SYNC goes high. If the error check is valid, the data is written to the selected register. If the error check fails, the FAULT pin goes low and the PEC error bit in the status register is set. After the status register is read, FAULT returns high (assuming that there are no other faults), and the PEC error bit is cleared automatically. The AD5735 is equipped with an ALERT pin. This pin is an active high CMOS output. The AD5735 also has an internal watchdog timer. When enabled, the watchdog timer monitors SPI communications. If 0x195 is not received by the software register within the timeout period, the ALERT pin is activated. INTERNAL REFERENCE The AD5735 contains an integrated 5 V voltage reference with initial accuracy of ±5 mV maximum and a temperature coefficient of ±10 ppm/°C maximum. The reference voltage is buffered and is externally available for use elsewhere within the system. UPDATE ON SYNC HIGH SYNC EXTERNAL CURRENT SETTING RESISTOR SCLK MSB D23 SDIN RSET is an internal sense resistor that is part of the voltage-tocurrent conversion circuitry (see Figure 71). The stability of the output current value over temperature is dependent on the stability of the RSET value. To improve the stability of the output current over temperature, the internal RSET resistor, R1, can be bypassed and an external, 15 kΩ, low drift resistor can be connected to the RSET_x pin of the AD5735. The external resistor is selected via the DAC control register (see Table 24). LSB D0 24-BIT DATA 24-BIT DATA TRANSFER—NO ERROR CHECKING UPDATE ON SYNC HIGH ONLY IF ERROR CHECK PASSED SYNC SCLK MSB D31 FAULT 24-BIT DATA D7 D0 8-BIT CRC FAULT PIN GOES LOW IF ERROR CHECK FAILS 09961-180 SDIN LSB D8 32-BIT DATA TRANSFER WITH ERROR CHECKING Figure 76. PEC Timing Packet error checking can be used for transmitting and receiving data packets. If status readback during a write is enabled, the PEC values returned during the status readback operation should be Table 1 provides the performance specifications for the AD5735 with both the internal RSET resistor and an external, 15 kΩ RSET resistor. The use of an external RSET resistor allows for improved performance over the internal RSET resistor option. The external RSET resistor specifications assume an ideal resistor; the actual performance depends on the absolute value and temperature coefficient of the resistor used. This directly affects the gain error of the output and, thus, the total unadjusted error. To arrive at the gain/TUE error of the output with a specific external RSET resistor, add the absolute error percentage of the RSET resistor directly to the gain/TUE error of the AD5735 with the external RSET resistor, as shown in Table 1 (expressed in % FSR). Rev. B | Page 40 of 48 Data Sheet AD5735 DIGITAL SLEW RATE CONTROL The digital slew rate control feature of the AD5735 allows the user to control the rate at which the output value changes. This feature is available on both the current and voltage outputs. With the slew rate control feature disabled, the output value changes at a rate limited by the output drive circuitry and the attached load. To reduce the slew rate, the user can enable the digital slew rate control feature using the SREN bit of the slew rate control register (see Table 29). When slew rate control is enabled, the output, instead of slewing directly between two values, steps digitally at a rate defined by the SR_CLOCK and SR_STEP parameters. These parameters are accessible via the slew rate control register (see Table 29). • • SR_CLOCK defines the rate at which the digital slew is updated; for example, if the selected update rate is 8 kHz, the output is updated every 125 µs. SR_STEP defines by how much the output value changes at each update. Together, these parameters define the rate of change of the output value. Table 34 and Table 35 list the range of values for the SR_CLOCK and SR_STEP parameters, respectively. Table 34. Slew Rate Update Clock Options SR_CLOCK 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 1 Update Clock Frequency1 64 kHz 32 kHz 16 kHz 8 kHz 4 kHz 2 kHz 1 kHz 500 Hz 250 Hz 125 Hz 64 Hz 32 Hz 16 Hz 8 Hz 4 Hz 0.5 Hz These clock frequencies are divided down from the 13 MHz internal oscillator (see Table 1, Figure 67, and Figure 68). The following equation describes the slew rate as a function of the step size, the update clock frequency, and the LSB size. Slew Rate = Output Change Step Size × Update Clock Frequency × LSB Size where: Slew Rate is expressed in seconds. Output Change is expressed in amperes for IOUT_x or in volts for VOUT_x. The update clock frequency for any given value is the same for all output ranges. The step size, however, varies across output ranges for a given value of step size because the LSB size is different for each output range. When the slew rate control feature is enabled, all output changes occur at the programmed slew rate (see the DC-to-DC Converter Settling Time section for more information). For example, if the CLEAR pin is asserted, the output slews to the clear value at the programmed slew rate (assuming that the channel is enabled to be cleared). If more than one channel is enabled for digital slew rate control, care must be taken when asserting the CLEAR pin. If a channel under slew rate control is slewing when the CLEAR pin is asserted, other channels under slew rate control may change directly to their clear code not under slew rate control. DYNAMIC POWER CONTROL When configured in current output mode, the AD5735 provides integrated dynamic power control using a dc-to-dc boost converter circuit. This circuit reduces power consumption compared with standard designs. In standard current input module designs, the load resistor values can range from typically 50 Ω to 750 Ω. Output module systems must source enough voltage to meet the compliance voltage requirement across the full range of load resistor values. For example, in a 4 mA to 20 mA loop when driving 20 mA, a compliance voltage of >15 V is required. When driving 20 mA into a 50 Ω load, a compliance voltage of only 1 V is required. The AD5735 circuitry senses the output voltage and regulates this voltage to meet the compliance requirements plus a small headroom voltage. The AD5735 is capable of driving up to 24 mA through a 1 kΩ load. Table 35. Slew Rate Step Size Options SR_STEP 000 001 010 011 100 101 110 111 Step Size (LSB) 1 2 4 16 32 64 128 256 Rev. B | Page 41 of 48 AD5735 Data Sheet DC-TO-DC CONVERTERS DC-to-DC Converter VMAX Functionality The AD5735 contains four independent dc-to-dc converters. These are used to provide dynamic control of the VBOOST_x supply voltage for each channel (see Figure 71). Figure 77 shows the discrete components needed for the dc-to-dc circuitry, and the following sections describe component selection and operation of this circuitry. The maximum VBOOST_x voltage is set in the dc-to-dc control register (23 V, 24.5 V, 27 V, or 29.5 V; see Table 28). When the maximum voltage is reached, the dc-to-dc converter is disabled, and the VBOOST_x voltage is allowed to decay by ~0.4 V. After the VBOOST_x voltage decays by ~0.4 V, the dc-to-dc converter is reenabled, and the voltage ramps up again to VMAX, if still required. This operation is shown in Figure 78. 10Ω VBOOST_x CFILTER 0.1µF SWx 29.6 Table 36. Recommended Components for a DC-to-DC Converter Component XAL4040-103 GRM32ER71H475KA88L PMEG3010BEA Value 10 µH 4.7 µF 0.285 VF 0mA TO 24mA RANGE, 24mA OUTPUT OUTPUT UNLOADED 29.4 Figure 77. DC-to-DC Circuit Symbol LDCDC CDCDC DDCDC VMAX DC-DCx BIT 29.5 Manufacturer Coilcraft® Murata NXP When a channel current output is enabled, the converter regulates the VBOOST_x supply to 7.4 V (±5%) or (IOUT × RLOAD + Headroom), whichever is greater (see Figure 51 for a plot of headroom supplied vs. output current). In voltage output mode with the output disabled, the converter regulates the VBOOST_x supply to 15 V (±5%). In current output mode with the output disabled, the converter regulates the VBOOST_x supply to 7.4 V (±5%). Within a channel, the VOUT_x and IOUT_x stages share a common VBOOST_x supply; therefore, the outputs of the IOUT_x and VOUT_x stages can be tied together (see the Voltage and Current Output Pins on the Same Terminal section). DC-to-DC Converter Settling Time In current output mode, the settling time for a step greater than ~1 V (IOUT × RLOAD) is dominated by the settling time of the dc-todc converter. The exception to this is when the required voltage at the IOUT_x pin plus the compliance voltage is below 7.4 V (±5%). Figure 47 shows a typical plot of the output settling time. This plot is for a 1 kΩ load. The settling time for smaller loads is faster. The settling time for current steps less than 24 mA is also faster. 29.1 DC-DC MaxV BITS = 29.5V DC-DCx BIT = 1 29.0 fSW = 410kHz 28.9 TA = 25°C 28.7 DC-DCx BIT = 0 28.6 0 DC-to-DC Converter Operation DC-to-DC Converter Output Voltage 29.2 28.8 It is recommended that a 10 Ω, 100 nF low-pass RC filter be placed after CDCDC. This filter consumes a small amount of power but reduces the amount of ripple on the VBOOST_x supply. The on-board dc-to-dc converters use a constant frequency, peak current mode control scheme to step up an AVCC input of 4.5 V to 5.5 V to drive the AD5735 output channel. These converters are designed to operate in discontinuous conduction mode with a duty cycle of <90% typical. Discontinuous conduction mode refers to a mode of operation where the inductor current goes to zero for an appreciable percentage of the switching cycle. The dc-to-dc converters are nonsynchronous; that is, they require an external Schottky diode. 29.3 0.5 1.0 1.5 2.0 2.5 TIME (ms) 3.0 3.5 4.0 09961-183 CDCDC 4.7µF RFILTER VBOOST_x VOLTAGE (mV) CIN ≥10µF DDCDC 10µH 09961-077 LDCDC AV CC Figure 78. Operation on Reaching VMAX As shown in Figure 78, the DC-DCx bit in the status register is asserted when the AD5735 ramps up to the VMAX value but is deasserted when the voltage decays to VMAX − ~0.4 V. DC-to-DC Converter On-Board Switch The AD5735 contains a 0.425 Ω internal switch. The switch current is monitored on a pulse-by-pulse basis and is limited to 0.8 A peak current. DC-to-DC Converter Switching Frequency and Phase The AD5735 dc-to-dc converter switching frequency can be selected from the dc-to-dc control register (see Table 28). The phasing of the channels can also be adjusted so that the dc-to-dc converters can clock on different edges. For typical applications, a 410 kHz frequency is recommended. At light loads (low output current and small load resistor), the dc-to-dc converter enters a pulse-skipping mode to minimize switching power dissipation. DC-to-DC Converter Inductor Selection For typical 4 mA to 20 mA applications, a 10 µH inductor (such as the XAL4040-103 from Coilcraft), combined with a switching frequency of 410 kHz, allows up to 24 mA to be driven into a load resistance of up to 1 kΩ with an AVCC supply of 4.5 V to 5.5 V. It is important to ensure that the inductor can handle the peak current without saturating, especially at the maximum ambient temperature. If the inductor enters saturation mode, efficiency decreases. The inductance value also drops during saturation and may result in the dc-to-dc converter circuit not being able to supply the required output power. Rev. B | Page 42 of 48 Data Sheet AD5735 DC-to-DC Converter External Schottky Diode Selection AICC SUPPLY REQUIREMENTS—STATIC The AD5735 requires an external Schottky diode for correct operation. Ensure that the Schottky diode is rated to handle the maximum reverse breakdown voltage expected in operation and that the maximum junction temperature of the diode is not exceeded. The average current of the diode is approximately equal to the ILOAD current. Diodes with larger forward voltage drops result in a decrease in efficiency. The dc-to-dc converter is designed to supply a VBOOST_x voltage of VBOOST_x = IOUT × RLOAD + Headroom See Figure 51 for a plot of headroom supplied vs. output current. Therefore, for a fixed load and output voltage, the output current of the dc-to-dc converter can be calculated by the following formula: DC-to-DC Converter Compensation Capacitors The output capacitor affects the ripple voltage of the dc-to-dc converter and indirectly limits the maximum slew rate at which the channel output current can rise. The ripple voltage is caused by a combination of the capacitance and the equivalent series resistance (ESR) of the capacitor. For typical applications, a ceramic capacitor of 4.7 µF is recommended. Larger capacitors or parallel capacitors improve the ripple at the expense of reduced slew rate. Larger capacitors also affect the current requirements of the AVCC supply while slewing (see the AICC Supply Requirements—Slewing section). The capacitance at the output of the dc-to-dc converter should be >3 µF under all operating conditions. The input capacitor provides much of the dynamic current required for the dc-to-dc converter and should be a low ESR component. For the AD5735, a low ESR tantalum or ceramic capacitor of 10 µF is recommended for typical applications. Ceramic capacitors must be chosen carefully because they can exhibit a large sensitivity to dc bias voltages and temperature. X5R or X7R dielectrics are preferred because these capacitors remain stable over wider operating voltage and temperature ranges. Care must be taken if selecting a tantalum capacitor to ensure a low ESR value. = I OUT × V BOOST (3) ηVBOOST × AVCC where: IOUT is the output current from IOUT_x in amperes. ηVBOOST is the efficiency at VBOOST_x as a fraction (see Figure 53 and Figure 54). AICC SUPPLY REQUIREMENTS—SLEWING The AICC current requirement while slewing is greater than in static operation because the output power increases to charge the output capacitance of the dc-to-dc converter. This transient current can be quite large (see Figure 79), although the methods described in the Reducing AICC Current Requirements section can reduce the requirements on the AVCC supply. If not enough AICC current can be provided, the AVCC voltage drops. Due to this AVCC drop, the AICC current required for slewing increases further, causing the voltage at AVCC to drop further (see Equation 3). In this case, the VBOOST_x voltage and, therefore, the output voltage, may never reach their intended values. Because the AVCC voltage is common to all channels, this voltage drop may also affect other channels. 0.8 30 0.7 25 0.6 0mA TO 24mA RANGE 1kΩ LOAD fSW = 410kHz INDUCTOR = 10µH (XAL4040-103) TA = 25°C 0.5 0.4 20 15 0.3 10 0.2 AICC IOUT VBOOST 0.1 Rev. B | Page 43 of 48 5 0 0 0 0.5 1.0 1.5 TIME (ms) 2.0 2.5 Figure 79. AICC Current vs. Time for 24 mA Step Through 1 kΩ Load with Internal Compensation Resistor 09961-184 DC-to-DC Converter Input and Output Capacitor Selection Power Out Efficiency × AVCC IOUT_x CURRENT (mA)/ VBOOST_x VOLTAGE (V) Alternatively, an external compensation resistor can be used in series with the compensation capacitor by setting the DC-DC comp bit in the dc-to-dc control register (see Table 28). In this case, a resistor of ~50 kΩ is recommended. The advantages of this configuration are described in the AICC Supply Requirements— Slewing section. For typical applications, a 10 nF dc-to-dc compensation capacitor is recommended. AI CC = AICC CURRENT (A) Because the dc-to-dc converter operates in discontinuous conduction mode, the uncompensated transfer function is essentially a single-pole transfer function. The pole frequency of the transfer function is determined by the output capacitance, input and output voltage, and output load of the dc-to-dc converter. The AD5735 uses an external capacitor in conjunction with an internal 150 kΩ resistor to compensate the regulator loop. (2) AD5735 Data Sheet Reducing AICC Current Requirements Using Slew Rate Control Two main methods can be used to reduce the AICC current requirements. One method is to add an external compensation resistor, and the other is to use slew rate control. These methods can be used together. Using slew rate control can greatly reduce the current requirements of the AVCC supply, as shown in Figure 82. 0.8 0.5 20 0.4 16 0.3 12 0.2 8 AICC IOUT VBOOST 0.1 4 0 0 0 0.5 1.0 1.5 TIME (ms) 0.3 12 0.2 8 0.1 4 2.0 2.5 AICC CURRENT (A) 0.6 28 24 0.5 20 0.4 16 0.3 12 0.2 8 0.1 4 0 0 0.5 1.0 1.5 TIME (ms) 2.0 IOUT_x CURRENT (mA)/V BOOST_x VOLTAGE (V) 0mA TO 24mA RANGE 500Ω LOAD fSW = 410kHz INDUCTOR = 10µH (XAL4040-103) TA = 25°C 0 2.5 2 3 TIME (ms) 4 5 6 When using slew rate control, it is important to remember that the output cannot slew faster than the dc-to-dc converter. The dc-to-dc converter slews slowest at higher currents through large loads (for example, 1 kΩ). The slew rate is also dependent on the configuration of the dc-to-dc converter. Two examples of the dc-to-dc converter output slew are shown in Figure 80 and Figure 81. (VBOOST corresponds to the output voltage of the dc-to-dc converter.) 09961-186 0.7 1 Figure 82. AICC Current vs. Time for 24 mA Step Through 1 kΩ Load with Slew Rate Control 32 AICC IOUT VBOOST 0 0 Figure 80. AICC Current vs. Time for 24 mA Step Through 1 kΩ Load with External 51 kΩ Compensation Resistor 0.8 IOUT_x CURRENT (mA)/ VBOOST_x VOLTAGE (V) 16 0 IOUT_x CURRENT (mA)/ VBOOST_x VOLTAGE (V) 24 20 0.4 09961-185 AICC CURRENT (A) 0.6 28 24 AICC IOUT VBOOST 0.5 32 0mA TO 24mA RANGE 1kΩ LOAD fSW = 410kHz INDUCTOR = 10µH (XAL4040-103) TA = 25°C 0.7 0.6 AICC CURRENT (A) A compensation resistor can be placed at the COMPDCDC_x pin in series with the 10 nF compensation capacitor. A 51 kΩ external compensation resistor is recommended. This compensation increases the slew time of the current output but reduces the AICC transient current requirements. Figure 80 shows a plot of AICC current for a 24 mA step through a 1 kΩ load when using a 51 kΩ compensation resistor. The compensation resistor reduces the current requirements through smaller loads even further, as shown in Figure 81. 28 09961-187 0.7 Adding an External Compensation Resistor 0.8 32 0mA TO 24mA RANGE 1kΩ LOAD fSW = 410kHz INDUCTOR = 10µH (XAL4040-103) TA = 25°C Figure 81. AICC Current vs. Time for 24 mA Step Through 500 Ω Load with External 51 kΩ Compensation Resistor Rev. B | Page 44 of 48 Data Sheet AD5735 APPLICATIONS INFORMATION VOLTAGE AND CURRENT OUTPUT PINS ON THE SAME TERMINAL When using a channel of the AD5735, the current and voltage output pins can be connected to two separate terminals or tied together and connected to a single terminal. The two output pins can be tied together because only the voltage output or the current output can be enabled at any one time. When the current output is enabled, the voltage output is in tristate mode, and when the voltage output is enabled, the current output is in tristate mode. When the two output pins are tied together, the POC pin must be tied low and the POC bit in the main control register set to 0, or, if the POC pin is tied high, the POC bit in the main control register must be set to 1 before the current output is enabled. As shown in the Absolute Maximum Ratings section, the output tolerances are the same for both the voltage and current output pins. The +VSENSE_x and −VSENSE_x connections are buffered so that current leakage into these pins is negligible when the part is operated in current output mode. CURRENT OUTPUT MODE WITH INTERNAL RSET When using the internal RSET resistor in current output mode, the output is significantly affected by how many other channels using the internal RSET are enabled and by the dc crosstalk from these channels. The internal RSET specifications in Table 1 are for all four channels enabled with the internal RSET selected and outputting the same code. For every channel enabled with the internal RSET, the offset error decreases. For example, with one current output enabled using the internal RSET, the offset error is 0.075% FSR. This value decreases proportionally as more current channels are enabled; the offset error is 0.056% FSR on each of two channels, 0.029% FSR on each of three channels, and 0.01% FSR on each of four channels. Similarly, the dc crosstalk when using the internal RSET is proportional to the number of current output channels enabled with the internal RSET. For example, with the measured channel at 0x8000 and another channel going from zero to full scale, the dc crosstalk is −0.011% FSR. With two other channels going from zero to full scale, the dc crosstalk is −0.019% FSR, and with all three other channels going from zero to full scale, it is −0.025% FSR. For the full-scale error measurement in Table 1, all channels are at 0xFFFF. This means that as any channel goes to zero scale, the full-scale error increases due to the dc crosstalk. For example, with the measured channel at 0xFFFF and three channels at zero scale, the full-scale error is 0.025% FSR. Similarly, if only one channel is enabled in current output mode with the internal RSET, the full-scale error is 0.025% FSR + 0.075% FSR = 0.1% FSR. PRECISION VOLTAGE REFERENCE SELECTION To achieve the optimum performance from the AD5735 over its full operating temperature range, a precision voltage reference must be used. Care should be taken with the selection of the precision voltage reference. The voltage applied to the reference inputs is used to provide a buffered reference for the DAC cores. Therefore, any error in the voltage reference is reflected in the outputs of the AD5735. Four possible sources of error must be considered when choosing a voltage reference for high accuracy applications: initial accuracy, long-term drift, temperature coefficient of the output voltage, and output voltage noise. Initial accuracy error on the output voltage of an external reference can lead to a full-scale error in the DAC. Therefore, to minimize these errors, a reference with a low initial accuracy error specification is preferred. Choosing a reference with an output trim adjustment, such as the ADR435, allows a system designer to trim out system errors by setting the reference voltage to a voltage other than the nominal. The trim adjustment can be used at any temperature to trim out any error. Long-term drift is a measure of how much the reference output voltage drifts over time. A reference with a tight long-term drift specification ensures that the overall solution remains relatively stable over its entire lifetime. The temperature coefficient of the reference output voltage affects INL, DNL, and TUE. A reference with a tight temperature coefficient specification should be chosen to reduce the dependence of the DAC output voltage on ambient temperature. In high accuracy applications, which have a relatively low noise budget, reference output voltage noise must be considered. Choosing a reference with as low an output noise voltage as practical for the system resolution required is important. Precision voltage references such as the ADR435 (XFET® design) produce low output noise in the 0.1 Hz to 10 Hz bandwidth. However, as the circuit bandwidth increases, filtering the output of the reference may be required to minimize the output noise. Table 37. Recommended Precision Voltage References Part No. ADR445 ADR02 ADR435 ADR395 AD586 Initial Accuracy (mV Maximum) ±2 ±3 ±2 ±5 ±2.5 Long-Term Drift (ppm Typical) 50 50 40 50 15 Rev. B | Page 45 of 48 Temperature Coefficient (ppm/°C Maximum) 3 3 3 9 10 0.1 Hz to 10 Hz Noise (µV p-p Typical) 2.25 10 8 8 4 AD5735 Data Sheet DRIVING INDUCTIVE LOADS MICROPROCESSOR INTERFACING When driving inductive or poorly defined loads, a capacitor may be required between the IOUT_x pin and the AGND pin to ensure stability. A 0.01 µF capacitor between IOUT_x and AGND ensures stability of a load of 50 mH. The capacitive component of the load may cause slower settling, although this may be masked by the settling time of the AD5735. There is no maximum capacitance limit for the current output of the AD5735. Microprocessor interfacing to the AD5735 is via a serial bus that uses a protocol compatible with microcontrollers and DSP processors. The communication channel is a 3-wire minimum interface consisting of a clock signal, a data signal, and a latch signal. The AD5735 requires a 24-bit data-word with data valid on the falling edge of SCLK. TRANSIENT VOLTAGE PROTECTION The AD5735 contains ESD protection diodes that prevent damage from normal handling. The industrial control environment can, however, subject I/O circuits to much higher transients. To protect the AD5735 from excessively high voltage transients, external power diodes and a surge current limiting resistor (RP) are required, as shown in Figure 83. A typical value for RP is 10 Ω. The two protection diodes and the resistor (RP) must have appropriate power ratings. AD5735-to-ADSP-BF527 Interface The AD5735 can be connected directly to the SPORT interface of the ADSP-BF527, an Analog Devices, Inc., Blackfin® DSP. Figure 84 shows how the SPORT interface can be connected to control the AD5735. AD5735 RFILTER CDCDC 4.7µF 10Ω SPORT_TFS SYNC SPORT_TSCLK SCLK SPORT_DT0 SDIN CFILTER 0.1µF ADSP-BF527 VBOOST_x IOUT_x AGND GPIO0 D2 RLOAD 09961-079 AD5735 D1 RP Figure 83. Output Transient Voltage Protection LDAC 09961-080 (FROM DC-TO-DC CONVERTER) The DAC output update is initiated either on the rising edge of LDAC or, if LDAC is held low, on the rising edge of SYNC. The contents of the registers can be read using the readback function. Figure 84. AD5735-to-ADSP-BF527 SPORT Interface LAYOUT GUIDELINES Grounding Further protection can be provided using transient voltage suppressors (TVSs), also referred to as transorbs. These components are available as unidirectional suppressors, which protect against positive high voltage transients, and as bidirectional suppressors, which protect against both positive and negative high voltage transients. Transient voltage suppressors are available in a wide range of standoff and breakdown voltage ratings. The TVS should be sized with the lowest breakdown voltage possible while not conducting in the functional range of the current output. It is recommended that all field connected nodes be protected. The voltage output node can be protected with a similar circuit, where D2 and the transorb are connected to AVSS. For the voltage output node, the +VSENSE_x pin should also be protected with a large value series resistance to the transorb, such as 5 kΩ. In this way, the IOUT_x and VOUT_x pins can also be tied together and share the same protection circuitry. In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. The printed circuit board on which the AD5735 is mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board. If the AD5735 is in a system where multiple devices require an AGND-to-DGND connection, the connection should be made at one point only. The star ground point should be established as close as possible to the device. The GNDSWx pin and the ground connection for the AVCC supply are referred to as PGND. PGND should be confined to certain areas of the board, and the PGND-to-AGND connection should be made at one point only. Supply Decoupling The AD5735 should have ample supply bypassing of 10 µF in parallel with 0.1 µF on each supply, located as close to the package as possible, ideally right up against the device. The 10 µF capacitors are the tantalum bead type. The 0.1 µF capacitors should have low effective series resistance (ESR) and low effective series inductance (ESL), such as the common ceramic types, which provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching. Rev. B | Page 46 of 48 Data Sheet AD5735 • The power supply lines of the AD5735 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals such as clocks should be shielded with digital ground to prevent radiating noise to other parts of the board and should never be run near the reference inputs. A ground line routed between the SDIN and SCLK traces helps reduce crosstalk between them (not required on a multilayer board that has a separate ground plane, but separating the lines helps). It is essential to minimize noise on the REFIN line because it couples through to the DAC output. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other to reduce the effects of feedthrough on the board. A microstrip technique is by far the best method, but it is not always possible with a double-sided board. In this technique, the component side of the board is dedicated to ground plane, and signal traces are placed on the solder side. DC-to-DC Converters To achieve high efficiency, good regulation, and stability, a well-designed printed circuit board layout is required. Keep high current traces as short and as wide as possible. The path from CIN through the inductor (LDCDC) to SWx and PGND should be able to handle a minimum of 1 A. Place the compensation components as close as possible to the COMPDCDC_x pin. Avoid routing high impedance traces near any node connected to SWx or near the inductor to prevent radiated noise injection. • • GALVANICALLY ISOLATED INTERFACE In many process control applications, it is necessary to provide an isolation barrier between the controller and the unit being controlled to protect and isolate the controlling circuitry from any hazardous common-mode voltages that may occur. The Analog Devices iCoupler® products can provide voltage isolation in excess of 2.5 kV. The serial loading structure of the AD5735 makes it ideal for isolated interfaces because the number of interface lines is kept to a minimum. Figure 85 shows a 4-channel isolated interface to the AD5735 using an ADuM1411. For more information, visit www.analog.com. MICROCONTROLLER Follow these guidelines when designing printed circuit boards (see Figure 77): • • • Keep the low ESR input capacitor, CIN, close to AVCC and PGND. Keep the high current path from CIN through the inductor (LDCDC) to SWx and PGND as short as possible. Keep the high current path from CIN through the inductor (LDCDC), the diode (DDCDC), and the output capacitor (CDCDC) as short as possible. Rev. B | Page 47 of 48 ADuM1411 SERIAL CLOCK OUT VIA SERIAL DATA OUT VIB SYNC OUT CONTROL OUT VIC VID ENCODE DECODE ENCODE DECODE ENCODE ENCODE DECODE DECODE VOA VOB VOC VOD TO SCLK TO SDIN TO SYNC TO LDAC Figure 85. 4-Channel Isolated Interface to the AD5735 09961-081 Traces AD5735 Data Sheet OUTLINE DIMENSIONS 0.60 MAX 9.00 BSC SQ 0.60 MAX 64 1 49 PIN 1 INDICATOR 48 PIN 1 INDICATOR 8.75 BSC SQ TOP VIEW 0.50 BSC (BOTTOM VIEW) 0.50 0.40 0.30 SEATING PLANE 0.25 MIN 7.50 REF 0.80 MAX 0.65 TYP 12° MAX 16 17 33 32 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 0.05 MAX 0.02 NOM 0.30 0.23 0.18 0.20 REF COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4 080108-C 1.00 0.85 0.80 7.25 7.10 SQ 6.95 EXPOSED PAD Figure 86. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 9 mm × 9 mm Body, Very Thin Quad (CP-64-3) Dimensions shown in millimeters ORDERING GUIDE Model 1 AD5735ACPZ AD5735ACPZ-REEL7 1 Resolution (Bits) 12 12 Temperature Range −40°C to +105°C −40°C to +105°C Z = RoHS Compliant Part. ©2011–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09961-0-5/12(B) Rev. B | Page 48 of 48 Package Description 64-Lead LFCSP_VQ 64-Lead LFCSP_VQ Package Option CP-64-3 CP-64-3