TI BQ51013AYFPR Integrated wireless power supply receiver Datasheet

bq51013A
bq51014
www.ti.com
SLUSAY6A – MARCH 2012 – REVISED JUNE 2012
INTEGRATED WIRELESS POWER SUPPLY RECEIVER,
Qi (WIRELESS POWER CONSORTIUM) COMPLIANT
Check for Samples: bq51013A, bq51014
FEATURES
1
•
•
•
•
•
•
•
•
•
•
•
Integrated Wireless Power Receiver Solution
with a 5V Regulated Supply
– 93% Overall Peak AC-DC Efficiency
– Full Synchronous Rectifier
– WPC v1.0 Compliant Communication
Control
– Output Voltage Conditioning
– Only IC Required Between RX coil and 5V
DC Output Voltage
Dynamic Rectifier Control for Improved Load
Transient Response
Dynamic Efficiency Scaling for Optimized
Performance Over any Range of Output Power
Adaptive Communication Limit for Robust
Communication During High Levels of Load
Current Noise
Supports 20-V Maximum Input
Low-power Dissipative Rectifier Overvoltage
Clamp (VOVP = 15V)
Thermal Shutdown
Multifunction NTC and Control Pin for
Temperature Monitoring, Done Charging and
Fault Host Control
Stand-alone Digital Controller
Programmable Termination Pin for Charge
Status 100% (CS100) Support
1.9 x 3mm DSBG or 4.5 x 3.5mm QFN Package
APPLICATIONS
•
•
•
•
•
•
WPC Compliant Receivers
Cell Phones, Smart Phones
Headsets
Digital Cameras
Portable Media Players
Hand-held Devices
DESCRIPTION
The bq5101x is an advanced, integrated, receiver IC
for wireless power transfer in portable applications.
The device provides the AC/DC power conversion
while integrating the digital control required to comply
with the Qi v1.0 communication protocol. Together
with the bq500210 transmitter controller, the bq5101x
enables a complete contact-less power transfer
system for a wireless power supply solution. By using
near-field inductive power transfer, the receiver coil
embedded in the portable device receives the power
transmitted by the transmitter coil via mutually
coupled inductors. The AC signal from the receiver
coil is then rectified and regulated to be used as a
power supply for down-system electronics. Global
feedback is established from the secondary to the
transmitter in order to stabilize the power transfer
process via back-scatter modulation. This feedback is
established by using the Qi v1.0 communication
protocol supporting up to 5 W applications.
The device integrates a low-impedance full
synchronous rectifier, low-dropout regulator, digital
control, and accurate voltage and current loops. The
entire power stage (rectifier and LDO) use low
resistive NMOS FET’s to ensures high efficiency and
low power dissipation.
Power
AC to DC
Drivers
bq5101x
Rectification
Voltage
Conditioning
Load
Communication
Controller
V/I
Sense
Controller
bq500210
Transmitter
Receiver
Figure 1. Wireless Power Consortium
(WPC or Qi) Inductive Power System
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012, Texas Instruments Incorporated
bq51013A
bq51014
SLUSAY6A – MARCH 2012 – REVISED JUNE 2012
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
Part NO
Marking
Function
Package
DSBGA-YFP
bq51013A
bq51013A
5V Regulated Power Supply
QFN-RHL
bq51014
bq51014
5V Regulated Power Supply
Ordering Number
(Tape and Reel)
Quantity
bq51013AYFPR
3000
bq51013AYFPT
250
bq51013ARHLR
3000
bq51013ARHLT
250
bq51014YFPR
3000
bq51014YFPT
250
DSBGA-YFP
AVAILABLE OPTIONS
WPC
Version
Device
Function
bq51013A
5V Power Supply
v1.0
15V
bq51014
5V Power Supply
v1.0
15V
(1)
(2)
VRECT-OVP
Over
Current
Shutdown
AD-OVP
5V
Disabled
Disabled
Disabled
Tracking + 1s HoldOff
5V
Enabled
12.5V
Enabled
Tracking + 1s HoldOff
VOUT-(REG)
Termination
(CS100)
Communication
Current Limit (1) (2)
Enabled if EN2 is low and disabled if EN2 is high
Communication current limit is disabled for 1 second at startup
ABSOLUTE MAXIMUM RATINGS (1) (2)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
Input Voltage
VALUES
PIN
UNITS
MIN
MAX
AC1, AC2, RECT, COM1, COM2, OUT, CHG,
CLAMP1, CLAMP2
-0.3
20
AD, AD-EN
-0.3
30
V
BOOT1, BOOT2
-0.3
26
V
EN1, EN2, TERM, FOD, TS-CTRL, ILIM
-0.3
7
V
2
A(RMS)
V
Input Current
AC1, AC2
Output Current
OUT
1.5
A
CHG
15
mA
COM1, COM2
1
A
-40
150
°C
-65
150
Output Sink Current
Junction temperature, TJ
Storage temperature, TSTG
ESD Rating (HBM) (100pF, 1.5KΩ)
(1)
(2)
2
All
2
°C
kV
All voltages are with respect to the VSS terminal, unless otherwise noted.
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
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Product Folder Link(s): bq51013A bq51014
bq51013A
bq51014
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SLUSAY6A – MARCH 2012 – REVISED JUNE 2012
THERMAL INFORMATION
THERMAL METRIC (1)
RHL
YFP
20 PiNS
28 PINS
θJA
Junction-to-ambient thermal resistance
37.7
58.9
θJCtop
Junction-to-case (top) thermal resistance
35.5
0.2
θJB
Junction-to-board thermal resistance
13.6
9.1
ψJT
Junction-to-top characterization parameter
0.5
1.4
ψJB
Junction-to-board characterization parameter
13.5
8.9
θJCbot
Junction-to-case (bottom) thermal resistance
2.7
n/a
(1)
UNITS
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
PINS
MIN
MAX
UNITS
Input voltage range, VIN
PARAMETER
RECT
4
10
V
Input current, IIN
RECT
1.5
A
Output current, IOUT
OUT
1.5
A
Sink current, IAD-EN
AD-EN
1
mA
COMM sink current, ICOMM
COMM
500
mA
125
ºC
Junction Temperature, TJ
0
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TYPICAL APPLICATION SCHEMATICS
bq5101x
System
Load
AD-EN
AD
OUT
C COMM1
C4
COMM1
CBOOT1
D1
BOOT1
RECT
C1
AC1
C3
COIL
R4
HOST
C2
TS-CTRL
AC2
NTC
BOOT2
CBOOT2
COMM2
CHG
CCOMM2
C CLAMP2
CCLAMP1
3 - State
CLAMP2
EN1 or TERM
Bi-State
CLAMP1
EN2
Bi-State
FOD
ILIM
R1
PGND
R TERM
(bq51014)
140Ω
Figure 2. bq5101x Used as a Wireless Power Receiver and Power Supply for System Loads
4
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bq51014
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SLUSAY6A – MARCH 2012 – REVISED JUNE 2012
System
Load
Q1
USB or
AC Adapter
Input
D2 (bq51014)
bq5101x
AD-EN
AD
OUT
C COMM1
C4
COMM1
C5
C BOOT1
D1
BOOT1
RECT
C1
AC1
C3
COIL
R4
C2
TS-CTRL
AC2
NTC
BOOT2
C BOOT2
HOST
COMM2
CHG
CCOMM2
CCLAMP2
C CLAMP1
Tri-State
CLAMP2
EN1 or TERM
Bi-State
CLAMP1
EN2
Bi-State
ILIM
R1
FOD
PGND
RTERM
(bq51014)
140Ω
Figure 3. bq5101x Used as a Wireless Power Receiver and Power Supply for System Loads With Adapter
Power-Path Multiplexing
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ELECTRICAL CHARACTERISTICS
over operating free-air temperature range, 0°C to 125°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
2.7
2.8
Undervoltage lock-out
VRECT: 0V → 3V
Hysteresis on UVLO
VRECT: 3V → 2V
Hysteresis on OVP
VRECT: 16V → 5V
Input overvoltage threshold
VRECT: 5V → 16V
Dynamic VRECT Threshold 1
ILOAD < 0.1 x IILIM (ILOAD rising)
7.08
Dynamic VRECT Threshold 2
0.1 x IILIM < ILOAD < 0.2 x IILIM
(ILOAD rising)
6.28
Dynamic VRECT Threshold 3
0.2 x IILIM < ILOAD < 0.4 x IILIM
(ILOAD rising)
5.53
Dynamic VRECT Threshold 4
ILOAD > 0.4 x IILIM (ILOAD rising)
5.11
ILOAD
ILOAD Hysteresis for dynamic VRECT
thresholds as a % of IILIM
ILOAD falling
VRECT-DPM
Rectifier undervoltage protection, restricts
IOUT at VRECT-DPM
VRECT-REV
Rectifier reverse voltage protection at the
output
UVLO
VHYS
VRECT
VRECT-REG
2.6
250
15
V
mV
150
14.5
UNIT
mV
15.5
V
V
4%
3
3.1
3.2
V
VRECT-REV = VOUT - VRECT,
VOUT = 10V
8
9
V
ILOAD = 0 mA, 0°C ≤ TJ ≤ 85°C
8
10
mA
ILOAD = 300 mA, 0°C ≤ TJ ≤
85°C
2
3.0
mA
VOUT = 5 V, 0°C ≤ TJ ≤ 85°C
20
35
µA
120
Ω
Quiescent Current
IRECT
Active chip quiescent current consumption
from RECT
IOUT
Quiescent current at the output when
wireless power is disabled (Standby)
ILIM Short Circuit
RILIM
Highest value of ILIM resistor considered a
fault (short). Monitored for IOUT > 100 mA
tDGL
Deglitch time transition from ILIM short to
IOUT disable
ILIM_SC
IOUT
RILIM: 200Ω → 50Ω. IOUT
latches off, cycle power to reset
1
ILIM-SHORT,OK enables the ILIM short
comparator when IOUT is greater than this
value
ILOAD: 0 → 20 0mA
Hysteresis for ILIM-SHORT,OK comparator
ILOAD: 0 → 200 mA
Maximum output current limit, CL
Maximum ILOAD that will be
delivered for 1 ms when ILIM is
shorted
120
145
ms
165
30
mA
mA
2.4
A
OUTPUT
ILOAD = 1000 mA
4.85
4.95
5
ILOAD = 10 mA
4.95
5
5.05
RLIM = KILIM / IILIM, where IILIM is
the hardware current limit. IOUT
=1A
280
300
320
230
250
270
VOUT-REG
Regulated output voltage
KILIM
Current programming factor for hardware
short circuit protection
KIMAX
IIMAX = KIMAX / RLIM where IMAX
Current programming factor for the nominal is the maximum normal
operating current
operating current.
IOUT = 1 A
IOUT
Current limit programming range
ICOMM
Current limit during WPC communication
tHOLD
Hold off time for the communication current
limit during startup
6
AΩ
AΩ
1500
IOUT > 300 mA
IOUT < 300 mA
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V
IOUT + 50
365
390
1
mA
mA
420
mA
s
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bq51013A
bq51014
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SLUSAY6A – MARCH 2012 – REVISED JUNE 2012
ELECTRICAL CHARACTERISTICS (continued)
over operating free-air temperature range, 0°C to 125°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Programmable termination factor as a
percentage of IMAX
RTERM = %IMAX x KTERM
160
200
240
Ω/%
High termination current threshold
calculation
ITERM-HI = (RTERM / KTERM) x 0.01 x IMAX, where IMAX = KIMAX / RILIM
TERMINATION (Charge Status 100%) – bq51014 ONLY
KTERM
ITERM
tTERM
Low termination current threshold
25
Constant current at the TERM pin to bias
the termination resistor
VTERM = 0 V
High termination threshold deglitch
ITERM-LOW< IOUT < ITERM-HI
High termination threshold deglitch
IOUT < ITERM-LOW
Internal TS Bias Voltage
ITS-Bias < 100 µA (periodically
driven see tTS-CTRL)
Rising threshold
VTS: 50% → 60%
Falling hysteresis
VTS: 60% → 50%
Falling threshold
VTS: 20% → 15%
Rising hysteresis
VTS: 15% → 20%
CTRL pin threshold for a high
48
51
mA
54
µA
180
sec
7
sec
TS / CTRL
VTS
2
2.2
2.4
56.5
58.7
60.8
18.5
19.6
VTS/CTRL: 50 → 150mV
80
100
130
mV
CTRL pin threshold for a low
VTS/CTRL: 150 → 50mV
50
80
100
mV
tTS-CTRL
Time VTS-Bias is active when TS
measurements occur
Synchronous to the
communication period
tTS
Deglitch time for all TS comparators
RTS
Pull-up resistor for the NTC network. Pulled
up to the voltage bias
VCOLD
VHOT
VCTRL
1
20.7
V
%VTS-Bias
1
18
24
ms
10
ms
20
22
kΩ
THERMAL PROTECTION
TJ
Thermal shutdown temperature
Thermal shutdown hysteresis
155
°C
20
°C
OUTPUT LOGIC LEVELS ON WPG
VOL
Open drain WPG pin
ISINK = 5 mA
500
mV
IOFF
WPG leakage current when disabled
VCHG = 20 V
1
µA
RDS(ON)
COM1 and COM2
VRECT = 2.6 V
fCOMM
Signaling frequency on COMM pin
IOFF
Comm pin leakage current
COMM PIN
1.5
Ω
2.00
Kb/s
VCOM1 = 20 V, VCOM2 = 20 V
1
µA
CLAMP PIN
RDS(ON)
Clamp1 and Clamp2
Ω
1
Adapter Enable
VAD-EN
VAD Rising threshold voltage. EN-UVLO
VAD 0 → 5 V
VAD-EN hysteresis, EN-HYS
VAD 5 → 0 V
IAD
Input leakage current
VRECT = 0V, VAD = 5V
VAD-OVP
Adapter mode OVP threshold
rising edge
VAD-OVP hysteresis
bq51014
VAD 10 → 15 V
3.5
RAD
VAD
Voltage difference between VAD and VAD-EN
VAD = 5 V, 0°C ≤ TJ ≤ 85°C
when adapter mode is enabled, EN-ON
3.8
400
12
VAD 15 → 10 V
Pull-up resistance from AD-EN to OUT
when adapter mode is disabled and VOUT > VAD = 0, VOUT = 5
VAD, EN-OUT
3.6
12.5
mV
60
μA
13
V
0.5
3
V
200
350
Ω
4.5
5
V
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7
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ELECTRICAL CHARACTERISTICS (continued)
over operating free-air temperature range, 0°C to 125°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
80
100
125
mA
Synchronous Rectifier
IOUT
VHS-DIODE
IOUT at which the synchronous rectifier
enters half synchronous mode, SYNC_EN
ILOAD 200 → 0 mA
Hysteresis for IOUT,RECT-EN (fullsynchronous mode enabled)
ILOAD 0 → 200 mA
High-side diode drop when the rectifier is in IAC-VRECT = 250 mA and TJ =
half synchronous mode
25°C
25
mA
0.7
V
EN1 and EN2
VIL
Input low threshold for EN1 and EN2
VIH
Input high threshold for EN1 and EN2
RPD
EN1 and EN2 pull down resistance
0.4
1.3
V
V
200
kΩ
±6
%
ADC (WPC Related Measurements and Coefficients)
PRECT
8
Rectified power accuracy as a percentage
of output power
0W – 5W of rectified power
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SLUSAY6A – MARCH 2012 – REVISED JUNE 2012
DEVICE INFORMATION
SIMPLIFIED BLOCK DIAGRAM
RECT
M1
I
OUT
VOUT,FB
+
_
+
_
VREF,ILIM
VILIM
VOUT,REG
VREF,IABS
VIABS,FB
+
_
VIN,FB
VIN,DPM
+
_
ILIM
AD
+
_
VREFAD,OVP
BOOT2
+
_
BOOT1
VREFAD,UVLO
AD-EN
AC1
AC2
Sync
Rectifier
Control
VREF,TS-BIAS
COMM1
COMM2
DATA _
OUT
CLAMP1
ADC
Digital Control
TS_COLD
VBG,REF
VIN,FB
VOUT,FB
VILIM
VIABS,FB
VIABS,REF
VIC,TEMP
CLAMP2
VFOD
+
_
TS_HOT
FOD
+
_
+
_
TS-CTRL
TS_DETECT
+
_
VREF_100MV
VFOD
50uA
+
_
CHG
ILIM
200kW
VRECT
VOVP,REF
+
_
OVP
EN1 or
TERM
EN2
200kW
PGND
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YFP Package
(TOP VIEW)
RHL Package
(TOP VIEW)
PGND
1
A1
PGND
A2
PGND
A3
PGND
A4
PGND
B1
AC2
B2
AC2
B3
AC1
B4
AC1
C1
BOOT2
C2
RECT
C3
RECT
C4
BOOT1
D1
OUT
D2
OUT
D3
OUT
PGND
20
AC1
2
AC2
19
BOOT1
3
RECT
18
OUT
4
BOOT2
17
CLMP1
5
CLMP2
16
COM1
6
COM2
15
CHG
7
FOD
14
AD-EN
8
TSCTRL
13
AD
9
ILIM
12
D4
OUT
E1
COM2
E2
CLMP2
E3
CLMP1
E4
COM1
F1
TS-CTRL
F2
FOD
F3
/AD-EN
F4
/CHG
G1
ILIM
G2
EN2
G3
G4
AD
EN1 or
TERM
EN1or
TERM
10
EN2
11
PIN FUNCTIONS
NAME
YFP
RHL
AC1
B3, B4
2
I
AC2
B1, B2
19
I
BOOT1
C4
3
O
BOOT2
C1
17
O
RECT
C2, C3
18
O
Filter capacitor for the internal synchronous rectifier. Connect a ceramic capacitor to PGND.
Depending on the power levels, the value may be 4.7 μF to 22 μF.
OUT
D1, D2, D3,
D4
4
O
Output pin, delivers power to the load.
O
Open-drain output used to communicate with primary by varying reflected impedance. Connect
through a capacitor to either AC1 or AC2 for capacitive load modulation (COM2 must be
connected to the alternate AC1 or AC2 pin). For resistive modulation connect COM1 and
COM2 to RECT via a single resistor; connect through separate capacitors for capacitive load
modulation.
Open-drain output used to communicate with primary by varying reflected impedance. Connect
through a capacitor to either AC1 or AC2 for capacitive load modulation (COM1 must be
connected to the alternate AC1 or AC2 pin). For resistive modulation connect COM1 and
COM2 to RECT via a single resistor; connect through separate capacitors for capacitive load
modulation.
COM1
E4
6
I/O
COM2
E1
15
O
CLMP2
E2
16
O
CLMP1
E3
5
O
PGND
A1, A2, A3,
A4
1, 20
10
DESCRIPTION
AC input from receiver coil antenna.
Bootstrap capacitors for driving the high-side FETs of the synchronous rectifier. Connect a 10
nF ceramic capacitor from BOOT1 to AC1 and from BOOT2 to AC2.
Open drain FETs which are utilized for a non-power dissipative over-voltage AC clamp
protection. When the RECT voltage goes above 15 V, both switches will be turned on and the
capacitors will act as a low impedance to protect the IC from damage. If used, Clamp1 is
required to be connected to AC1, and Clamp2 is required to be connected to AC2 via 0.47µF
capacitors.
Power ground
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PIN FUNCTIONS (continued)
NAME
YFP
ILIM
RHL
G1
12
I/O
DESCRIPTION
I/O
Programming pin for the over current limit. Connect external resistor to VSS. Size RILIM with
the following equation: RILIM = 250 / IMAX where IMAX is the expected maximum output current
of the wireless power supply. The hardware current limit (IILIM) will be 20% greater than IMAX
or 1.2 x 1MAX. If the supply is meant to operate in current limit use
RILIM = 300 / IILIM
RILIM = R1 + 140
AD
G4
9
I
Connect this pin to the wired adapter input. When a voltage is applied to this pin wireless
charging is disabled and AD_EN is driven low. Connect to GND through a 1 µF capacitor. If
unused, capacitor is not required and should be grounded directly. For the bq51014, there is
an OVP protection of 12.5 V. If the AD voltage is greater than 12.5 V, wireless charging will
remain active.
AD-EN
F3
8
O
Push-pull driver for external PFET connecting AD and OUT. This node is pulled to the higher
of OUT and AD when turning off the external FET. This voltage tracks approximately 4 V below
AD when voltage is present at AD and provides a regulated VSG bias for the external FET.
Float this pin if unused.
Must be connected to ground via a resistor. If an NTC function is not desired connect to GND
with a 10 kΩ resistor. As a CTRL pin pull to ground to send end power transfer (EPT) fault to
the transmitter or pull-up to an internal rail (i.e. 1.8 V) to send EPT termination to the
transmitter. Note that a 3-state driver should be used to interface this pin (see the 3-state
Driver section for further description)
TS-CTRL
F1
13
I
EN1
G3
10
I
EN2
G2
11
I
TERM
G3
10
I
Input that allows allows the upper termination threshold (ITERM-HI) to be programmable. KTERM =
200 Ω/%. Set the termination threshold by applying the following equation RTERM = %IMAX x
KTERM where %IMAX is the desired percentage of the maximum output current when
termination should occur (i.e. 10% of 1 A = 0.1 mA)
FOD
F2
14
O
Input for the rectified power measurement. Connect to GND with a 140 Ω resistor
CHG
F4
7
O
Open-drain output – active when output current is being delivered to the load (i.e. when the
output of the supply is enabled).
Inputs that allow user to enable/disable wireless and wired charging <EN1 EN2>:
<00> wireless charging is enabled unless AD voltage > 3.6 V
<01> Dynamic communication current limit disabled
<10> AD-EN pulled low, wireless charging disabled
<11> wired and wireless charging disabled.
Spacer
TYPICAL CHARACTERISTICS
100.0
100.0
90.0
90.0
Efficiency (%)
Efficiency (%)
Full Sync Mode Enabled
80.0
80.0
70.0
60.0
0.0
1.0
2.0
3.0
4.0
Output Power (W)
Figure 4. Rectifier Efficiency
5.0
6.0
70.0
1.0
2.0
3.0
Output Power (W)
4.0
5.0
Figure 5. IC Efficiency from AC Input to DC Output
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TYPICAL CHARACTERISTICS (continued)
Rising
Falling
70
<−−− Dynamic Efficiency Scaling
7.0
Rectifier Voltage (V)
Efficiency (%)
60
50
40
30
6.5
<−−− Dynamic Rectifier Control
6.0
20
5.5
RILIM=500
RILIM=220
10
1
2
3
Output Power (W)
4
5
0.2
0.4
0.6
Output Current (A)
0.8
G000
1.0
G007
Figure 6. Light Load Efficiency Improvement due to
Dynamic Efficiency Scaling Feature(1)
Figure 7. VRECT vs. ILOADat RILIM = 220Ω
1.2
RILIM=220
RILIM=500
1.1
1.0
7.0
RILIM=250
RILIM=400
RILIM=700
RILIM=300
Thermal Shutdown −−−>
Current Limit (A)
Rectifier Voltage (V)
0.9
6.5
6.0
0.8
0.7
0.6
0.5
0.4
0.3
5.5
0.0
0.2
0.2
0.4
0.6
Output Current (A)
0.8
0.1
1.0
1.0
2.0
3.0
Output Voltage (V)
4.0
G007
Figure 8. VRECT vs. ILOAD at RILIM = 220 Ω and 500 Ω
12
5.0
G001
Figure 9. VOUT Sweep (I-V Curve)(2)
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TYPICAL CHARACTERISTICS (continued)
100.0
5.01
90.0
5.00
Output Ripple (mV)
Output Voltage (V)
80.0
4.99
4.98
4.97
70.0
60.0
50.0
4.96
40.0
4.95
0.2
0.4
0.6
0.8
Load Current (A)
1.0
1.2
Figure 10. ILOAD Sweep (I-V Curve)
30.0
0.0
0.2
0.4
0.6
Load Current (A)
0.8
1.0
Figure 11. Output Ripple vs. ILOAD (COUT = 1µF)
5.004
Vout (V)
5.002
5.000
4.998
0
20
40
60
80
Temperature (°C)
100
Figure 12. VOUT vs Temperature
120
Figure 13. 1A Instantaneous Load Step(3)
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TYPICAL CHARACTERISTICS (continued)
VRECT
VOUT
Figure 14. 1A Instantaneous Load Dump(3)
Figure 15. 1A Load Step Full System Response
VRECT
VRECT
VOUT
VOUT
Figure 16. 1A Load Dump Full System Response
Figure 17. Rectifier Overvoltage Clamp (fop = 110kHz)
VTS/CTRL
VRECT
VRECT
VOUT
Figure 18. TS Fault
14
Figure 19. Adapter Insertion (VAD = 10V)
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TYPICAL CHARACTERISTICS (continued)
VAD
VRECT
VAD_EN
VOUT
VOUT
Figure 20. Adapter Insertion (VAD = 10V) Illustrating BreakBefore-Make Operation
Figure 21. 20V adapter Insertion with AD OVP Enabled
(bq51014) and Wireless Power not Present
VAD_EN
VAD
VAD
VOUT
VRECT
Figure 22. AD OVP Condition While Wireless Charging is
Active (bq51014)
Figure 23. On the Go Enabled (VOTG = 3.5V)(4)
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TYPICAL CHARACTERISTICS (continued)
IOUT
IOUT
VRECT
VRECT
VOUT
VOUT
Figure 24. bq5101x Typical Startup with a 1A System Load
Figure 25. Adaptive Communication Limit Event Where the
400 mA Current Limit is Enabled (IOUT-DC < 300 mA)
IOUT
VRECT
VOUT
Figure 26. Adaptive Communication Limit Event Where the
Current Limit is IOUT + 50 mA (IOUT-DC > 300 mA)
Figure 27. Rx Communication Packet Structure
(1) Efficiency measured from DC input to the transmitter to DC output of the receiver. Transmitter was the bq500210 EVM. Measurement
subject to change if an alternate transmitter is used.
(2) Curves illustrates the resulting ILIM current by sweeping the output voltage at different RILIM settings. ILIM current collapses due to the
increasing power dissipation as the voltage at the output is decreased—thermal shutdown is occurring.
(3) Total droop experienced at the output is dependent on receiver coil design. The output impedance must be low enough at that particular
operating frequency in order to not collapse the rectifier below 5V.
(4) On the go mode is enabled by driving EN1 high. In this test the external PMOS is connected between the output of the bq5101x IC and
the AD pin; therefore, any voltage source on the output is supplied to the AD pin.
16
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PRINCIPLE OF OPERATION
Power
AC to DC
bq5101x
Drivers
Rectification
Voltage
Conditioning
Load
Communication
Controller
V/I
Sense
Controller
bq500210
Transmitter
Receiver
Figure 28. WPC Wireless Power System Indicating the Functional Integration of the bq5101x
A Brief Description of the Wireless System:
A wireless system consists of a charging pad (transmitter or primary) and the secondary-side equipment
(receiver or secondary). There is a coil in the charging pad and in the secondary equipment which are
magnetically coupled to each other when the secondary is placed on the primary. Power is then transferred from
the transmitter to the receiver via coupled inductors (e.g. an air-core transformer). Controlling the amount of
power transferred is achieved by sending feedback (error signal) communication to the primary (e.g. to increase
or decrease power).
The receiver communicates with the transmitter by changing the load seen by the transmitter. This load variation
results in a change in the transmitter coil current, which is measured and interpreted by a processor in the
charging pad. The communication is digital - packets are transferred from the receiver to the transmitter.
Differential Bi-phase encoding is used for the packets. The bit rate is 2-kbps.
Various types of communication packets have been defined. These include identification and authentication
packets, error packets, control packets, end power packets, and power usage packets.
The transmitter coil stays powered off most of the time. It occasionally wakes up to see if a receiver is present.
When a receiver authenticates itself to the transmitter, the transmiter will remain powered on. The receiver
maintains full control over the power transfer using communication packets.
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Using the bq5101x as a Wireless Power Supply: (See Figure 3)
Figure 3 is the schematic of a system which uses the bq5101x as power supply while power multiplexing the
wired (adapter) port.
When the system shown in Figure 3 is placed on the charging pad, the receiver coil is inductively coupled to the
magnetic flux generated by the coil in the charging pad which consequently induces a voltage in the receiver coil.
The internal synchronous rectifier feeds this voltage to the RECT pin which has the filter capacitor C3.
The bq5101x identifies and authenticates itself to the primary using the COM pins by switching on and off the
COM FETs and hence switching in and out CCOMM. If the authentication is successful, the transmitter will remain
powered on. The bq5101x measures the voltage at the RECT pin, calculates the difference between the actual
voltage and the desired voltage VRECT-REG, (threshold 1 at no load) and sends back error packets to the primary.
This process goes on until the input voltage settles at VRECT-REG. During a load transient, the dynamic rectifier
algorithm will set the targets specified by VRECT-REG thresholds 1, 2, 3, and 4. This algorithm is termed Dynamic
Rectifier Control and is used to enhance the transient response of the power supply.
During power-up, the LDO is held off until the VRECT-REG threshold 1 converges. The voltage control loop ensures
that the output voltage is maintained at VOUT-REG to power the system. The bq5101x meanwhile continues to
monitor the input voltage, and maintains sending error packets to the primary every 250ms. If a large transient
occurs, the feedback to the primary speeds up to every 32ms in order to converge on an operating point in less
time.
Details of a Qi Wireless Power System and bq5101x Power Transfer Flow Diagrams
The bq5101x family integrates a fully compliant WPC v1.0 communication algorithm in order to streamline
receiver designs (no extra software development required). Other unique algorithms such has Dynamic Rectifier
Control are also integrated to provide best in class system performance. This section provides a high level
overview of these features by illustrating the wireless power transfer flow diagram from startup to active
operation.
During startup operation, the wireless power receiver must comply with proper handshaking to be granted a
power contract from the Tx. The Tx will initiate the hand shake by providing an extended digital ping. If an Rx is
present on the Tx surface, the Rx will then provide the signal strength, configuration and identification packets to
the Tx (see volume 1 of the WPC specification for details on each packet). These are the first three packets sent
to the Tx. The only exception is if there is a true shutdown condition on the EN1/EN2, AD, or TS-CTRL pins
where the Rx will shut down the Tx immediately. See Table 4 for details. Once the Tx has successfully received
the signal strength, configuration and identification packets, the Rx will be granted a power contract and is then
allowed to control the operating point of the power transfer. With the use of the bq5101x Dynamic Rectifier
Control algorithm, the Rx will inform the Tx to adjust the rectifier voltage above 7 V prior to enabling the output
supply. This method enhances the transient performance during system startup. See Figure 29 for the startup
flow diagram details.
18
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Tx Powered
without Rx
Active
Tx Extended Digital Ping
EN1/EN2/AD/TS-CTRL
EPT Condition?
Yes
Send EPT packet with
reason value
No
Identification and
Configuration and SS,
Received by Tx?
No
Yes
Power Contract
Established. All
proceeding control is
dictated by the Rx.
Yes
VRECT < 7V?
Send control error packet
to increase VRECT
No
Startup operating point
established. Enable the
Rx output.
Rx Active
Power Transfer
Stage
Figure 29. Wireless Power Startup Flow Diagram
Once the startup procedure has been established, the Rx will enter the active power transfer stage. This is
considered the “main loop” of operation. The Dynamic Rectifier Control algorithm will determine the rectifier
voltage target based on a percentage of the maximum output current level setting (set by KIMAX and the ILIM
resistance to GND). The Rx will send control error packets in order to converge on these targets. As the output
current changes, the rectifier voltage target will dynamically change. As a note, the feedback loop of the WPC
system is relatively slow where it can take up to 90 ms to converge on a new rectifier voltage target. It should be
understood that the instantaneous transient response of the system is open loop and dependent on the Rx coil
output impedance at that operating point. More details on this will be covered in the section Receiver Coil LoadLine Analysis. The “main loop” will also determine if any conditions in Table 4 are true in order to discontinue
power transfer. See Figure 30 which illustrates the active power transfer loop.
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Rx Active
Power Transfer
Stage
Rx Shutdown
conditions per the EPT
Table?
Yes
Tx Powered
without Rx
Active
Send EPT packet with
reason value
No
IOUT < 10% of IMAX?
Yes VRECT target = 7V. Send
control error packets to
converge.
No
Yes
VRECT target = 6.3V.
Send control error packets
to converge.
Yes
VRECT target = 5.5V.
Send control error packets
to converge.
Yes
TERM STATE
(bq51014 only)
IOUT < 20% of IMAX?
No
IOUT < 40% of IMAX?
No
VRECT target= 5.1V.
Send control error packets
to converge.
Measure Rectified Power
and Send Value to Tx
BQ51014?
No
Figure 30. Active Power Transfer Flow Diagram
Another requirement of the WPC v1.0 specification is to send the measured rectifier power. This entitles the Rx
to determine the rectifier voltage and output current in order to report this to the Tx as a percentage of the
maximum output power. This is also handled in the active power transfer loop.
If the device is a bq51014, a special state called the “TERM STATE” is enabled in the active power transfer loop.
This state is used to determine the level of the output current versus the programmed level of termination current
(set by the KTERM factor and RTERM resistor). The primary purpose of this feature is to determine if the charge
status is 100% based on the output current from the Rx. In a condition where the mobile device battery is fully
charged, a low system current (output current from Rx) signature can be determined. This current level
(signature) is set by the end system designer and is termed ITERM-HI. In addition to this current level, there is a noload termination current level termed ITERM-LO which is fixed at 40 mA. For the high termination condition to be
20
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true, the output current must be between ITERM-HI and ITERM-LO for approximately 180s. Once this condition is true,
the Rx will send charge status of 100% to the Tx. The Tx can then illustrate that the mobile device has been fully
charged (100% charged). If the output current remains below ITERM-LO for ~7s then the charge status of 100% is
immediately sent. This condition can occur if the mobile device is put into a low standby mode after the battery is
fully charged. See Figure 31 for the flow diagram of the “TERM STATE”.
TERM STATE
(bq51014 only)
IOUT < 45mA?
Yes
Send charge status100%
and reset t TERM-LO timer
Yes
Send charge status100%
and reset t TERM-HI timer
No
No
IOUT < ITERM-HI?
Yes
tTERM-LO Expired?
Yes
tTERM-HI Expired?
No
No
Rx Active
Power Transfer
Stage
Figure 31. TERM STATE Flow Diagram for the bq51014 Only
Dynamic Rectifier Control
The Dynamic Rectifier Control algorithm offers the end system designer optimal transient response for a given
max output current setting. This is achieved by providing enough voltage headroom across the internal regulator
at light loads in order to maintain regulation during a load transient. The WPC system has a relatively slow global
feedback loop where it can take up to 90 ms to converge on a new rectifier voltage target. Therefore, a transient
response is dependent on the loosely coupled transformers output impedance profile. The Dynamic Rectifier
Control allows for a 2 V change in rectified voltage before the transient response will be observed at the output of
the internal regulator (output of the bq5101x). A 1-A application allows up to a 2 Ω output impedance. The
Dynamic Rectifier Control behavior is illustrated in Figure 7 where RILIM is set to 220 Ω.
Dynamic Efficiency Scaling
The Dynamic Efficiency Scaling feature allows for the loss characteristics of the bq5101x to be scaled based on
the maximum expected output power in the end application. This effectively optimizes the efficiency for each
application. This feature is achieved by scaling the loss of the internal LDO based on a percentage of the
maximum output current. Note that the maximum output current is set by the KIMAX term and the RILIM resistance
(where RILIM = KIMAX / IMAX). The flow diagram show in Figure 30 illustrates how the rectifier is dynamically
controlled (Dynamic Rectifier Control) based on a fixed percentage of the IMAX setting. The below table
summarizes how the rectifier behavior is dynamically adjusted based on two different RILIM settings.
Table 1.
Output Current Percentage
RILIM = 500Ω
IMAX = 0.5A
RILIM = 220 Ω
IMAX = 1.14 A
VRECT
0 to 10%
0 A to 0.05 A
0 A to 0.114 A
7.08 V
10 to 20%
0.05 A to 0.1A
0.114 A to 0.227 A
6.28 V
20 to 40%
0.1 A to 0.2 A
0.227 A to 0.454 A
5.53 V
>40%
> 0.2 A
> 0.454 A
5.11 V
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Figure 8 illustrates the shift in the Dynamic Rectifier Controll behavior based on the two different RILIM settings.
With the rectifier voltage (VRECT) being the input to the internal LDO, this adjustment in the Dynamic Rectifier
Control thresholds will dynamically adjust the power dissipation across the LDO where:
(
)
PDIS = VRECT - VOUT × IOUT
(1)
Figure 6 illustrates how the system efficiency is improved due to the Dynamic Efficiency Scaling feature. Note
that this feature balances efficiency with optimal system transient response.
RILIM Calculations
The bq5101x includes a means of providing hardware overcurrent protection by means of an analog current
regulation loop. The hardware current limit provides an extra level of safety by clamping the maximum allowable
output current (e.g. a current compliance). The RILIM resistor size also set the thresholds for the dynamic rectifier
levels and thus providing efficiency tuning per each application’s maximum system current. The calculation for
the total RILIM resistance is as follows:
R ILIM = 250
IMAX
IILIM = 1.2 ´ IMAX = 300
R ILIM
R ILIM = R1 + 140
(2)
Where IMAX is the expected maximum output current during normal operation and IILIM is the hardware over
current limit. When referring to the application diagram shown in Figure 2, RILIM is the sum of 140 and the R1
resistance (e.g. the total resistance from the ILIM pin to GND).
Termination Calculations (bq51014 only)
The bq51014 includes a programmable upper termination threshold. This pin can be used to send the charge
status 100% packet (CS100) to the transmitter in order to indicate a full charge status. The header for this packet
is 0x05. Note that this packet does not turn off the transmitter and is only used as an informative indication of the
mobile device’s charge status. The upper termination threshold is calculated using Equation 3:
R TERM = 200 ´ %IMAX
I
%IMAX = TERM-HI ´100
IMAX
IMAX = 250
R ILIM
(3)
The 200 constant is specified in the datasheet as KTERM. The upper termination threshold is set as a percentage
of the IIMAX setting. For example, if the ILIM resistance is set to 250 Ω the IIMAX current will be 1A (250 ÷ 250). If
the upper termination threshold is desired to be 100 mA, this would be 10% of IIMAX. The RTERM resistor would
then equal 2kΩ (200 x 10).
When the output current is in between ITERM-HI and ITERM-LO, the CS100 packet is sent approximately every 3 min.
When the output current is below ITERM-LO, the CS100 packet is sent approximately every 7 seconds. The output
current must remain in one of the termination conditions for that specific amount of time for the first CS100
packet to be sent (deglitch). See Figure 32 for details:
I OUT
ITERM-HI
ITERM-LO
t
t LO = 7s
tHI = 180s
Figure 32. Termination Deglitch Timings for the CS100 Packet
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Input Overvoltage
If the input voltage suddenly increases in potential (e.g. a change in position of the equipment on the charging
pad), the voltage-control loop inside the bq5101x becomes active, and prevents the output from going beyond
VOUT-REG. The receiver then starts sending back error packets to the transmitter every 30ms until the input
voltage comes back to the VRECT-REG target, and then maintains the error communication every 250ms.
If the input voltage increases in potential beyond VOVP, the IC switches off the LDO and communicates to the
primary to bring the voltage back to VRECT-REG. In addition, a proprietary voltage protection circuit is activated by
means of CCLAMP1 and CCLAMP2 that protects the IC from voltages beyond the maximum rating of the IC (e.g.
20V).
Adapter Enable Functionality and EN1/EN2 Control
Figure 3 is an example application that shows the bq5101x used as a wireless power receiver that can power
mutliplex between wired or wireless power for the down-system electronics. In the default operating mode pins
EN1 and EN2 are low, which activates the adapter enable functionality. In this mode, if an adapter is not present
the AD pin will be low, and AD-EN pin will be pulled to the higher of the OUT and AD pins so that the PMOS
between OUT and AD will be turned off. If an adapter is plugged in and the voltage at the AD pin goes above
3.6V then wireless charging is disabled and the AD-EN pin will be pulled approximately 4V below the AD pin to
connect AD to the secondary charger. The difference between AD and AD-EN is regulated to a maximum of 7V
to ensure the VGS of the external PMOS is protected.
The EN1 and EN2 pins include internal 200kΩ pull-down resistors, so that if these pins are not connected
bq5101x defaults to AD-EN control mode. However, these pins can be pulled high to enable other operating
modes as described in Table 2:
Table 2.
EN1
EN2
Result
0
0
Adapter control enabled. If adapter is present then secondary charger is
powered by adapter, otherwise wireless charging is enabled when wireless
power is available. Communication current limit is enabled.
0
1
Disables communication current limit.
1
0
AD-EN is pulled low, whether or not adapter voltage is present. This feature
can be used, e.g., for USB OTG applications.
1
1
Adapter and wireless charging are disabled, i.e., power will never be
delivered by the OUT pin in this mode.
Table 3.
(1)
(2)
Adaptive
Communication
Limit
EPT Termination
Disabled
Enabled
Not Sent to Tx
Disabled
Disabled
Not Sent to Tx
N/A
Sent to Tx
N/A
Sent to Tx
EN1
EN2
Wireless Power
Wired Power
OTG Mode
0
0
Enabled
Priority (1)
0
1
Enabled
Priority (1)
1
0
Disabled
Enabled
1
1
Disabled
Disabled
Enabled
(2)
Disabled
If both wired and wireless power are present, wired power is given priority.
Allows for a boost-back supply to be driven from the output terminal of the Rx to the adapter port via the external back-to-back PMOS
FET.
As described in Table 2, pulling EN2 high disables the adapter mode and only allows wireless charging. In this
mode the adapter voltage will always be blocked from the OUT pin. An application example where this mode is
useful is when USB power is present at AD, but the USB is in suspend mode so that no power can be taken from
the USB supply. Pulling EN1 high enables the off-chip PMOS regardless of the presence of a voltage. This
function can be used in USB OTG mode to allow a charger connected to the OUT pin to power the AD pin.
Finally, pulling both EN1 and EN2 high disables both wired and wireless charging.
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NOTE
It is required to connect a back-to-back PMOS between AD and OUT so that voltage is
blocked in both directions. Also, when AD mode is enabled no load can be pulled from the
RECT pin as this could cause an internal device overvoltage in bq5101x.
End Power Transfer Packet (WPC Header 0x02)
The WPC allows for a special command for the receiver to terminate power transfer from the trasmitter termed
End Power Transfer (EPT) packet. Table 4 specifies the v1.0 Reasons columb and their responding data field
value. The Condition column corresponds to the values sent by the bq5101x for a given reason.
Table 4.
Reason
Value
Condition
Unknown
0x00
AD > 3.6V
Charge Complete
0x01
TS/CTRL = 1, or EN1 = 1, or <EN1 EN2> = <11>
Internal Fault
0x02
TJ > 150°C or RILIM < 100Ω
Over Temperature
0x03
TS < VHOT, TS > VCOLD, or TS/CTRL < 100mV
Over Voltage
0x04
Not Sent
Over Current
0x05
IOUT > 90% of ILIM (bq51014 only)
Battery Failure
0x06
Not Sent
Reconfigure
0x07
Not Sent
No Response
0x08
VRECT target doesn't converge
Over Current Shutdown (bq51014)
The bq51014 includes an over current shutdown feature where the Rx sends an end power transfer packet to the
Tx when the output current reaches 100% of the IILIM setting or 120% of the IIMAX setting. The Tx will shut down
as soon as the end power transfer packet is received which discontinues power transfer. This feature disallows
the Rx from operating in a current limit situation in order to protect from down system shorts or failures.
Status Outputs
bq5101x has one status output, CHG. This output is an open-drain NMOS device that is rated to 20V. The opendrain FET connected to the CHG pin will be turned on whenever the output of the power supply is enabled.
Please note, the output of the power supply will not be enabled if the VRECT-REG does not converge at the no-load
target voltage.
WPC Communication Scheme
The WPC communication uses a modulation technique termed “back-scatter modulation” where the receiver coil
is dynamically loaded in order to provide amplitude modulation of the transmitters coil voltage and current. This
scheme is possible due to the fundamental behavior between two loosely coupled inductors (e.g. between the Tx
and Rx coil). This type of modulation can be accomplished by switching in and out a resistor at the output of the
rectifier, or by switching in and out a capacitor across the AC1/AC2 net. Figure 33 shows how to implement
resistive modulation.
CRES1
AC1
VRECT
R MOD
COIL
C RES2
AC2
GND
Figure 33. Resistive Modulation
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Figure 34 Shows how to implement capacitive modulation.
CRES1
AC1
VRECT
C MOD
COIL
C RES2
AC2
GND
Figure 34. Capacitive Modulation
The amplitude change in Tx coil voltage or current can be detected by the transmitters decoder. The resulting
signal observed by the Tx is shown in Figure 35.
Power
AC to DC
bq5101x
Drivers
Voltage
Conditioning
Rectification
Load
Communication
Controller
V/I
Sense
Controller
bq500210
Transmitter
0
Receiver
1
0
1
0
TX COIL VOLTAGE / CURRENT
Figure 35.
The WPC protocol uses a differential bi-phase encoding scheme to modulate the data bits onto the Tx coil
voltage/current. Each data bit is aligned at a full period of 0.5 ms (tCLK) or 2 kHz. An encoded ONE results in two
transitions during the bit period and an encoded ZERO results in a single transition. See Figure 36 for an
example of the differential bi-phase encoding.
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Figure 36. Differential Bi-phase Encoding Scheme (WPC volume 1: Low Power, Part 1 Interface
Definition)
The bits are sent LSB first and use an 11-bit asynchronous serial format for each portion of the packet. This
includes one start bit, n-data bytes, a parity bit, and a single stop bit. The start bit is always ZERO and the parity
bit is odd. The stop bit is always ONE. Figure 37 shows the details of the asynchronous serial format.
Figure 37. Asynchronous Serial Formatting (WPC volume 1: Low Power, Part 1 Interface Definition)
Each packet format is organized as shown in Figure 38.
Preamble
Header
Message
Checksum
Figure 38. Packet Format (WPC volume 1: Low Power, Part 1 Interface Definition)
Figure 27 above shows an example waveform of the receiver sending a rectified power packet (header 0x04).
Communication Modulator
bq5101x provides two identical, integrated communication FETs which are connected to the pins COM1 and
COM2. These FETs are used for modulating the secondary load current which allows bq5101x to communicate
error control and configuration information to the transmitter. Figure 39 below shows how the COMM pins can be
used for resistive load modulation. Each COMM pin can handle at most a 24Ω communication resistor.
Therefore, if a COMM resistor between 12Ω and 24Ω is required COM1 and COM2 pins must be connected in
parallel. bq5101x does not support a COMM resistor less than 12Ω.
26
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RECTIFIER
24W
COMM1
24W
COMM2
COMM_DRIVE
Figure 39. Resistive Load Modulation
In addition to resistive load modulation, the bq5101x is also capable of capacitive load modulation as shown in
Figure 40 below. In this case, a capacitor is connected from COM1 to AC1 and from COM2 to AC2. When the
COMM switches are closed there is effectively a 22 nF capacitor connected between AC1 and AC2. Connecting
a capacitor in between AC1 and AC2 modulates the impedance seen by the coil, which will be reflected in the
primary as a change in current.
Figure 40. Capacitive Load Modulation
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Adaptive Communication Limit
The Qi communication channel is established via backscatter modulation as described in the previous sections.
This type of modulation takes advantage of the loosely coupled inductor relationship between the Rx and Tx coil.
Essentially the switching in-and-out of the communication capacitor or resistor adds a transient load to the Rx
coil in order to modulate the Tx coil voltage/current waveform (amplitude modulation). The consequence of this
technique is that a load transient (load current noise) from the mobile device has the same signature. In order to
provide noise immunity to the communication channel, the output load transients must be isolated from the Rx
coil. The proprietary feature Adaptive Communication Limit achieves this by dynamically adjusting the current
limit of the regulator. When the regulator is put in current limit, any load transients will be offloaded to the battery
in the system.
Note that this requires the battery charger IC to have input voltage regulation (weak adapter mode). The output
of the Rx appears as a weak supply if a transient occurs above the current limit of the regulator.
The Adaptive Communication Limit feature has two current limit modes and is detailed in the table below:
Table 5.
IOUT
Communication Current Limit
< 300 mA
Fixed 400 mA
> 300 mA
IOUT + 50 mA
The first mode is illustrated in Figure 25. In this plot, an output load pulse of 300 mA is periodically introduced on
a DC current level of 200 mA. Therefore, the 400 mA current limit is enabled. The pulses on VRECT indicate that a
communication packet event is occurring. When the output load pulse occurs, the regulator limits the pulse to a
constant 400 mA and; therefore, preserves communication. Note that VOUT drops to 4.5 V instead of GND. A
charger IC with an input voltage regulation set to 4.5 V allows this to occur by offloading the load transient
support to the mobile device’s battery
The second mode is illustrated in Figure 26. In this plot, an output pulse of 200 mA is periodically introduced on a
DC current level of 400 mA. Therefore, the tracking current mode (IOUT + 50 mA) is enabled. In this mode the
bq5101x measures the active output current and sets the regulators current limit 50 mA above this
measurement. When the load pulse occurs during a communication packet event, the output current is regulated
to 450 mA. As the communication packet event has finished the output load is allowed to increase. Note that
during the time the regulator is in current limit VOUT is reduced to 4.5 V and 5 V when not in current limit.
Synchronous Rectification
The bq5101x provides an integrated, self-driven synchronous rectifier that enables high-efficiency AC to DC
power conversion. The rectifier consists of an all NMOS H-Bridge driver where the backgates of the diodes are
configured to be the rectifier when the synchronous rectifier is disabled. During the initial startup of the WPC
system the synchronous rectifier is not enabled. At this operating point, the DC rectifier voltage is provided by the
diode rectifier. Once VRECT is greater than UVLO, half synchronous mode will be enabled until the load current
surpasses 120 mA. Above 120 mA the full synchronous rectifier stays enabled until the load current drops back
below 100 mA where half synchronous mode is enabled instead.
Temperature Sense Resistor Network (TS)
bq5101x includes a ratiometric external temperature sense function. The temperature sense function has two
ratiometric thresholds which represent a hot and cold condition. An external temperature sensor is recommended
in order to provide safe operating conditions for the receiver product. This pin is best used for monitoring the
surface that can be exposed to the end user (e.g. place the NTC resistor closest to the user).
Figure 41 allows for any NTC resistor to be used with the given VHOT and VCOLD thresholds.
28
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VTSB (2.2V)
20kΩ
R2
TS-CTRL
R1
R3
NTC
Figure 41. NTC Circuit Used for Safe Operation of the Wireless Receiver Power Supply
The resistors R1 and R3 can be solved by resolving the system of equations at the desired temperature
thresholds. The two equations are:
(
(
)
)
æ R R
+ R1 ö÷
ç
3
NTC TCOLD
ç
÷
+ R1 ÷
ç R 3 + R NTC
TCOLD
è
ø ´100
%VCOLD =
æ R R
ö
R
+
ç
3
NTC TCOLD
1 ÷
ç
÷ + R2
+ R1 ÷
ç R 3 + R NTC
TCOLD
è
ø
)
)
æ R R
+ R1 ) ö÷
ç
3 ( NTC THOT
ç
÷
+ R1 )÷
ç R 3 + (R NTC
THOT
è
ø ´100
%VHOT =
æ R R
ö
R
+
ç
3 ( NTC THOT
1) ÷
ç
÷ + R2
+ R1 )÷
ç R 3 + (R NTC
THOT
è
ø
(
(
(4)
Where:
R NTC
TCOLD
R NTC
THOT
bæçç 1TCOLD-1To ö÷÷
ø
= R oe è
bæçç 1
-1 ö÷÷
= R oe è THOT To ø
(5)
where, TCOLD and THOT are the desired temperature thresholds in degrees Kelvin. RO is the nominal resistance
and β is the temperature coefficient of the NTC resistor. RO is fixed at 20 kΩ. An example solution is provided:
• R1 = 4.23kΩ
• R3 = 66.8kΩ
where the chosen parameters are:
• %VHOT = 19.6%
• %VCOLD = 58.7%
• TCOLD = –10°C
• THOT = 100°C
• β = 3380
• RO = 10kΩ
The plot of the percent VTSB vs. temperature is shown in Figure 42:
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Figure 42. Example Solution for an NTC resistor with RO = 10KΩ and β = 4500
Figure 43 illustrates the periodic biasing scheme used for measuring the TS state. The TS_READ signal enables
the TS bias voltage for 24ms. During this period the TS comparators are read (each comparator has a 10 ms
deglitch) and appropriate action is taken based on the temperature measurement. After this 24ms period has
elapsed, the TS_READ signal goes low, which causes the TS-Bias pin to become high impedance. During the
next 35ms (priority packet period) or 235ms (standard packet period), the TS voltage is monitored and compared
to 100mV. If the TS voltage is greater than 100mV then a secondary device is driving the TS/CTRL pin and a
CTRL = ‘1’ is detected.
Figure 43. Timing Diagram for TS Detection Circuit
3-state Driver Recommendations for the TS-CTRL Pin
The TS-CTRL pin offers three functions with one 3-state driver interface
1. NTC temperature monitoring,
2. Fault indication,
30
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3. Charge done indication
A 3-state driver can be implemented with the circuit in Figure 44 and the use of two GPIO connections.
BATT
M3
TERM
TS-CTRL
FAULT
M4
Figure 44. 3-state Driver for TS-CTRL
Note that the signals “TERM” and “FAULT” are given by two GPIO’s. The truth table for this circuit is found in
Table 6:
Table 6.
TERM
FAULT
F (Result)
1
0
Z (Normal Mode)
0
0
Charge Complete
1
1
System Fault
The default setting is TERM = 1 and FAULT = 0. In this condition, the TS-CTRL net is high impedance (hi-z) and;
therefore, the NTC is function is allowed to operate. When the TS-CTRL pin is pulled to GND by setting FAULT =
1, the Rx is shutdown with the indication of a fault. When the TS-CTRL pin is pulled to the battery by setting
TERM = 1, the Rx is shutdown with the indication of a charge complete condition. Therefore, the host controller
can indicate whether the Rx is system is turning off due to a fault or due to a charge complete condition.
Thermal Protection
The bq5101x includes a thermal shutdown protection. If the die temperature reaches TJ(OFF), the LDO is shut
off to prevent any further power dissipation.
Series and Parallel Resonant Capacitor Selection
Shown in Figure 2, the capacitors C1 (series) and C2 (parallel) make up the dual resonant circuit with the
receiver coil. These two capacitors must be sized correctly per the WPC v1.0 specification. Figure 45 illustrates
the equivalent circuit of the dual resonant circuit:
C1
Ls’
C2
Figure 45. Dual Resonant Circuit with the Receiver Coil
Section 4.2 (Power Receiver Design Requirements) in volume 1 of the WPC v1.0 specification highlights in detail
the sizing requirements. To summarize, the receiver designer will be required take inductance measurements
with a fixed test fixture. The test fixture is shown in Figure 46:
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Figure 46. WPC v1.0 Receiver Coil Test Fixture for the Inductance Measurement Ls’ (copied from System
Description Wireless Power Transfer, volume 1: Low Power, Part 1 Interface Definition, Version 1.0.1,
Figure 4-4)
The primary shield is to be 50 mm x 50 mm x 1 mm of Ferrite material PC44 from TDK Corp. The gap dZ is to be
3.4 mm. The receiver coil, as it will be placed in the final system (e.g. the back cover and battery must be
included if the system calls for this), is to be placed on top of this surface and the inductance is to be measured
at 1-V RMS and a frequency of 100 kHz. This measurement is termed Ls’. The same measurement is to be
repeated without the test fixture shown in Figure 11. This measurement is termed Ls or the free-space
inductance. Each capacitor can then be calculated using Equation 6:
-1
é
ù
2
C = ê f × 2p × L' ú
1 ê S
Sú
ë
(
)
û
é
ù
2
C = ê f × 2p × L - 1 ú
2 ê D
S C ú
1û
ë
(
)
-1
(6)
Where fS is 100 kHz +5/-10% and fD is 1 MHz ±10%. C1 must be chosen first prior to calculating C2.
The quality factor must be greater than 77 and can be determined by Equation 7:
2p× f × LS
D
Q=
R
(7)
where R is the DC resistance of the receiver coil. All other constants are defined above.
Receiver Coil Load-Line Analysis
When choosing a receiver coil, it is recommend to analyze the transformer characteristics between the primary
coil and receiver coil via load-line analysis. This will capture two important conditions in the WPC system:
1. Operating point characteristics in the closed loop of the WPC system.
2. Instantaneous transient response prior to the convergence of the new operating point.
An example test configuration for conducting this analysis is shown in Figure 47:
32
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A
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CP
VIN
CS
LP
L S CD
CB
RL
V
Figure 47. Load-Line Analysis Test Bench
Where:
• VIN is a square-wave power source that should have a peak-to-peak operation of 19V.
• CP is the primary series resonant capacitor (i.e. 100 nF for Type A1 coil).
• LP is the primary coil of interest (i.e. Type A1).
• LS is the secondary coil of interest.
• CS is the series resonant capacitor chosen for the receiver coil under test.
• CD is the parallel resonant capacitor chosen for the receiver coil under test.
• CB is the bulk capacitor of the diode bridge (voltage rating should be at least 25 V and capacitance value of at
least 10µ F)
• V is a Kelvin connected voltage meter
• A is a series ammeter
• RL is the load of interest
It is recommended that the diode bridge be constructed of Schottky diodes.
The test procedure is as follows
• Supply a 19V AC signal to LP starting at a frequency of 210 kHz
• Measure the resulting rectified voltage from no load to the expected full load
• Repeat the above steps for lower frequencies (stopping at 110 kHz)
An example load-line analysis is shown in Figure 48:
20
18
175 kHz
160 kHz
16
150 kHz
VRECT (V)
14
140 kHz
125 kHz
12
115 kHz
135 kHz
10
130 kHz
8
6
4
2
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
LOAD (A)
Figure 48. Example Load-Line Results
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What this plot conveys about the operating point is that a specific load and rectifier target condition consequently
results in a specific operating frequency (for the type A1 TX). For example, at 1 A the dynamic rectifier target is
5.15 V. Therefore, the operating frequency will be between 150kHz and 160kHz in the above example. This is an
acceptable operating point. If the operating point ever falls outside the WPC frequency range (110kHz –
205kHz), the system will never converge and will become unstable.
In regards to transient analysis, there are two major points of interest:
1. Rectifier voltage at the ping frequency (175kHz).
2. Rectifier voltage droop from no load to full load at the constant operating point.
In this example, the ping voltage will be approximately 5 V. This is above the UVLO of the bq5101x and;
therefore, startup in the WPC system can be ensured. If the voltage is near or below the UVLO at this frequency,
then startup in the WPC system may not occur.
If the max load step is 1 A, the droop in this example will be Approximately1V with a voltage at 1 A of
Approximately 5.5 V (140 kHz load-line). To analyze the droop locate the load-line that starts at 7 V at no-load.
Follow this load-line to the max load expected and take the difference between the 7V no-load voltage and the
full-load voltage at that constant frequency. Ensure that the full-load voltage at this constant frequency is above
5V. If it descends below 5V, the output of the power supply will also droop to this level. This type of transient
response analysis is necessary due to the slow feedback response of the WPC system. This simulates the step
response prior to the WPC system adjusting the operating point.
NOTE
Coupling between the primary and secondary coils will worsen with misalignment of the
secondary coil. Therefore, it is recommended to re-analyze the load-lines at multiple
misalignments to determine where, in planar space, the receiver will discontinue operation.
34
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Recommended Rx coils can be found in Table 7:
Table 7.
Manufacturer
Part Number
Dimensions
Ls
Ls’
Output Current
Range
Application
TDK
WR-483250-15M2-G
48 x 32mm
10.4 μH
12 μH (1)
50-1000 mA
General 5V Power
Supply
TDK
WR-383250-17M2-G
38 x 32mm
11.1 μH
12.3 μH (1)
50-1000 mA
Space limited 5V Power
Supply
Vishay
IWAS-4832FF-50
48 x 32mm
10.8 μH
12.5 μH (1)
50-1000 mA
General 5V Power
Supply
Mingstar
312-00012
48 x 32mm
10.8 μH
12.9 μH (1)
50-1000 mA
General 5V power
Supply
Mingstar
312-00015
28 x 14mm
36.5 μH
45 μH (2)
150-1000 mA
Space limited 5V Power
Supply
(1)
(2)
Ls’ measurements conducted with a standard battery behind the Rx coil assembly. This measurement is subject to change based on
different battery sizes, placements, and casing material.
Battery not present behind the Rx coil assembly. Subject to drop in inductance depending on the placement of the battery.
It is recommended that all inductance measurements are repeated in the designers specific system as there are
many influence on the final measurements.
Package Summary
YFP Package
(Top View)
A1
A2
A3
A4
B1
B2
B3
B4
C1
C2
C3
C4
D1
D2
D3
D4
E1
E2
E3
E4
F1
F2
F3
F4
G1
G2
G3
G4
YFP Package Symbol
(Top Side Symbol for bq51013A)
D
TI YMLLLLS
bq51013A
0-Pin A1 Marker, TI-TI Letters, YM- Year Month Date Code,
LLLL-Lot Trace Code, S-Assembly Site Code
E
Figure 49. Chip Scale Packaging Dimensions
•
•
D = 3.0mm ± 0.035mm
E = 1.88mm ± 0.035mm
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REVISION HISTORY
Changes from Original (March 2012) to Revision A
•
36
Page
Deleted VRECT-TRACK from the Electrical Characteristics table ............................................................................................... 6
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PACKAGE OPTION ADDENDUM
www.ti.com
4-Jun-2012
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
Samples
(Requires Login)
BQ51013ARHLR
ACTIVE
QFN
RHL
20
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
BQ51013ARHLT
ACTIVE
QFN
RHL
20
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
BQ51013AYFPR
ACTIVE
DSBGA
YFP
28
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
BQ51013AYFPT
ACTIVE
DSBGA
YFP
28
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
BQ51014YFPR
ACTIVE
DSBGA
YFP
28
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
BQ51014YFPT
ACTIVE
DSBGA
YFP
28
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
4-Jun-2012
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jun-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
BQ51013ARHLR
Package Package Pins
Type Drawing
QFN
RHL
20
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
3000
330.0
12.4
3.8
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
4.8
1.6
8.0
12.0
Q1
BQ51013ARHLT
QFN
RHL
20
250
180.0
12.4
3.8
4.8
1.6
8.0
12.0
Q1
BQ51013AYFPR
DSBGA
YFP
28
3000
180.0
8.4
2.0
3.13
0.6
4.0
8.0
Q1
BQ51013AYFPT
DSBGA
YFP
28
250
180.0
8.4
2.0
3.13
0.6
4.0
8.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jun-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
BQ51013ARHLR
QFN
RHL
20
3000
346.0
346.0
29.0
BQ51013ARHLT
QFN
RHL
20
250
210.0
185.0
35.0
BQ51013AYFPR
DSBGA
YFP
28
3000
210.0
185.0
35.0
BQ51013AYFPT
DSBGA
YFP
28
250
210.0
185.0
35.0
Pack Materials-Page 2
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