Hynix GMS87C5108 Hynix semiconductor inc. 8-bit single-chip microcontroller Datasheet

HYNIX SEMICONDUCTOR INC.
8-BIT SINGLE-CHIP MICROCONTROLLERS
GMS81C5108
User’s Manual (Ver. 1.0)
Version 1.0
Published by
MCU Application Team
200
2001 Hynix Semiconductor Inc. All rights reserved.
Additional information of this manual may be served by Hynix Semiconductor offices in Korea or Distributors and Representatives listed at address directory.
Hynix Semiconductor reserves the right to make changes to any information here in at any time without notice.
The information, diagrams and other data in this manual are correct and reliable; however, Hynix Semiconductor is in no
way responsible for any violations of patents or other rights of the third party generated by the use of this manual.
GMS81C5108
Table of Contents
1. OVERVIEW ...........................................1
Description .........................................................1
Features .............................................................1
Development Tools ............................................2
Ordering Information
2. BLOCK DIAGRAM ................................3
3. PIN ASSIGNMENT ...............................4
4. PACKAGE DIAGRAM ...........................5
5. PIN FUNCTION .....................................6
6. PORT STRUCTURES ...........................8
7. ELECTRICAL CHARACTERISTICS ...11
8-Bit Capture Mode ......................................... 50
16-bit Capture Mode ....................................... 53
8-Bit (16-Bit) Compare OutPut Mode .............. 53
PWM Mode ..................................................... 53
13. Watch Timer/Watch Dog Timer......... 56
Watch Timer .................................................... 56
Watch Dog Timer ............................................ 57
14. Analog To Digital Converter ..............58
15. Buzzer Output Function ....................60
16. Serial Communication Interface ........62
Data Transmit/Receive Timing........................ 63
The method of Serial I/O ................................. 64
Absolute Maximum Ratings .............................11
Recommended Operating Conditions ..............11
DC Electrical Characteristics ...........................12
LCD Characteristics .........................................13
A/D Converter Characteristics .........................13
AC Characteristics ...........................................14
Serial I/O Characteristics .................................15
Typical Characteristics..................................... 16
17. INTERRUPTS ...................................65
8. MEMORY ORGANIZATION ................18
Configuration of LCD driver ............................. 71
Control of LCD Driver Circuit ........................... 72
LCD Display Memory ...................................... 73
Control Method of LCD Driver ......................... 74
Registers ..........................................................18
Program Memory .............................................21
Data Memory ................................................... 24
Addressing Mode ............................................. 27
9. I/O PORTS ..........................................31
Interrupt Sequence .......................................... 66
BRK Interrupt .................................................. 68
Multi Interrupt .................................................. 68
External Interrupt ............................................. 69
18. KEY SCAN ........................................70
19. LCD DRIVER .................................... 71
20. Remocon Carrier Generator ............. 76
Remocon Signal Output Control ..................... 76
Carrier Frequency ........................................... 77
Registers for Port .............................................31
I/O Ports Configuration ....................................32
21. OSCILLATOR CIRCUIT ....................80
10. CLOCK GENERATOR ......................34
22. RESET ..............................................81
Operation Mode ...............................................36
Operation Mode Switching ...............................37
POWER SAVING OPERATION .......................39
External Reset Input ........................................ 81
Watchdog Timer Reset ................................... 81
11. BASIC INTERVAL TIMER .................43
12. Timer / Counter .................................45
8-Bit Timer/Counter Mode ................................48
16 Bit Timer/Counter Mode ..............................50
A. CONTROL REGISTER LIST ................. i
B. INSTRUCTION .................................... iii
Terminology List................................................ iii
JUNE 2001 Ver 1.0
23. SUPPLY VOLTAGE DETECTION ....82
24. DEVEMOPMENT TOOLS .................83
OTP Programming .......................................... 83
Emulator S/W Setting ...................................... 84
Instruction Map ..................................................iv
Instruction Set ....................................................v
C. MASK ORDER SHEET ....................... xi
GMS81C5108
GMS81C5108
CMOS SINGLE-CHIP 8-BIT MICROCONTROLLER
WITH LCD CONTROLLER/DRIVER AND
INFRARED REMOTE CONTROL TRANSMITTERS
1. OVERVIEW
1.1 Description
The GMS81C5108 is an advanced CMOS 8-bit microcontroller with 8K bytes of ROM. The device is one of GMS800 family. The Hynix GMS81C5108 is a powerful microcontroller which provides a high flexibility and cost effective solution to
many LCD applications. The GMS81C5108 provides the following standard features: 8K bytes of ROM, 192 bytes of RAM,
37 Nibbles of Display RAM, 8/16-bit timer/counter, on-chip oscillator and clock circuitry. In addition, the GMS81C5108
supports power saving modes to reduce power consumption.
This document is only explained for the base of GMS81C5108, the eliminated functions are same as below.
Device name
ROM Size
OTP Size
RAM Size
I/O
Package
GMS81C5108
8K bytes
-
192 bytes
24
80QFP
8K bytes
192bytes
24
80QFP
GMS87C5108
1.2 Features
• 8K Bytes of On-chip Program Memory
• Carrier Generator for Remote Controller
• 192 Bytes of On-chip Data RAM
• 11 Interrupt sources
- 3 External interrupts (INT0 ~ 2)
- 8 Internal interrupts (BIT, Timer × 2, WT,
A/DC, SIO, REM, Keyscan)
• 37 Nibbles of Display RAM
• Instruction Cycle Time:
- 1us at 4MHz (2 cycle NOP instruction)
• 24 Programmable I/O pins
• 6-bit Buzzer Driving port
- 500Hz ~ 250kHz (@4MHz)
• 2V to 4V Operating Range
• 4-channel 8-bit On-chip A/D Converter
• Dual Clock Operation
- main : 400kHz ~ 4.2MHz
- sub. : 32.768kHz
• Power Saving Mode
- STOP, SLEEP, Sub Active mode
• One 8-bit Basic Interval Timer/Counter
• Key Scan Interrupt
• Two 8-bit Timer/ Counter
(It can be used one 16-bit Timer/Counter)
• LCD display/controller (LCDC)
- Static Mode (37Seg × 1Com, 1/3 Bias)
- 1/2 Duty Mode (36Seg × 2Com, 1/3 Bias)
- 1/3 Duty Mode (35Seg × 3Com, 1/3 Bias)
- 1/4 Duty Mode (34Seg × 4Com, 1/3 Bias)
• LCD Display Voltage Booster
• Watch Timer (2Hz, 4Hz, 16Hz, 1/64Hz)
• 8-bit Serial I/O (SIO)
• Supply Voltage Detector(SVD)
- 2 level detector (2.2V, 1.7V)
• One 10-bit High Speed PWM Output
JUNE 2001 Ver 1.0
1
GMS81C5108
1.3 Development Tools
98TM.
Note: There are several setting switches in the Emulator.
User should read carefully and do setting properly before
developing the program refer to "24.2 Emulator S/W Setting" on page 84. Otherwise, the Emulator may not work
properly.
Software
- MS- Window base assembler
- Linker / Editor / Debugger
Hardware
(Emulator)
- CHOICE-Dr.
- CHOICE-Dr. EVA 81C51 B/D
OTP Writer
- CHOICE - SIGMA (Single writer)
- CHOICE - GANG4 (Gang writer)
Please contact sales part of Hynix Semiconductor.
The GMS81C5108 is supported by a full-featured macro assembler, an in-circuit emulator CHOICE-Dr.TM and OTP programmers. There are two different type programmers such as single
type and gang type. For mode detail, refer to OTP Programming
chapter. Macro assembler operates under the MS-Windows 95/
1.4 Ordering Information
Device name
ROM Size (bytes)
RAM size
Package
Mask ROM version
GMS81C5108
8K bytes
192 bytes
80QFP
OTP ROM version
GMS87C5108
8K bytes OTP
192 bytes
80QFP
2
JUNE 2001 Ver 1.0
GMS81C5108
2. BLOCK DIAGRAM
Common Drive Output
COM0
COM1/SEG36
COM2/SEG35
COM3/SEG34
VCL0
VCL1
VCL2
CAPH
CAPL
VLCDC
Segment Drive Output
SEG0 ~ SEG33
LCD Display
LCD Controller/Driver (LCDC)
Voltage Booster
PSW
ALU
Accumulator
Stack Pointer
LCD
Display
Memory
Interrupt Controller
RESET
System controller
System
Clock Controller
PC
Data
Memory
Program
Memory
Data Table
8-bit B asic
Interval Tim er
Timing generator
XIN
XOUT
SXIN
SXOUT
VDD
VSS
AVDD
AVSS
Power
Supply
High freq.
Low freq.
Clock
Generator
Watch/Watch Dog
Timer
Power
Supply
Circuit
VREG
JUNE 2001 Ver 1.0
WDTOUT
High Speed
PWM
PC
8-bit A /D
C onverter
8/16-bit
SIO Tim er/C ounter
R3
R2
R1
R0
R30
R31 / PWM
R32
R33
R20 / AN0
R21 / AN1
R22 / AN2
R23 / AN3
R10 / KS0
R11 / KS1
R12 / KS2
R13 / KS3
R14 / KS4
R15 / KS5
R16 / KS6
R17 / KS7
R00 / INT0
R01 / INT1
R02 / INT2
R03 / EC0
R04 / BUZ
R05 / SCK
R06 / SO
R07 / SI
Buzzer
Driver
Remocon
(REM)
REMOUT
3
4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
SEG32
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
XOUT
XIN
VDD
REMOUT
R07 / SI
R06 / S0
R05 / SCK
R04 / BUZ
R03 / EC0
R02 / INT2
R01 / INT1
R33
R32
R31 / PWM
R30
R17 / KS7
R16 / KS6
R15 / KS5
R14 / KS4
R13 / KS3
R12 / KS2
R11 / KS1
R10 / KS0
R00 / INT0
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
GMS81C5108
3. PIN ASSIGNMENT
RESET
65
40
AVSS
VREG
66
39
R23 / AN3
WDTOUT
67
38
R22 / AN2
SXIN
68
37
R21 / AN1
SXOUT
69
36
R20 / AN0
VCL0
70
35
AVDD
VLCDC
71
34
SEG0
VCL1
72
33
VSS
VCL2
73
32
SEG1
CAPH
74
31
SEG2
CAPL
75
30
SEG3
COM0
76
29
SEG4
SEG36 / COM1
77
28
SEG5
SEG35 / COM2
78
27
SEG6
SEG34 / COM3
79
26
SEG7
SEG33
80
25
SEG8
GMS81C5108
JUNE 2001 Ver 1.0
GMS81C5108
4. PACKAGE DIAGRAM
24.15
23.65
14.10
13.90
SEE DETAIL "A"
0.36
0.10
0-7°
3.10 max.
0.45
0.30
0.8 BSC
1.03
0.73
0.23
0.13
18.15
17.65
max
-----------min
UNIT: mm
20.10
19.90
1.95
REF
DETAIL “A”
Figure 4-1 Package Diagram
JUNE 2001 Ver 1.0
5
GMS81C5108
5. PIN FUNCTION
VDD: Supply voltage.
used as outputs or inputs or schmitt trigger inputs. Also, pullup resistors and open-drain outputs can be assigned by software.
VSS: Circuit ground.
AVDD: Supply voltage to the ladder resistor of ADC circuit. To enhance the resolution of analog to digital converter, use independent power source as well as possible, other
than digital power source.
AVSS: ADC circuit ground
RESET: Reset the MCU.
WDTOUT: Output for detection of a program malfunction. If the user wants to use this pin, connect it to the RESET pin.
REMOUT: Signal output of an infrared remote controller.
XIN: Input to the inverting oscillator amplifier and input to
the internal main clock operating circuit.
XOUT: Output from the inverting oscillator amplifier.
SXIN: Input to the internal sub system clock operating circuit.
SXOUT: Output from the inverting subsystem oscillator
amplifier.
SEG0~SEG36: Segment signal output pins for the LCD
display. See "19. LCD DRIVER" on page 71 for details.
COM0~COM3: Common signal output pins for the LCD
display. See "19. LCD DRIVER" on page 71 for details.
SEG34~SEG36 and COM1~COM3 are selected by LCDD
of the LCR register.
R00~R07: R0 is an 8-bit CMOS bidirectional I/O port. R0
pins 1 or 0 written to the Port Direction Register can be
used as outputs or inputs. Also, pull-up resistors and opendrain outputs can be assigned by software.
In addition, R0 serves the functions of the various following special features.
In addition, R1 serves the functions of the various following special features.
Port pin
R10
R11
R12
R13
R14
R15
R16
R17
R00
R01
R02
R03
R04
R05
R06
R07
Alternate function
INT0 (External interrupt 0)
INT1 (External interrupt 1)
INT2 (External interrupt 2)
Event counter input
Buzzer Output
SCK (SPI CLK Input/Output)
SO (SPI Serial Data Output)
SI (SPI Serial Data Input)
R10~R17: R1 is an 8-bit CMOS bidirectional I/O port. R1
pins 1 or 0 written to the Port Direction Register can be
6
KS0 (Key scan input 0)
KS1 (Key scan input 1)
KS2 (Key scan input 2)
KS3 (Key scan input 3)
KS4 (Key scan input 4)
KS5 (Key scan input 5)
KS6 (Key scan input 6)
KS7 (Key scan input 7)
R20~R23: R2 is a 4-bit CMOS bidirectional I/O port. Each
pins 1 or 0 written to the Port Direction Register can be
used as outputs or inputs. Also, pull-up resistors and opendrain outputs can be assigned by software.
In addition, R2 serves the functions of the various following special features.
Port pin
R20
R21
R22
R23
Alternate function
AN0 (Analog Input Port0)
AN1 (Analog Input Port1)
AN2 (Analog Input Port2)
AN3 (Analog Input Port3)
R30~R33: R3 is a 4-bit CMOS bidirectional I/O port. Each
pins 1 or 0 written to the Port Direction Register can be
used as outputs or inputs. Also, pull-up resistors and opendrain outputs can be assigned by software.
In addition, R3 serves the functions of the various following special features.
Port pin
Port pin
Alternate function
R31
Alternate function
PWM (PWM Output)
VCL0~VCL2: Power supply pins for the LCD driver. The
voltage on each pin is VCL2> VCL1> VCL0. See "19.
LCD DRIVER" on page 71 for details.
VLCDC: LCD drive voltage booster reference.
CAPH, CAPL: LCD drive voltage booster capacitor.
VREG: Output of the voltage regular for the sub clock oscillation circuit. Connect external 0.1uF capacitor to this
pin when using the sub system clock.
JUNE 2001 Ver 1.0
GMS81C5108
Primary Function
PIN NAME
Secondary Function
Pin No.
I/O
Description
I/O
Description
State @ Reset
State @ STOP
VDD
62
-
Supply Voltage
-
-
-
-
VSS
33
-
Circuit Ground
-
-
-
-
AVDD
35
-
Supply Voltage for
ADC
-
-
-
-
AVSS
40
-
Ground for ADC
-
-
-
-
RESET
65
I
Reset (low active)
-
-
‘L’ input
‘H’ input
WDTOUT
67
O
Watch dog output
-
-
Floating (To be
connect Pull-up)
State of before
STOP
REMOUT
61
O
Remocon output
-
-
XIN, XOUT
63, 64
I,O
Main clock oscillator
-
-
SXIN, SXOUT
68, 69
I,O
Sub clock oscillator
-
-
66
-
Sub clock voltage
-
-
-
-
70,72,73
-
LCD drive voltage
-
-
Internal VCL0
Connected
State of before
STOP
71
-
LCD drive voltage
booster reference
-
-
-
-
74,75
-
LCD drive voltage
booster capacitor
-
-
Internal VCL0
Connected
State of before
STOP
SEG0 ~ SEG33 34, 32~1
O
LCD segment output
-
-
Segment output
COM0
76
O
LCD common output
-
-
Common output
79~77
O
LCD common output.
-
LCD segment
output
R00/INT0
41
I/O
I
Interrupt Input
R01/INT1
54
I/O
I
Interrupt Input
R02/INT2
55
I/O
I
Interrupt Input
R03/EC0
56
I/O
I
Event counter input
R04/BUZ
57
I/O
O
Buzzer output
R05/SCK
58
I/O
I/O
Serial clock I/O
R06/SO
59
I/O
O
Serial Data Output
R07/SI
60
I/O
I
Serial Data Input
R10 ~ R17/
KS0 ~ KS7
42~49
I/O
I
Key wake-up input
R20 ~ R23/
AN0 ~ AN3
36~39
I/O
I
A/D converter
analog input
50,52,53
I/O
-
-
51
I/O
O
PWM output
VREG
VCL0~VCL2
VLCDC
CAPH,CAPL
SEG34/COM3
SEG35/COM2
SEG36/COM1
R30,R32,R33
R31/PWM
General I/O port
‘L’ output
Oscillation
‘L’, ‘L’
Oscillation
Common output
State of before
STOP
Input port
Table 5-1 Port Function Description
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7
GMS81C5108
6. PORT STRUCTURES
R00~R03/INT0~INT2, R03/EC0, R07/SI
P u ll up
R e g.
P ull up
R eg .
Pull-up Tr.
Open Drain
Reg.
Data Reg.
Pin
Dir. Reg.
Data Reg.
Pin
KSMR<0:7>
VSS
VSS
MUX
RD
INT0 ~ IN T2
EC0,SI
VDD
Dir. Reg.
PMR<0:3,7>
MUX
Pull-up Tr.
Open Drain
Reg.
VDD
Data Bus
Data Bus
R10~R17/KS0~KS7
RD
RD
Noise
Canceller
RD
Noise
Canceller
Key Scan
KS0 ~ KS7
Key Scan
Enable
R04/BUZ, R06/SO
Pull up
Reg.
Pull-up Tr.
R20~R23/AN0~AN3
VDD
P u ll up
R e g.
Data Reg.
Pull-up Tr.
Open Drain
Reg.
BUZ,SO
Dir. Reg.
Pin
MUX
VSS
Data Bus
Data Bus
Open Drain
Reg.
VDD
Data Reg.
Pin
Dir. Reg.
RD
VSS
RD
MUX
R05/SCK
RD
RD
Pull up
Reg.
Pull-up Tr.
A/D converter
AN0 ~ AN3
VDD
Data Bus
Open Drain
Reg.
A/D Enable
channel select
Data Reg.
SCK(OUT)
Dir. Reg.
Pin
SCK(IN)_EN
VSS
MUX
RD
SCK(IN)
8
Noise
Canceller
RD
JUNE 2001 Ver 1.0
GMS81C5108
R30, R32, R33
COM0
P u ll up
R e g.
VCL2 or VCL1
Pull-up Tr.
VCL2
Frame Counter
Data Bus
Open Drain
Reg.
VDD
Pin
LCD Control
Data Reg.
VCL1 or VSS
Pin
Dir. Reg.
MUX
VSS
COM1/SEG36, COM2/SEG35, COM3/SEG34
RD
RD
VCL2 or VCL1
VCL2
R31
DB
LCD Data
Reg.
Frame Counter
Pull up
Reg.
Pull-up Tr.
Pin
LCD Control
VDD
VCL1 or VSS
Data Bus
Open Drain
Reg.
Data Reg.
VCL0 ~ VCL2, CAPH, CAPL
PWMO
Dir. Reg.
VCL0 ~ VCL2, CAPH, CAPL
Pin
MUX
Pin
VSS
RD
RD
VLCDC, VREG
SEG0 ~ SEG33
VCL2 or VCL1
VDD
VCL2
DB
LCD Data
Reg.
VCLDC, VREG
Frame Counter
Pin
LCD Control
Pin
VCL1 or VSS
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9
GMS81C5108
REMOUT
XIN, XOUT (Crystal or Ceramic resonator Option)
VDD
VDD
Main frequency
clock
VDD
XOUT
REMOUT
Pin
VSS
VDD
VDD
XIN
RESET
STOP
VSS
GMS87C5108 (OTP)
XIN, XOUT (RC Option)
Internal RESET
RESET
VDD
Noise
Canceller
Main frequency
clock
XOUT
VSS
VSS
VDD
GMS81C5108 (MASK)
Internal RESET
VDD
VDD
Internal Cap.
= 5.0pF
Mask Option
Default no pull-up
RC
Oscillator
VDD
XIN
RESET
Noise
Canceller
STOP
VSS
SXIN, SXOUT
VSS
VDD
WDTOUT
Sub clock
SXOUT
VDD
VSS
VDD
WDTOUT
WDTOUTEN
Pin
VSS
SXIN
VSS
10
JUNE 2001 Ver 1.0
GMS81C5108
7. ELECTRICAL CHARACTERISTICS
7.1 Absolute Maximum Ratings
Supply voltage ........................................... -0.3 to +7.0 V
Storage Temperature ................................-40 to +125 °C
Voltage on any pin with respect to Ground (VSS)
............................................................... -0.3 to VDD+0.3
Maximum current sunk by (IOL per I/O Pin) ........20 mA
Maximum output current sourced by (IOH per I/O Pin)
...............................................................................15 mA
Maximum current (ΣIOH)...................................... 60 mA
Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of
the device at any other conditions above those indicated in
the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Maximum current (ΣIOL) ....................................100 mA
7.2 Recommended Operating Conditions
Specifications
Parameter
Symbol
Condition
Unit
Min.
Typ.
Max.
Supply Voltage
VDD
fMAIN=4MHz
fSUB=32.768kHz
2.0
-
4.0
V
Main Operating Frequency
fMAIN
VDD=2~4V
0.4
-
4.2
MHz
Sub Operating Frequency
fSUB
VDD=2~4V
-
32.768
-
kHz
Operating Temperature
TOPR
-20
-
70
°C
JUNE 2001 Ver 1.0
11
GMS81C5108
7.3 DC Electrical Characteristics
(TA=-20~70°C, VDD=AVDD=2~4V, VSS=AVSS=0V)
Parameter
Symbol
Condition
Specifications
Min.
Typ.
Max.
Unit
VIH1
R0~R3
0.7VDD
-
VDD
VIH2
RESET, XIN, INT0~INT2, EC0, SI, SCK
0.8VDD
-
VDD
VIH3
SXIN
0.8VREG
-
VREG
VIL1
R0~R3
0
-
0.3 VDD
VIL2
RESET, XIN, INT0~INT2, EC0, SI, SCK
0
-
0.2VDD
VIL3
SXIN
0
-
0.2VREG
VOH1
R0~R3, IOH1=-0.7mA
VDD-0.3
-
-
VOH2
XOUT, IOH2=-50µA
VDD-0.5
-
-
VOH3
SXOUT, IOH3=-5µA
VREG-0.3
-
-
VOL1
R0~R3, WDTOUT, IOL1=1mA
-
-
0.4
VOL2
XOUT, IOL2=50µA
-
-
0.5
VOL3
SXOUT, IOL3=5µA
-
-
0.5
Input High
Leakage Current
IIH
R0~R3, VIN=VDD
-
-
1
Input Low
Leakage Current
IIL
R0~R3, VIN=0V
-
-
-1
Output High
Leakage Current
IOH
REMOUT, VDD=3V, VOH= VDD-1.0V
-30
-
-5
Output Low
Leakage Current
IOL
REMOUT, VDD=3V, VOL= 1.0V
0.5
-
3
RP1
R0~R3, VDD=3V
50
100
200
RP2
RESET, VDD=3V
(GMS81C5108 Mask Option)
30
60
120
RF1
Main OSC Feedback Resister VDD=3V
0.5
-
1.5
RF2
Sub OSC Feedback Resister VDD=3V
5.
-
15
FRC
R=30kΩ, VDD=3V
1
2
3
MHz
2.0
2.2
2.4
V
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Pull-up Resister
Feed Back Resister
RC Oscillator
Frequency
VREG Voltage
Supply Current
V
V
V
V
µA
mA
VREG
VREG=0.2uF
IDD1
Main Active Mode
VDD=4V±10%, XIN=4MHz, SXIN=0
-
2.7
4.0
IDD2
Main Sleep Mode
VDD=4V±10%, XIN=4MHz, SXIN=0
-
0.47
1.2
IDD3
Stop Mode
V D D =4V ±10% , XIN=0, SXIN=0
-
2.0
10
IDD4
Sub Active mode1
VDD=3V±10%, XIN=0, SXIN=32.768kH z
-
35(70)
80(150)
IDD5
Sub Sleep mode
VDD=4V±10%, XIN=0, SXIN=32.768kH z
-
6.0
15
kΩ
MΩ
mA
µA
1. IDD4 is tested by only nop operation. The value of ( ) is tested at OTP.
12
JUNE 2001 Ver 1.0
GMS81C5108
7.4 LCD Characteristics
(TA=-20~70°C, VDD=AVDD=2~4V, VSS=AVSS=0V)
Specifications
Parameter
VLCDC Output Voltage
Symbol
Condition
VLCDC
Unit
Min.
Typ.
Max.
VDD=3V, TA=25°C,
R1=1MΩ, R2=300kΩ
0.7
0.9
1.1
0.9
-
2.0
V
LCD Reference
Output Voltage
VCL0
External Variable Resistance
(0 to 1MΩ)
Double Output Voltage
VCL1
C1~C4=0.47uF
1.9VCL0
2.0VCL0
-
Triple Output Voltage
VCL2
C1~C4=0.47uF
2.85VCL0
3.0VCL0
-
LCD Common
Output Current
ICOM
Output Voltage Deviation=0.2V
30
-
-
LCD Segment
Output Current
ISEG
V
µA
Output Voltage Deviation=0.2V
5
−
-
7.5 A/D Converter Characteristics
(TA=25°C, VDD=3V, AVDD=3.072V, VSS=AVSS=0V)
Specifications
Parameter
Symbol
Condition
Unit
Min.
Typ.
Max.
AVDD
-
AVSS
-
AVDD
VAN
-
AVSS-0.3
-
AVDD+0.3
Current Following Between AVDD and AVSS
IAVDD
-
-
-
200
Overall Accuracy
CAIN
-
-
±1.0
±2.0
Non Linearity Error
NNLE
-
-
±1.0
±2.0
NDNLE
-
-
±1.0
±2.0
Zero Offset Error
NZOE
-
-
±0.5
±1.5
Full Scale Error
NFSE
-
-
±0.25
±0.5
Gain Error
NGE
-
-
±1.0
±1.5
TCONV
fMAIN=4MHz
-
-
30
Analog Power Supply Input Voltage Range
Analog Input Voltage Range
Differential Non Linearity Error
Conversion Time
JUNE 2001 Ver 1.0
V
µA
LSB
µS
13
GMS81C5108
7.6 AC Characteristics
(TA=25°C, VDD=4V, AVDD=4V, VSS=AVSS=0V)
Specifications
Parameter
Symbol
Pins
Unit
Min.
Typ.
Max.
Main Operating Frequency
fMCP
XIN
0.455
-
4.19
MHz
Sub Operating Frequency
fSCP
SXIN
30
32.768
35
kHz
System Clock Frequency1
tSYS
-
0.477
-
4.395
µS
-
-
20
-
-
60
-
-
100
SXIN, SXOUT
-
1
2
S
Main Oscillation
Stabilization Time (4MHz)
Main Oscillation
Stabilization Time (910kHz)
XIN, XOUT
tMST
Main Oscillation
Stabilization Time (455kHz)
tSST
Sub Oscillation
Stabilization Time
mS
External Clock
“H” or “L” Pulse Width
tMCPW
XIN
80
-
-
nS
tSCPW
SXIN
5
-
-
µS
Interrupt Pulse Width
tIW
INT0, INT1, INT2
2
-
-
tSYS
RESET Input Pulse “L” Width
tRST
RESET
8
-
-
tSYS
Event Counter Input
“H” or “L” Pulse Width
tECW
EC0
2
-
-
tSYS
1.SCMR=XXXX000X that is fMAIN/2
1/fMCP
tMCPW
tMCPW
0.8VDD
XIN
0.2VDD
tSYS
tSCPW
1/fSCP
tSCPW
0.8VDD
SXIN
0.2VDD
tRST
RESET
0.2VDD
tECW
tECW
0.8VDD
EC0
0.2VDD
Figure 7-1 AC Timing Chart
14
JUNE 2001 Ver 1.0
GMS81C5108
7.7 Serial I/O Characteristics
(TA=25°C, VDD=AVDD=2~4V, VSS=AVSS=0V)
Specifications
Parameter
Symbol
Pins
Unit
Min.
Typ.
Max.
SCK Input Clock Pulse Period
tSCYC
2tSYS+200
-
-
SCK Input Clock “H” or “L” Pulse Width
tSCKW
tSYS+70
-
-
SCK Output Clock Cycle Time
tSCYC
4tSYS
-
16tSYS
SCK output Clock “H” or “L” Pulse Width
tSCKW
2tSYS-30
-
-
tDS
-
-
100
SI input Setup Time (External SCK)
tESUS
100
-
-
SI input Setup Time (Internal SCK)
tISUS
100
-
-
tSYS+100
-
-
SCK output Clock Delay Time
SCK
SI
tHS
SI input Hold Time
nS
tSCYC
tSCKW
tSCKW
0.8VDD
SCK
0.2VDD
tSUS
tHS
0.8VDD
SI
0.2VDD
tDS
SO
0.8VDD
0.2VDD
Figure 7-2 Serial I/O Timing Chart
JUNE 2001 Ver 1.0
15
GMS81C5108
7.8 Typical Characteristics
These graphs and tables are for design guidance only and
are not tested or guaranteed.
The data is a statistical summary of data collected on units
from different lots over a period of time. “Typical” represents the mean of the distribution while “max” or “min”
represents (mean + 3σ) and (mean − 3σ) respectively
where σ is standard deviation
In some graphs or tables, the datas presented are outside specified operating range (e.g. outside specified
VDD range). This is for information only and devices
are guaranteed to operate properly only within the
specified range.
IOH−VOH, VDD=4.2V
IOH
(mA)
-16
-14
IOL
(mA)
40
-20°C
25°C
70°C
IOL−VOL, VDD=4.2V
-20°C
R
(kΩ)
25°C
70°C
-12
R−
−Ta
R0,R1,R2,R3 pin
200
30
-10
-8
20
VDD=4.0V
100
-6
-4
10
0
-2
0
1.0
2.0
3.0
VOH
4.0 (V)
1.0
R0~R3 pin
VIH2
(V)
fMAIN=4MHz
Ta=25°C
4
4
3
3
2
2
1
1
0
2
2.5
3
3.5
VDD
4 (V)
2
2
1
1
0
16
R−
−Ta
2.5
25
50
75
Ta
(°C)
RESET pin
R
(kΩ)
100
VDD=4.0V
50
2
VIL1
(V)
fMAIN=4MHz
Ta=25°C
2.5
fMAIN=4MHz
Ta=25°C
0
3
3.5
VDD
4 (V)
0
-25
0
25
50
75
Ta
(°C)
VDD−VIL2
R0~R3 pin
2
4.0
RESET,XIN,INT0~INT2,EC0.SI.SCK
0
VDD−VIL1
VIL1
(V)
3.0
VDD−VIH2
VDD−VIH1
VIH1
(V)
2.0
-25
VOL
(V)
3
3.5
VDD
4 (V)
RESET,XIN,INT0~INT2,EC0.SI.SCK
fMAIN=4MHz
Ta=25°C
0
2
2.5
3
3.5
VDD
4 (V)
JUNE 2001 Ver 1.0
GMS81C5108
Operating Area
fMAIN−VDD
fMAIN
(MHz)
fMAIN
(MHz) Ta= -20~70°C
(Main-clock)
6
Ta=25°C
4
R = 20kΩ
5
3
4
R = 47kΩ
2
3
R = 68kΩ
1
2
4
0
VDD
0
IDD
(mA)
2
R = 100kΩ
1
2.5
3
3.5
2
2.5
3
3.5
4
VDD
4.5 (V)
4 (V)
Normal Mode (Main opr.)
IDD1−VDD
Ta=25°C
fMAIN=4MHz
IDD
(µA)
Sleep Mode (Main opr.)
ISLEEP (IDD2)−VDD
IDD
(µA)
Ta=25°C
fMAIN=4MHz
400
4
3
300
3
2
200
2
1
100
1
0
2
IDD
(µA)
100
2.5
3
3.5
0
VDD
4 (V)
2
Normal Mode (Sub opr.)
IDD4−VDD
IDD
(µA)
fSXIN=32kHz
Ta=25°C
8
75
6
50
4
25
2
0
2
2.5
JUNE 2001 Ver 1.0
3
3.5
VDD
4 (V)
2.5
3
VDD
4 (V)
3.5
Stop Mode
ISTOP (IDD3)−VDD
Ta=25°C
fMAIN=0Hz
0
2
2.5
3
3.5
VDD
4 (V)
Sleep Mode (Sub opr.)
ISLEEP (IDD5)−VDD
f SX IN = 3 2 kH z
Ta=25°C
0
2
2.5
3
3.5
VDD
4 (V)
17
GMS81C5108
8. MEMORY ORGANIZATION
The GMS81C5108 has separate address spaces for Program memory, Data Memory and Display memory. Program memory can only be read, not written to. It can be up
to 8K bytes of Program memory. Data memory can be read
and written to up to 192 bytes including the stack area. Display memory has prepared 37 bytes for LCD.
8.1 Registers
This device has six registers that are the Program Counter
(PC), a Accumulator (A), two index registers (X, Y), the
Stack Pointer (SP), and the Program Status Word (PSW).
The Program Counter consists of 16-bit register.
A
ACCUMULATOR
X
X REGISTER
Y
Y REGISTER
SP
PCH
STACK POINTER
PCL
PROGRAM COUNTER
PSW
PROGRAM STATUS
WORD
Generally, SP is automatically updated when a subroutine
call is executed or an interrupt is accepted. However, if it
is used in excess of the stack area permitted by the data
memory allocating configuration, the user-processed data
may be lost.
The stack can be located at any position within 00H to BFH
of the internal data memory. The SP is not initialized by
hardware, requiring to write the initial value (the location
with which the use of the stack starts) by using the initialization routine. Normally, the initial value of “BF H” is
used.
Stack Address (00H ~ BFH)
15
8
7
0
Figure 8-1 Configuration of Registers
Accumulator: The Accumulator is the 8-bit general purpose register, used for data operation such as transfer, temporary saving, and conditional judgement, etc.
The Accumulator can be used as a 16-bit register with Y
Register as shown below.
0
SP
Hardware fixed
Caution:
The Stack Pointer must be initialized by software because its value is undefined after RESET.
Example: To initialize the SP
LDX
TXSP
Y
Y
#0BFH
; SP ← BFH
A
A
Two 8-bit Registers can be used as a “YA” 16-bit Register
Figure 8-2 Configuration of YA 16-bit Register
Program Counter: The Program Counter is a 16-bit wide
which consists of two 8-bit registers, PCH and PCL. This
counter indicates the address of the next instruction to be
executed. In reset state, the program counter has reset routine address (PCH:0FFH, PCL:0FEH).
X, Y Registers: In the addressing mode which uses these
index registers, the register contents are added to the specified address, which becomes the actual address. These
modes are extremely effective for referencing subroutine
tables and memory tables. The index registers also have increment, decrement, comparison and data transfer functions, and they can be used as simple accumulators.
Program Status Word: The Program Status Word (PSW)
contains several bits that reflect the current state of the
CPU. The PSW is described in Figure 8-3. It contains the
Negative flag, the Overflow flag, the Break flag the Half
Carry (for BCD operation), the Interrupt enable flag, the
Zero flag, and the Carry flag.
Stack Pointer: The Stack Pointer is an 8-bit register used
for occurrence interrupts and calling out subroutines. Stack
Pointer identifies the location in the stack to be accessed
(save or restore).
This flag stores any carry or borrow from the ALU of CPU
after an arithmetic operation and is also changed by the
Shift Instruction or Rotate Instruction.
18
[Carry flag C]
JUNE 2001 Ver 1.0
GMS81C5108
[Zero flag Z]
or data transfer is “0” and is cleared by any other result.
This flag is set when the result of an arithmetic operation
MSB
PSW
N
LSB
V
G
B
H
I
Z
C
RESET VALUE : 00H
CARRY FLAG RECEIVES
CARRY OUT
NEGATIVE FLAG
OVERFLOW FLAG
ZERO FLAG
SELECT DIRECT PAGE
when g=1, page is addressed by RPR
INTERRUPT ENABLE FLAG
HALF CARRY FLAG RECEIVES
CARRY OUT FROM BIT 1 OF
ADDITION OPERLANDS
BRK FLAG
Figure 8-3 PSW (Program Status Word) Register
[Interrupt disable flag I]
This flag enables/disables all interrupts except interrupt
caused by Reset or software BRK instruction. All interrupts are disabled when cleared to “0”. This flag immediately becomes “0” when an interrupt is served. It is set by
the EI instruction and cleared by the DI instruction.
[Half carry flag H]
After operation, this is set when there is a carry from bit 3
of ALU or there is no borrow from bit 4 of ALU. This bit
can not be set or cleared except CLRV instruction with
Overflow flag (V).
[Break flag B]
This flag is set by software BRK instruction to distinguish
BRK from TCALL instruction with the same vector address.
[Direct page flag G]
JUNE 2001 Ver 1.0
This flag assigns RAM page for direct addressing mode. In
the direct addressing mode, addressing area is from zero
page 00H to 0FFH when this flag is "0". If it is set to "1",
addressing area is assigned by RPR register (address
0F3H). It is set by SETG instruction and cleared by CLRG.
[Overflow flag V]
This flag is set to “1” when an overflow occurs as the result
of an arithmetic operation involving signs. An overflow
occurs when the result of an addition or subtraction exceeds +127 (7FH) or −128 (80H). The CLRV instruction
clears the overflow flag. There is no set instruction. When
the BIT instruction is executed, bit 6 of memory is copied
to this flag.
[Negative flag N]
This flag is set to match the sign bit (bit 7) status of the result of a data or arithmetic operation. When the BIT instruction is executed, bit 7 of memory is copied to this flag.
19
GMS81C5108
At acceptance
of interrupt
At execution of a
CALL/TCALL/PCALL
00BC
00BC
00BD
00BD
PSW
00BE
PCL
00BF
PCH
00BE
PCL
00BF
PCH
Push
down
At execution
of RET instruction
00BC
00BC
00BD
Push
down
At execution
of RETI instruction
00BE
PCL
00BF
PCH
Pop
up
00BD
PSW
00BE
PCL
00BF
PCH
SP before
execution
00BF
00BF
00BD
00BC
SP after
execution
00BD
00BC
00BF
00BF
At execution
of PUSH instruction
PUSH A (X,Y,PSW)
At execution
of POP instruction
POP A (X,Y,PSW)
00BC
00BC
00BD
00BD
00BE
00BF
Pop
up
0000H
Stack
depth
00BE
A
Push
down
00BF
A
SP before
execution
00BF
00BE
SP after
execution
00BE
00BF
Pop
up
00BFH
Figure 8-4 Stack Operation
20
JUNE 2001 Ver 1.0
GMS81C5108
8.2 Program Memory
A 16-bit program counter is capable of addressing up to
64K bytes, but this device has 8K bytes program memory
space only physically implemented. Accessing a location
above FFFFH will cause a wrap-around to 0000H.
Example: Usage of TCALL
Figure 8-5 shows a map of Program Memory. After reset,
the CPU begins execution from reset vector which is stored
in address FFFEH and FFFFH as shown in Figure 8-6.
;
;TABLE CALL ROUTINE
;
FUNC_A: LDA
LRG0
RET
;
FUNC_B: LDA
LRG1
2
RET
;
;TABLE CALL ADD. AREA
;
ORG
0FFC0H
DW
FUNC_A
DW
FUNC_B
As shown in Figure 8-5, each area is assigned a fixed location in Program Memory. Program Memory area contains
the user program.
E000H
PROGRAM
MEMORY
FEFFH
FF00H
FFC0H
FFDFH
FFE0H
FFFFH
TCALL
AREA
PCALL
AREA
INTERRUPT
VECTOR AREA
Figure 8-5 Program Memory Map
LDA
#5
TCALL 0FH
:
:
Table Call (TCALL) causes the CPU to jump to each
TCALL address, where it commences the execution of the
service routine. The Table Call service area spaces 2-byte
for every TCALL: 0FFC0H for TCALL15, 0FFC2H for
TCALL14, etc., as shown in Figure 8-7.
1
;TCALL ADDRESS AREA
The interrupt causes the CPU to jump to specific location,
where it commences the execution of the service routine.
The External interrupt 0, for example, is assigned to location 0FFFAH. The interrupt service locations spaces 2-byte
interval: 0FFF8H and 0FFF9H for External Interrupt 1,
0FFFAH and 0FFFBH for External Interrupt 0, etc.
Any area from 0FF00H to 0FFFFH, if it is not going to be
used, its service location is available as general purpose
Program Memory.
Address
0FFE0H
Page Call (PCALL) area contains subroutine program to
reduce program byte length by using 2 bytes PCALL instead of 3 bytes CALL instruction. If it is frequently called,
it is more useful to save program byte length.
;1BYTE INSTRUCTION
;INSTEAD OF 2 BYTES
;NORMAL CALL
Vector Area Memory
-
E2
-
E4
-
E6
-
E8
Watch Timer Interrupt Vector Area
EA
Serial I/O Interrupt Vector Area
EC
AD Converter Interrupt Vector Area
EE
Remocon Interrupt Vector Area
F0
External Interrupt 2 Vector Area
F2
Timer/Counter 1 Interrupt Vector Area
F4
Timer/Counter 0 Interrupt Vector Area
F6
External Interrupt 1 Vector Area
F8
External Interrupt 0 Vector Area
FA
Basic Interval Timer Interrupt Vector Area
FC
Key Scan Interrupt Vector Area
FE
RESET Vector Area
NOTE:
“-” means reserved area.
Figure 8-6 Interrupt Vector Area
JUNE 2001 Ver 1.0
21
GMS81C5108
Address
Address
Program Memory
0FFC0H
C1
TCALL 15
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
PCALL Area Memory
0FF00H
PCALL Area
(256 Bytes)
TCALL 14
TCALL 13
TCALL 12
TCALL 11
TCALL 10
TCALL 9
TCALL 8
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
0FFFFH
TCALL 7
TCALL 6
TCALL 5
TCALL 4
TCALL 3
TCALL 2
TCALL 1
TCALL 0 / BRK *
NOTE:
* means that the BRK software interrupt is using
same address with TCALL0.
Figure 8-7 PCALL and TCALL Memory Area
PCALL→
→ rel
TCALL→
→n
4F35
4A
PCALL 35H
TCALL 4
4A
4F
35
~
~
~
~
~
~
0D125H
~
~
NEXT
0FF00H
0FF35H
0FFFFH
01001010
➊
PC: 11111111 11010110
FH FH
D H 6H
➌
NEXT
0FF00H
0FFD6H
25
0FFD7H
D1
Reverse
➋
0FFFFH
22
JUNE 2001 Ver 1.0
GMS81C5108
Example: The usage software example of Vector address and the initialize part.
ORG
0FFE0H
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
NOT_USED
NOT_USED
NOT_USED
NOT_USED
WT_INT
SIO
AD_Con
Carrier_INT
INT2
TMR1_INT
TMR0_INT
INT1
INT0
BIT_INT
KEY_INT
RESET
ORG
0F000H
;
;
;
;
;
;
;
;
;
;
;
;
Watch Timer
Serial I/O
AD converter
Carrier
Int.2
Timer-1
Timer-0
Int.1
Int.0
BIT
Key Scan
Reset
;********************************************
;
MAIN
PROGRAM
*
;********************************************
;
RESET:
DI
;Disable All Interrupts
CLRG
LDX
#0
RAM_CLR: LDA
#0
;RAM Clear(!0000H->!00BFH)
STA
{X}+
CMPX
#0C0H
BNE
RAM_CLR
;
LDX
#0BFH
;Stack Pointer Initialize
TXSP
;
CALL
LCD_CLR
;Clear LCD display memory
;
LDM
R0, #0
;Normal Port 0
LDM
R0DR,#1000_0010B
;Normal Port Direction
LDM
R0PU,#1000_0010B
;Pull Up Selection Set
LDM
R0CR,#0000_0001B
;R0 port Open Drain control
:
:
LDM
SCMR,#1111_0000B
;System clock control
:
:
JUNE 2001 Ver 1.0
23
GMS81C5108
8.3 Data Memory
Figure 8-8 shows the internal Data Memory space available. Data Memory is divided into four groups, a user RAM,
control registers, Stack, and LCD memory.
Note that unoccupied addresses may not be implemented
on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect.
0000H
USER MEMORY
(Including STACK Area)
(192 Bytes)
Control Registers
The control registers are used by the CPU and Peripheral
function blocks for controlling the desired operation of the
device. Therefore these registers contain control and status
bits for the interrupt system, the timer/ counters, analog to
digital converters and I/O ports. The control registers are in
address range of 0C0H to 0FFH.
PAGE0
More detailed informations of each register are explained
in each peripheral section.
00BFH
00C0H
00FFH
0100H
0124H
Note: Write only registers can not be accessed by bit manipulation instruction. Do not use read-modify-write instruction. Use byte manipulation instruction.
PERIPHERAL CONTROL
REGISTERS
LCD DISPLAY
MEMORY
PAGE1
Example; To write at CKCTLR
LDM
Figure 8-8 Data Memory Map
CKCTLR,#05H ;Divide ratio ÷8
User Memory
The GMS81C5108 has 192 × 8 bits for the user memory
(RAM).
Stack Area
The stack provides the area where the return address is
saved before a jump is performed during the processing
routine at the execution of a subroutine call instruction or
the acceptance of an interrupt.
There are two page internal RAM. Page is selected by Gflag and RAM page selection register RPR. When G-flag
is cleared to “0”, always page 0 is selected regardless of
RPR value. If G-flag is set to “1”, page will be selected according to RPR value.
When returning from the processing routine, executing the
subroutine return instruction [RET] restores the contents of
the program counter from the stack; executing the interrupt
return instruction [RETI] restores the contents of the program counter and flags.
The save/restore locations in the stack are determined by
the stack pointed (SP). The SP is automatically decreased
after the saving, and increased before the restoring. This
means the value of the SP indicates the stack location
number for the next save. Refer to Figure 8-4 on page 20.
Page 0
RPR=0, G=0
RPR=1, G=1
Page 1
Page 0: 00~FFH
Page 1: 100~124H
LCD Display Memory
LCD display data area is handled in LCD section.
See "19.3 LCD Display Memory" on page 73.
Figure 8-9 RAM page configuration
24
JUNE 2001 Ver 1.0
GMS81C5108
Address
Register Name
Symbol
R/W
Initial Value
Addressing
Mode
Page
7 6 5 4 3 2 1 0
00C0
R0 port data register
R0
R/W
00000000
byte, bit1
32
00C1
R1 port data register
R1
R/W
00000000
byte, bit
32
00C2
R2 port data register
R2
R/W
- - - - 0000
byte, bit
33
00C3
R3 port data register
R3
R/W
- - - - 0000
byte, bit
33
32
00C8
R0 port I/O direction register
R0DR
W
00000000
byte2
00C9
R1 port I/O direction register
R1DR
W
00000000
byte
32
00CA
R2 port I/O direction register
R2DR
W
- - - - 0000
byte
33
00CB
R3 port I/O direction register
R3DR
W
- - - - 0000
byte
33
00D0
R0 port pull-up register
R0PU
W
00000000
byte
32
00D1
R1 port pull-up register
R1PU
W
00000000
byte
32
00D2
R2 port pull-up register
R2PU
W
- - - - 0000
byte
33
00D3
R3 port pull-up register
R3PU
W
- - - - 0000
byte
33
00D4
R0 port open drain control register
R0CR
W
00000000
byte
32
00D5
R1 port open drain control register
R1CR
W
00000000
byte
32
00D6
R2 port open drain control register
R2CR
W
- - - - 0000
byte
33
00D7
R3 port open drain control register
R3CR
W
- - - - 0000
byte
33
00D8
Ext. interrupt edge selection register
IESR
R/W
- - 000000
byte, bit
69
00D9
Port selection register
PMR
R/W
- 0 - 00000
byte, bit
32
00DA
Interrupt enable low register
IENL
R/W
- 0000 - - -
byte, bit
65
00DB
Interrupt enable high register
IENH
R/W
- 0000000
byte, bit
65
00DC
Interrupt request flag low register
IRQL
R/W
- 0000 - - -
byte, bit
65
00DD
Interrupt request flag high register
IRQH
R/W
- 0000000
byte, bit
65
00DE
Sleep mode register
SMR
R/W
- - - - - - - 0
byte, bit
39
00E0
Timer 0 mode register
TM0
R/W
- - 000000
byte, bit
45
T0
R
00000000
byte, bit
45
Timer 0 data register
TDR0
W
11111111
byte
45
Timer 0 input capture register
CDR0
R
00000000
byte, bit
45
Timer 1 mode register
TM1
R/W
00000000
byte, bit
45
Timer 1 data register
TDR1
W
11111111
byte
45
T1PPR
W
11111111
byte
45
T1
R
00000000
byte, bit
45
Timer 1 input capture register
CDR1
R
00000000
byte, bit
45
PWM0 pulse duty register
T1PDR
R/W
00000000
byte, bit
45
PWMHR
W
- - - - 0000
byte
45
Timer 0 counter register
00E1
00E2
00E3
PWM0 pulse period register
Timer 1 counter register
00E4
00E5
PWM0 high register
00EC
A/D converter mode register
ADMR
R/W
- 0 - - 0001
byte, bit
58
00ED
A/D converter data register
ADDR
R
x x x x x x x x
byte, bit
58
Table 8-1 Control Registers
JUNE 2001 Ver 1.0
25
GMS81C5108
Address
Register Name
Symbol
R/W
Initial Value
Addressing
Mode
Page
7 6 5 4 3 2 1 0
00EF
Watch timer mode register
WTMR
R/W
- 0000000
byte, bit
56
00F0
Key scan mode register
KSMR
R/W
00000000
byte, bit
70
00F1
LCD control register
LCR
R/W
00000000
byte, bit
72
00F3
RAM paging register
RPR
R/W
- - - - - - 00
byte, bit
73
Basic interval timer register
BITR
R
00000000
byte, bit
43
CKCTLR
W
- - - - 0111
byte
43
SCMR
R/W
00000000
byte, bit
34
00F4
Clock control register
00F5
System clock mode register
00F6
Remocon mode register
RMR
R/W
- 0000000
byte, bit
76
00F7
Carrier frequency high selection
CFHS
W
- - 111111
byte
76
00F8
Carrier frequency low selection
CFLS
W
- - 111111
byte
76
00F9
Remocon data high register
RDHR
W
11111111
byte
76
Remocon data low register
RDLR
W
11111111
byte
76
Remocon data counter
RDC
R
00000000
byte, bit
76
RODR
R/W
- - - - - - - 0
byte, bit
76
00FA
00FB
Remocon output data register
00FC
Remocon output buffer
ROB
R/W
- - - - - - - 0
byte, bit
76
00FD
Buzzer data register
BDR
W
00000000
byte
60
00FE
Serial I/O mode register
SIOM
R/W
00000001
byte, bit
62
00FF
Serial I/O data register
SIOD
R/W
x x x x x x x x
byte, bit
62
Table 8-1 Control Registers
1. “byte”, “bit” means that register can be addressed by not only bit but byte manipulation instruction.
2. “byte” means that register can be addressed by only byte manipulation instruction. On the other hand, do not use any read-modify-write
instruction such as bit manipulation.
26
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GMS81C5108
8.4 Addressing Mode
The GMS81C5108 uses six addressing modes;
(3) Direct Page Addressing → dp
• Register addressing
In this mode, a address is specified within direct page.
• Immediate addressing
Example; G=0
• Direct page addressing
C535
LDA
;A ←RAM[35H]
35H
• Absolute addressing
• Indexed addressing
35H
• Register-indirect addressing
data
➋
~
~
(1) Register Addressing
Register addressing accesses the A, X, Y, C and PSW.
~
~
0E550H
C5
0E551H
35
➊
data → A
(2) Immediate Addressing → #imm
In this mode, second byte (operand) is accessed as a data
immediately.
(4) Absolute Addressing → !abs
Example:
0435
ADC
#35H
MEMORY
04
A+35H+C → A
35
Absolute addressing sets corresponding memory data to
Data, i.e. second byte (Operand I) of command becomes
lower level address and third byte (Operand II) becomes
upper level address.
With 3 bytes command, it is possible to access to whole
memory area.
ADC, AND, CMP, CMPX, CMPY, EOR, LDA, LDX,
LDY, OR, SBC, STA, STX, STY
Example;
0735F0
ADC
;A ←ROM[0F035H]
!0F035H
When G-flag is 1, then RAM address is defined by 16-bit
address which is composed of 8-bit RAM paging register
(RPR) and 8-bit immediate data.
Example: G=1, RPR=01H
E45535
LDM
data
0F035H
~
~
0F100H
➊
0F100H
data ← 55H
data
0135H
➋
35H,#55H
~
~
~
~
~
~
➊
A+data+C → A
07
0F101H
35
0F102H
F0
address: 0F035
➋
E4
0F101H
55
0F102H
35
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27
GMS81C5108
The operation within data memory (RAM)
ASL, BIT, DEC, INC, LSR, ROL, ROR
Example; Addressing accesses the address 0135H regardless of G-flag and RPR.
981501
INC
;A ←ROM[115H]
!0115H
X indexed direct page, auto increment→
→ {X}+
In this mode, a address is specified within direct page by
the X register and the content of X is increased by 1.
LDA, STA
Example; G=0, X=35H
DB
data
115H
~
~
LDA
{X}+
➌
~
~
➋
35H
data+1 → data
~
~
0F100H
98
➊
0F101H
15
address: 0115
0F102H
01
➋
data
~
~
data → A
➊
36H → X
DB
(5) Indexed Addressing
X indexed direct page (no offset) → {X}
X indexed direct page (8 bit offset) → dp+X
In this mode, a address is specified by the X register.
This address value is the second byte (Operand) of command plus the data of -register. And it assigns the memory in Direct page.
ADC, AND, CMP, EOR, LDA, OR, SBC, STA, XMA
Example; X=15H, G=1, RPR=01H
D4
LDA
{X}
;ACC←RAM[X].
ADC, AND, CMP, EOR, LDA, LDY, OR, SBC, STA
STY, XMA, ASL, DEC, INC, LSR, ROL, ROR
Example; G=0, X=0F5H
C645
115H
data
~
~
0E550H
LDA
45H+X
➋
~
~
data → A
➊
3AH
data
➌
D4
~
~
28
➋
~
~
0E550H
C6
0E551H
45
data → A
➊
45H+0F5H=13AH
JUNE 2001 Ver 1.0
GMS81C5108
Y indexed direct page (8 bit offset) → dp+Y
3F35
JMP
[35H]
This address value is the second byte (Operand) of command plus the data of Y-register, which assigns Memory in
Direct page.
This is same with above (2). Use Y register instead of X.
35H
0A
36H
E3
Y indexed absolute → !abs+Y
~
~
Sets the value of 16-bit absolute address plus Y-register
data as Memory. This addressing mode can specify memory in whole area.
Example; Y=55H
D500FA
LDA
~
~
0FA00H
D5
0F101H
00
0F102H
FA
~
~
➋ jump to address 0E30AH
NEXT
~
~
➊
3F
35
!0FA00H+Y
0F100H
0FA55H
0E30AH
~
~
➊
0FA00H+55H=0FA55H
~
~
➋
data
➌
data → A
X indexed indirect → [dp+X]
Processes memory data as Data, assigned by 16-bit pair
memory which is determined by pair data
[dp+X+1][dp+X] Operand plusX-register data in Direct
page.
ADC, AND, CMP, EOR, LDA, OR, SBC, STA
Example; G=0, X=10H
1625
ADC
[25H+X]
(6) Indirect Addressing
Direct page indirect → [dp]
Assigns data address to use for accomplishing command
which sets memory data (or pair memory) by Operand.
Also index can be used with Index register X,Y.
JMP, CALL
35H
05
36H
E0
0E005H
~
~ ➋
~
~
0E005H
~
~
Example; G=0
0FA00H
~
~
16
25
JUNE 2001 Ver 1.0
➊ 25 + X(10) = 35H
data
➌ A + data + C → A
29
GMS81C5108
Y indexed indirect → [dp]+Y
Absolute indirect → [!abs]
Processes memory data as Data, assigned by the data
[dp+1][dp] of 16-bit pair memory paired by Operand in Direct pageplus Y-register data.
The program jumps to address specified by 16-bit absolute
address.
ADC, AND, CMP, EOR, LDA, OR, SBC, STA
Example; G=0, Y=10H
1725
ADC
JMP
Example; G=0
1F25E0
JMP
[!0E025H]
[25H]+Y
PROGRAM MEMORY
25H
26H
05
0E025H
25
E0
0E026H
E7
~
~
0E015H
~
~
0FA00H
~
~
➊
0E725H
~
~
0FA00H
17
➌ A + data + C → A
➋
jump to
address 0E725H
NEXT
~
~
~
~
25
30
0E005H + Y(10) = 0E015H
➊
data
~
~
➋
~
~
1F
25
E0
JUNE 2001 Ver 1.0
GMS81C5108
9. I/O PORTS
The GMS81C5108 has seven ports (R0, R1, R2 and R3),
and LCD segment port (SEG0~SEG36), and LCD common port (COM0~COM3).
These ports pins may be multiplexed with an alternate
function for the peripheral features on the device.
9.1 Registers for Port
Port Data Registers
The Port Data Registers (R0, R1, R2, R3) are represented
as a D-Type flip-flop, which will clock in a value from the
internal bus in response to a “write to data register” signal
from the CPU. The Q output of the flip-flop is placed on
the internal bus in response to a “read data register” signal
from the CPU. The level of the port pin itself is placed on
the internal bus in response to “read data register” signal
from the CPU. Some instructions that read a port activating
the “read register” signal, and others activating the “read
pin” signal.
Port Direction Registers
All pins have data direction registers which can define
these ports as output or input. A “1” in the port direction
register configure the corresponding port pin as output.
Conversely, write “0” to the corresponding bit to specify it
as input pin. For example, to use the even numbered bit of
R0 as output ports and the odd numbered bits as input
ports, write “55H” to address 0C8H (R0 port direction register) during initial setting as shown in Figure 9-1.
All the port direction registers in the GMS81C5108 have 0
written to them by reset function. On the other hand, its initial status is input.
pull-up port. It is connected or disconnected by Pull-up
Control register (RnPU). The value of that resistor is typically 100kΩ. Refer to DC characteristics for more details.
When a port is used as key input, input logic is firmly either low or high, therefore external pull-down or pull-up
resisters are required practically. The GMS81C5108 has
internal pull-up, it can be logic high by pull-up that can be
able to configure either connect or disconnect individually
by pull-up control registers RnPU.
When ports are configured as inputs and pull-up resistor is
selected by software, they are pulled to high.
VDD
VDD
PULL-UP RESISTOR
PORT PIN
Pull-up control bit
0: Disconnect
1: Connect
GND
Figure 9-2 Pull-up Port Structure
WRITE “55H” TO PORT R0 DIRECTION REGISTER
0C0H
R0 DATA
0C1H
R1 DATA
~
~
0C8H
0C9H
0 1 0 1 0 1 0 1
7 6 5 4 3 2 1 0
Open drain port Registers
BIT
~
~
R0 DIRECTION
I O
R1 DIRECTION
7 6 5 4 3 2 1 0
I
O
I
O
I
O PORT
The R0, R1, R2 and R3 ports have open drain port resistors
R0CR~R3CR.
Figure 9-3 shows an open drain port configuration by control register. It is selected as either push-pull port or open-drain port by
R0CR, R1CR, R2CR and R3CR.
I : INPUT PORT
O : OUTPUT PORT
Figure 9-1 Example of port I/O assignment
Pull-up Control Registers
The R0, R1,R2 and R3 ports have internal pull-up resistors. Figure 9-2 shows a functional diagram of a typical
JUNE 2001 Ver 1.0
PORT PIN
GND
Open drain port selection bit
0: Push-pull
1: Open drain
Figure 9-3 Open-drain Port Structure
31
GMS81C5108
9.2 I/O Ports Configuration
R0 Ports
.
R0 is an 8-bit CMOS bidirectional I/O port (address
0C0H). Each I/O pin can independently used as an input or
an output through the R0DR register (address 0C8 H).
R0 has internal pull-ups that is independently connected or
disconnected by R0PU. The control registers for R0 are
shown below.
ADDRESS : 0C0H
RESET VALUE : 00H
R0 Data Register
R0
R07
R06
R05
R04
R03
R02
R01
R0DR
Port Direction
0: Input
1: Output
R0 Pull-up
Selection Register
R00
R01
R02
R03
R04
R31
INT0 (External Interrupt 0)
INT1 (External Interrupt 1)
INT2 (External Interrupt 2)
EC0 (Timer0 Event Input)
BUZ (Buzzer Output)
PWM (PWM Output)
R1 Ports
R00
ADDRESS : 0C8H
RESET VALUE : 00H
R0 Direction Register
Alternate Function
Port Pin
ADDRESS :0D0H
RESET VALUE : 00H
R1 is an 8-bit CMOS bidirectional I/O port (address
0C1H). Each I/O pin can independently used as an input or
an output through the R1DR register (address 0C9H).
R1 has internal pull-ups that is independently connected or
disconnected by register R1PU. If the key scan function is
used, these pin can input the key switch signal without external pull-up registers. For more details refer to "18. KEY
SCAN" on page 70.
The control registers for R1 are shown below.
R0PU
Pull-up select
0: Without pull-up
1: With pull-up
ADDRESS : 0C1H
RESET VALUE : 00H
R1 Data Register
R0 Open Drain
Selection Register
ADDRESS :0D4H
RESET VALUE : 00H
R1
R17
R16
R15
R14
R0CR
Open Drain select
0: No Open Drain
1: Open Drain
-
PWMO
-
BUZ
EC0
INT2
INT1
INT0
PWMO (PWM Output)
0: R31 Port
1: PWM
BUZ (Buzzer Output)
0: R04 Port
1: BUZ
EC0 (Timer0 Event Input)
0: R03 Port
1: EC0
INT2 (External Interrupt)
0: R02 Port
1: INT2
INT1 (External Interrupt)
0: R01 Port
1: INT1
INT0 (External Interrupt)
0: R00 Port
1: INT0
R12
R11
R10
ADDRESS : 0C9H
RESET VALUE : 00H
R1DR
Port Direction
0: Input
1: Output
ADDRESS :0D9H
RESET VALUE : -0-00000B
Port Mode Register
PMR
R1 Direction Register
R13
R1 Pull-up
Selection Register
ADDRESS : 0D1H
RESET VALUE : 00H
R1PU
Pull-up select
0: Without pull-up
1: With pull-up
R1 Open Drain
Selection Register
ADDRESS :0D5H
RESET VALUE : 00H
R1CR
In addition, Port R0 and R3 are multiplexed with various
special features. The control register PMR (address 0D9H)
controls the selection of alternate function. After reset, this
value is “0”, port may be used as normal I/O port.
To use alternate function such as External Interrupt rather
than normal I/O, write “1” in the corresponding bit of
PMR0.
32
Open Drain select
0: No Open Drain
1: Open Drain
KEY SCAN Mode Register
ADDRESS :0F0H
RESET VALUE : 00H
KSMR
KEY Input select
0: Port selection
1: KS selection
JUNE 2001 Ver 1.0
GMS81C5108
Port R1 is multiplexed with various special features.The
control registers controls the selection of alternate function. After reset, this value is “0”, port may be used as normal I/O port. The way to select alternate function such as
comparator input or buzzer will be shown in each peripheral section.
In addition, R1 port is used as key scan function which operate with normal input port.
Input or output is configured automatically by each function register (KSMR) regardless of R1DR.
R3 Port
R3 is a 4-bit CMOS bidirectional I/O port (address 0C3H).
Each I/O pin can independently used as an input or an output through the R3DR register (address 0CBH).
R3
R2 is a 4-bit CMOS bidirectional I/O port (address 0C2H).
Each I/O pin can independently used as an input or an output through the R2DR register (address 0CAH).
R2 has internal pull-ups that is independently connected or
disconnected by R2PU (address 0D2 H). The control registers for R2 are shown as below.
R3DR
-
-
-
-
-
-
-
R23
R22
R21
R20
ADDRESS : 0CAH
RESET VALUE : ----0000B
R2 Direction Register
-
-
-
-
-
R2 Open Drain
Selection Register
-
R31
R30
-
-
-
ADDRESS : 0D3H
RESET VALUE : ----0000B
-
Pull-up select
0: Without pull-up
1: With pull-up
R3 Open Drain
Selection Register
R3CR
-
-
ADDRESS : 0D7H
RESET VALUE : ----0000B
-
Pull-up select
0: No Open Drain
1: Open Drain
SEG0~SEG36
ADDRESS : 0D2H
RESET VALUE : ----0000B
Pull-up select
0: Without pull-up
1: With pull-up
-
-
R32
-
R2 Pull-up
Selection Register
-
-
R33
ADDRESS : 0CBH
RESET VALUE : ----0000B
R3 Pull-up
Selection Register
Port Direction
0: Input
1: Output
R2CR
-
ADDRESS: 0C2H
RESET VALUE: ----0000B
R2 Data Register
R2PU
-
Port Direction
0: Input
1: Output
R3PU
R2DR
-
R3 Direction Register
R2 Port
R2
ADDRESS: 0C3H
RESET VALUE: ----0000B
R3 Data Register
ADDRESS : 0D6H
RESET VALUE : ----0000B
-
-
Segment signal output pins for the LCD display. See "19.
LCD DRIVER" on page 71 for details.
COM0~COM3
Common signal output pins for the LCD display. See "19.
LCD DRIVER" on page 71 for details.
SEG34~SEG36 and COM1~COM3 are selected by LCDD
of the LCR register.
Pull-up select
0: No Open Drain
1: Open Drain
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33
GMS81C5108
10. CLOCK GENERATOR
As shown in Figure 10-1, the clock generator produces the
basic clock pulses which provide the system clock to be
supplied to the CPU and the peripheral hardware. It contains two oscillators: a main-frequency clock oscillator and
a sub-frequency clock oscillator. Power consumption can
be reduced by switching them to the low power operation
frequency clock can be easily obtained by attaching a resonator between the XIN and XOUT pin and the SXIN and
SXOUT pin, respectively. The system clock can also be obtained from the external oscillator.
Instruction cycle time
CPU clock
fMAIN = 4MHz
fSUB = 32.768kHz
÷2
0.5 us
61 us
÷8
2.0 us
244 us
÷ 16
4.0 us
488 us
÷ 64
16.0 us
1953 us
To the peripheral block, the clock among the not-divided
original clocks, divided by 2, 4,..., up to 1024 can be provided. Peripheral clock is enabled or disabled by STOP instruction. The peripheral clock is controlled by clock
control register (CKCTLR). See "11. BASIC INTERVAL
TIMER" on page 43 for details.
The clock generator produces the system clocks forming
clock pulse, which are supplied to the CPU and the peripheral hardware. The internal system clock can be selected
by bit2, and bit3 of the system clock mode register (SCMR). The registers are shown in Figure 10-2.
SYCC<1>
** Clock is frozen by STOP or SLEEP[SMR.0] Instruction.
** Clock is released
1) by BIT overflow when previos state has been STOP mode.
2) by interrupts when previos state has been SLEEP mode.
SYCC<0>
SLEEP Mode
STOP Mode
SCS[1:0]
select clock
XIN
0
SXIN
1
PRESCALER
OSC Stop
÷2
÷8
Internal system clock
MUX
÷16
÷64
PRESCALER
PS0
÷1
PS1
÷2
PS2
÷4
PS3
÷8
PS4
÷16
PS5
÷32
PS6
÷64
PS7
÷128
PS8
÷256
PS9
PS10
÷512 ÷1024
Peripheral clock
fEX (Hz)
PS0
PS1
PS2
PS3
PS4
PS5
PS6
PS7
PS8
PS9
PS10
Frequency
4M
2M
1M
500K
250K
125K
62.5K
31.25K
15.63K
7.183K
3.906K
period
250n
500n
1u
2u
4u
8u
16u
32u
64u
128u
256u
4M
Figure 10-1 Block Diagram of Clock Generator
34
JUNE 2001 Ver 1.0
GMS81C5108
The system clock is decided by bit1 of the system clock
mode register, SCMR. In selection Sub clock, to oscillate
or stop the Main clock is decided by bit0 of SCMR.
On the initial reset, internal system clock is PS1 which is
the fastest and other clock can be provided by bit2 and bit3
of SCMR.
SCMR (System Clock Mode Register)
MSB
R/W
R/W
R/W
R
R/W
R/W
R/W
LSB
R/W
ADDRESS: 0F5H
INITIAL VALUE: 00H
SYCC[1:0] (System clock control)
00: main clock on
01: main clock on
10: sub clock on (main clock on)
11: sub clock on (main clock off)
SVD[1:0] (SVD Flag)
SVD0 : set at VDD=2.2V
SVD1 : set at VDD=1.7V
SCS[1:0] (System clock source select)
00: fMAIN÷2 or fSUB÷2
01: fMAIN÷8 or fSUB÷8
10: fMAIN÷16 or fSUB÷16
11: fMAIN÷64 or fSUB÷64
SVRT (System Reset Control by SVD1 Bit)
0 : System reset by SVD1 Flag
1 : Don’t system reset by SVD1 Flag (Freeze)
SVEN (SVD Operation Enable Bit)
0 : SVD Operation Enable
1 : SVD Operation Disable
* The values of 1.7V and 2.2V could be changed by ±0.2V according to the process of work.
Figure 10-2 SCMR : System Clock Control Registers
JUNE 2001 Ver 1.0
35
GMS81C5108
10.1 Operation Mode
The system clock controller starts or stops the main-frequency clock oscillator and switches between the sub frequency clock. The operating mode is generally divided
into the main active mode and the sub active mode, which
are controlled by System clock mode register (SCMR).
Figure 10-3 shows the operating mode transition diagram.
Sub Active mode
System clock control is performed by the system clock
mode register, SCMR. During reset, this register is initialized to “0” so that the main-clock operating mode is selected.
SLEEP mode
This mode is low-frequency operating mode
In this mode, the CPU and the peripheral hardware clock
are provided by low-frequency clock oscillation, so power
consumption can be reduced.
In this mode, the CPU clock stops while peripherals and
the oscillation source continue to operate normally.
STOP mode
Main Active mode
In this mode, the system operations are all stopped, holding
the internal states valid immediately before the stop at the
low power consumption level.
This mode is fast-frequency operating mode.
The CPU and the peripheral hardwares are operated on the
high-frequency clock. At reset release, this mode is invoked.
Main : Oscillation
Sub : Oscillation
System Clock : Sub
Main : Oscillation
Sub : Oscillation
System Clock : Main
SET1 SCMR.1
Main Active
Mode
Sub Active
Mode 1
* Note1 : Stop released by
Reset, Key Scan
Watch Timer interrupt
Timer interrupt (event counter)
SIO (External clock)
External interrupt
R
M
O
P
ST
* Note1 / * Note2
STOP / SET1 SMR.0
Main : Stop or Oscillation (case of **1)
Sub : Oscillation
System Clock : Stop
* Note3 : this is sequential
1) CLR1 SCMR.0
2) Oscillation stabilation time (more than 65ms)
3) CLR1 SCMR.1
- Sub clock cannot be stopped by STOP instruction.
H
03
,#
Mode
* Note2 : Sleep released by
Reset, Key Scan
All interrupts
SC
/(
**
1)
SE
T1
SM
R
.0
STOP / SET1 SMR.0
M
LD
Stop / Sleep
CLR1 SCMR.0
SET1 SCMR.0
* Note1 / * Note2
*N
ot
e1
e3
ot
*N
/N
ot
e2
CLR1 SCMR.1
Sub Active
Mode 2
Main : Stop
Sub : Oscillation
System Clock : Sub
Figure 10-3 Operating Mode
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JUNE 2001 Ver 1.0
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10.2 Operation Mode Switching
In the Main active mode, only the high-frequency clock oscillator is used.
In the Sub active mode, the low-frequency clock oscillation is used, so the low power voltage operation or the low
power consumption operation can be enabled. Instruction
execution does not stop during the change of operation
mode. In this case, some peripheral hardware capabilities
may be affected. For details, refer to the description of the
relevant operation.
The following describes the switching between the Main
active mode and the Sub active mode. During reset, the
system clock mode register is initialized at the Main active
mode. It must be set to the Sub active mode for reducing
the power consumption.
:
:
:
;about 65ms software delay
DELAY: LDA
#0
DELAY0: INC
A
CMP
#85H
BCC
DELAY0
RET
Shifting from the Normal operation to the SLEEP
mode
Switching from Main active to Sub active
By setting bit 0 of SMR, the CPU clock stops and the
SLEEP mode is invoked. The CPU stops while other peripherals are operate normally.
First, write “02H” into lower 2 bits of SCMR to switch the
main system clock to the sub-frequency clock.
Next, write “03H” to turn off main frequency oscillation.
The way of release from this mode is RESET and all available interrupts.
Example:
For more detail, See " SLEEP Mode" on page 39
:
:
:
LDM
LDM
:
:
Shifting from the Normal operation to the STOP
mode
SCMR,#02H
SCMR,#03H
;Switch to sub active
;Turn off main clock
Returning from Sub active to Main active
First, write “02H” into lower 2 bits of the SCMR to turn on
the main-frequency oscillation. This time, the stabilization
(warm-up) time needs to be taken by the software delay
routine. Sub active mode can also be released by setting the
RESET pin to low, which immediately performs the reset
operation. After reset, the GMS81C5108 is placed in Main
active mode.
Example:
:
:
:
LDM SCMR,#02H
CALL DELAY
LDM SCMR,#0
JUNE 2001 Ver 1.0
By executing STOP instruction, the main-frequency clock
oscillation stops and the STOP mode is invoked. But subfrequency clock oscillation is operated continuously.
After the STOP operation is released by reset, the operation mode is changed to Main active mode.
The methods of release are RESET, Key scan interrupt,
Watch Timer interrupt, Timer/Event counter1 (EC0 pin),
SIO (External clock) and External Interrupt.
For more details, see " STOP Mode" on page 40.
Note: In the STOP and SLOW operating modes, the power
consumption by the oscillator and the internal hardware is
reduced. However, the power for the pin interface (depending on external circuitry and program) is not directly associated with the low-power consumption operation. This must
be considered in system design as well as interface circuit
design.
;Turn on main-clock
;Wait until stable
;Move to main active
37
GMS81C5108
~
~
Sub freq. clock
(SXIN pin)
~
~
~
~
Main freq. clock
(XIN pin)
~
~
~
~
Operation clock
Main-clock operation
Sub-clock operation
Changed to the Sub-clock
SCMR ← XXXX XX10B
Turn off main clock
SCMR ← XXXX XX11B
(a) Main active mode → Sub active mode
~
~
~
~
Main freq. clock
(XIN pin)
Stabilizing Time > 60ms
~
~
Sub freq. clock
(SXIN pin)
Operation clock
~
~
Sub-clock operation
Changed to the Transition
SCMR ← XXXX XX10B
Main-clock operation
Changed to the Main-clock
SCMR ← XXXX XX00B
or XXXX XX01B
(b) Sub active mode → Main active mode
Figure 10-4 System Clock Switching Timing
38
JUNE 2001 Ver 1.0
GMS81C5108
10.3 Power Saving Operation
GMS81C5108 has 2 power-saving mode. In power-saving
mode, power consumption is reduced considerably that in
Battery operation Battery life can be extended a lot.
It is released by RESET or interrupt. To be released by interrupt, interrupt should be enabled before Sleep mode.
Sleep mode is entered by setting bit 0 of Sleep Mode Register (SMR), and STOP Mode is entered by STOP instruction.
ADDRESS : 0DEH
RESET VALUE : -------0B
Sleep Mode Register
-
SMR
-
-
-
-
-
-
SLEEP Mode
0: Release Sleep Mode
1: Enter Sleep Mode
In this mode, the internal oscillation circuits remain active.
Oscillation continues and peripherals are operate normally
but CPU stops. Movement of all Peripherals is shown in
Table 10-1. Sleep mode is entered by setting bit 0 of SMR
(address 0DEH).
~
~
Oscillator
(XIN or SXIN pin)
Figure 10-5 SLEEP Mode Register
~
~
Internal CPU Clock
Interrupt
Release
Set bit 0 of SMR
Normal Operation
Stand-by Mode
Normal Operation
Figure 10-6 Sleep Mode Release Timing by External Interrupt
.
~
~
~
~
Oscillator
(XIN or SXIN pin)
Internal CPU Clock
Release
Set bit 0 of SMR
0
1
2
Clear & Start
Normal Operation
Stand-by Mode
~
~
~ ~
~
~ ~
~
BIT Counter
~ ~
~
~
~
~
RESET
FE
FF
0
1
2
tST = 62.5ms
Normal Operation
at 4.19MHz by hardware
tST =
1
fMAIN ÷1024
x 256
Figure 10-7 SLEEP Mode Release Timing by RESET pin
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GMS81C5108
STOP Mode
ing program execution. In Stop mode, the on-chip mainfrequency oscillator, system clock, and peripheral clock
are stopped (Watch timer clock is oscillating continuously:. With the clock frozen, all functions are stopped, but the
on-chip RAM and Control registers are held. The port pins
output the values held by their respective port data register,
the port direction registers. The status of peripherals during
Stop mode is shown below.
For applications where power consumption is a critical
factor, device provides STOP mode for reducing power
consumption.
Start The Stop Operation
The STOP mode can be entered by STOP instruction durPeripheral
STOP Mode
Sleep Mode
CPU
All CPU operations are disabled
All CPU operations are disabled
RAM
Retain
Retain
Operates continuously
Operates continuously
Halted
Operates continuously
Halted (Only when the Event counter mode
is enabled, Timer 0,1 operates normally)
Timer/Event counter 0,1 operates continuously
Operates continuously
Operates continuously
Active
Active
Main-oscillation
Stop (XIN=L, XOUT=L)
Oscillation1
Sub-oscillation
Oscillation
Oscillation
I/O ports
Retain
Retain
Control Registers
Retain
Retain
Release method
by RESET, Key Scan interrupt,
SIO interrupt, Watch Timer interrupt,
Timer interrupt (EC0), and External interrupt
by RESET, All interrupts
LCD driver
Basic Interval Timer
Timer/Event counter 0,1
Watch Timer
Key Scan
Table 10-1 Peripheral Operation during Power Saving Mode
1. refer to the Table 10-2
Operating
Clock source
Main
Operating Mode
Main
Sleep Mode
Sub
Operating Mode
Sub
Sleep Mode
Stop Mode
Main Clock
Oscillation
Oscillation
SCMR<1:0>
00,01,10 → Oscillation
11 → Stop
SCMR<1:0>
00,01,10 → Oscillation
11 → Stop
Stop
Sub Clock
Oscillation
Oscillation
Oscillation
Oscillation
Oscillation
System Clock
Active
Stop
Active
Stop
Stop
Peri. Clock
Active
Active
Active
Active
Stop
Table 10-2 Clock Operation of STOP and SLEEP mode
Note: Since the XIN pin is connected internally to GND to
avoid current leakage due to the crystal oscillator in STOP
mode, do not use STOP instruction when an external clock
is used as the main system clock.
In the Stop mode of operation, VDD can be reduced to minimize power consumption. Be careful, however, that VDD
40
is not reduced before the Stop mode is invoked, and that
VDD is restored to its normal operating level before the
Stop mode is terminated.
The reset should not be activated before VDD is restored to
its normal operating level, and must be held active long
enough to allow the oscillator to restart and stabilize.
And after STOP instruction, at least two or more NOP instruction should be written as shown in example below.
JUNE 2001 Ver 1.0
GMS81C5108
Example)
:
LDM
STOP
NOP
NOP
:
To release STOP mode, corresponding interrupt should be
enabled before STOP mode.
Specially as a clock source of Timer/Event counter, EC0
pin can release it by Timer/Event counter Interrupt request
CKCTLR,#0000_1111B
The Interval Timer Register CKCTLR should be initialized by software in order that oscillation stabilization time
should be longer than 20ms before STOP mode.
Reset redefines all the control registers but does not change
the on-chip RAM. External interrupts allow both on-chip
RAM and Control registers to retain their values.
Release the STOP mode
Start-up is performed to acquire the time for stabilizing oscillation. During the start-up, the internal operations are all
stopped.
The exit from STOP mode is using hardware reset or external interrupt, watch timer, SIO interrupt, key scan or timer
interrupt (EC0).
~ ~
~
~
~ ~
~
~
Oscillator
(XIN pin)
~
~
Internal Clock
~
~
STOP Instruction
Executed
n+1 n+2
n+3
1
0
~
~
~ ~
n
~ ~
~
~
BIT Counter
~
~
External Interrupt
FE
FF
0
1
2
Clear
Normal Operation
Stop Operation
Normal Operation
tST > 20ms
by software
Before executing Stop instruction, Basic Interval Timer must be set
properly by software to get stabilization time which is longer than 20ms.
Figure 10-8 STOP Mode Release Timing by External Interrupt
STOP Instruction
Executed
n+3
n+4
1
0
~
~
~ ~
n+1 n+2
~ ~
~
~
n
~ ~
~
~
~
~
BIT Counter
~
~
Internal Clock
RESET
~ ~
~
~
~
~
Oscillator
(XIN pin)
FE
FF
0
1
2
Clear
Normal Operation
Stop Operation
Normal Operation
tST > 62.5ms
at 4.19MHz by hardware
tST =
1
fMAIN ÷1024
x 256
Figure 10-9 STOP Mode Release Timing by RESET
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GMS81C5108
Minimizing Current Consumption
The Stop mode is designed to reduce power consumption.
To minimize current drawn during Stop mode, the user
should turn-off output drivers that are sourcing or sinking
current, if it is practical.
Note: In the STOP operation, the power dissipation associated with the oscillator and the internal hardware is lowered; however, the power dissipation associated with the
pin interface (depending on the external circuitry and program) is not directly determined by the hardware operation
of the STOP feature. This point should be little current flows
when the input level is stable at the power voltage level
(VDD/VSS); however, when the input level becomes higher
than the power voltage level (by approximately 0.3V), a current begins to flow. Therefore, if cutting off the output transistor at an I/O port puts the pin signal into the highimpedance state, a current flow across the ports input transistor, requiring it to fix the level by pull-up or other means.
It should be set properly that current flow through port
doesn't exist.
First consider the setting to input mode. Be sure that there
is no current flow after considering its relationship with
external circuit. In input mode, the pin impedance viewing
from external MCU is very high that the current doesn’t
flow.
But input voltage level should be VSS or VDD. Be careful
that if unspecified voltage, i.e. if unfirmed voltage level
(not VSSor VDD) is applied to input pin, there can be little
current (max. 1mA at around 2V) flow.
If it is not appropriate to set as an input mode, then set to
output mode considering there is no current flow. Setting
to High or Low is decided considering its relationship with
external circuit. For example, if there is external pull-up resistor then it is set to output mode, i.e. to High, and if there
is external pull-saving register, it is set to low.
VDD
INPUT PIN
INPUT PIN
VDD
VDD
internal
pull-up
VDD
i=0
OPEN
O
i
O
i
GND
Very weak current flows
VDD
X
X
i=0
O
OPEN
Weak pull-up current flows
GND
O
When port is configured as an input, input level should
be closed to 0V or VDD to avoid power consumption.
Figure 10-10 Application Example of Unused Input Port
OUTPUT PIN
OUTPUT PIN
VDD
ON
OPEN
OFF
ON
OFF
ON
O
OFF
i
VDD
GND
VDD
L
L
OFF
ON
i
GND
i=0
GND
ON
X
OFF
X
O
O
In the left case, Tr. base current flows from port to GND.
To avoid power consumption, there should be low output
to the port.
In the left case, much current flows from port to GND.
Figure 10-11 Application Example of Unused Output Port
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JUNE 2001 Ver 1.0
GMS81C5108
11. BASIC INTERVAL TIMER
The GMS81C5108 has one 8-bit Basic Interval Timer that
is free-run and can not stop. Block diagram is shown in
Figure 11-1.
interrupt to be generated. The Basic Interval Timer is controlled by the clock control register (CKCTLR) shown in
Figure 11-2.
The Basic Interval Timer Register (BITR) is increased every internal count pulse which is divided by prescaler.
Since prescaler has divided ratio by 8 to 1024, the count
rate is 1/8 to 1/1024 of the oscillator frequency. After reset,
the BCK bits are all set, so the longest oscillation stabilization time is obtained.
Source clock can be selected by lower 3 bits of CKCTLR.
When write “1” to bit BCL of CKCTLR, BITR register is
cleared to “0” and restart to count up. The bit BCL becomes “0” automatically after one machine cycle by hardware.
BITR and CKCTLR are located at same address, and address 0F4H is read as a BITR, and written to CKCTLR.
It also provides a Basic interval timer interrupt (BITF).
The count overflow of BITR from FFH to 00H causes the
fMAIN÷23
fMAIN÷24
fMAIN÷25
fMAIN÷26
fMAIN÷27
fMAIN÷28
or fSUB÷23
or fSUB÷24
or fSUB÷25
or fSUB÷26
or fSUB÷27
or fSUB÷28
MUX
overflow
BITF
BITR
Basic Interval Timer Interrupt
[0F4H]
fMAIN÷29 or fSUB÷29
fMAIN÷210 or fSUB÷210
clear
Select Input clock
BCK<2:0>
fMAIN: main-clock frequency
fSUB: sub-clock frequency
8-bit up-counter
source
clock
3
BCL
CKCTLR
[0F4H]
Basic Interval Timer
clock control register
Internal bus line
Figure 11-1 Block Diagram of Basic Interval Timer
Source clock
BCK
<2:0>
000
001
010
011
100
101
110
111
Interrupt (overflow) Period
SCM R[1:0]=
00 or 01
SCM R[1:0]=
10 or 11
At fMAIN=4MHz
fMAIN÷23
fMAIN÷24
fMAIN÷25
fMAIN÷26
fMAIN÷27
fMAIN÷28
fMAIN÷29
fMAIN÷210
fSUB÷23
fSUB÷24
fSUB÷25
fSUB÷26
fSUB÷27
fSUB÷28
fSUB÷29
fSUB÷210
0.512 ms
1.024
2.048
4.096
8.192
16.384
32.768
65.536
At fSUB=32.768kHz
62.5 ms
125.0
250.0
500.0
1000.0
2000.0
4000.0
8000.0
Table 11-1 Basic Interval Timer Interrupt Time
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43
GMS81C5108
CKCTLR
7
-
6
-
5
-
4
-
3
2
1
0
BCL BCK2 BCK1 BCK0
Basic Interval Timer source clock select
000: fMAIN÷23 or fSUB÷23
001: fMAIN÷24 or fSUB÷24
fMAIN: main-clock frequency
010: fMAIN÷25 or fSUB÷25
fSUB: sub-clock frequency
011: fMAIN÷26 or fSUB÷26
100: fMAIN÷27 or fSUB÷27
101: fMAIN÷28 or fSUB÷28
110: fMAIN÷29 or fSUB÷29
111: fMAIN÷210 or fSUB÷210
Caution:
Both register are in same address,
when write, to be a CKCTLR,
when read, to be a BITR.
7
6
ADDRESS: 0F4H
INITIAL VALUE: ----0111B
Clear bit
0: Normal operation (free-run)
1: Clear 8-bit counter (BITR) to "0". This bit becomes 0 automatically
after one machine cycle.
5
4
3
2
BITR
1
0
ADDRESS: 0F4H
INITIAL VALUE: 00H
8-BIT BINARY COUNTER
Figure 11-2 BITR: Basic Interval Timer Mode Register
Example 1:
Interrupt request flag is generated every 8.192ms at 4MHz.
:
LDM
SET1
EI
:
44
CKCTLR,#0CH
BITE
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GMS81C5108
12. Timer / Counter
Timer/Event Counter consists of prescaler, multiplexer, 8bit timer data register, 8-bit counter register, mode register,
input capture register and Comparator as shown in Figure
12-3. And the PWM high register for PWM is consisted
separately.
ternal clock input. Since a least clock consists of 2 and
most clock consists of 1024 oscillator periods, the count
rate is 1/2 to 1/1024 of the oscillator frequency in Timer0.
And Timer1 can use the same clock source too. In addition,
Timer1 has more fast clock source (1/1 to 1/8).
The timer/counter has seven operating modes.
- 8 Bit Timer/Counter Mode
- 8 Bit Capture Mode
- 8 Bit Compare Output Mode
- 16 Bit Timer/Counter Mode
- 16 Bit Capture Mode
- 16 Bit Compare Output Mode
- PWM Mode
In the “counter” function, the register is increased in response to a 0-to-1 (rising edge) transition at its corresponding external input pin EC0 (Timer 0).
In the “timer” function, the register is increased every internal clock input. Thus, one can think of it as counting in-
In addition the “capture” function, the register is increased
in response external interrupt same with timer function.
When external interrupt edge input, the count register is
captured into capture data register CDRx.
Timer1 is shared with “PWM” function and “Compare
output” function.
Example 1:
Example 3:
Timer 0 = 8-bit timer mode, 8ms interval at 4MHz
Timer 1 = 8-bit timer mode, 4ms interval at 4MHz
Timer0 = 8-bit event counter, 2ms interval at 4MHz
Timer1 = 8-bit capture mode, 2us sampling count.
LDM
LDM
LDM
LDM
LDM
SCMR,#0
;Main clock mode
TDR0,#249
TM0,#0001_0011B
TDR1,#124
TM1,#0000_1111B
SET1
SET1
EI
:
:
:
T0E
T1E
LDM
LDM
LDM
TDR0,#99
;99+1, 100 count
TM0,#01FH
;event counter
R0DR,#XXXX_1XXXB ;R03input
LDM
LDM
LDM
LDM
IESR,#XXXX_01XXB
PMR,#XXXX_1X1XB
TDR1,#0FFH
TM1,#0001_1011B
SET1
SET1
SET1
EI
:
T0E;ENABLE TIMER 0
T1E;ENABLE TIMER 1
INT1E;ENABLE EXT. INT1
;FALLING
;EC0,INT1
;2us
X: don’t care.
Example 2:
Example 4:
Timer0 = 16-bit timer mode, 0.5s at 4MHz
Timer0 = 16-bit capture mode, 8us sampling count. at 4MHz
LDM
LDM
LDM
LDM
LDM
SCMR,#0
TDR0,#23H
TDR1,#0F4H
TM0,#0FH
TM1,#4CH
SET1
EI
:
:
:
T0E
;Main clock mode
;FMAIN/32, 8us
LDM
LDM
LDM
LDM
TDR0,#0FFH
TDR1,#0FFH
TM0,#02FH
TM1,#04FH
LDM
LDM
IESR,#XXXX_XX01B
PMR,#XXXX_XXX1B
SET1
SET1
EI
:
T0E;ENABLE TIMER 0
INT0E;ENABLE EXT. INT0
;AS INT0
X: don’t care.
JUNE 2001 Ver 1.0
45
GMS81C5108
TM0 (Timer0 Mode Register)
Bit :
7
6
R/W
5
R/W
4
R/W
3
R/W
2
R/W
1
R/W
0
-
-
CAP0
T0CK2
T0CK1
T0CK0
T0CN
T0ST
ADDRESS: 0E0H
INITIAL VALUE:--000000B
Reserved
CAP0 (Capture Mode Selection Bit)
0: Capture Disable
1: Capture Enable
T0CN (Timer 0 Continue Start)
0: Stop Counting
1: Start Counting
T0ST (Timer 0 Start Control)
0: stop counting
1: clear the counter and start count again
T0CK[2:0] (Timer 0 Input Clock Selection)
000: fMAIN÷2 or fSUB÷2
001: fMAIN÷22 or fSUB÷22
010: fMAIN÷23 or fSUB÷23
011: fMAIN÷25 or fSUB÷25
fMAIN: main-clock frequency
100: fMAIN÷27 or fSUB÷27
fSUB: sub-clock frequency
9
9
101: fMAIN÷2 or fSUB÷2
10
10
110: fMAIN÷2 or fSUB÷2
111: External Event clock (EC0)
TM1 (Timer1 Mode Register)
Bit :
R/W
7
R/W
6
R/W
5
R/W
4
R/W
3
R/W
2
R/W
1
R/W
0
POL
16BIT
PWME
CAP1
T1CK1
T1CK0
T1CN
T1ST
POL (PWM Output Polarity Selection)
0: Duty Active Low
1: Duty Active High
16BIT (16 Bit Mode Selection)
0: 8-Bit Mode
1: 16-Bit Mode
ADDRESS: 0E2H
INITIAL VALUE:00000000B
T1CK[1:0] (Timer 1 Input Clock Selection)
or fSUB
00: fMAIN
01: fMAIN÷2 or fSUB÷2
3
10: fMAIN÷2 or fSUB÷23
11: Timer 0 Clock
T1CN (Timer 1 Continue Start)
0: Stop Counting
1: Start Counting
PWME (PWM Enable Bit)
0: PWM Disable
1: PWM Enable
CAP1 (Capture Mode Selection Bit)
0: Capture Disable
1: Capture Enable
T1ST (Timer 1 Start Control)
0: stop counting
1: clear the counter and start count again
**The counter will be cleared and restarted only when the TxST bit cleared and set again.
If TxST bit set again when TxST bit is set, the counter can’t be cleared but only start again.
Figure 12-1 Timer0,1 Registers
46
JUNE 2001 Ver 1.0
GMS81C5108
CDR0 (Input Capture Register)
T0 (Timer 0 Counter Register)
Bit :
R
7
R
6
R
5
R
4
R
3
R
2
R
1
R
0
CDR07
CDR06
CDR05
CDR04
CDR03
CDR02
CDR01
CDR00
ADDRESS: E1H
INITIAL VALUE:00H
In Timer mode, this register is the value of Timer 0 counter and in Capture mode, this register is the value of input capture.
TDR0 (Timer 0 Data Register)
Bit :
W
7
W
6
W
5
W
4
W
3
W
2
W
1
W
0
TDR07
TDR06
TDR05
TDR04
TDR03
TDR02
TDR01
TDR00
ADDRESS: 0E1H
INITIAL VALUE:FFH
If the counter of Timer 0 and the data of TDR0 is equal, interrupt is occurred.
CDR1 (Input Capture Register)
T1 (Timer 1 Counter Register)
Bit :
R
7
R
6
R
5
R
4
R
3
R
2
R
1
R
0
CDR17
CDR16
CDR15
CDR14
CDR13
CDR12
CDR11
CDR10
ADDRESS: 0E4H
INITIAL VALUE:00H
In Timer mode, this register is the value of Timer 1 counter and in Capture mode, this register is the value of input capture.
TDR1 (Timer 1 Data Register)
Bit :
W
7
TDR17
W
6
W
5
W
4
W
3
W
2
W
1
W
0
TDR16
TDR15
TDR14
TDR13
TDR12
TDR11
TDR10
ADDRESS: 0E3H
INITIAL VALUE:FFH
If the counter of Timer 1 and the data of TDR1 is equal, interrupt is occurred.
T1PPR (Timer 1 Pulse Period Register)
Bit :
W
7
W
6
W
5
W
4
W
3
W
2
W
1
W
0
T1PPR7 T1PPR6 T1PPR5 T1PPR4 T1PPR3 T1PPR2 T1PPR1 T1PPR0
ADDRESS: 0E3H
INITIAL VALUE:FFH
The period is decided by PWM.
T1PDR (Timer 1 Pulse Duty Register)
Bit :
W/R
7
W/R
6
W/R
5
W/R
4
W/R
3
W/R
2
W/R
1
W/R
0
T1PDR7 T1PDR6 T1PDR5 T1PDR4 T1PDR3 T1PDR2 T1PDR1 T1PDR0
ADDRESS: 0E4H
INITIAL VALUE:00H
In PWM mode, decide the pulse duty.
PWMHR (PWM High Register)
Bit :
7
6
5
4
-
-
-
-
W
3
W
2
W
1
W
0
PWM03 PWM02 PWM01 PWM00
ADDRESS: 0E5H
INITIAL VALUE:----0000B
Reserved
PWM Period = [PWMHR[3:2] + T1PPR] x Source Clock
PWM Duty = [PWMHR[1:0] + T1PDR] x Source Clock
Figure 12-2 Related Registers with Timer/Counter
JUNE 2001 Ver 1.0
47
GMS81C5108
16BIT
CAP0
CAP1
PWME
T0CK[2:0] T1CK[1:0]
PWMO
Timer 0
Timer 1
0
0
0
0
XXX
XX
0
8 Bit Timer
8 Bit Timer
0
0
1
0
111
XX
0
8 Bit Event Counter
8 Bit Capture
0
1
0
0
XXX
XX
1
8 Bit Capture
8 Bit Compare Output
0
0
0
1
XXX
XX
1
8 Bit Timer/Counter
10 Bit PWM
1
0
0
0
XXX
11
0
16 Bit Timer
1
0
0
0
111
11
0
16 Bit Event Counter
1
1
X1
0
XXX
11
0
16 Bit Capture
1
0
0
0
XXX
11
1
16 Bit Compare Output
1. X: The value “0” or “1” corresponding your operation.
Table 12-1 Operating Modes of Timer 0 and Timer 1
12.1 8-Bit Timer/Counter Mode
The GMS81C5108 has two 8-bit Timer/Counters, Timer 0,
Timer 1, as shown in Figure 12-3.
The “timer” or “counter” function is selected by mode registers TMx as shown in Figure 12-1 and Table 12-1. To use
TM0
-
TM1
-
as an 8-bit timer/counter mode, bit CAP0 of TM0 is
cleared to “0” and bits 16BIT of TM1 should be cleared to
“0” (Table 12-1 ).
CAP0
T0CK2
T0CK1
T0CK0
T0CN
T0ST
0
X
X
X
X
X
T1CN
T1ST
X
X
POL
16BIT
PWME
CAP1
T1CK1
T1CK0
X
0
0
0
X
X
ADDRESS : 0E0H
RESET VALUE : --000000B
ADDRESS : 0E2H
RESET VALUE : 00000000B
X : The value “0” or “1” corresponding your operation.
T0CK[2:0]
T0ST
0 : Stop
1 : Clear and Start
Edge Detector
EC0
1
XIN
0X
SXIN
1X
2
SCMR[1:0]
÷2
÷4
÷8
÷ 32
÷ 128
÷ 512
÷ 1024
÷1
÷2
÷8
T0 (8-bit)
MUX
CLEAR
TIMER 0
INTERRUPT
T0IF
T0CN
COMPARATOR
TDR0 (8-bit)
T1CK[1:0]
[PMR.6]
PWMO
T1ST
0 : Stop
1 : Clear and Start
1
MUX
T1 (8-bit)
CLEAR
F/F
COMPO PIN (R31)
T1IF
T1CN
COMPARATOR
TIMER 1
INTERRUPT
TDR1 (8-bit)
Figure 12-3 Block Diagram of Timer/Event Counter
48
JUNE 2001 Ver 1.0
GMS81C5108
These timers have each 8-bit count register and data register. The count register is increased by every internal or external clock input. The internal clock has a prescaler divide
ratio option of 2, 4, 8, 32,128, 512, 1024 (selected by control bits T0CK2, T0CK1 and T0CK0 of register TM0) and
1, 2, 8 (selected by control bits T1CK1 and T1CK0 of register TM1).
In counter function, the counter is increased every 0-to 1
(rising edge) transition of EC0 pin. In order to use counter
function, the bit R03 of the R0 Direction Register (R0DR)
should be set to “0” and the bit EC0 of Port Mode Register
(PMR) should set to “1”. The Timer 0 can be used as a
counter by pin EC0 input, but Timer 1 can not used as a
counter.
In the Timer, timer register TX increases from 00H until it
matches TDRX and then reset to 00H. If the value of TX is
equal with TDRX, Timer X interrupt is occurred (latched in
TXIF bit). TDR0 and T0 register are in same address, so
this register is read from T0 and written to TDR0.
Note: The contents of TDR0 and TDR1 must be initialized
(by software) with the value between 1H and 0FFH,
not 0H.
TDR0
n
n-1
~~
up
-c
ou
nt
~~
PCP
~~
9
8
7
6
5
4
3
2
1
0
Timer 0 (T0IF)
Interrupt
TIME
Interrupt period
= PCP x (n+1)
Occur interrupt
Occur interrupt
Occur interrupt
Figure 12-4 Counting Example of Timer Data Registers
TDR0
disable
up
-c
ou
nt
~~
clear & start
enable
stop
~~
TIME
Timer 0 (T0IF)
Interrupt
Occur interrupt
Occur interrupt
T0ST
Start & Stop
T0ST = 0
T0ST = 1
T0CN
Control count
T0CN = 0
T0CN = 1
Figure 12-5 Timer Count Operation
JUNE 2001 Ver 1.0
49
GMS81C5108
12.2 16 Bit Timer/Counter Mode
The Timer register is running with 16 bits. A 16-bit timer/
counter register T0, T1 are increased from 0000H until it
matches TDR0, TDR1 and then resets to 0000 H . The
match output generates Timer 0 interrupt not Timer 1 interrupt.
TM0
-
TM1
-
The clock source of the Timer 0 is selected either internal
or external clock by bit T0CK2, T0CK1 and T0CK0.
In 16-bit mode, the bits T1CK1,T1CK0 and 16BIT of TM1
should be set to “1” respectively.
CAP0
T0CK2
T0CK1
T0CK0
T0CN
T0ST
0
X
X
X
X
X
T1CN
T1ST
X
X
POL
16BIT
PWME
CAP1
T1CK1
T1CK0
X
1
0
0
1
1
ADDRESS : 0E0H
RESET VALUE : --000000B
ADDRESS : 0E2H
RESET VALUE : 00000000B
X : The value “0” or “1” corresponding your operation.
T0ST
T0CK[2:0]
0 : Stop
1 : Clear and Start
Edge Detector
EC0
1
XIN
0X
SXIN
1X
2
SCMR[1:0]
÷2
÷4
÷8
÷ 32
÷ 128
÷ 512
÷ 1024
T1 (8-bit)
MUX
T 0 (8 -b it)
CLEAR
T0CN
T0IF
TIMER 0
INTERRUPT
COMPARATOR
F/F
TDR1 (8-bit)
TDR0 (8-bit)
COMPO (R31)
PWMO
[PMR.6]
Figure 12-6 16-bit Timer / Counter Mode
12.3 8-Bit Capture Mode
The Timer 0 capture mode is set by bit CAP0 of timer
mode register TM0 (bit CAP1 of timer mode register TM1
for Timer 1) as shown in Figure 12-7.
As mentioned above, not only Timer 0 but Timer 1 can also
be used as a capture mode.
The Timer/Counter register is increased in response internal or external input. This counting function is same with
normal timer mode, and Timer interrupt is generated when
timer register T0 (T1) increases and matches TDR0
(TDR1).
This timer interrupt in capture mode is very useful when
the pulse width of captured signal is more wider than the
maximum period of Timer.
For example, in Figure 12-9, the pulse width of captured
signal is wider than the timer data value (FF H ) over 2
times. When external interrupt is occurred, the captured
value (13H) is more little than wanted value. It can be obtained correct value by counting the number of timer over-
50
flow occurrence.
Timer/Counter still does the above, but with the added feature that a edge transition at external input INTx pin causes
the current value in the Timer x register (T0,T1), to be captured into registers CDRx (CDR0, CDR1), respectively.
After captured, Timer x register is cleared and restarts by
hardware.
It has three transition modes: “falling edge”, “rising edge”,
“both edge” which are selected by interrupt edge selection
register IESR (Refer to External interrupt section). In addition, the transition at INTx pin generate an interrupt.
Note: The CDR0, TDR0 and T0 are in same address. In
the capture mode, reading operation is read the
CDR0 and in timer mode, reading operation is read
the T0. TDR0 is only for writing operation.
The CDR1, T1 are in same address, the TDR1 is located in different address. In the capture mode,
reading operation is read the CDR1
JUNE 2001 Ver 1.0
GMS81C5108
TM0
-
TM1
-
CAP0
T0CK2
T0CK1
T0CK0
T0CN
T0ST
1
X
X
X
X
X
POL
16BIT
PWME
CAP1
T1CK1
T1CK0
T1CN
T1ST
X
0
0
1
X
X
X
X
ADDRESS : 0E0H
RESET VALUE : --000000B
ADDRESS : 0E2H
RESET VALUE : 00000000B
T0ST
0 : Stop
1 : Clear and Start
T0CK[2:0]
Edge Detector
EC0
1
0X
XIN
1X
SXIN
2
SCMR[1:0]
÷2
÷4
÷8
÷ 32
÷ 128
÷ 512
÷ 1024
CLEAR
T0 (8-bit)
MUX
T0CN
CAPTURE
T0IF
TIMER 0
INTERRUPT
INT0IF
INT 0
INTERRUPT
T1IF
TIMER 1
INTERRUPT
INT1IF
INT 1
INTERRUPT
COMPARATOR
CDR0 (8-bit)
TDR0 (8-bit)
INT0
T0ST
0 : Stop
1 : Clear and Start
IESR[1:0]
÷1
÷2
÷8
1
MUX
CLEAR
T1 (8-bit)
T1CN
T1CK[1:0]
COMPARATOR
IESR[3:2]
CDR1 (8-bit)
TDR1 (8-bit)
CAPTURE
INT1
Figure 12-7 8-bit Capture Mode
JUNE 2001 Ver 1.0
51
GMS81C5108
This value is loaded to CDR0
n
T0
n-1
up
-c
ou
nt
~~
~~
9
8
7
6
5
4
~~
3
2
1
0
TIME
Ext. INT0 Pin
Interrupt Request
(INT0IF)
Interrupt Interval Period
Ext. INT0 Pin
Interrupt Request
(INT0IF)
Delay
Capture
(Timer Stop)
Clear & Start
Figure 12-8 Input Capture Operation
Ext. INT0 Pin
Interrupt Request
(INT0IF)
Interrupt Interval Period = FFH + 01H + FFH +01H + 13H = 213H
Interrupt Request
(T0IF)
FFH
FFH
T0
13H
00H
00H
Figure 12-9 Excess Timer Overflow in Capture Mode
52
JUNE 2001 Ver 1.0
GMS81C5108
12.4 16-bit Capture Mode
16-bit capture mode is the same as 8-bit capture, except
that the Timer register is running with 16 bits.
In 16-bit mode, the bits T1CK1,T1CK0 and 16BIT of TM1
should be set to “1” respectively.
The clock source of the Timer 0 is selected either internal
or external clock by bit T0CK2, T0CK1 and T0CK0.
TM0
-
TM1
-
CAP0
T0CK2
T0CK1
T0CK0
T0CN
T0ST
1
X
X
X
X
X
T1CN
T1ST
X
X
POL
16BIT
PWME
CAP1
T1CK1
T1CK0
X
1
0
X
1
1
ADDRESS : 0E0H
RESET VALUE : --000000B
ADDRESS : 0E2H
RESET VALUE : 00000000B
X : The value “0” or “1” corresponding your operation.
T0CK[2:0]
T0ST
0 : Stop
1 : Clear and Start
Edge Detector
EC0
1
XIN
0X
SXIN
1X
2
SCMR[1:0]
÷2
÷4
÷8
÷ 32
÷ 128
÷ 512
÷ 1024
CLEAR
T0 + T1 (16-bit)
MUX
T0CN
T0IF
TIMER 0
INTERRUPT
COMPARATOR
CAPTURE
CDR1
(8-bit)
CDR0
(8-bit)
TDR1
(8-bit)
TDR0
(8-bit)
INT0
INT0IF
INT 0
INTERRUPT
IESR[1:0]
Figure 12-10 16-bit Capture Mode
12.5 8-Bit (16-Bit) Compare OutPut Mode
The GMS81C5108 has a function of Timer Compare Output. To pulse out, the timer match can goes to port pin
(R31) as shown in Figure 12-3 and Figure 12-6. Thus,
pulse out is generated by the timer match. These operation
is implemented to pin, R31/PWM.
In this mode, the bit PWMO of Port Mode Register (PMR)
should be set to “1”, and the bit PWME of Timer1 Mode
Register (TM1) should be cleared to “0”.
In addition, 16-bit Compare output mode is available, also.
This pin output the signal having a 50 : 50 duty square
wave, and output frequency is same as below equation.
Oscillation Frequency
f COMP = -------------------------------------------------------------------------------------2 × Prescaler Value × ( TDR + 1 )
12.6 PWM Mode
The GMS81C5108 has one high speed PWM (Pulse Width
Modulation) function which shared with Timer1.
In PWM mode, the R31/PWM pin operates as a 10-bit resolution PWM output port. For this mode, the bit PWM of
Port Mode Register (PMR) and the bit PWME of timer1
mode register (TM1) should be set to “1” respectively.
The period of the PWM output is determined by the
T1PPR (PWM Period Register) and PWMHR[3:2] (bit3,2
JUNE 2001 Ver 1.0
of PWM High Register) and the duty of the PWM output
is determined by the T1PDR (PWM Duty Register) and
PWMHR[1:0] (bit1,0 of PWM High Register).
The user can use PWM data by writing the lower 8-bit period value to the T1PPR and the higher 2-bit period value
to the PWMHR[3:2]. And the duty value can be used with
the T1PDR and the PWMHR[1:0] in the same way.
The T1PDR is configured as a double buffering for glitch-
53
GMS81C5108
PWM Period = [PWMHR[3:2]T1PPR+1] X Source Clock
less PWM output. In Figure 12-11, the duty data is transferred from the master to the slave when the period data
matched to the counted value. (i.e. at the beginning of next
duty cycle).
PWM Duty = [PWMHR[1:0]T1PDR+1] X Source Clock
If it needed more higher frequency of PWM, it should be
reduced resolution.
The bit POL0 of TM1 decides the polarity of duty cycle.
Note: If the duty value and the period value are same, the
PWM output is determined by the bit POL0 (1: High,
0: Low). And if the duty value is set to “00H”, the
PWM output is determined by the bit POL0(1: Low,
0: High). The period value must be same or more
than the duty value, and 00H cannot be used as the
period value.
The duty value can be changed when the PWM outputs.
However the changed duty value is output after the current
period is over. And it can be maintained the duty value at
present output when changed only period value shown as
Figure 12-13. As it were, the absolute duty time is not
changed in varying frequency.
Note: If the user need to change mode from the Timer1
mode to the PWM mode, the Timer1 should be
stopped firstly, and then set period and duty register
value. If user writes register values and changes
mode to PWM mode while Timer1 is in operation,
the PWM data would be different from expected
data in the beginning.
Frequency
Resolution
T1CK[1:0]
=00 (250nS)
T1CK[1:0]
=01 (500nS)
T1CK[1:0]
=10 (2uS)
10-bit
3.9KHz
1.95KHz
0.49KHZ
9-bit
7.8KHz
3.9KHz
0.98KHZ
8-bit
15.6KHz
7.8KHz
1.95KHz
7-bit
31.25KHz
15.6KHz
3.90KHz
The relation of frequency and resolution is in inverse proportion. Table 12-2 shows the relation of PWM frequency
vs. resolution.
Table 12-2 PWM Frequency vs. Resolution at 4MHz
TM1
PWMHR
POL
16BIT
PWME
CAP1
T1CK1
T1CK0
T1CN
T1ST
X
0
1
0
X
X
X
X
-
-
-
-
PWM03
PWM02
PWM01
PWM00
X
X
X
X
Period High
T1ST
ADDRESS : 0E5H
RESET VALUE : ----0000B
Bit Manipulation Not Available
Duty High
X : The value “0” or “1” corresponding your operation.
PWMHR[3:2]
T0 clock source
ADDRESS : 0E2H
RESET VALUE : 00H
T1PPR (8-bit)
0 : Stop
1 : Clear and Start
COMPARATOR
R31/PWM
S Q
CLEAR
1
XIN
0X
SXIN
1X
2
SCMR[1:0]
÷1
÷2
÷8
MUX
COMPARATOR
T1CK[1:0]
R
T1 (8-bit)
PWMO
[PMR.6]
POL
T1CN
Slave
T1PDR (8-bit)
PWMHR[1:0]
Master
T1PDR (8-bit)
Figure 12-11 PWM Mode
54
JUNE 2001 Ver 1.0
GMS81C5108
~
~
~
~
fxin
01
02
03
04
80
81
3FF
00
01
02
~
~
~
~
PWM
POL=1
7F
~
~
~ ~
00
~ ~
~ ~
~
~
T1
~
~
PWM
POL=0
Duty Cycle [80H+1 x 250nS = 32.25uS]
Period Cycle [3FFH x 250nS = 256uS, 3.9kHz]
T1CK[1:0] = 00 (250nS)
PWMHR = 0CH
Period
PWM03
PWM02
T1PPR (8-bit)
1
1
FFH
PWM01
PWM00
T1PDR (8-bit)
0
0
80H
T1PPR = FFH
T1PDR = 80H
Duty
Figure 12-12 Example of PWM at 4MHz
T 1C K [1:0] = 10 (2uS )
P W M H R = 00 H
T 1P P R = 0D H
T 1P D R = 04 H
Write T1PPR to 09H
Period changed
Source
clock
T1
00 01 02 03 04 05 06 07 08
09 0A 0B 0C 0D 00 01 02 03 04 05 06 07 08 09 00 01 02 03
04
PWM
POL=1
Duty Cycle
[04H+1 x 2uS = 10uS]
Duty Cycle
[04H+1 x 2uS = 10uS]
Period Cycle [0DH+1 x 2uS = 28uS, 35.7kHz]
Duty Cycle
[04H+1 x 2uS = 10uS]
Period Cycle [09H+1 x 2uS = 20uS, 50kHz]
Figure 12-13 Example of Changing the Period in Absolute Duty Cycle (@4MHz)
Example:
Timer1 @4Mhz, 4kHz - 20% duty PWM mode
LDM
LDM
LDM
LDM
LDM
LDM
LDM
R3DR,#0000_XX1XB
TM1,#0010_0000B
T1PWHR,#0000_1100B
T1PPR,#1110_0111B
T1PDR,#1100_0111B
RSR,#X1XX_XXXXB
TM1,#0010_0011B
;R31 output
;pwm enable
;20% duty
;period 250uS
;duty 50uS
;set pwm port.
;timer1 start
X means don’t care
JUNE 2001 Ver 1.0
55
GMS81C5108
13. Watch Timer/Watch Dog Timer
This has two functions, one is the interrupt occurrence for
watch time and the other is the signal generation of
WDTOUTB for watch dog.
13.1 Watch Timer
The watch timer consists of the clock selector, 21-bit binary counter and watch timer mode register. It is a multi-purpose timer. It is generally used for watch design.
clock source, if the CPU enters into stop mode, the mainclock is stopped and then watch timer is also stopped. If the
sub-clock is the source clock, the watch timer count cannot
be stopped. Therefore, the sub-clock does not stop but continues to oscillate even when the CPU is in the STOP
mode. The timer counter consists of 21-bit binary counter
and it can count to max 64 seconds at sub-clock.
The bit 1,2 of WTMR select the clock source of watch timer among sub-clock, fMAIN÷27 of main-clock and fMAIN of
main-clock. The fMAIN of main-clock is used usually for
watch timer test, so generally it is not used for the clock
source of watch timer. The fMAIN÷27 of main-clock is used
when the single clock system is organized. In fMAIN÷27
The bit 2, 3 of WTMR select the interrupt request interval
of watch timer among 2Hz, 4Hz, 16Hz and 1/64Hz.
WTMR (Watch Timer Mode Register)
Bit :
7
R/W
6
R/W
5
R/W
4
R/W
3
R/W
2
R/W
1
R/W
0
-
WTEN
WDTEN
WDTCL
WTIN1
WTIN0
WTCK1
WTCK0
ADDRESS: 0EFH
INITIAL VALUE:-0000000B
WTEN (Watch Timer Enable Bit)
0: Watch Timer Disable
1: Watch Timer Enable
WDTEN (Watch Dog Timer Enable Bit)
0: Watch Dog Timer Disable
1: Watch Dog Timer Enable
WDTCL (Watch Dog Timer Clear Bit)
0: Timer running
1: WDT Clear (Auto reset after 1 cycle)
WTIN[1:0] (Watch Timer Interrupt Interval Selection)
00: 16Hz
01:
4Hz
10:
2Hz
11: 1/64Hz
WTCK[1:0] (Watch Timer Clock Source Selection)
00: Sub. Clock (fSUB)
01: Main Clock (fMAIN÷27)
10: Main Clock (fMAIN)
11: -
* When fSUB = 32.768 kHz and fMAIN = 4.19 MHz
Figure 13-1 Watch Timer Mode Register
WTIN[1:0]
WTCK[1:0]
fSUB
fMAIN÷27
fMAIN
21 BIT
Binary Counter
MUX
16 Hz
4 Hz
2 Hz
1/64 Hz
MUX
WTIF
Watch Timer
Interrupt
WDTOUT
WTEN
2 Bit
F/F
WDTCL
WDTEN
Figure 13-2 Watch Timer Block Diagram
56
JUNE 2001 Ver 1.0
GMS81C5108
13.2 Watch Dog Timer
The watch dog timer (WDT) function is used for checking
program malfunction. If the watch dog timer is not reset in
a fixed time, the WDTOUTB pin outputs a low signal.
Therefore, by connecting the WDTOUTB pin and the reset
pin externally, the MCU can be reset when the malfunction
is occurred.
Usually the stop mode is used to reduce the power consumption. When the stop mode is released by watch timer
interrupt, it is recommend to set the WDTCL to clear the
2-Bit counter and enter the stop mode. If the clock source
is 1/64Hz, the WDTCL cannot be cleared in 500ms. In this
case, the user should disable the WDT by clearing the
WDTEN or disconnect the WDTOUTB pin and reset pin.
Usage of Watch Timer in STOP Mode
When the system is off and the watch should be kept working, follow the steps below.
1. Determines which mode is to be performed between
main mode and sub mode when the MCU is released
from Stop mode and set the clock source of watch timer
to sub-clock.
2. Enters in STOP mode.
3. After released by watch timer interrupt, counts up timer
and refreshes LCD Display. When the performing count
up and refresh the LCD, the CPU operates either in main
frequency mode or sub frequency mode.
4. Enters in STOP mode again.
5. Repeats 3 and 4.
When using STOP mode, if the watch timer interrupt interval is selected to 2Hz, the power consumption can be
reduced considerably.
fW/211 (16Hz)
fW/213 (4Hz)
fW/214 (2Hz)
INTWT (16Hz)
INTWT (4Hz)
INTWT (2Hz)
WDTCL
WDT Reset
Signal
WDTOUTB
500msec
The WDTCL should
be set during this interval.
JUNE 2001 Ver 1.0
500msec
The WDTCL should
be set during this interval.
If the WDTCL is not cleared
during this interval, the WDTOUTB
will be low during next interval.
57
GMS81C5108
14. ANALOG TO DIGITAL CONVERTER
The analog-to-digital converter (A/D) allows conversion
of an analog input signal to a corresponding 8-bit digital
value. The A/D module has four analog inputs, which are
multiplexed into one sample and hold. The output of the
sample and hold is the input into the converter, which generates the result via successive approximation. The analog
supply voltage is connected to AVDD of ladder resistance
of A/D module.
setting input mode by R2DR direction register. And select
the corresponding channel to be converted by setting
ADAN[1:0].
The processing of conversion is start when the start bit
ADST is set to “1”. After one cycle, it is cleared by hardware. The register ADDR contains the result of the A/D
conversion. When the conversion is completed, the result
is loaded into the ADDR, the A/D conversion status bit
ADF is set to “1”, and the A/D interrupt flag ADIF is set.
The block diagram of the A/D module is shown in Figure
14-1. The A/D status bit ADF is automatically set when A/
D conversion is completed, cleared when A/D conversion
is in process. The conversion time takes maximum 30 uS
(at fMAIN = 4MHz).
The A/D module has two registers which are the A/D mode
register (ADMR) and A/D data register (ADDR). The
ADMR register, shown in Figure 14-1, controls the operation of the A/D converter module. The port pins can be
configured as analog inputs or digital I/O. To use analog
inputs, each port should be assigned analog input port by
ADAN[1:0]
A/D Converter
Data Register
ANEN
11
R23/AN3
ADDR (8-bit)
ADDRESS : 0EDH
RESET VALUE : Undefined
ANEN
10
R22/AN2
Sample & Hold
ANEN
Comparator
S/H
Successive
Approximation
Circuit
01
R21/AN1
A D IF
A/D Interrupt
ANEN
00
R20/AN0
Resistor
Ladder
Circuit
ANEN
AVDD
ADMR (A/D Mode Register)
Bit :
7
R/W
6
5
4
R/W
3
R/W
2
R/W
1
R
0
-
ADEN
-
-
ADAN1
ADAN0
ADST
ADF
ADDRESS : 0ECH
RESET VALUE : -0--0001B
ADAN[1:0] (A/D Converter Input Selection)
00 : Channel 0 (R20/AN0)
01 : Channel 1 (R21/AN1)
10 : Channel 2 (R22/AN2)
11 : Channel 3 (R23/AN3)
ADEN (A/D Converter Enable bit)
1 : Enable
0 : Disable
ADST (A/D Start bit)
1 : A/D Conversion is started
After 1 cycle, cleared to “0”
0 : Bit force to zero
ADF (A/D Status bit)
0 : A/D Conversion is in process
1 : A/D Conversion is completed
ADDR (A/D Data Register)
Bit :
R
7
R
6
R
5
R
4
R
3
R
2
R
1
R
0
ADD7
ADD6
ADD5
ADD4
ADD3
ADD2
ADD1
ADD0
ADDRESS : 0EDH
RESET VALUE : Undefined
Figure 14-1 A/D Converter Block Diagram & Registers
58
JUNE 2001 Ver 1.0
GMS81C5108
to noise on pins AVDD and AN0 to AN3. Since the effect
increases in proportion to the output impedance of the analog input source, it is recommended that a capacitor is
connected externally as shown below in order to reduce
noise.
ENABLE A/D CONVERTER
A/D INPUT CHANNEL SELECT
Analog
Input
ANALOG REFERENCE SELECT
AN0~AN3
100~1000pF
A/D START (ADST = 1)
Figure 14-3 Analog Input Pin Connecting Capacitor
NOP
(3) Pins AN0/R20 to AN3/R23
NO
ADF = 1
YES
READ ADDR
Figure 14-2 A/D Converter Operation Flow
A/D Converter Cautions
(1) Input range of AN0 to AN3
The input voltages of AN0 to AN3 should be within the
specification range. In particular, if a voltage above AVDD
or below VSS is input (even if within the absolute maximum rating range), the conversion value for that channel
can not be indeterminated. The conversion values of the
other channels may also be affected.
(2) Noise countermeasures
The analog input pins AN0 to AN3 also function as input/
output port (PORT R2) pins. When A/D conversion is performed with any of pins AN0 to AN3 selected, be sure not
to execute a PORT input instruction while conversion is in
progress, as this may reduce the conversion resolution.
Also, if digital pulses are applied to a pin adjacent to the
pin in the process of A/D conversion, the expected A/D
conversion value may not be obtainable due to coupling
noise. Therefore, avoid applying pulses to pins adjacent to
the pin undergoing A/D conversion.
(4) AVDD pin input impedance
A series resistor string of approximately 10KΩ is connected between the AVDD pin and the VSS pin.
Therefore, if the output impedance of the reference voltage
source is high, this will result in parallel connection to the
series resistor string between the AVDD pin and the VSS
pin, and there will be a large reference voltage error.
In order to maintain 8-bit resolution, attention must be paid
JUNE 2001 Ver 1.0
59
GMS81C5108
15. Buzzer Output Function
The buzzer driver consists of 6-bit binary counter, the
buzzer data register BDR and the clock selector. It generates square-wave which is very wide range frequency (500
Hz~125 KHz at fMAIN = 4MHz) by user programmable
counter.
The bit 0 to 5 of BDR determines output frequency for
buzzer driving. BCD is undefined after reset, so it must be
initialized to between 0H and 3FH by software. Note that
BDR is a write-only register. Frequency calculation is following as shown below.
Pin R04 is assigned for output port of Buzzer driver by setting the bit BUZ of Port Mode Register (PMR) to “1”.
Oscillator Frequency
f BUZ ( Hz ) = -----------------------------------------------------------------------------2 × Prescaler Ratio × ( BCD + 1 )
The 6-bit buzzer counter is cleared and start the counting
by writing signal to the register BDR. It is increased from
00H until it matches with BDR[5:0].
The bits BCK1, BCK0 of BDR select the source clock
from prescaler output
fBUZ: BUZ pin frequency
Prescaler ratio: Prescaler divide ratio by BDR[7:6]
BCD value: 6-bit compare data, BCD[5:0].
Also, it is cleared by counter overflow and count up to output the square wave pulse of duty 50%.
BDR (Buzzer Data Register)
W
7
W
6
W
5
W
4
W
3
W
2
W
1
W
0
BCK1
BCK0
BCD5
BCD4
BCD3
BCD2
BCD1
BCD0
Bit :
ADDRESS : 0FDH
RESET VALUE : 00H
Bit manipulation is not available.
BCK[1:0] (Buzzer Clock Source)
00: fMAIN÷23
01: fMAIN÷24
10: fMAIN÷25
11: fMAIN÷26
or fSUB÷23
or fSUB÷24
or fSUB÷25
or fSUB÷26
BCD[5:0] (Buzzer Control Data)
Buzzer Period Data
PMR (Port Mode Register)
-
PWMO
-
BUZ
EC0
INT2
INT1
INT0
ADDRESS :0D9H
RESET VALUE : -0-00000B
BUZ (Buzzer Output)
0: R04 Port (turn off buzzer)
1: BUZ port (turn on buzzer)
SCMR[1:0]
2
XIN
0X
SXIN
1X
÷8
÷ 16
÷ 32
÷ 64
MUX
COUNTER (6-bit)
F/F
BCK[1:0]
COMPARATOR
BCD (6-bit)
R04/BUZ PIN
BUZ
[PMR.4]
Figure 15-1 Buzzer Driver
Example: 2.5kHz output at 4MHz.
LDM
LDM
LDM
R0DR,#XXX1_XXXXB
BDR,#1001_1000B
PMR,#XXX1_XXXXB
;Buzzer ON
X means don’t care
60
JUNE 2001 Ver 1.0
GMS81C5108
Buzzer Output Frequency
When main-frequency is 4MHz, buzzer frequency is
shown as below and if sub-frequency is selected as clock
BDR
[5:0]
Frequency Output (kHz)
00
01
10
11
source, buzzer frequency is used after dividing by 128.
BDR
[5:0]
Frequency Output (kHz)
00
01
10
11
00
01
02
03
04
05
06
07
250.000
125.000
83.333
62.500
50.000
41.667
35.714
31.250
125.000
62.500
41.667
31.250
25.000
20.833
17.857
15.625
62.500
31.250
20.833
15.625
12.500
10.417
8.929
7.813
31.250
15.625
10.417
7.813
6.250
5.208
4.464
3.906
20
21
22
23
24
25
26
27
7.576
7.353
7.143
6.944
6.757
6.579
6.410
6.250
3.788
3.676
3.571
3.472
3.378
3.289
3.205
3.125
1.894
1.838
1.786
1.736
1.689
1.645
1.603
1.563
0.947
0.919
0.893
0.868
0.845
0.822
0.801
0.781
08
09
0A
0B
0C
0D
0E
0F
27.778
25.000
22.727
20.833
19.231
17.857
16.667
15.625
13.889
12.500
11.364
10.417
9.615
8.929
8.333
7.813
6.944
6.250
5.682
5.208
4.808
4.464
4.167
3.906
3.472
3.125
2.841
2.604
2.404
2.232
2.083
1.953
28
29
2A
2B
2C
2D
2E
2F
6.098
5.952
5.814
5.682
5.556
5.435
5.319
5.208
3.049
2.976
2.907
2.841
2.778
2.717
2.660
2.604
1.524
1.488
1.453
1.420
1.389
1.359
1.330
1.302
0.762
0.744
0.727
0.710
0.694
0.679
0.665
0.651
10
11
12
13
14
15
16
17
14.706
13.889
13.158
12.500
11.905
11.364
10.870
10.417
7.353
6.944
6.579
6.250
5.952
5.682
5.435
5.208
3.676
3.472
3.289
3.125
2.976
2.841
2.717
2.604
1.838
1.736
1.645
1.563
1.488
1.420
1.359
1.302
30
31
32
33
34
35
36
37
5.102
5.000
4.902
4.808
4.717
4.630
4.545
4.464
2.551
2.500
2.451
2.404
2.358
2.315
2.273
2.232
1.276
1.250
1.225
1.202
1.179
1.157
1.136
1.116
0.638
0.625
0.613
0.601
0.590
0.579
0.568
0.558
18
19
1A
1B
1C
1D
1E
1F
10.000
9.615
9.259
8.929
8.621
8.333
8.065
7.813
5.000
4.808
4.630
4.464
4.310
4.167
4.032
3.906
2.500
2.404
2.315
2.232
2.155
2.083
2.016
1.953
1.250
1.202
1.157
1.116
1.078
1.042
1.008
0.977
38
39
3A
3B
3C
3D
3E
3F
4.386
4.310
4.237
4.167
4.098
4.032
3.968
3.906
2.193
2.155
2.119
2.083
2.049
2.016
1.984
1.953
1.096
1.078
1.059
1.042
1.025
1.008
0.992
0.977
0.548
0.539
0.530
0.521
0.512
0.504
0.496
0.488
Table 15-1 Buzzer Output Frequency
JUNE 2001 Ver 1.0
61
GMS81C5108
16. Serial Communication Interface
The SCI module allows 8-bits of data to be synchronously
transmitted and received. This is useful for communication
with other peripheral of microcontroller devices.This con-
sists of serial I/O data register, serial I/O mode register,
clock selection circuit octal counter and control circuit as
shown in Figure 16-1.
SIOM (Seriol I/O Mode Register)
Bit :
R/W
7
R/W
6
R/W
5
R/W
4
R/W
3
R/W
2
R/W
1
R/W
0
POL
MSBS
SIO1
SIO0
SICK1
SICK0
SIOST
SIOSF
POL (Polarity Selection)
0 : Data Transmission at falling edge
(Received data latch at rising edge)
1 : Data Transmission at rising edge
(Received data latch at falling edge)
ADDRESS : 0FEH
RESET VALUE : 00000001B
MSBS (MSB First Transmit and Receive Selection)
0 : LSB First
1 : MSB First
SIO[1:0] (Serial I/O Operation Mode)
00 : Normal Port (R05, R06, R07)
01 : Transmit Mode (SCK, SO, R07)
10 : Receive Mode (SCK, R06, SI)
11 : Transmit & Receive Mode (SCK, SO, SI)
SIOST (Serial I/O Operation Start Control)
0 : SIO Operation Stop
1 : SIO Operation Start
(After one SCK clock become “0”)
SICK[1:0] (Serial I/O Clock Source Selection)
00: fMAIN ÷4 or fSUB ÷4
01: fMAIN ÷16 or fSUB ÷16
10: T0O (Timer 0 Output)
11: External Clock
SIOSF (Serial I/O Status Flag)
0 : During SIO Operation
1 : SIO Operation Finished
SIOD (Serial I/O Data Register)
Bit :
R/W
7
R/W
6
R/W
5
R/W
4
R/W
3
R/W
2
R/W
1
R/W
0
SIOD7
SIOD6
SIOD5
SIOD4
SIOD3
SIOD2
SIOD1
SIOD0
SCMR[1:0]
ADDRESS : 0FFH
RESET VALUE : Undefined
SICK[1:0]
2
2
XIN
0X
SXIN
1X
fMAIN÷22 or fSUB÷22
Prescaler
fMAIN÷24 or fSUB÷24
POL
00
SIOST
Start
01
Complete
SIOSF
SIO Control Circuit
T0OV(Timer 0 Overflow)
10
Clock
Clear
Shift Clock
SIO
Interrupt
11
R05SCK
Octal Counter
(3-Bit)
SIO[1:0] = 00
SIOIF
1
SCK
SICK[1:0] ≠ 11
& SIO[1:0] ≠ 00
MSBS
MSB
0
R07/SI
LSB
SIOD(8-Bit)
SIO Data Register
1
SIO[1] = 1
0
1
R06/SO
SIO[0] = 1
MSBS
Figure 16-1 SCI Registers and Block Diagram
62
JUNE 2001 Ver 1.0
GMS81C5108
To accomplish communication, typically three pins are
used:
- Serial Data In
- Serial Data Out
- Serial Clock
ting the SIO1 and SIO0 and the transfer clock rate is decided by setting the SICK1 and SICK0 of SCI Mode Control
Register as shown in Figure 16-1. And the polarity of
transfer clock is selected by setting the POL. The MSBS
bit is used to select which bit would be sending or receiving.
R07/SI
R06/SO
R05/SCK
The serial data transfer operation mode is decided by set-
SIO1
SIO0
Function Selection
0
0
0
Port Selection
R05/SCK
R06/SO
R07/SI
-
R05
R06
R07
1
Transmit Mode
SCK
SO
R07
1
0
Receive Mode
SCK
R06
SI
1
1
Transmit and Receive
SCK
SO
SI
16.1 Data Transmit/Receive Timing
The SCI operation is executed by setting the SIOST bit to
“1”. The SIOST bit is cleared to “0” automatically after 1
machine cycle. The Serial output data is shift in or shift out
at edge decided by POL. Interrupt is occurred when the
eight in/out datas is counted by octal counter.
MSBS=0
SIOST
R05/SCK
(POL=1)
R05/SCK
(POL=0)
R06/SO
R07/SI
D0
D0
D1
D1
D2
D2
D3
D3
D4
D4
D5
D5
D6
D6
D7
D7
SIOSF
SIOIF
(SCI Int. Req)
Figure 16-2 SCI Timing Diagram
JUNE 2001 Ver 1.0
63
GMS81C5108
16.2 The method of Serial I/O
1. Select transmission/receiving mode
If both transmission mode is selected and transmission is performed simultaneously it would be made error.
When external clock is used, the frequency should be less than
1MHz and recommended duty is 50%.
4. The SIO interrupt is generated at the completion of SIO and
SIOSF is set to “1”.
2. In case of sending mode, write data to be send to SIOD.
5. In case of receiving mode, the received data is acquired by
reading the SIOD.
3. Set SIOST to “1” to start serial transmission.
SIOST
SCLK [R05]
(POL=1)
SOUT [R06]
SIN [R07]
D0
D0
D1
D1
D2
D2
D3
D3
D4
D4
D5
D5
D6
D6
D7
D7
SIOSF
SIOIF
Figure 16-3 SCI Timing Diagram at POL=1
64
JUNE 2001 Ver 1.0
GMS81C5108
17. INTERRUPTS
The GMS81C5108 interrupt circuits consist of Interrupt
enable register (IENH, IENL), Interrupt request flag
(IRQH, IRQL), Interrupt Edge Selection Register (IESR),
priority circuit and Master enable flag (“I” flag of PSW).
The configuration of interrupt circuit is shown in Figure
17-1 and Interrupt priority is shown in Table 17-1 .
The flags that actually generate these interrupts are bit
INT0F, INT1F and INT2F in Register IRQH. When an external interrupt is generated, the flag that generated it is
cleared by the hardware when the service routine is vectored to only if the interrupt was transition-activated.
The Timer 0 and Timer 2 Interrupts are generated by T0IF
and T1IF, which are set by a match in their respective timer/counter register. The AD converter Interrupt is generated by ADIF which is set by finishing the analog to digital
conversion. The Basic Interval Timer Interrupt is generat-
ed by BITIF which is set by overflow of the Basic Interval
Timer Register (BITR).
Reset/Interrupt
Symbol Priority
Hardware Reset
RESET
Key Scan Interrupt
KS
BIT Interrupt
BIT
External Interrupt 0
INT0
External Interrupt 1
INT1
Timer 0 Interrupt
T0
Timer 1 Interrupt
T1
External Interrupt 2
INT2
Remocon Interrupt
REM
AD Interrupt
AD
SIO Interrupt
SIO
Watch Timer Interrupt
WT
Vector Addr.
1
2
3
4
5
6
7
8
9
10
11
FFFEH
FFFCH
FFFAH
FFF8H
FFF6H
FFF4H
FFF2H
FFF0H
FFEEH
FFECH
FFEAH
FFE8H
Table 17-1 Interrupt Priority
Internal bus line
IENH
IRQH
KSIF
BIT
BITIF
Ext. Int. 0
INT0IF
Ext. Int. 1
INT1IF
IESR
6
5
4
Timer 0
TOIF
2
Timer 1
T1IF
1
INT2IF
0
Ext. Int. 2
Remocon
REMIF
A/D Converter
ADIF
SIO
SIOIF
WT
WTIF
IRQL
Release STOP
3
Priority Control
Key Scan
Interrupt Enable
Register (Higher byte)
I-flag is in PSW, it is cleared by “DI”, set by
“EI” instruction.When it goes interrupt service,
I-flag is cleared by hardware, thus any other
interrupt are inhibited. When interrupt service is
completed by “RETI” instruction, I-flag is set to
“1” by hardware.
To CPU
I Flag
Interrupt Master
Enable Flag
Interrupt
Vector
Address
Generator
6
5
4
3
IENL
Interrupt Enable
Register (Lower byte)
Internal bus line
Figure 17-1 Block Diagram of Interrupt Function
JUNE 2001 Ver 1.0
65
GMS81C5108
The External Interrupts INT0, INT1 and INT2 can each be
transition-activated (1-to-0, 0-to-1 and both transiton).The
interrupts are controlled by the interrupt master enable flag
I-flag (bit 2 of PSW), the interrupt enable register (IENH,
IENL) and the interrupt request flag (IRQH, IRQL) except
Power-on reset and software BRK interrupt.
Interrupt enable registers are shown in Figure 17-2. These
registers are composed of interrupt enable flags of each interrupt source, these flags determine whether an interrupt
will be accepted or not. When enable flag is “0”, a corresponding interrupt source is prohibited. Note that PSW
contains also a master enable bit, I-flag, which disables all
interrupts at once. When an interrupt is occurred, the I-flag
is cleared and disable any further interrupt, the return address and PSW are pushed into the stack and the PC is vectored to. Once in the interrupt service routine the source(s)
of the interrupt can be determined by polling the interrupt
request flag bits.
The interrupt request flag bit(s) must be cleared by software before re-enabling interrupts to avoid recursive interrupts. The Interrupt Request flags are able to be read and
written.
IENH (Interrupt Enable High Register)
Bit :
7
R/W
6
R/W
5
R/W
4
R/W
3
R/W
2
R/W
1
R/W
0
-
KSE
BITE
INT0E
INT1E
T0E
T1E
INT2E
0
ADDRESS : 0DBH
RESET VALUE : -0000000B
IENL (Interrupt Enable Low Register)
Bit :
7
R/W
6
R/W
5
R/W
4
R/W
3
2
1
-
REME
ADE
SIOE
WTE
-
-
-
ADDRESS : 0DAH
RESET VALUE : -0000---B
Enables or disables the interrupt individually
If flag is cleared, the interrupt is disabled.
0 : Disable
1 : Enable
IRQH (Interrupt Request High Register)
Bit :
7
R/W
6
R/W
5
R/W
4
R/W
3
R/W
2
R/W
1
R/W
0
-
KSIF
BITIF
INT0IF
INT1IF
T0IF
T1IF
INT2IF
ADDRESS : 0DDH
RESET VALUE : -0000000B
IRQL (Interrupt Request Low Register)
Bit :
7
R/W
6
R/W
5
R/W
4
R/W
3
2
-
REMIF
ADIF
SIOIF
WTIF
-
1
-
0
-
ADDRESS : 0DCH
RESET VALUE : -0000---B
Shows the interrupt occurrence
0 : Not occurred
1 : Interrupt request is occurred
Figure 17-2 Interrupt Enable Registers and Interrupt Request Registers
17.1 Interrupt Sequence
An interrupt request is held until the interrupt is accepted
or the interrupt latch is cleared to “0” by a reset or an instruction. Interrupt acceptance sequence requires 8 f OSC (2
µs at fMAIN=4MHz) after the completion of the current instruction execution. The interrupt service task is terminated upon execution of an interrupt return instruction
[RETI].
Interrupt acceptance
1. The interrupt master enable flag (I-flag) is cleared to
“0” to temporarily disable the acceptance of any following maskable interrupts. When a non-maskable interrupt is accepted, the acceptance of any following
66
interrupts is temporarily disabled.
2. Interrupt request flag for the interrupt source accepted is
cleared to “0”.
3. The contents of the program counter (return address)
and the program status word are saved (pushed) onto the
stack area. The stack pointer decreases 3 times.
4. The entry address of the interrupt service program is
read from the vector table address and the entry address
is loaded to the program counter.
5. The instruction stored at the entry address of the interrupt service program is executed.
JUNE 2001 Ver 1.0
GMS81C5108
System clock
Instruction Fetch
SP
Address Bus
PC
Data Bus
Not used
SP-1
PCH
PCL
SP-2
PSW
V.L.
V.L.
V.H.
ADL
New PC
ADH
OP code
Internal Read
Internal Write
Interrupt Processing Step
Interrupt Service Routine
V.L. and V.H. are vector addresses.
ADL and ADH are start addresses of interrupt service routine as vector contents.
Figure 17-3 Timing chart of Interrupt Acceptance and Interrupt Return Instruction
Basic Interval Timer
Vector Table Address
Entry Address
The following method is used to save/restore the generalpurpose registers.
Example: Register saving
0FFFAH
0FFFBH
012H
0E3H
0E312H
0E313H
0EH
2EH
Correspondence between vector table address for BIT interrupt
and the entry address of the interrupt service program.
An interrupt request is not accepted until the I-flag is set to
“1” even if a requested interrupt has higher priority than
that of the current interrupt being serviced.
When nested interrupt service is required, the I-flag should
be set to “1” by “EI” instruction in the interrupt service
program. In this case, acceptable interrupt sources are selectively enabled by the individual interrupt enable flags.
Saving/Restoring General-purpose Register
During interrupt acceptance processing, the program
counter and the program status word are automatically
saved on the stack, but accumulator and other registers are
not saved itself. If necessary, these registers should be
saved by the software. Also, when multiple interrupt services are nested, it is necessary to avoid using the same
data memory area for saving registers.
JUNE 2001 Ver 1.0
INTxx:
PUSH
PUSH
PUSH
A
X
Y
;SAVE ACC.
;SAVE X REG.
;SAVE Y REG.
interrupt processing
POP
POP
POP
RETI
Y
X
A
;RESTORE Y REG.
;RESTORE X REG.
;RESTORE ACC.
;RETURN
General-purpose registers are saved or restored by using
push and pop instructions.
main routine
acceptance of
interrupt
interrupt
service routine
saving
registers
restoring
registers
interrupt return
67
GMS81C5108
17.2 BRK Interrupt
Software interrupt can be invoked by BRK instruction,
which has the lowest priority order.
Interrupt vector address of BRK is shared with the vector
of TCALL 0 (Refer to Program Memory Section). When
BRK interrupt is generated, B-flag of PSW is set to distinguish BRK from TCALL 0.
B-FLAG
=1
BRK or
TCALL0
Each processing step is determined by B-flag as shown in
Figure 17-4.
=0
BRK
INTERRUPT
ROUTINE
TCALL0
ROUTINE
RETI
RET
Figure 17-4 Execution of BRK/TCALL0
17.3 Multi Interrupt
If two requests of different priority levels are received simultaneously, the request of higher priority level is serviced. If requests of the interrupt are received at the same
time simultaneously, an internal polling sequence determines by hardware which request is serviced.
However, multiple processing through software for special
features is possible. Generally when an interrupt is accepted, the I-flag is cleared to disable any further interrupt. But
as user sets I-flag in interrupt routine, some further interrupt can be serviced even if certain interrupt is in progress.
Example: Even though Timer1 interrupt is in progress,
INT0 interrupt serviced without any suspend.
TIMER1: PUSH
PUSH
PUSH
LDM
LDM
EI
:
:
:
:
:
:
LDM
LDM
POP
POP
POP
RETI
68
A
X
Y
IENH,#80H
IENL,#0
.
Main Program
service
TIMER 1
service
enable INT0
disable other
INT0
service
EI
Occur
TIMER1 interrupt
Occur
INT0
enable INT0
enable other
;Enable INT0 only
;Disable other
;Enable Interrupt
In this example, the INT0 interrupt can be serviced without any
pending, even TIMER1 is in progress.
Because of re-setting the interrupt enable registers IENH,IENL
and master enable "EI" in the TIMER1 routine.
IENH,#0FFH ;Enable all interrupts
IENL,#0F0H
Y
X
A
Figure 17-5 Execution of Multi Interrupt
JUNE 2001 Ver 1.0
GMS81C5108
17.4 External Interrupt
The external interrupt on INT0, INT1 and INT2 pins are
edge triggered depending on the edge selection register
IESR (address 0D8H) as shown in Figure 17-6.
The edge detection of external interrupt has three transition
activated mode: rising edge, falling edge, and both edge.
INT0
INT0IF
INT1IF
edge selection
INT1
INT2
INT2IF
INT0 INTERRUPT
INT1 INTERRUPT
INT2 INTERRUPT
IESR
[0D8H]
IESR (Ext. Interrupt Edge Selection Register)
Interrupt Edge Selection Register)
Bit :
7
6
R/W
5
R/W
4
R/W
3
R/W
2
R/W
1
R/W
0
-
-
INT21
INT20
INT11
INT10
INT01
INT00
INT2[1:0] (INT2 Edge Selections)
00 : Int. Disable
01 : Falling (1-to-0 transition)
10 : Rising (0-to-1 transition)
11 : Both (Rising & Falling)
INT1[1:0] (INT1 Edge Selection)
00 : Int. Disable
01 : Falling (1-to-0 transition)
10 : Rising (0-to-1 transition)
11 : Both (Rising & Falling)
Example: To use as an INT0 and INT2
:
:
;**** Set port as an input port R0
LDM
R0DR,#1111_1010B
;
;**** Set port as an interrupt port
LDM
PMR,#0000_0101B
;
;**** Set Falling-edge Detection
LDM
IESR,#0001_0001B
:
:
:
Response Time
The INT0, INT1 and INT2 edge are latched into INT0F,
INT1F and INT2F at every machine cycle. The values are
not actually polled by the circuitry until the next machine
cycle. If a request is active and conditions are right for it to
be acknowledged, a hardware subroutine call to the requested service routine will be the next instruction to be
executed. The DIV itself takes twelve cycles. Thus, a maximum of twelve complete machine cycles elapse between
activation of an external interrupt request and the beginning of execution of the first instruction of the service routine.
Interrupt response timings are shown in Figure 17-7.
ADDRESS : 0D8H
RESET VALUE : --000000B
INT0[1:0] (INT0 Edge Selections)
00 : Int. Disable
01 : Falling (1-to-0 transition)
10 : Rising (0-to-1 transition)
11 : Both (Rising & Falling)
Figure 17-6 External Interrupt Block Diagram
max. 12 fOSC
Interrupt Interrupt
latched
goes
active
8 fOSC
Interrupt
processing
Interrupt
routine
Figure 17-7 Interrupt Response Timing Diagram
JUNE 2001 Ver 1.0
69
GMS81C5108
18. KEY SCAN
The key-scan block consists of key scan mode register
(KSMR) and R1 pull-up register (R1PU). When the key
scan interrupt is used, key scan mode register KSMR (address 0F0H) should be set properly as shown in Figure 181. The pins which is to be used as key scan input should be
set by KSMR and the strobe output pins should be set as
open drain. The strobe output pins could be selected from
among R0[7:0], R1[7:0], R2[3:0] and R3[3:0].
If the “L” signal is input to any one or more of key scan input pins, the KSIF request flag is set to “1”. This generates
an interrupt request. It also can be used in the way of release from STOP mode.
VDD
R1PU[7:0]
KSMR
R10/KS0
R11/KS1
R12/KS2
Key Scan
Interrupt
R13/KS3
KSIF
R14/KS4
R15/KS5
R16/KS6
R17/KS7
KSMR (Key Scan Mode Register)
Bit :
R/W
7
R/W
6
R/W
5
R/W
4
R/W
3
R/W
2
R/W
1
R/W
0
KS7
KS6
KS5
KS4
KS3
KS2
KS1
KS0
ADDRESS : 0F0H
RESET VALUE : 00H
0 : Port Function (I/O) Selection
1 : Key Scan Input Selection
Figure 18-1 Key Scan Interrupt Block Diagram
Usage of Key Scan
When key board scanning, it is recommended that set the
output strobe to “L” first and then read R1 port after 60us
delay time. Because the rising time of the output strobe
port from “L” to “H” is so long. The Figure 18-2 explain
this reason.
;Program Example,
LDM
CALL
LDA
R3,#0000_1110b ;R3<0> Port set to low
Delay_60us
;60us time delay routine
R1
;read R1 port
If the rising time is so long, the key scanning could be
detected double key with R3<0> and R3<1>.
60µs
R3<0>
60µs
R3<1>
R1 Port Read Timing
Figure 18-2 Key Scan Timing
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JUNE 2001 Ver 1.0
GMS81C5108
19. LCD DRIVER
The GMS81C5108 has the circuit that directly drives the
liquid crystal display (LCD) and its control circuit. The
Segment/Common Driver directly drives the LCD panel,
and the LCD Controller generates the segment/common
signals according to the RAM which stores display data. In
addition, VCL2 ~ VCL0 pin are provided as the drive power pins.
The GMS81C5108 has the following pins connected with
LCD.
1. Segment output port 37 pins (SEG0-SEG36)
2.Common output port 4 pins (COM0-COM3)
19.1 Configuration of LCD driver
Figure 19-1 shows the configuration of the LCD driver.
WTMR[1:0]
01
fSUB
fMAIN÷27
10
fMAIN
00
MUX
Prescaler
÷ 32
÷ 64
÷ 128
MUX
÷ 256
clock
LCD
Timing Control
INTERNAL BUS LINE
(37Nibbles)
Segment/Common Driver
Display Memory
Display Data Buffer register
Display Data Select Control
SEG0
SEG33
SEG34/COM3
Select clock
SEG35/COM2
LCD
Control Register
LCDEN
SEG36/COM1
Select Duty
COM0
LCR[0F1H]
Figure 19-1 LCD Driver Block Diagram
JUNE 2001 Ver 1.0
71
GMS81C5108
19.2 Control of LCD Driver Circuit
The LCD driver is controlled by the LCD Control Register
(LCR). The LCR[1:0] determines the frequency of COM
signal scanning of each segment output. RESET clears the
LCD control register LCR values to logic zero. The LCD
display can continue to operate during SLEEP and STOP
modes if a sub-frequency clock is used as system clock
source. The constant voltage booster circuit for using LCD
driver is built in, so the definite voltage could supplied regardless of power source voltage fluctuations.
Note: The Sub clock is used as voltage booster source
clock, so the stabilization time is need to use voltage booster. Normally, the stabilization time is need more than
500ms. The external bias registers cannot be used for LCD
display supply voltage.
LCR(LCD Control Register)
Bit :
7
6
R/W
5
R/W
4
R/W
3
R/W
2
R/W
1
R/W
0
-
-
LCDEN
VBCL
LCDD1
LCDD0
LCK1
LCK0
ADDRESS : 0F1H
RESET VALUE : --000000B
LCDEN (LCD Display Enable Bit)
0: LCD Display Disable
1: LCD Display Enable
VBCL (Voltage Booster Enable Bit)
0: Voltage Booster Disable
1: Voltage Booster Enable
LCDD[1:0] (LCD Duty Selection)
00: 1/4 Duty
01: 1/3 Duty (COM[3] are used as SEG[34])
10: 1/2 Duty (COM[3:2] are used as SEG[34:35])
11: Static (COM[3:1] are used as SEG[34:36])
LCK (LCD Clock source selection)
00: fS ÷ 32
01: fS ÷ 64
10: fS ÷ 128
11: fS ÷ 256
*The fs can be selected among fSUB (Sub clock), fMAIN÷27 (Main clck) and fMAIN (Main clock).
And sub or main is selected by WTCK[1:0] of WTMR.
Figure 19-2 LCD Control Register
Selecting Frame Frequency
Frame frequency is set to the base frequency as shown in
the following Table 19-1. The fS is selected to fSUB (sub
clock) which is 32.768kHz.
Frame Frequency (Hz)
LCR[1:0]
00
01
10
11
LCD clock
fS ÷ 32
fS ÷ 64
fS ÷ 128
fS ÷ 256
Duty = Static
Duty = 1/2
Duty = 1/3
Duty = 1/4
1024
512
256
128
512
256
128
64
341.3
170.7
85.3
42.7
256
128
64
32
Table 19-1 Setting of LCD Frame Frequency
The matters to be attended to use LCD driver
In reset state, LCD source clock is sub clock. So, when the
power is supplied, the LCD display would be flickered before the oscillation of sub clock is stabilized. It is recommended to use LCD display on after the stabilization time
of sub clock is considered enough. If the LCD is reset during display, the display would be blotted by the capacity of
LCD power circuit. The external circuit of constant voltage
booster for using LCD driver is shown at right.
VCL2
VCL1
VCL0
GMS81C5108
GMS87C5108
C1~C4=0.47uF
R1=400KΩ
R2=1MΩ
R1
C1
C2
C3
R2
CAPH
C4
CAPL
Figure 19-3 LCD Power Booster Circuit
72
JUNE 2001 Ver 1.0
GMS81C5108
19.3 LCD Display Memory
Display data are stored to the display data area (page 1) in
the data memory.
The display data stored to the display data area (address
0100H-0124H) are read automatically and sent to the LCD
driver by the hardware. The LCD driver generates the segment signals and common signals in accordance with the
display data and drive method. Therefore, display patterns
can be changed by only overwriting the contents of the display data area with a program. The table look up instruction is mainly used for this overwriting.
Figure 19.3 shows the correspondence between the display
data area and the SEG/COM pins. The LCD lights when
the display data is “1” and turn off when “0”.
Bit
0
1
2
3
4
5
6
7
SEG36
0124H
SEG35
0123H
SEG34
0122H
SEG33
0121H
SEG32
0120H
SEG31
011FH
SEG30
011EH
SEG29
011DH
SEG28
011CH
SEG27
011BH
SEG26
011AH
LCD display memory in this location that are not used for
LCD display can be allocated for general purpose use.
SEG25
0119H
SEG24
0118H
The SEG data for display is controlled by RPR (RAM Paging Register).
SEG23
0117H
SEG22
0116H
SEG21
0115H
SEG20
0114H
SEG19
0113H
6
5
4
-
-
-
-
R/W
3
R/W
2
R/W
1
R/W
0
-
-
RPR1
RPR0
ADDRESS : 0F3H
RESET VALUE : ------00B
RAM Page Instruction
RPR1
RPR0
0 Page
CLRG
x
x
0 Page
SETG
0
0
1 Page
SETG
0
1
0111H
SEG16
0110H
SEG15
010FH
SEG14
010EH
SEG13
010DH
SEG12
010CH
SEG11
010BH
SEG10
010AH
SEG9
0109H
SEG8
0108H
SEG7
0107H
SEG6
0106H
SEG5
0105H
SEG4
0104H
SEG3
0103H
SEG2
0102H
SEG1
0101H
SEG0
0100H
COM0
Figure 19-4 Setting of RAM Paging Register
0112H
SEG17
COM3
7
COM2
Bit :
SEG18
COM1
RPR (RAM Paging Register)
Figure 19-5 LCD Display Memory
JUNE 2001 Ver 1.0
73
GMS81C5108
19.4 Control Method of LCD Driver
Initial Setting
Flow chart of initial setting is shown in Figure 19-6.
Example: Driving of LCD
Select Frame Frequency
Clear
LCD Display
Memory
Turn on LCD
LDM
:
LDM
SETG
LDX
C_LCD1: LDA
STA
CMPX
BNE
CLRG
:
SET1
:
LCR,#12H
;fF=64Hz, 1/4 duty(fSUB= 32.768kHz)
RPR,#1
;Select LCD Memory(1 page)
#0
#0
;RAM Clear
;(0100H->0124H)
{X}+
#025H
C_LCD1
LCR.5
;Enable display
.
COM0
COM1
Setting of LCD drive method
COM2
COM3
SEG0
SEG1
Initialize of display memory
Example: display “2”
Enable display
bit 7
6
5
4
3
2
1
0
100H
*
*
*
*
0
0
1
1
101H
*
*
*
*
1
1
1
0
Note: * are don’t care.
Figure 19-6 Initial Setting of LCD Driver
Figure 19-7 Example of Connection COM & SEG
Display Data
Normally, display data are kept permanently in the program memory and then stored at the display data area by
the table look-up instruction. This can be explained using
character display with 1/4 duty LCD as an example as well
as any LCD panel. The COM and SEG connections to the
LCD and display data are the same as those shown is Figure 19-7. Following is showing the Programming example
for displaying character.
74
Note: When power on RESET, sub oscillation start up time
is required. Enable LCD display after sub oscillation is stabilized, or LCD may occur flicker at power on time shortly.
JUNE 2001 Ver 1.0
GMS81C5108
:
CLRG
LDX
GOLCD:
Write into the
LCD Memory
FONT
Font data
LDA
TAY
LDA
LDM
SETG
LDX
STA
XCN
STA
CLRG
:
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
#<DISPRAM
;Address included the data
;to be displayed.
{X}
!FONT+Y
RPR,#1
;LOAD FONT DATA
;Set RPR = 1 to access LCD
;Set Page 1
#0
{X}+
;LOWER 4 BITS OF ACC. seg0
{X}
;UPPER 4 BITS OF ACC. seg1
;Set Page = 0
1101_0111B
0000_0110B
1110_0011B
1010_0111B
0011_0110B
1011_0101B
1111_0101B
0000_0111B
1111_0111B
0011_0111B
;
;
;
;
;
;
;
;
;
;
“0”
“1”
“2”
“3”
“4”
“5”
“6”
“7”
“8”
“9”
LCD Waveform
The LCD duty can be selected by LCR register. The kinds
of LCD waveforms are four totally. Among them, static
COM3
COM2
COM1
COM0
1/4 Duty, 1/3 Bias Drive
and 1/4 duty waveforms are shown Figure 19-8.
COM0
VCL2
VCL1
VCL0
GND
COM1
VCL2
VCL1
VCL0
GND
COM2
VCL2
VCL1
VCL0
GND
COM3
VCL2
VCL1
VCL0
GND
SEG0
SEG1
COM0
COM1
COM2
SEG0
COM3
SEG0
SEG1
SEG1
VCL2
VCL1
VCL0
GND
VCL2
VCL1
VCL0
GND
SEG0 - COM0
VCL2
VCL1
VCL0
0
-VCL0
-VCL1
-VCL2
SEG1 - COM0
VCL2
VCL1
VCL0
0
-VCL0
-VCL1
-VCL2
Figure 19-8 Example of LCD drive output
JUNE 2001 Ver 1.0
75
GMS81C5108
20. REMOCON CARRIER GENERATOR
The GMS81C5108 has a circuit to generate carriers for the
remote controller. This circuit consists of Remocon Mode
Register (RMR), Carrier Frequency High Selection (CFHS), Carrier Frequency Low Selection (CFLS), Remocon
Data High Register (RDHR), Remocon Data Low Register
(RDLR), Remocon Data Counter (RDC), Remocon Output
Data Register (RODR) and Remocon Output Buffer
(ROB) as shown in Figure 20-1. A carrier duty and frequency are determined by the contents of these registers. A
source clock input to the 6-bit counter is selected by diving
the frequency of the system clock by two (main or sub
clock).
20.1 Remocon Signal Output Control
The output of the REMOUT pin which outputs carriers is
controlled by RODR and ROB register. While the Bit-0 of
RODR is “1”, the REMOUT pin outputs a carrier signal
generated by the remote controller carrier generator. While
this Bit is “0”, the output of the REMOUT pin is low.
RODR by an interrupt signal generated by the 8-Bit timer.
The content of the RODR.0 is output to the REMOUT pin.
Namely, the REMOUT pin outputs a high-level signal
when RODR.0 is “1” and a low-level signal when RODR.0
is “0”.
The content of the ROB is automatically transferred to the
REN ≠ 0
RDCK[2:0]
2
÷8
fxin ÷ 16
fxin ÷ 32
fxin ÷ 64
fxin ÷ 128
fxin ÷ 256
fxin ÷ 512
fxin
fxin is fMAIN or fSUB.
SCMR[1:0]
2
XIN
0X
SXIN
1X
Prescaler
RDHR (8-Bit)
RDLR (8-Bit)
Comparator
REMF
MUX
Remocon
Interrupt
RDC(8Bit)
RDPE
REN
ROB (1Bit)
÷1
fxin ÷ 2
fxin ÷ 4
fxin ÷ 8
fxin
MUX
6-Bit Counter
RODR (1Bit)
Comparator
REMOUT
REN ≠ 0
& CCK[1:0]
CFHS (6-Bit)
CFLS (6-Bit)
RMR (Remocon Mode Register)
Bit :
7
-
R/W
6
R/W
5
R/W
4
R/W
3
R/W
2
R/W
1
R/W
0
REN
CCK1
CCK0
RDPE
RDCK2
RDCK1
RDCK0
ADDRESS : 0F6H
RESET VALUE : -0000000B
REN (Remocon Operation Enable)
0 : Disable
1 : Enable
RDPE (Remocon Data Pulse Enable)
0 : Disable
1 : Enable
RDCK[2:0] (Remocon Data Clock Selection)
000: fMAIN÷23 or fSUB÷23
001: fMAIN÷24 or fSUB÷24
010: fMAIN÷25 or fSUB÷25
011: fMAIN÷26 or fSUB÷26
100: fMAIN÷27 or fSUB÷27
101: fMAIN÷28 or fSUB÷28
110: fMAIN÷29 or fSUB÷29
111: Carrier Signal
CCK[1:0] (Carrier Clock Source Selection)
or fSUB
00: fMAIN
01: fMAIN÷2 or fSUB÷2
2
10: fMAIN÷2 or fSUB÷22
11: fMAIN÷23 or fSUB÷23
fMAIN: main-clock frequency
fSUB: sub-clock frequency
Figure 20-1 Remocon Carrier Generator Block Diagram
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JUNE 2001 Ver 1.0
GMS81C5108
CFHS (Carrier Frequency High Selection)
Bit :
7
-
W
5
W
4
W
3
W
2
W
1
W
0
CFH5
CFH4
CFH3
CFH2
CFH1
CFH0
6
-
ADDRESS : 0F7H
RESET VALUE : --111111B
Carrier High Interval = The Value of CFHS x Clock Source Period
CFLS (Carrier Frequency Low Selection)
Bit :
7
-
W
5
W
4
W
3
W
2
W
1
W
0
CFL5
CFL4
CFL3
CFL2
CFL1
CFL0
6
-
ADDRESS : 0F8H
RESET VALUE : --111111B
Carrier Low Interval = The Value of CFLS x Clock Source Period
RDHR (Remocon Data High Register)
Bit :
W
7
RDH7
W
6
RDH6
W
5
W
4
RDH5
RDH4
W
3
W
2
W
1
W
0
RDH3
RDH2
RDH1
RDH0
ADDRESS : 0F9H
RESET VALUE : 11111111B
Remocon Data High Interval = The Value of RDHR x Clock Source Period
RDLR (Remocon Data Low Register)
Bit :
W
7
RDL7
W
6
RDL6
W
5
RDL5
W
4
RDL4
W
3
W
2
W
1
W
0
RDL3
RDL2
RDL1
RDL0
ADDRESS : 00FAH
RESET VALUE : 11111111B
Remocon Data Low Interval = The Value of RDLR x Clock Source Period
RDC (Remocon Data Counter)
Bit :
R
7
RDC7
R
6
RDC6
R
5
R
4
R
3
R
2
R
1
R
0
RDC5
RDC4
RDC3
RDC2
RDC1
RDC0
1
R/W
0
ADDRESS : 00FAH
RESET VALUE : 00000000B
Remocon Data Counter Value
RODR (Remocon Output Data Register)
Bit :
7
-
6
-
5
4
3
2
-
-
-
-
-
RDD0
ADDRESS : 0FBH
RESET VALUE : -------0B
Remocon Data Output Value
ROB (Remocon Output Buffer)
Bit :
7
-
6
5
4
3
2
1
R/W
0
-
-
-
-
-
-
RDB0
ADDRESS : 0FCH
RESET VALUE : -------0B
Remocon Data Output Buffer
Figure 20-2 Remocon Registers
20.2 Carrier Frequency
The carrier frequency and the pulse of data are calculated
by below formula. The the lengths of carrier frequency and
pulse of data are shown in Figure 20-3.
JUNE 2001 Ver 1.0
tH = source clock(RMR[5:4]) × CFHS
tL = source clock(RMR[5:4]) × CFHS
fC (Carrier Frequency) = 1/(tH+tL)
tDH = source clock(RMR[2:0]) × RDHR
tDL = source clock(RMR[2:0]) × RDLR
77
GMS81C5108
tH
tL
Carrier Frequency
tDL
tDH
Pulse of Data
ROD0 = 01H
ROD0 = 00H
As soon as the carrier interrupt is occurred,
the content of ROB is transferred to RODR.
Figure 20-3 Carrier Frequency & Pulse of Data
The Table 20-1 shows high and low length of carrier frequency according to CFLS and CFHS. This only shows
Set Value
Selection of PS0
Selection of PS2
when the source clock is selected fMAIN and fMAIN÷22 at
4MHz.
Set Value
Selection of PS0
Selection of PS2
CFHS
CFLS
tH(us)
tL(us)
tH(us)
tL(us)
CFHS
CFLS
tH(us)
tL(us)
tH(us)
tL(us)
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
2.50
2.75
3.00
3.25
3.50
3.75
4.00
4.25
4.50
4.75
5.00
5.25
5.50
5.75
6.00
6.25
6.50
6.75
7.00
7.25
7.50
7.75
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
2.50
2.75
3.00
3.25
3.50
3.75
4.00
4.25
4.50
4.75
5.00
5.25
5.50
5.75
6.00
6.25
6.50
6.75
7.00
7.25
7.50
7.75
1.00
2.00
3.00
4.00
5.00
6.00
7.00
8.00
9.00
10.00
11.00
12.00
13.00
14.00
15.00
16.00
17.00
18.00
19.00
20.00
21.00
22.00
23.00
24.00
25.00
26.00
27.00
28.00
29.00
30.00
31.00
1.00
2.00
3.00
4.00
5.00
6.00
7.00
8.00
9.00
10.00
11.00
12.00
13.00
14.00
15.00
16.00
17.00
18.00
19.00
20.00
21.00
22.00
23.00
24.00
25.00
26.00
27.00
28.00
29.00
30.00
31.00
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
8.00
8.25
8.50
8.75
9.00
9.25
9.50
9.75
10.00
10.25
10.50
10.75
11.00
11.25
11.50
11.75
12.00
12.25
12.50
12.75
13.00
13.25
13.50
13.75
14.00
14.25
14.50
14.75
15.00
15.25
15.50
15.75
8.00
8.25
8.50
8.75
9.00
9.25
9.50
9.75
10.00
10.25
10.50
10.75
11.00
11.25
11.50
11.75
12.00
12.25
12.50
12.75
13.00
13.25
13.50
13.75
14.00
14.25
14.50
14.75
15.00
15.25
15.50
15.75
32.00
33.00
34.00
35.00
36.00
37.00
38.00
39.00
40.00
41.00
42.00
43.00
44.00
45.00
46.00
47.00
48.00
49.00
50.00
51.00
52.00
53.00
54.00
55.00
56.00
57.00
58.00
59.00
60.00
61.00
62.00
63.00
32.00
33.00
34.00
35.00
36.00
37.00
38.00
39.00
40.00
41.00
42.00
43.00
44.00
45.00
46.00
47.00
48.00
49.00
50.00
51.00
52.00
53.00
54.00
55.00
56.00
57.00
58.00
59.00
60.00
61.00
62.00
63.00
Table 20-1 Length of Carrier Frequency (at 4MHz)
78
JUNE 2001 Ver 1.0
GMS81C5108
Example:
Carrier Frequency = 37.8kHz, high = 8.52ms, low = 4.24ms, @4MHz
Rem_sig: LDM
LDM
LDM
CLR1
LDM
LDM
LDM
LDX
Loop1:
RMR,#0001_0010B
CFHS,#18
CFLS,#35
ROD0
R_bit,#1111_1000B
RDHR,#213
RDLR,#177
#9
CALL
SET1
SET1
SET1
DATA
RMR.6
RMR.3
IENL.6
NOP
CMPX
BNE
#0
Loop1
Finish: CLR1
CLR1
RET
ROD0
ROB0
;********
Data:
ROL
BCS
CLR1
RET
R_bit
Set_rob0
ROB0
;carrier clock(PS1), remocon data clock(PS5)
;carrier low(IR LED)=18*PS1(0.5us)=9us
;carrier high(IR LED)=35*PS1(0.5us)=17.5us
;213*5*PS5(8us)=8.52ms
;177*3*PS5(8us)=4.248ms
;Remocon operation enable
;Remocon data pulse enable
;Remocon int.
Set_rob0:SET1ROB0
RET
;***********************************************;
;
Remocon int service routine
;
;***********************************************;
;
Remocon_INT:
CALL
DEC
RETI
Data
X
JUNE 2001 Ver 1.0
79
GMS81C5108
21. OSCILLATOR CIRCUIT
The GMS81C5108 has two oscillation circuits internally.
XIN and XOUT are input and output for main frequency and
SXIN and SXOUT are input and output for sub frequency,
respectively, inverting amplifier which can be configured
for being used as an on-chip oscillator, as shown in Figure
21-1.
C3
C1
XOUT
C2
4.19MHz
SXOUT
C4
XIN
32.768KHz
VSS
VSS
Recommend
Crystal Oscillator
C1,C2 = 20pF
Ceramic Resonator
C1,C2 = 20pF
SXIN
Recommend
C3,C4 = 30pF
Crystal or Ceramic Oscillator
Open
XOUT
XOUT
REXT
External Clock
Select R value according to AC Characteristics.
The Cap. is built in(5pF).
XIN
XIN
External Oscillator
RC Oscillator
Figure 21-1 Oscillation Circuit
Oscillation circuit is designed to be used either with a ceramic resonator or crystal oscillator. Since each crystal and
ceramic resonator have their own characteristics, the user
should consult the crystal manufacturer for appropriate
values of external components.
In addition, see Figure 21-2 for the layout of the crystal.
XOUT
Note: Minimize the wiring length. Do not allow the wiring to
intersect with other signal conductors. Do not allow the wiring to come near changing high current. Set the potential of
the grounding position of the oscillator capacitor to that of
VSS. Do not ground it to any ground pattern where high current is present. Do not fetch signals from the oscillator.
XIN
Figure 21-2 Layout of Oscillator PCB circuit
80
JUNE 2001 Ver 1.0
GMS81C5108
22. RESET
The GMS81C5108 have two types of reset generation procedures; one is an external reset input, the other is a watchOn-chip Hardware
Program counter
RAM page register
Initial Value
(PC)
dog timer reset. Table 22-1 shows on-chip hardware initialization by reset action.
On-chip Hardware
(FFFFH) - (FFFEH)
Initial Value
Peripheral clock
On
(RPR)
0
SVD
(G)
0
Control registers
Refer to Table 8-1 on page 25
Main-frequency clock
Voltage Booster
Disable
G-flag
Operation mode
Enable
Table 22-1 Initializing Internal Status by Reset Action
22.1 External Reset Input
The reset input is the RESET pin, which is the input to a
Schmitt Trigger. A reset in accomplished by holding the
RESET pin to low for at least 8 oscillator periods, within
the operating voltage range and oscillation stable, it is applied, and the internal state is initialized. After reset,
65.5ms (at 4MHz) add with 7 oscillator periods are required to start execution as shown in Figure 22-2.
A connection for simple power-on-reset is shown in Figure
22-1.
VDD
VDD
100kΩ
Mask Option
RESET
Internal RAM is not affected by reset. When VDD is turned
on, the RAM content is indeterminate. Therefore, this
RAM should be initialized before read or tested it.
+
1uF
−
MCU
GND
When the RESET pin input goes to high, the reset operation is released and the program execution starts at the vector address stored at FFFEH - FFFFH.
Figure 22-1 Simple Power-on-Reset Circuit
1
3
?
?
4
5
6
7
~
~
2
System Clock
~
~
RESET
?
?
FFFE FFFF Start
~
~ ~
~
?
?
?
?
FE
ADL
ADH
OP
~
~
DATA
BUS
~
~
ADDRESS
BUS
Stabilization Time
tST = 65.5mS at 4MHz
RESET Process Step
tST =
1
fMAIN ÷1024
MAIN PROGRAM
x 256
Figure 22-2 Timing Diagram after RESET
22.2 Watchdog Timer Reset
Refer to “13.2 Watch Dog Timer” on page 57.
JUNE 2001 Ver 1.0
81
GMS81C5108
23. SUPPLY VOLTAGE DETECTION
The GMS81C5108 has an on-chip low voltage detection
circuitry to detect the VDD voltage. A configuration register, SCMR, can enable or disable the low voltage detect
circuitry. This GMS81C5108 has two level detector(SVD0, SVD1). The SVD0 flag is set when the V DD
falls below 2.2V and if the V DD is rise above 2.2V the
SVD0 is cleared automatically. The SVD1 flag is set when
the VDD falls below 1.7V and if this flag is set once, it is
SCMR (System
Clock Mode Register)
MSB
R/W
R/W
R/W
R
R/W
R/W
not cleared automatically although the VDD rises above
1.7V. It can be cleared by writing.
If the SVD1 is set, the MCU can be RESET or frozen by
the flag SVRT. In the in-circuit emulator, supply voltage
detection is not implemented and user can not experiment
with it. Therefore, after final development of user program,
this function may be experimented or evaluated.
R/W
LSB
R/W
ADDRESS: 0F5H
INITIAL VALUE: 00H
SYCC[1:0] (System clock control)
00: main clock on
01: main clock on
10: sub clock on (main clock on)
11: sub clock on (main clock off)
SCS[1:0] (System clock source select)
fMAIN÷2 or fSUB÷2
fMAIN÷23 or fSUB÷23
fMAIN÷24 or fSUB÷24
6
6
SVRT (System Reset Control by SVD1 Bit) fMAIN÷2 or fSUB÷2
0 : System reset by SVD1 Flag
1 : Don’t system reset by SVD1 Flag (Freeze)
SVD[1:0] (SVD Flag)
SVD0 : set at VDD=2.2V
SVD1 : set at VDD=1.7V
SVEN (SVD Operation Enable Bit)
0 : SVD Operation Enable
1 : SVD Operation Disable
* The values of 1.7V and 2.2V could be changed by ±0.2V according to the process of work.
Figure 23-1 Low Voltage Detector Register
VDD
Internal
RESET
VDD
SVD MAX
SVD MIN
65.5mS
SVD MAX
SVD MIN
When SVRT = 0
Internal
RESET
65.5mS
t < 65.5mS
VDD
Internal
RESET
SVD MAX
SVD MIN
65.5mS
VDD
SVD MAX
SVD MIN
System
Clock
When SVRT = 1
VDD
SVD MAX
SVD MIN
System
Clock
Figure 23-2 Power Fail Processor Situations
82
JUNE 2001 Ver 1.0
GMS81C5108
24. DEVEMOPMENT TOOLS
24.1 OTP Programming
The GMS87C5108 is an OTP (One Time Programmable) microcontrollers. Its internal user memory is constructed with EPROM
(Electrically Programmable Read Only Memory).
Programming Procedure
The OTP microcontroller is generally used for chip evaluation,
first production, small amount production, fast mass production,
etc.
2. Load the *.OTP file from the PC. The file is composed
of Motorola-S1 format.
1. Select device GMS87C5108 you want.
3. Set the programming address range as below table.
Blank OTP’s internal EPROM is filled by 00H, not FFH.
Note: In any case, you have to use the *.OTP file for programming, not the *.HEX file. After assemble, both OTP
and HEX file are generated by automatically. The HEX file
is used during program emulation on the emulator.
Address
Set Value
Buffer start address
E000H
Buffer end address
FFFFH
Device start address
E000H
How to Program
4. Mount the socket adapter on the programmer.
To program the OTP devices, user can use Hynix own programmer.
5. Start program/verify.
Hynix own programmer list
Manufacturer: Hynix Semiconductor Programmer:
Choice-Sigma
Choice-Gang4
The Choice-Sigma is a Hynix Universal Single Programmer for
all of Hynix OTP devices, also the Choice-Gang4 can program
four OTPs at once for Hynix OTP.
Ask to Hynix sales part for purchasing or more detail
Pin Function
VPP (Program Voltage)
VPP is the input for the program voltage for programming the
EPROM.
CE (Chip Enable)
CE is the input for programming and verifying internal EPROM.
OE (Output Enable)
OE is the input of data output control signal for verify.
A0~A15 (Address Bus)
A0~A15 are address input pins for internal EPROM.
O0~O7 (EPROM Data Bus)
These are data bus for internal EPROM.
JUNE 2001 Ver 1.0
83
VLCDC
OFF ON
SW 5
1
2
3
4
5
6
7
SW 4
LCD_VDD
RUN
STOP
GMS81C51 EVA
VR2
VR1
POWER
X2
/RESET
2 1
SW 1
RESET
SW 2
SLEEP
External Oscillator
Socket
+5V
CHOICE-Dr. EVA 81C51 B/D Rev 1.0 S/N. ---------------
24.2 Emulator S/W Setting
GMS81C5108
CONNECTB
1
2
CONNECTA
XOUT
J_USERB J_USERA
OFF ON
X1 (OSC)
CONNECTC
V_USER
SEG46
SEG44
SEG42
SEG40
SEG38
VREG
COM1/S36
COM3/S34
SEG32
SEG30
SEG28
SEG26
SEG24
SEG22
SEG20
SEG18
SEG16
SEG14
SEG12
SEG10
SEG8
SEG6
SEG4
SEG2
SEG0
JUNE 2001 Ver 1.0
J_USERA
GND
SEG47
VCL0
SEG45
VCL2
SEG43
CA
SEG41
GND
SEG39
/U_RST
SEG37
U_XOUT
COM0
GND
COM2/S35
R37
SEG33
R35
SEG31
R20
SEG29
R22
SEG27
R24
SEG25
R26
SEG23
R17
SEG21
R15
SEG19
R13
SEG17
R11
SEG15
R07
SEG13
R05
SEG11
R03
SEG9
R01
SEG7
R33
SEG5
R31
SEG3
+5V
SEG1
GND
VCL1
VLCDC
CB
GND
REMOUT (TONED)
GND
R36
R34
R21
R23
R25
R27
R16
R14
R12
R10
R06
R04
R02
R00
R32
R30
+5V
84
J_USERB
GMS81C5108
DIP Switch and VR Setting
Before execute the user program, keep in your mind the below configuration
DIP S/W, VR
SW1
-
Description
ON/OFF Setting
Emulator Reset Switch. Reset the Emulator.
Reset the Emulator.
Normally OFF.
EVA. chip can be reset by external
user target system board.
ON : Reset is available by user
target system board.
OFF : MCU is reset by REST switch
on EVA. board.
SW2-1
EVA.
Chip
1
RESET pin
OFF ON
SW2
Normally OFF.
MCU XOUT pin are disconnected
by Emulator internally. Some circumstance user may connect this
circuit.
ON : Output XOUT signal
OFF : Disconnect circuit
SW2-2
XOUT pin
EVA.
Chip
2
Oscillator
External Resistor
and Capacitor
VDD
Adjust Contrast
SW4-1
1
2
3
VCL2
SW4-2
10kΩ × 3
VCL1
OFF ON
Normally ON.
It serves the external bias resistors.
If user want to use external circuit
instead of internal R, turn on these
switches.
SW4-3
VCL0
0.47uF × 3
SW4
VR1 50kΩ
4
5
6
7
VSS
LCD Voltage booster circuit.
Must be ON position.
It is used for the GMS81C5108.
Select the Stack Page.
Must be OFF position.
This switch decide the Stack page 0
(off) or page 1 (on).
ON : For the GMS81C7XXX
OFF : For the GMS81C5108
VDD
EVA.
Chip
LVD pin
SW4-8
8
GMS81C5108 detect the VDD voltage but Emulator can not do
because Emulator can not operate if VDD is below normal opr.
voltage (5V), This switch serves LVD environment through the
applying 0V to LVD pin of EVA. chip during 5V normal operation.
JUNE 2001 Ver 1.0
Position ON during normal operation.
ON : Normal operation
OFF : Force to detect the LVD, refer
to "23. SUPPLY VOLTAGE DETECTION" on page 82.
85
GMS81C5108
DIP S/W, VR
SW5
Description
ON/OFF Setting
1
Internal power supply to sub-oscillation circuit.
Must be ON position.
2
Reserved for other purpose.
Must be OFF position.
VR1
-
Adjust the LCD contrast. It control the VCL2 voltage.
Refer to above SW4-1,2,3 figure.
Adjust the proper position as well as
LCD display good.
VR2
-
Reserved for other purpose.
Don’t care.
OFF ON
86
JUNE 2001 Ver 1.0
GMS81C5108
Book History
This Book Ver 1.0 (JUNE 2001)
First edition.
JUNE 2001 Ver 1.0
87
APPENDIX
GMS81C5108 APPENDIX
A. CONTROL REGISTER LIST
Address
Register Name
Symbol
R/W
Initial Value
Page
7 6 5 4 3 2 1 0
00C0
R0 port data register
R0
R/W
00000000
32
00C1
R1 port data register
R1
R/W
00000000
32
00C2
R2 port data register
R2
R/W
- - - - 0000
33
00C3
R3 port data register
R3
R/W
- - - - 0000
33
00C8
R0 port I/O direction register
R0DR
W
00000000
32
00C9
R1 port I/O direction register
R1DR
W
00000000
32
00CA
R2 port I/O direction register
R2DR
W
- - - - 0000
33
00CB
R3 port I/O direction register
R3DR
W
- - - - 0000
33
00D0
R0 port pull-up register
R0PU
W
00000000
32
00D1
R1 port pull-up register
R1PU
W
00000000
32
00D2
R2 port pull-up register
R2PU
W
- - - - 0000
33
00D3
R3 port pull-up register
R3PU
W
- - - - 0000
33
00D4
R0 port open drain control register
R0CR
W
00000000
32
00D5
R1 port open drain control register
R1CR
W
00000000
32
00D6
R2 port open drain control register
R2CR
W
- - - - 0000
33
00D7
R3 port open drain control register
R3CR
W
- - - - 0000
33
00D8
Ext. interrupt edge selection register
IESR
R/W
- - 000000
69
00D9
Port selection register
PMR
R/W
- 0 - 00000
32
00DA
Interrupt enable low register
IENL
R/W
- 0000 - - -
65
00DB
Interrupt enable high register
IENH
R/W
- 0000000
65
00DC
Interrupt request flag low register
IRQL
R/W
- 0000 - - -
65
00DD
Interrupt request flag high register
IRQH
R/W
- 0000000
65
00DE
Sleep mode register
SMR
R/W
- - - - - - - 0
39
00E0
Timer 0 mode register
TM0
R/W
- - 000000
45
T0
R
00000000
45
Timer 0 data register
TDR0
W
11111111
45
Timer 0 input capture register
CDR0
R
00000000
45
Timer 1 mode register
TM1
R/W
00000000
45
Timer 1 data register
TDR1
W
11111111
45
T1PPR
W
11111111
45
T1
R
00000000
45
Timer 1 input capture register
CDR1
R
00000000
45
PWM0 pulse duty register
T1PDR
R/W
00000000
45
PWMHR
W
- - - - 0000
45
Timer 0 counter register
00E1
00E2
00E3
PWM0 pulse period register
Timer 1 counter register
00E4
00E5
PWM0 high register
00EC
A/D converter mode register
ADMR
R/W
- 0 - - 0001
58
00ED
A/D converter data register
ADDR
R
x x x x x x x x
58
JUNE 2001 Ver 1.0
i
GMS81C5108 APPENDIX
Address
Register Name
Symbol
R/W
Initial Value
Page
7 6 5 4 3 2 1 0
00EF
Watch timer mode register
WTMR
R/W
- 0000000
56
00F0
Key scan mode register
KSMR
R/W
00000000
70
00F1
LCD control register
LCR
R/W
00000000
72
00F3
RAM paging register
RPR
R/W
- - - - - - 00
73
Basic interval timer register
BITR
R
00000000
43
CKCTLR
W
- - - - 0111
43
SCMR
R/W
00000000
34
00F4
00F5
System clock mode register
00F6
Remocon mode register
RMR
R/W
- 0000000
76
00F7
Carrier frequency high selection
CFHS
W
- - 111111
76
00F8
Carrier frequency low selection
CFLS
W
- - 111111
76
00F9
Remocon data high register
RDHR
W
11111111
76
Remocon data low register
RDLR
W
11111111
76
Remocon data counter
RDC
R
00000000
76
RODR
R/W
- - - - - - - 0
76
00FA
ii
Clock control register
00FB
Remocon output data register
00FC
Remocon output buffer
ROB
R/W
- - - - - - - 0
76
00FD
Buzzer data register
BDR
W
00000000
60
00FE
Serial I/O mode register
SIOM
R/W
00000001
62
00FF
Serial I/O data register
SIOD
R/W
x x x x x x x x
62
JUNE 2001 Ver 1.0
GMS81C5108 APPENDIX
B. INSTRUCTION
B.1 Terminology List
Terminology
Description
A
Accumulator
X
X - register
Y
Y - register
PSW
Program Status Word
#imm
8-bit Immediate data
dp
!abs
Direct Page Offset Address
Absolute Address
[]
Indirect expression
{}
Register Indirect expression
{ }+
Register Indirect expression, after that, Register auto-increment
.bit
Bit Position
A.bit
Bit Position of Accumulator
dp.bit
Bit Position of Direct Page Memory
M.bit
Bit Position of Memory Data (000H~0FFFH)
rel
upage
Relative Addressing Data
U-page (0FF00H~0FFFFH) Offset Address
n
Table CALL Number (0~15)
+
Addition
Upper Nibble Expression in Opcode
0
x
Bit Position
Upper Nibble Expression in Opcode
1
y
Bit Position
−
Subtraction
×
Multiplication
/
Division
()
Contents Expression
∧
AND
∨
OR
⊕
Exclusive OR
~
NOT
←
Assignment / Transfer / Shift Left
→
Shift Right
↔
Exchange
=
Equal
≠
Not Equal
JUNE 2001 Ver 1.0
iii
GMS81C5108 APPENDIX
B.2 Instruction Map
LOW 00000
HIGH
00
SET1
dp.bit
00010
02
00011
03
BBS
BBS
A.bit,rel dp.bit,rel
00100
04
00101
05
00110
06
00111
07
01000
08
01001
09
01010
0A
01011
0B
01100
0C
01101
0D
01110
0E
01111
0F
ADC
#imm
ADC
dp
ADC
dp+X
ADC
!abs
ASL
A
ASL
dp
TCALL
0
SETA1
.bit
BIT
dp
POP
A
PUSH
A
BRK
000
-
001
CLRC
SBC
#imm
SBC
dp
SBC
dp+X
SBC
!abs
ROL
A
ROL
dp
TCALL CLRA1
2
.bit
COM
dp
POP
X
PUSH
X
BRA
rel
010
CLRG
CMP
#imm
CMP
dp
CMP
dp+X
CMP
!abs
LSR
A
LSR
dp
TCALL
4
NOT1
M.bit
TST
dp
POP
Y
PUSH
Y
PCALL
Upage
011
DI
OR
#imm
OR
dp
OR
dp+X
OR
!abs
ROR
A
ROR
dp
TCALL
6
OR1
OR1B
CMPX
dp
POP
PSW
PUSH
PSW
RET
100
CLRV
AND
#imm
AND
dp
AND
dp+X
AND
!abs
INC
A
INC
dp
TCALL AND1
8
AND1B
CMPY
dp
CBNE
dp+X
TXSP
INC
X
101
SETC
EOR
#imm
EOR
dp
EOR
dp+X
EOR
!abs
DEC
A
DEC
dp
TCALL EOR1
10
EOR1B
DBNE
dp
XMA
dp+X
TSPX
DEC
X
110
SETG
LDA
#imm
LDA
dp
LDA
dp+X
LDA
!abs
TXA
LDY
dp
TCALL
12
LDC
LDCB
LDX
dp
LDX
dp+Y
XCN
DAS
111
EI
LDM
dp,#imm
STA
dp
STA
dp+X
STA
!abs
TAX
STY
dp
TCALL
14
STC
M.bit
STX
dp
STX
dp+Y
XAX
STOP
10011
13
10100
14
10101
15
10110
16
10111
17
11000
18
11001
19
11010
1A
11011
1B
11100
1C
11101
1D
11110
1E
11111
1F
ADC
{X}
ADC
!abs+Y
ADC
[dp+X]
ADC
[dp]+Y
ASL
!abs
ASL
dp+X
TCALL
1
JMP
!abs
BIT
!abs
ADDW
dp
LDX
#imm
JMP
[!abs]
TEST
!abs
SUBW
dp
LDY
#imm
JMP
[dp]
TCLR1 CMPW
!abs
dp
CMPX
#imm
CALL
[dp]
LOW 10000
HIGH
iv
00001
01
10
10001
11
10010
12
000
BPL
rel
001
BVC
rel
SBC
{X}
SBC
!abs+Y
SBC
[dp+X]
SBC
[dp]+Y
ROL
!abs
ROL
dp+X
TCALL
3
CALL
!abs
010
BCC
rel
CMP
{X}
CMP
!abs+Y
CMP
[dp+X]
CMP
[dp]+Y
LSR
!abs
LSR
dp+X
TCALL
5
MUL
011
BNE
rel
OR
{X}
OR
!abs+Y
OR
[dp+X]
OR
[dp]+Y
ROR
!abs
ROR
dp+X
TCALL
7
DBNE
Y
CMPX
!abs
LDYA
dp
CMPY
#imm
RETI
100
BMI
rel
AND
{X}
AND
!abs+Y
AND
[dp+X]
AND
[dp]+Y
INC
!abs
INC
dp+X
TCALL
9
DIV
CMPY
!abs
INCW
dp
INC
Y
TAY
101
BVS
rel
EOR
{X}
EOR
!abs+Y
EOR
[dp+X]
EOR
[dp]+Y
DEC
!abs
DEC
dp+X
TCALL
11
XMA
{X}
XMA
dp
DECW
dp
DEC
Y
TYA
110
BCS
rel
LDA
{X}
LDA
!abs+Y
LDA
[dp+X]
LDA
[dp]+Y
LDY
!abs
LDY
dp+X
TCALL
13
LDA
{X}+
LDX
!abs
STYA
dp
XAY
DAA
111
BEQ
rel
STA
{X}
STA
!abs+Y
STA
[dp+X]
STA
[dp]+Y
STY
!abs
STY
dp+X
TCALL
15
STA
{X}+
STX
!abs
CBNE
dp
XYX
NOP
CLR1
BBC
BBC
dp.bit
A.bit,rel
dp.bit,rel
JUNE 2001 Ver 1.0
GMS81C5108 APPENDIX
B.3 Instruction Set
Arithmetic / Logic Operation
No.
Mnemonic
Op
Code
Byte
No
Cycle
No
2
2
Add with carry.
A←(A)+(M)+C
Operation
1
ADC #imm
04
2
ADC dp
05
2
3
3
ADC dp + X
06
2
4
4
ADC !abs
07
3
4
5
ADC !abs + Y
15
3
5
6
ADC [ dp + X ]
16
2
6
7
ADC [ dp ] + Y
17
2
6
8
ADC { X }
14
1
3
9
AND #imm
84
2
2
Logical AND
10
AND dp
85
2
3
A← (A)∧(M)
11
AND dp + X
86
2
4
12
AND !abs
87
3
4
13
AND !abs + Y
95
3
5
14
AND [ dp + X ]
96
2
6
15
AND [ dp ] + Y
97
2
6
16
AND { X }
94
1
3
17
ASL A
08
1
2
18
ASL dp
09
2
4
19
ASL dp + X
19
2
5
20
ASL !abs
18
3
5
21
CMP #imm
44
2
2
22
CMP dp
45
2
3
23
CMP dp + X
46
2
4
24
CMP !abs
47
3
4
25
CMP !abs + Y
55
3
5
26
CMP [ dp + X ]
56
2
6
27
CMP [ dp ] + Y
57
2
6
28
CMP { X }
54
1
3
29
CMPX #imm
5E
2
2
Flag
NVGBHIZC
NV--H-ZC
N-----Z-
Arithmetic shift left
C
7 6 5 4 3 2 1 0
← ←←←←←←←←
N-----ZC
← “0”
Compare accumulator contents with memory contents
(A) -(M)
N-----ZC
Compare X contents with memory contents
30
CMPX dp
6C
2
3
31
CMPX !abs
7C
3
4
32
CMPY #imm
7E
2
2
33
CMPY dp
8C
2
3
34
CMPY !abs
9C
3
4
35
COM dp
2C
2
4
1’S Complement : ( dp ) ← ~( dp )
N-----Z-
36
DAA
DF
1
3
Decimal adjust for addition
N-----ZC
37
DAS
CF
1
3
Decimal adjust for subtraction
N-----ZC
38
DEC A
A8
1
2
Decrement
N-----Z-
39
DEC dp
A9
2
4
40
DEC dp + X
B9
2
5
N-----Z-
41
DEC !abs
B8
3
5
N-----Z-
42
DEC X
AF
1
2
N-----Z-
43
DEC Y
BE
1
2
N-----Z-
JUNE 2001 Ver 1.0
(X)-(M)
N-----ZC
Compare Y contents with memory contents
(Y)-(M)
M← (M)-1
N-----ZC
N-----Z-
v
GMS81C5108 APPENDIX
No.
Op
Code
Byte
No
Cycle
No
Flag
Operation
44
DIV
9B
1
12
Divide : YA / X Q: A, R: Y
45
EOR #imm
A4
2
2
Exclusive OR
NVGBHIZC
NV--H-Z-
A← (A)⊕(M)
46
EOR dp
A5
2
3
47
EOR dp + X
A6
2
4
48
EOR !abs
A7
3
4
49
EOR !abs + Y
B5
3
5
50
EOR [ dp + X ]
B6
2
6
51
EOR [ dp ] + Y
B7
2
6
52
EOR { X }
B4
1
3
53
INC A
88
1
2
54
INC dp
89
2
4
55
INC dp + X
99
2
5
N-----Z-
56
INC !abs
98
3
5
N-----Z-
57
INC X
8F
1
2
N-----Z-
58
INC Y
9E
1
2
N-----Z-
59
LSR A
48
1
2
60
LSR dp
49
2
4
61
LSR dp + X
59
2
5
62
LSR !abs
58
3
5
63
MUL
5B
1
9
Multiply : YA ← Y × A
64
OR #imm
64
2
2
Logical OR
65
OR dp
65
2
3
66
OR dp + X
66
2
4
67
OR !abs
67
3
4
68
OR !abs + Y
75
3
5
69
OR [ dp + X ]
76
2
6
N-----Z-
Increment
N-----ZC
M← (M)+1
N-----Z-
OR [ dp ] + Y
77
2
6
74
1
3
72
ROL A
28
1
2
73
ROL dp
29
2
4
74
ROL dp + X
39
2
5
75
ROL !abs
38
3
5
76
ROR A
68
1
2
Rotate right through Carry
77
ROR dp
69
2
4
78
ROR dp + X
79
2
5
7 6 5 4 3 2 1 0
→→→→→→→→
79
ROR !abs
78
3
5
SBC #imm
24
2
2
SBC dp
25
2
3
82
SBC dp + X
26
2
4
83
SBC !abs
27
3
4
N-----Z-
A ← (A)∨(M)
OR { X }
81
N-----ZC
7 6 5 4 3 2 1 0
C
“0” → → → → → → → → → →
71
80
N-----Z-
Logical shift right
70
Rotate left through Carry
C
N-----ZC
7 6 5 4 3 2 1 0
←←←←←←←←
N-----ZC
C
Subtract with Carry
A ← ( A ) - ( M ) - ~( C )
NV--HZC
84
SBC !abs + Y
35
3
5
85
SBC [ dp + X ]
36
2
6
86
SBC [ dp ] + Y
37
2
6
87
SBC { X }
34
1
3
88
TST dp
4C
2
3
Test memory contents for negative or zero, ( dp ) - 00H
N-----Z-
5
Exchange nibbles within the accumulator
A7~A4 ↔ A3~A0
N-----Z-
89
vi
Mnemonic
XCN
CE
1
JUNE 2001 Ver 1.0
GMS81C5108 APPENDIX
Register / Memory Operation
No.
Mnemonic
Op
Code
Byte
No
Cycle
No
Operation
1
LDA #imm
C4
2
2
2
LDA dp
C5
2
3
3
LDA dp + X
C6
2
4
4
LDA !abs
C7
3
4
5
LDA !abs + Y
D5
3
5
6
LDA [ dp + X ]
D6
2
6
7
LDA [ dp ] + Y
D7
2
6
8
LDA { X }
D4
1
3
9
LDA { X }+
DB
1
4
X- register auto-increment : A ← ( M ) , X ← X + 1
10
LDM dp,#imm
E4
3
5
Load memory with immediate data : ( M ) ← imm
Load X-register
11
LDX #imm
1E
2
2
12
LDX dp
CC
2
3
13
LDX dp + Y
CD
2
4
14
LDX !abs
DC
3
4
Flag
NVGBHIZC
Load accumulator
A←(M)
N-----Z-
X ←(M)
-------N-----Z-
15
LDY #imm
3E
2
2
16
LDY dp
C9
2
3
Load Y-register
17
LDY dp + X
D9
2
4
18
LDY !abs
D8
3
4
19
STA dp
E5
2
4
20
STA dp + X
E6
2
5
21
STA !abs
E7
3
5
22
STA !abs + Y
F5
3
6
23
STA [ dp + X ]
F6
2
7
24
STA [ dp ] + Y
F7
2
7
25
STA { X }
F4
1
4
26
STA { X }+
FB
1
4
X- register auto-increment : ( M ) ← A, X ← X + 1
27
STX dp
EC
2
4
Store X-register contents in memory
28
STX dp + Y
ED
2
5
29
STX !abs
FC
3
5
30
STY dp
E9
2
4
31
STY dp + X
F9
2
5
32
STY !abs
F8
3
5
33
TAX
E8
1
2
Transfer accumulator contents to X-register : X ← A
N-----Z-
34
TAY
9F
1
2
Transfer accumulator contents to Y-register : Y ← A
N-----Z-
Y←(M)
N-----Z-
Store accumulator contents in memory
(M)←A
--------
(M)← X
--------
Store Y-register contents in memory
(M)← Y
--------
35
TSPX
AE
1
2
Transfer stack-pointer contents to X-register : X ← sp
N-----Z-
36
TXA
C8
1
2
Transfer X-register contents to accumulator: A ← X
N-----Z-
37
TXSP
8E
1
2
Transfer X-register contents to stack-pointer: sp ← X
N-----Z-
38
TYA
BF
1
2
Transfer Y-register contents to accumulator: A ← Y
N-----Z-
39
XAX
EE
1
4
Exchange X-register contents with accumulator :X ↔ A
--------
40
XAY
DE
1
4
Exchange Y-register contents with accumulator :Y ↔ A
--------
Exchange memory contents with accumulator
41
XMA dp
BC
2
5
42
XMA dp+X
AD
2
6
43
XMA {X}
BB
1
5
44
XYX
FE
1
4
JUNE 2001 Ver 1.0
(M)↔A
Exchange X-register contents with Y-register : X ↔ Y
N-----Z--------
vii
GMS81C5108 APPENDIX
16-BIT operation
No.
Mnemonic
Op
Code
Byte
No
Cycle
No
Flag
Operation
NVGBHIZC
1
ADDW dp
1D
2
5
16-Bits add without Carry
YA ← ( YA ) + ( dp +1 ) ( dp )
NV--H-ZC
2
CMPW dp
5D
2
4
Compare YA contents with memory pair contents :
(YA) − (dp+1)(dp)
N-----ZC
3
DECW dp
BD
2
6
Decrement memory pair
( dp+1)( dp) ← ( dp+1) ( dp) - 1
N-----Z-
4
INCW dp
9D
2
6
Increment memory pair
( dp+1) ( dp) ← ( dp+1) ( dp ) + 1
N-----Z-
5
LDYA dp
7D
2
5
Load YA
YA ← ( dp +1 ) ( dp )
N-----Z-
6
STYA dp
DD
2
5
Store YA
( dp +1 ) ( dp ) ← YA
--------
7
SUBW dp
3D
2
5
16-Bits subtract without carry
YA ← ( YA ) - ( dp +1) ( dp)
NV--H-ZC
Op
Code
Byte
No
Cycle
No
Bit Manipulation
No.
Mnemonic
Flag
Operation
NVGBHIZC
1
AND1 M.bit
8B
3
4
Bit AND C-flag : C ← ( C ) ∧ ( M .bit )
-------C
2
AND1B M.bit
8B
3
4
Bit AND C-flag and NOT : C ← ( C ) ∧ ~( M .bit )
-------C
3
BIT dp
0C
2
4
Bit test A with memory :
MM----Z-
5
Z ← ( A ) ∧ ( M ) , N ← ( M7 ) , V ← ( M6 )
4
BIT !abs
1C
3
5
CLR1 dp.bit
y1
2
4
Clear bit : ( M.bit ) ← “0”
--------
6
CLRA1 A.bit
2B
2
2
Clear A bit : ( A.bit ) ← “0”
--------
7
CLRC
20
1
2
Clear C-flag : C ← “0”
-------0
8
CLRG
40
1
2
Clear G-flag : G ← “0”
--0-----
9
CLRV
80
1
2
Clear V-flag : V ← “0”
-0--0---
10
EOR1 M.bit
AB
3
5
Bit exclusive-OR C-flag : C ← ( C ) ⊕ ( M .bit )
-------C
11
EOR1B M.bit
AB
3
5
Bit exclusive-OR C-flag and NOT : C ← ( C ) ⊕ ~(M .bit)
-------C
12
LDC M.bit
CB
3
4
Load C-flag : C ← ( M .bit )
-------C
13
LDCB M.bit
CB
3
4
Load C-flag with NOT : C ← ~( M .bit )
-------C
14
NOT1 M.bit
4B
3
5
Bit complement : ( M .bit ) ← ~( M .bit )
--------
15
OR1 M.bit
6B
3
5
Bit OR C-flag : C ← ( C ) ∨ ( M .bit )
-------C
16
OR1B M.bit
6B
3
5
Bit OR C-flag and NOT : C ← ( C ) ∨ ~( M .bit )
-------C
17
SET1 dp.bit
x1
2
4
Set bit : ( M.bit ) ← “1”
--------
18
SETA1 A.bit
0B
2
2
Set A bit : ( A.bit ) ← “1”
--------
19
SETC
A0
1
2
Set C-flag : C ← “1”
-------1
20
SETG
C0
1
2
Set G-flag : G ← “1”
--1-----
21
STC M.bit
EB
3
6
Store C-flag : ( M .bit ) ← C
--------
22
TCLR1 !abs
5C
3
6
Test and clear bits with A :
A - ( M ) , ( M ) ← ( M ) ∧ ~( A )
N-----Z-
23
TSET1 !abs
3C
3
6
Test and set bits with A :
A-(M), (M)← (M)∨(A)
N-----Z-
viii
JUNE 2001 Ver 1.0
GMS81C5108 APPENDIX
Branch / Jump Operation
No.
Mnemonic
Op
Code
Byte
No
Cycle
No
Operation
Flag
NVGBHIZC
1
BBC A.bit,rel
y2
2
4/6
Branch if bit clear :
2
BBC dp.bit,rel
y3
3
5/7
if ( bit ) = 0 , then pc ← ( pc ) + rel
3
BBS A.bit,rel
x2
2
4/6
Branch if bit set :
4
BBS dp.bit,rel
x3
3
5/7
if ( bit ) = 1 , then pc ← ( pc ) + rel
5
BCC rel
50
2
2/4
Branch if carry bit clear
if ( C ) = 0 , then pc ← ( pc ) + rel
--------
6
BCS rel
D0
2
2/4
Branch if carry bit set
if ( C ) = 1 , then pc ← ( pc ) + rel
--------
7
BEQ rel
F0
2
2/4
Branch if equal
if ( Z ) = 1 , then pc ← ( pc ) + rel
--------
8
BMI rel
90
2
2/4
Branch if minus
if ( N ) = 1 , then pc ← ( pc ) + rel
--------
9
BNE rel
70
2
2/4
Branch if not equal
if ( Z ) = 0 , then pc ← ( pc ) + rel
--------
10
BPL rel
10
2
2/4
Branch if minus
if ( N ) = 0 , then pc ← ( pc ) + rel
--------
11
BRA rel
2F
2
4
Branch always
pc ← ( pc ) + rel
--------
12
BVC rel
30
2
2/4
Branch if overflow bit clear
if (V) = 0 , then pc ← ( pc) + rel
--------
13
BVS rel
B0
2
2/4
Branch if overflow bit set
if (V) = 1 , then pc ← ( pc ) + rel
--------
14
CALL !abs
3B
3
8
Subroutine call
M( sp)←( pcH ), sp←sp - 1, M(sp)← (pcL), sp ←sp - 1,
if !abs, pc← abs ; if [dp], pcL← ( dp ), pcH← ( dp+1 ) .
--------
Compare and branch if not equal :
--------
15
CALL [dp]
5F
2
8
16
CBNE dp,rel
FD
3
5/7
---------------
if ( A ) ≠ ( M ) , then pc ← ( pc ) + rel.
17
CBNE dp+X,rel
8D
3
6/8
18
DBNE dp,rel
AC
3
5/7
Decrement and branch if not equal :
19
DBNE Y,rel
7B
2
4/6
if ( M ) ≠ 0 , then pc ← ( pc ) + rel.
20
JMP !abs
1B
3
3
--------
Unconditional jump
pc ← jump address
21
JMP [!abs]
1F
3
5
22
JMP [dp]
3F
2
4
23
PCALL upage
4F
2
6
U-page call
M(sp) ←( pcH ), sp ←sp - 1, M(sp) ← ( pcL ),
sp ← sp - 1, pcL ← ( upage ), pcH ← ”0FFH” .
--------
24
TCALL n
nA
1
8
Table call : (sp) ←( pcH ), sp ← sp - 1,
M(sp) ← ( pcL ),sp ← sp - 1,
pcL ← (Table vector L), pcH ← (Table vector H)
--------
JUNE 2001 Ver 1.0
--------
ix
GMS81C5108 APPENDIX
Control Operation & Etc.
No.
1
x
Mnemonic
BRK
Op
Code
Byte
No
Cycle
No
Operation
0F
1
8
Software interrupt : B ← ”1”, M(sp) ← (pcH), sp ←sp-1,
M(s) ← (pcL), sp ← sp - 1, M(sp) ← (PSW), sp ← sp -1,
pcL ← ( 0FFDEH ) , pcH ← ( 0FFDFH) .
Flag
NVGBHIZC
---1-0--
2
DI
60
1
3
Disable all interrupts : I ← “0”
-----0--
3
EI
E0
1
3
Enable all interrupt : I ← “1”
-----1--
4
NOP
FF
1
2
No operation
--------
5
POP A
0D
1
4
sp ← sp + 1, A ← M( sp )
6
POP X
2D
1
4
sp ← sp + 1, X ← M( sp )
7
POP Y
4D
1
4
sp ← sp + 1, Y ← M( sp )
8
POP PSW
6D
1
4
sp ← sp + 1, PSW ← M( sp )
-------restored
9
PUSH A
0E
1
4
M( sp ) ← A , sp ← sp - 1
10
PUSH X
2E
1
4
M( sp ) ← X , sp ← sp - 1
11
PUSH Y
4E
1
4
M( sp ) ← Y , sp ← sp - 1
12
PUSH PSW
6E
1
4
M( sp ) ← PSW , sp ← sp - 1
13
RET
6F
1
5
Return from subroutine
sp ← sp +1, pcL ← M( sp ), sp ← sp +1, pcH ← M( sp )
--------
14
RETI
7F
1
6
Return from interrupt
sp ← sp +1, PSW ← M( sp ), sp ← sp + 1,
pcL ← M( sp ), sp ← sp + 1, pcH ← M( sp )
restored
15
STOP
EF
1
3
Stop mode ( halt CPU, stop oscillator )
--------
--------
JUNE 2001 Ver 1.0
C. MASK ORDER SHEET
MASK ORDER & VERIFICATION SHEET
GMS81C5108 - UD
Customer should write inside thick line box.
2. Device Information
1. Customer Information
Company Name
Application
Package
80QFP
ROM Size
8K
OSC Option
YYYY
Order Date
MM
DD
Reset Pull Up
Crystal
R
YES
NO
Hitel
Tel:
Chollian
File Name : (
Check Sum : (
Fax:
E-mail address:
0000H
Mask Data
Name &
Signature:
Set “00” in
this area
DFFFH
E000H
FFFFH
3. Marking Specification (Please check mark into
Internet
.OTP)
)
.OTP file data
)
C ustom er’s Area
G M S81C 5108-U D
YYW W KO R EA
G M S81C 5108-UD
YYW W KO R EA
If the customer logo & part number must be used in this area,
please submit a clean original logo & part number.
4. Delivery Schedule
Date
Customer sample
Risk order
Quantity
YYYY
MM
DD
YYYY
MM
DD
HYNIX Confirmation
pcs
pcs
5. ROM Code Verification
Please confirm out verification data.
YYYY
Verification date:
Check sum:
Tel:
E-mail address:
Name &
Signature:
MM
DD
Approval date:
YYYY
MM
DD
I agree with your verification data and confirm you to
make mask set.
Fax:
Tel:
Fax:
E-mail address:
Name &
Signature:
FEB. 2001
Hynix Sem iconductor Inc.