LINER LTC3616 ±6a monolithic synchronous step-down regulator for ddr termination Datasheet

LTC3617
±6A Monolithic Synchronous
Step-Down Regulator
for DDR Termination
Description
Features
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±6A Output Current
2.25V to 5.5V Input Voltage Range
±10mV Output Voltage Accuracy
Optimized for Low Output Voltages Down to 0.5V
High Efficiency
Integrated Buffer for VTTR = VDDQIN • 0.5
Shutdown Current: <1µA
Adjustable Switching Frequency: Up to 4MHz
Optional Internal Compensation
Internal Soft-Start
Power Good Status Output
Input Overvoltage Protected
Thermally Enhanced 24-Pin 3mm × 5mm
QFN Package
Applications
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DDR Termination
Supports DDR, DDR2 and DDR3 Standards
Tracking Supplies
The LTC®3617 is a high efficiency monolithic synchronous
buck regulator utilizing a current mode, constant frequency
architecture. It operates from an input voltage range of
2.25V to 5.5V and provides a regulated output voltage
equal to 0.5 • VDDQIN while sourcing and sinking up to
6A of load current. An internal amplifier provides a VTTR
output voltage equal to 0.5 • VDDQIN with an output current capability of ±10mA.
The operating frequency is externally programmable up to
4MHz, allowing the use of small surface mount inductors.
For switching-noise-sensitive applications, the LTC3617
can be synchronized to an external clock up to 4MHz.
Forced continuous mode operation in the LTC3617 reduces
noise and RF interference. Adjustable external compensation allows the transient response to be optimized over a
wide range of loads and output capacitors.
The internal synchronous switch increases efficiency and
eliminates the need for an external catch diode, minimizing
external component count and board space. The LTC3617
is offered in a leadless 24-pin 3mm × 5mm thermally
enhanced QFN package.
L, LT, LTC, LTM, Linear Technology, the Linear logo and Burst Mode are registered trademarks
of Linear Technology Corporation. All other trademarks are the property of their respective
owners. Protected by U.S. Patents, including 6580258, 5481178, 6498466, 6611131.
Typical Application
Efficiency and Power Loss
vs Load Current
100
PVIN
SVIN
LTC3617
PGOOD
ITH
SYNC
0.15µH
VTT
1.25V
47µF ±6A
×2
SW
SGND
PGND
VFB
80
70
1
60
50
40
0.1
30
POWER LOSS (W)
VREF
1.25V
0.1µF ±10mA
VTTR
RUN
VDDQIN
RT
10
90
22µF
×4
EFFICIENCY (%)
VIN
2.5V
20
3617 TA01a
10
0
0.1
1
LOAD CURRENT (A)
10
0.01
3617 TA01b
3617fa
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LTC3617
Pin Configuration
VFB
PGOOD
VDDQIN
ITH
TOP VIEW
PVIN, SVIN Voltages...................................... –0.3V to 6V
SW Voltage.................................. –0.3V to (PVIN + 0.3V)
ITH, RT, SYNC Voltages............... –0.3V to (SVIN + 0.3V)
VTTR, RUN, VFB Voltages............ –0.3V to (SVIN + 0.3V)
VDDQIN, PGOOD Voltages............................ –0.3V to 6V
Operating Junction Temperature Range
(Notes 2, 8)............................................. –40°C to 125°C
Storage Temperature.............................. –65°C to 150°C
24 23 22 21
RT 1
20 SYNC
SGND 2
19 RUN
VTTR 3
18 SVIN
PVIN 4
17 PVIN
25
PGND
SW 5
16 SW
SW 6
15 SW
SW 7
14 SW
SW 8
13 SW
10 11 12
NC
NC
9
PVIN
(Note 1)
PVIN
Absolute Maximum Ratings
UDD PACKAGE
24-LEAD (3mm × 5mm) PLASTIC QFN
TJMAX = 125°C, θJA = 43°C/W
EXPOSED PAD (PIN 25) IS PGND, MUST BE SOLDERED TO PCB
Order Information
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC3617EUDD#PBF
LTC3617EUDD#TRPBF
LFXC
24-Lead (3mm × 5mm) Plastic QFN
–40°C to 125°C
LTC3617IUDD#PBF
LTC3617IUDD#TRPBF
LFXC
24-Lead (3mm × 5mm) Plastic QFN
–40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
Electrical Characteristics
The l denotes the specifications which apply over the full operating junction
temperature range, otherwise specifications are at TA = 25°C. PVIN = SVIN = 3.3V, RT = SVIN unless otherwise specified (Notes 1, 2, 8).
SYMBOL
PARAMETER
CONDITIONS
MIN
l
2.25
l
l
1.7
TYP
MAX
VIN
Input Voltage Operating Range
VUVLO
Undervoltage Lockout Threshold
SVIN Ramping Down
SVIN Ramping Up
VOVLO
Overvoltage Lockout Threshold
SVIN Ramping Up
Hysteresis
VTTR
VTTR Output Voltage with Line and Load
Regulation
VDDQIN = 1.5V, Load = ±10mA
l 0.49 • VDDQIN 0.5 • VDDQIN 0.51 • VDDQIN
6.5
250
VTTR Maximum Output Current
VFB
Feedback Voltage Accuracy
VDDQIN = 1.5V (Note 3)
l
IFB
Feedback Input Current
VFB = 0.75V
l
VTTR – 10
VTTR
UNITS
5.5
V
2.2
V
V
7
V
mV
V
±10
mA
VTTR + 10
mV
±30
nA
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LTC3617
Electrical Characteristics
The l denotes the specifications which apply over the full operating junction
temperature range, otherwise specifications are at TA = 25°C. PVIN = SVIN = 3.3V, RT = SVIN unless otherwise specified (Notes 1, 2, 8).
SYMBOL
PARAMETER
CONDITIONS
MIN
∆VFB(LINEREG) Feedback Voltage Line Regulation
SVIN = PVIN = 2.25V to 5.5V,
VDDQIN = 1.5V (Notes 3, 4)
∆VFB(LOADREG) Feedback Voltage Load Regulation
ITH from 0.5V to 0.9V (Notes 3, 4)
VITH = SVIN (Note 5)
IQ
RDS(ON)
ILIM
Input DC Supply Current
Active Mode
Shutdown
VFB = 0.6V, VDDQIN = 1.5V (Note 6)
SVIN = PVIN = 5.5V, VRUN = 0V
Top Switch On-Resistance
PVIN = 3.3V
Bottom Switch On-Resistance
PVIN = 3.3V
Top Switch Positive Peak Current Limit
Sourcing (Note 7), VFB = 0.5V
1100
0.1
Sinking (Note 7)
Error Amplifier Transconductance
–5µA < IITH < 5µA (Note 4)
–12
IEAO
Error Amplifier Maximum Output Current (Note 4)
tSS
Internal Soft-Start Time
VFB from 0.075V to 0.675V,
VDDQIN = 1.5V
fOSC
Oscillator Frequency
Internal Oscillator Frequency
RT = 370k
VRT = SVIN
fSYNC
Synchronization Frequency Range
0.3
VSYNC
SYNC Input Threshold High Voltage
SYNC Input Threshold Low Voltage
1.2
l
l
ISW(LKG)
Switch Leakage Current
SVIN = PVIN = 5.5V, VRUN = 0V
PGOOD
Power Good Voltage Windows
VDDQIN = 1.5V, Entering Window
VFB Ramping Up
VFB Ramping Down
Power Good Pull-Down On-Resistance
VRUN
RUN voltage
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3617 is tested under pulsed load conditions such that
TJ ≈ TA. The LTC3617E is guaranteed to meet performance specifications
over the 0°C to 85°C operating junction temperature range. Specifications
over the –40°C to 125°C operating junction temperature range are
assured by design, characterization and correlation with statistical process
controls. The LTC3617I is guaranteed to meet specifications over the
full –40°C to 125°C operating junction temperature range. Note that
the maximum ambient temperature is determined by specific operating
conditions in conjunction with board layout, the rated package thermal
resistance and other environmental factors. The junction temperature
(TJ, in °C) is calculated from the ambient temperature (TA, in °C) and
power dissipation (PD, in watts) according to the formula:
TJ = TA + (PD • θJA), where θJA (in °C/W) is the package thermal
impedance.
0.25
0.25
%
%
1
µA
µA
mΩ
14
–8
–5
A
A
200
µS
±30
µA
0.85
2
ms
0.8
1.8
1
2.25
1.2
2.7
MHz
MHz
4
MHz
–3.5
3.5
l
l
mΩ
10
0.1
Entering and Leaving Window
Input High
Input Low
%/V
0.4
VDDQIN = 1.5V, Leaving Window
VFB Ramping Up
VFB Ramping Down
Power Good Blanking Time
UNITS
0.2
25
8
Top Switch Negative Peak Current Limit
tPGOOD
MAX
35
gm(EA)
RPGOOD
TYP
l
0.3
V
V
1
µA
–5
5
%
%
8
–8
10
–10
%
%
70
105
140
µs
8
17
33
Ω
0.4
V
V
1
Note 3: This parameter is tested in a feedback loop which servos VFB to
the midpoint for the error amplifier (VITH = 0.75V).
Note 4: External compensation on ITH pin.
Note 5: Tying the ITH pin to SVIN enables the internal compensation.
Note 6: Dynamic supply current is higher due to the internal gate charge
being delivered at the switching frequency.
Note 7: In sourcing mode the average output current is flowing out of the
SW pin. In sinking mode the average output current is flowing into the SW
Pin.
Note 8: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
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LTC3617
Typical Performance Characteristics
TA = 25°C, VIN = 3.3V, fO = 1MHz unless otherwise noted.
Efficiency vs Input Voltage
Efficiency vs Load Current
90
100
VOUT = 1.25V
VOUT = 1.25V
90
80
EFFICIENCY (%)
70
60
50
40
30
70
60
VIN = 2.5V
VIN = 3.3V
VIN = 5V
10
0
0.1
1
LOAD CURRENT (A)
ILOAD = 600mA
ILOAD = 2A
IOUT = 6A
50
40
2.25
10
2.75
3.25 3.75 4.25 4.75
INPUT VOLTAGE (V)
3617 G01
75
5.25
150nH
330nH
470nH
65
60
1
1.5
2
2.5
3
FREQUENCY (MHz)
3.5
4
3617 G03
Line Regulation
Output Voltage vs Time
0.3
VOUT = 1.25V
0.2
0.2
0.1
0.1
VOUT ERROR (%)
VOUT ERROR (%)
80
3617 G02
Load Regulation
0
–0.1
SW
2V/DIV
0
VOUT
20mV/DIV
–0.1
IL
1A/DIV
–0.2
–0.2
–0.3
85
70
20
0.3
VOUT = 1.25V
95
90
80
EFFICIENCY (%)
Efficiency vs Frequency
100
EFFICIENCY (%)
100
–6
–4
0
2
–2
LOAD CURRENT (A)
4
6
–0.3
2.20
2.75
3.30 3.85 4.40
INPUT VOLTAGE (V)
4.95
3617 G04
5.50
VOUT = 1.25V
ILOAD = 100mA
2µs/DIV
3617 G06
3617 G05
Load Step Transient
Load Step Transient
VOUT
200mV/DIV
VOUT
100mV/DIV
IL
5A/DIV
IL
4A/DIV
40µs/DIV
VOUT = 1.25V
ILOAD = 100mA TO 6A
COMPENSATION FIGURE 1
3617 G07
40µs/DIV
VOUT = 1.25V
ILOAD = –6A TO 6A
COMPENSATION FIGURE 1
3617 G09
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LTC3617
Typical Performance Characteristics
TA = 25°C, VIN = 3.3V, fO = 1MHz unless otherwise noted.
Sinking Current
Internal Start-Up
SW
2V/DIV
RUN
5V/DIV
PGOOD
5V/DIV
VOUT
20mV/DIV
VOUT
500mV/DIV
IL
2A/DIV
Tracking Up/Down
PGOOD
5V/DIV
VOUT/VTTR
500mV/DIV
VDDQIN
2V/DIV
IL
2A/DIV
3617 G10
2µs/DIV
VOUT = 1.25V
ILOAD = –3A
VOUT = 1.25V
ILOAD = 0A
3617 G11
500µs/DIV
VOUT = 1.25V
ILOAD = 3A
Switch On-Resistance
vs Input Voltage
50
40
40
RDS(0N) (mΩ)
RDS(0N) (mΩ)
MAIN SWITCH
30
SYNCHRONOUS SWITCH
20
10
30
MAIN SWITCH
SYNCHRONOUS SWITCH
20
10
0
2.5
3.0
4.0
4.5
3.5
INPUT VOLTAGE (V)
5.0
0
–50 –30 –10 10 30 50 70 90 110 130
TEMPERATURE (°C)
5.5
3617 G15
3617 G14
Frequency vs RT Resistor
Frequency vs Temperature
0.6
FREQUENCY VARIATION (%)
3.5
FREQUENCY (MHz)
0.8
RT = SVIN
4.0
3.0
2.5
2.0
1.5
1.0
0.5
0
3617 G12
Switch On-Resistance
vs Temperature
50
4.5
2ms/DIV
RT = SVIN
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
0
200 400 600 800 1000 1200 1400
RESISTOR ON RT/SYNC PIN (kΩ)
3617 G16
–1.2
–50 –30 –10 10 30 50 70 90 100 130
TEMPERATURE (°C)
3617 G17
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LTC3617
Typical Performance Characteristics
TA = 25°C, VIN = 3.3V, fO = 1MHz unless otherwise noted.
Switch Leakage Current
vs Temperature, Main Switch
1.0
8
0.5
7
SWITCH LEAKAGE (µA)
FREQUENCY VARIATION (%)
Frequency vs Input Voltage
0
–0.5
–1.0
–1.5
–2.0
6
5
4
3
2
1
–2.5
2.25
2.75
3.25 3.75 4.25 4.75
INPUT VOLTAGE (V)
0
–50 –30 –10 10 30 50 70 90 110 130
TEMPERATURE (°C)
5.25
3617 G18
3617 G19
Dynamic Supply Current
vs Temperature
Switch Leakage Current vs
Temperature, Synchronous Switch
50
8
7
40
SWITCH LEAKAGE (µA)
DYNAMIC SUPPLY CURRENT (mA)
VIN = 2.25V
VIN = 3.3V
VIN = 5.5V
30
20
10
0
–50
VIN = 2.5V
VIN = 3.3V
VIN = 5V
–25
0
25
50
75
TEMPERATURE (°C)
100
125
3617 G21
VIN = 2.25V
VIN = 3.3V
VIN = 5.5V
6
5
4
3
2
1
0
–50 –30 –10 10 30 50 70 90 110 130
TEMPERATURE (°C)
3617 G20
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LTC3617
Pin Functions
RT (Pin 1): Oscillator Frequency. This pin provides two
ways of setting the constant switching frequency:
1. Connecting a resistor from RT to ground will set the
switching frequency based on the resistor value.
2. Tying the RT pin to SVIN enables the internal 2.25MHz
oscillator frequency.
SGND (Pin 2): Signal Ground. All small-signal and compensation components should connect to this ground,
which in turn should connect to PGND at a single point.
VTTR (Pin 3): Voltage Buffer Output. This pin is the output
of an internal voltage buffer whose voltage is equal to
VDDQIN • 0.5. Output current capability is ±10mA. VTTR
is also the reference voltage of the error amplifier, which
sets the output voltage. VFB will regulate to VTTR. Do not
exceed 0.1µF capacitance on this pin.
PVIN (Pins 4, 10, 11, 17): Power Input Supply. PVIN connects to the source of the internal P-channel power MOSFET.
This pin is independent of SVIN and may be connected to
the same supply or to a lower voltage.
SW (Pins 5, 6, 7, 8, 13, 14, 15, 16): Switch Node. Connection to the inductor. These pins connect to the drains
of the internal power MOSFET switches.
NC (Pins 9, 12): Can be connected to ground or left open.
SVIN (Pin 18): Signal Input Supply. This pin powers the
internal control circuitry and is monitored by the undervoltage lockout comparator.
RUN (Pin 19): Enable Input. Pulling this pin high enables
the LTC3617 and forcing it to ground shuts the regulator
down. In shutdown, all functions are disabled and the chip
draws <1µA of supply current.
SYNC (Pin 20): External Synchronization Input. When
a clock signal is applied to this pin, the switching frequency synchronizes to this clock signal. This pin can
be either floating or tied to ground if an external clock
is not being used.
PGOOD (Pin 21): Power Good. This open-drain output
is pulled down to SGND on start-up and when the FB
voltage is outside the power good voltage window. If the
FB voltage increases and stays inside the power good
window for more than 100µs the PGOOD pin is released.
If the FB voltage leaves the power good window for more
than 100µs the PGOOD pin is pulled low.
The power good window moves in relation to the VDDQIN
pin voltage. In shutdown the PGOOD output will actively
pull low and may be used to discharge the output capacitors via an external resistor.
VFB (Pin 22): Voltage Feedback Input Pin. Senses the
feedback voltage from the external resistive divider across
the output.
ITH (Pin 23): Error Amplifier Compensation. The current
comparator’s threshold increases with this control voltage.
Tying this pin to SVIN enables internal compensation.
VDDQIN (Pin 24): External Reference Input. An internal
resistor divider sets the VTTR and VFB regulated voltages
to be equal to half the voltage applied to this input.
PGND (Exposed Pad Pin 25): Power Ground. This pin
connects to the source of the internal N-channel power
MOSFET. This pin should be connected close to the (–)
terminal of CIN and COUT.
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LTC3617
FUNCTIONAL Block Diagram
18
2
19
3
24
RUN
1
SGND
SVIN
BANDGAP
AND
BIAS
20
RT
SYNC
23
4
ITH
+
ITH SENSE
COMPARATOR
INTERNAL
COMPENSATION
OSCILLATOR
SVIN – 0.3V
–
11
17
CURRENT
SENSE
VTTR
VDDQIN
–
ITH
LIMIT
PMOS CURRENT
COMPARATOR
+
+
–
SOFT-START
SLOPE
COMPENSATION
+
22
10
PVIN PVIN PVIN PVIN
SW
DRIVER
VFB
–
1.08VDDQIN/2
SW
ERROR
AMPLIFIER
SW
+
SW
SW
–
SW
LOGIC
SW
+
0.92VDDQIN/2
–
VTTR
+
0.45V
–
SW
5
6
7
8
13
14
15
16
REVERSE CURRENT
COMPARATOR
IREV
+
–
PGND
25
EXPOSED PAD
PGOOD
21
3617 BD
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LTC3617
Operation
Main Control Loop
The LTC3617 is a monolithic, constant frequency, current
mode step-down DC/DC converter. During normal operation, the internal top power switch (P-channel MOSFET) is
turned on at the beginning of each clock cycle. Current in
the inductor increases until the current comparator trips
and turns off the top power switch. The peak inductor
current when the current comparator trips is controlled
by the voltage on the ITH pin. The error amplifier adjusts
the voltage on the ITH pin by comparing the feedback
signal from a resistor divider on the VFB pin with a reference voltage on the VTTR pin. VTTR is the output of an
op amp buffer that expresses one-half the voltage on the
VDDQIN pin. When the load current increases, it causes a
reduction in the feedback voltage relative to the reference.
The error amplifier raises the ITH voltage until the average
inductor current matches the new load current. Typical
voltage range for the ITH pin is from 0.2V to 1.05V with
0.575V corresponding to zero current.
When the top power switch shuts off, the synchronous
bottom power switch (N-channel MOSFET) turns on until
either the bottom current limit is reached or the next clock
cycle begins. The bottom current limit is typically set at
–10A.
The operating frequency defaults to 2.25MHz when RT is
connected to SVIN, or can be set by an external resistor
connected between the RT pin and ground, or by a clock
signal applied to the RT pin. The switching frequency can
be set from 300kHz to 4MHz.
Overvoltage and undervoltage comparators pull the
PGOOD output low if the output voltage varies more than
±8% (typical) from the set point.
VTTR Voltage Buffer Output
An internal high accuracy op amp buffer generates a VTTR
pin voltage that is equal to VDDQIN • 0.5. VTTR can source
and sink up to 10mA and is stable with a maximum bypass
capacitor of 0.1µF. Short-circuit current limit is set around
20mA to prevent damage to the op amp. VTTR is also the
reference voltage of the error amplifier which controls the
output voltage. Therefore, large transients on this pin will
impact the behavior of the output.
VIN Overvoltage Protection
In order to protect the internal power MOSFET devices
against transient voltage spikes, the LTC3617 constantly
monitors the VIN pin for an overvoltage condition. When
VIN rises above 6.5V, the regulator suspends operation by
shutting off both MOSFETS. The regulator executes its
soft-start function when exiting an overvoltage condition.
Low Supply Operation
The LTC3617 is designed to operate down to an input
supply voltage of 2.25V. An important consideration at low
input supply voltages is that the RDS(ON) of the P-channel
and N-channel power switches increases. The user should
calculate the power dissipation when the LTC3617 is used
at 100% duty cycle with low input voltages to ensure that
thermal limits are not exceeded. See the Typical Performance Characteristics graphs.
Short-Circuit Protection
The peak inductor current when the current comparator
shuts off the top power switch is controlled by the voltage
on the ITH pin.
If the output current increases, the error amplifier raises the
ITH pin voltage until the average inductor current matches
the new load current. In normal operation the LTC3617
clamps the maximum ITH pin voltage at approximately 1.05V
which corresponds typically to 10A peak inductor current.
When the output is shorted to ground, the inductor current decays very slowly during a single switching cycle.
To prevent current runaway from occurring, a secondary
current limit is imposed on the inductor current. If the
inductor current measured through the bottom MOSFET
increases beyond 12A typical, the top power MOSFET will
be held off and switching cycles will be skipped until the
inductor current decreases below this limit.
3617fa
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LTC3617
Applications Information
The basic LTC3617 application circuit is shown in Figure 1.
Operating Frequency
Selection of the operating frequency is a trade-off between
efficiency and component size. High frequency operation
allows the use of smaller inductor and capacitor values.
Operation at lower frequencies improves efficiency by
reducing internal gate charge losses but requires larger
inductance values and/or capacitance to maintain low
output voltage ripple.
The operating frequency of the LTC3617 is determined
by an external resistor that is connected between the RT
pin and ground. The value of the resistor sets the ramp
current that is used to charge and discharge an internal
timing capacitor within the oscillator and can be calculated
by using the following equation:
Tying the RT pin to SVIN sets the default internal operating
frequency to 2.25MHz ±20%.
Frequency Synchronization
The LTC3617’s internal oscillator can be synchronized to
an external frequency by applying a square wave clock
signal to the SYNC pin. During synchronization, the top
switch turn-on is locked to the falling edge of the external
frequency source. The synchronization frequency range
is 300kHz to 4MHz.
The frequency set by the resistor on the RT pin should be
the same as the external clock frequency to ensure the
internal oscillator properly adjusts when the clock signal
is applied or removed.
VIN
RT
3.82 • 1011Hz
RT =
Ω – 16kΩ
fOSC (Hz )
SYNC
SGND
Although frequencies as high as 4MHz are possible, the
minimum on-time of the LTC3617 imposes a minimum
limit on the operating duty cycle. The minimum on-time
is typically 80ns; therefore, the minimum duty cycle is
equal to 80ns • fOSC(Hz)•100%.
VIN
2.5V
RPG
100k
RT
365k
PGOOD
SVIN
RUN
VDDQIN
RT
CC
680pF
CIN
22µF
×4
VIN
0.4V
0.1µF
L1
0.33µH
SW
SGND
COUT
100µF
VTTR
1.25V
±10mA
VOUT
1.25V
±6A
fOSC
2.25MHz
LTC3617
SVIN
RT
fOSC ∝1/RT
SYNC
SGND
RT
VIN
VTTR
LTC3617
PGOOD
RC
10k
PVIN
LTC3617
SVIN
RT
LTC3617
SVIN
RT
SYNC
SGND
fOSC
1/TP
1.2V
0.3V
TP
3617 F02
CC1
10pF
(OPT)
ITH
SYNC
PGND
VFB
3617 F01
Figure 2. Setting Switching Frequency
Figure 1. 1.25V, ±6A at 1MHz from 2.5V
3617fa
10
LTC3617
Applications Information
Inductor Selection
For a given input and output voltage, the inductor value
and operating frequency determine the ripple current. The
ripple current ∆IL increases with higher VIN and decreases
with higher inductance:
 V
  V 
∆IL =  OUT  •  1– OUT 
VIN 
 fSW • L  
Having a lower ripple current reduces the core losses
in the inductor, the ESR losses in the output capacitors
and the output voltage ripple. A reasonable starting point
for selecting the ripple current is ∆IL = 0.3 • IOUT(MAX).
The largest ripple current occurs at the highest VIN. To
guarantee that the ripple current stays below a specified
maximum, the inductor value should be chosen according
to the following equation:

 
VOUT 
VOUT
•
1–
L=
 

 fSW • ∆IL(MAX)   VIN(MAX) 
Inductor Core Selection
Once the value for L is known, the type of inductor must be
selected. Actual core loss is independent of core size for a
fixed inductor value, but it is very dependent on the inductance selected. As the inductance increases, core losses decrease. Unfortunately, increased inductance requires more
turns of wire and therefore, copper losses will increase.
Ferrite designs have very low core losses and are preferred at high switching frequencies, so design goals can
concentrate on copper loss and preventing saturation.
Ferrite core material saturates “hard,” meaning that inductance collapses abruptly when the peak design current is
exceeded. This results in an abrupt increase in inductor
ripple current and consequently output voltage ripple. Do
not allow a ferrite core to saturate!
Different core materials and shapes will change the size/
current and price/current relationship of an inductor. Toroid
or shielded pot cores in ferrite or permalloy materials are
small and don’t radiate much energy, but generally cost
more than powdered iron core inductors with similar
characteristics. The choice of which style inductor to use
mainly depends on the price versus size requirements
and any radiated field/EMI requirements. Table 1 shows
some typical surface mount inductors that work well in
LTC3617 applications.
Input Capacitor (CIN) Selection
In continuous mode, the source current of the top Pchannel MOSFET is a square wave of duty cycle VOUT/
VIN. To prevent large input voltage transients, a low ESR
capacitor sized for the maximum RMS current must be
used at VIN.
The maximum RMS capacitor current is given by:
IRMS =IOUT(MAX) •
 V

VOUT
•  IN – 1
VIN
 VOUT 
This formula has a maximum at VIN = 2 • VOUT, where IRMS =
IOUT/2. This simple worst-case condition is commonly used
for design because even significant deviations do not offer
much relief. Note that ripple current ratings from capacitor
manufacturers are often based on only 2000 hours of life
which makes it advisable to further derate the capacitor,
or choose a capacitor rated at a higher temperature than
required. Several capacitors may also be paralleled to meet
size or height requirements in the design.
3617fa
11
LTC3617
Applications Information
Table 1. Representative Surface Mount Inductors
INDUCTANCE
(μH)
DCR
(mΩ)
SATURATION
CURRENT (A)
DIMENSIONS
(mm)
HEIGHT
(mm)
Vishay IHLP-2525CZ-01
0.10
1.5
60
6.5 × 6.9
3
0.15
1.9
52
6.5 × 6.9
3
0.20
2.4
41
6.5 × 6.9
3
0.22
2.5
40
6.5 × 6.9
3
0.33
3.5
30
6.5 × 6.9
3
0.47
4
26
6.5 × 6.9
3
Sumida CDMC6D28 Series
0.2
2.5
21.7
7.25 × 6.5
3
0.3
3.2
15.4
7.25 × 6.5
3
0.47
4.2
13.6
7.25 × 6.5
3
Cooper HCM0703 Series
0.22
2.8
40
6.8 × 7.1
3.0
0.47
4.2
26
6.8 × 7.1
3.0
0.68
5.5
25
6.8 × 7.1
3.0
Würth Electronik WE-HC744310 Series
0.24
1.8
40
7 × 6.9
3.0
0.52
3.7
20
7 × 6.9
3.0
Coilcraft SLC7530 Series
0.100
0.123
20
7.5 × 6.7
3
0.188
0.100
21
7.5 × 6.7
3
0.272
0.100
14
7.5 × 6.7
3
0.350
0.100
11
7.5 × 6.7
3
0.400
0.100
8
7.5 × 6.7
3
Output Capacitor (COUT ) Selection
The selection of COUT is typically driven by the required
ESR to minimize voltage ripple and load step transients
(low ESR ceramic capacitors are discussed in the next
section). Typically, once the ESR requirement is satisfied,
the capacitance is adequate for filtering. The output ripple
∆VOUT is determined by:


1
∆VOUT ≤ ∆IL •  ESR +
8 • fSW • COUT 

where fOSC = operating frequency, COUT = output capacitance and ∆IL = ripple current in the inductor. The output
ripple is highest at maximum input voltage since ∆IL
increases with input voltage.
In surface mount applications, multiple capacitors may
have to be paralleled to meet the capacitance, ESR or RMS
current handling requirement of the application. Aluminum
electrolytic, special polymer, ceramic and dry tantalum
capacitors are all available in surface mount packages.
Tantalum capacitors have the highest capacitance density,
but can have higher ESR and must be surge tested for
use in switching power supplies. Aluminum electrolytic
capacitors have significantly higher ESR, but can often
be used in extremely cost-sensitive applications provided
that consideration is given to ripple current ratings and
long-term reliability.
Ceramic Input and Output Capacitors
Ceramic capacitors have the lowest ESR and can be cost
effective, but also have the lowest capacitance density,
have high voltage and temperature coefficients, and exhibit
audible piezoelectric effects. In addition, the high Q of
ceramic capacitors along with trace inductance can lead
to significant ringing.
They are attractive for switching regulator use because of
their very low ESR, but care must be taken when using
only ceramic input and output capacitors.
Ceramic capacitors are prone to temperature effects
which require the designer to check loop stability over
the operating temperature range. To minimize their large
temperature and voltage coefficients, only X5R or X7R
ceramic capacitors should be used.
When a ceramic capacitor is used at the input and the power
is being supplied through long wires, such as from a wall
adapter, a load step at the output can induce ringing at the
VIN pin. At best, this ringing can couple to the output and
be mistaken as loop instability. At worst, the ringing at the
input can be large enough to damage the part.
3617fa
12
LTC3617
Applications Information
Since the ESR of a ceramic capacitor is so low, the input
and output capacitor must instead fulfill a charge storage
requirement. During a load step, the output capacitor must
instantaneously supply the current until the feedback loop
raises the switch current enough to support the load. The
time required for the feedback loop to respond is dependent
on the compensation components and the output capacitor size. Typically, 3 to 4 switching cycles are required to
respond to a load step, but only in the first cycle does the
output drop linearly. The output droop, VDROOP , is usually
about 2 to 4 times the linear drop of the first cycle; however,
this behavior can vary depending on the compensation
component values. Thus, a good place to start is with the
output capacitor size of approximately:
COUT ≈
3.5 • ∆IOUT
fSW • VDROOP
This is only an approximation; more capacitance may
be needed depending on the duty cycle and load step
requirements.
In most applications, the input capacitor is merely required
to supply high frequency bypassing, since the impedance
to the supply is very low.
Output Voltage Programming
In most applications, VOUT is connected directly to VFB.
The output voltage will be equal to one-half of the voltage
on the VDDQIN pin for this case.
VOUT =
VDDQIN
2
If a different output relationship is desired, an external
resistor divider from VOUT to VFB can be used. The output
voltage will then be set according to the following equation:
VOUT =
VDDQIN  R2 
•  1+ 
 R1
2
VOUT
R2
VFB
LTC3617
R1
SGND
3617 F03
Figure 3. Setting the Output Voltage
Internal and External Compensation
The regulator loop response can be checked by looking at
the load current transient response. Switching regulators
take several cycles to respond to a step in DC load current.
When a load step occurs, VOUT shifts by an amount equal
to ∆ILOAD • ESR, where ESR is the effective series resistance of COUT . ∆ILOAD also begins to charge or discharge
COUT , generating the feedback error signal that forces the
regulator to adapt to the current change and return VOUT to
its steady-state value. During this recovery time VOUT can
be monitored for excessive overshoot or ringing, which
would indicate a stability problem. The availability of the
ITH pin allows the transient response to be optimized over
a wide range of output capacitance.
The ITH external components (RC and CC) shown in Figure 1 provide adequate compensation as a starting point
for most applications. The values can be modified slightly
to optimize transient response once the final PCB layout
is done and the particular output capacitor type and value
have been determined. The output capacitors need to be
selected because the various types and values determine
the loop gain and phase. The gain of the loop will be increased by increasing RC and the bandwidth of the loop
will be increased by decreasing CC. If RC is increased by
the same factor that CC is decreased, the zero frequency
will be kept the same, thereby keeping the phase shift the
same in the most critical frequency range of the feedback
loop. The output voltage settling behavior is related to the
stability of the closed-loop system. The external capacitor, CC1, (Figure 1) is not needed for loop stability, but it
helps filter out any high frequency noise that may couple
onto that node.
3617fa
13
LTC3617
Applications Information
The first circuit in the Typical Applications section uses
faster compensation to improve step response.
A second, more severe transient is caused by switching
in loads with large (>1μF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with COUT , causing a rapid drop in VOUT . No regulator can
alter its delivery of current quickly enough to prevent this
sudden step change in output voltage if the load switch
resistance is low and it is driven quickly. More output
capacitance may be required depending on the duty cycle
and load step requirements.
Internal Compensation
The LTC3617 provides the option to use a fixed internal
loop compensation network to reduce the required external
component count and design time. The internal loop compensation network can be selected by connecting the ITH
pin to SVIN. However, selecting the internal compensation
might result in an unstable output voltage when tracking
down to 0V.
Shutdown and Soft-Start
The RUN pin provides a means to shut down the LTC3617.
Tying the RUN pin to SGND places the regulator in a low
quiescent current shutdown state (IQ < 1µA).
Pulling the RUN pin high enables the regulator which allows
an internal soft-start to slowly ramp the VTTR pin voltage
at a rate of approximately 850mV/ms. During this startup time, the regulator will operate in discontinuous mode
until the VTTR pin voltage exceeds approximately 0.45V.
When RUN is pulled low, the regulator will force the peak
inductor current to discharge to around 0A before shutting
off both power MOSFETs.
Output Power Good
VOUT
50mV/DIV
IL
2A/DIV
VIN = 3.3V
40µs/DIV
VOUT = 1.25V
ILOAD = 100mA TO 3A
COMPENSATION FIGURE 1
3617 F04
Figure 4. Load Step Transient with
External Compensation
VOUT
50mV/DIV
The PGOOD output of the LTC3617 is driven by a 17Ω
(typical) open-drain pull-down MOSFET. This MOSFET
turns off approximately 3ms to 4ms after the beginning
of start-up and once the output voltage is within 5% (typical) of 0.5 • VDDQIN, allowing the voltage at PGOOD to
rise via an external pull-up resistor (100k typical). If the
output voltage exits an 8% (typical) regulation window
of 0.5 • VDDQIN or the VTTR pin is lower than 0.45V, the
open-drain output will pull low, thus dropping the PGOOD
pin voltage. To prevent unwanted PGOOD glitches during
transients or dynamic VOUT changes, the LTC3617 PGOOD
falling edge includes a filter time of approximately 105μs.
Efficiency Considerations
IL
2A/DIV
VIN = 3.3V
40µs/DIV
VOUT = 1.25V
ILOAD = 100mA TO 3A
VITH = 3.3V
OUTPUT CAPACITOR VALUE FIGURE 1
3617 F05
Figure 5. Load Step Transient with
Internal Compensation
The efficiency of a switching regulator is equal to the output
power divided by the input power times 100%. It is often
useful to analyze individual losses to determine what is
limiting the efficiency and which change would produce
the most improvement. Efficiency can be expressed as:
Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percentage of input power.
3617fa
14
LTC3617
Applications Information
Although all dissipative elements in the circuit produce
losses, two main sources usually account for most of
the losses: VIN quiescent current and I2R losses. The VIN
quiescent current loss dominates the efficiency loss at
very low load currents whereas the I2R loss dominates
the efficiency loss at medium to high load currents. In a
typical efficiency plot, the efficiency curve at very low load
currents can be misleading since the actual power lost is
usually of no consequence.
1. The VIN quiescent current is due to two components: the
DC bias current as given in the Electrical Characteristics
and the internal main switch and synchronous switch
gate charge currents. The gate charge current results
from switching the gate capacitance of the internal power
MOSFET switches. Each time the gate is switched from
low to high to low again, a packet of charge dQ moves
from VIN to ground. The resulting dQ/dt is the current
into VIN due to gate charge, and it is typically larger than
the DC bias current. Both the DC bias and gate charge
losses are proportional to VIN; thus, their effects will
be more pronounced at higher supply voltages.
2. I2R losses are calculated from the resistances of the
internal switches, RSW , and external inductor, RL. In
continuous mode the average output current flowing
through inductor L is “chopped” between the main
switch and the synchronous switch. Thus, the series
resistance looking into the SW pin is a function of both
top and bottom MOSFET RDS(ON) and the duty cycle
(DC) as follows:
RSW = (RDS(ON)TOP)(DC) + (RDS(ON)BOT)(1 – DC)
The RDS(ON) for both the top and bottom MOSFETs can
be obtained from the Typical Performance Characteristics curves. To obtain I2R losses, simply add RSW to
RL and multiply the result by the square of the average
output current.
Other losses including CIN and COUT ESR dissipative
losses and inductor core losses generally account for
less than 2% of the total loss.
Thermal Considerations
In most applications, the LTC3617 does not generate much
heat due to its high efficiency.
However, in high current applications where the LTC3617
is running at high ambient temperature with low supply
voltage and high duty cycles, such as in dropout, the heat
generated may exceed the maximum junction temperature
of the part. If the junction temperature reaches approximately 160°C, both power switches will be turned off and
the SW node will become high impedance.
To prevent the LTC3617 from exceeding the maximum
junction temperature, some thermal analysis is required.
The temperature rise is given by:
TRISE = (PD) • (θJA)
where PD is the power dissipated by the regulator and θJA
is the thermal resistance from the junction of the die to
the ambient temperature. The junction temperature, TJ,
is given by:
TJ = TA + TRISE
where TA is the ambient temperature.
As an example, consider the case when the LTC3617 is
used in a DDR application where VIN = 3.3V, IOUT = 6A,
f = 1MHz, VOUT = 1.25V. The equivalent power MOSFET
resistance RSW is:
RSW = RDS(ON)TOP •
= 35mΩ •
 V 
VOUT
+RDS(ON)BOT •  1– OUT 
VIN
VIN 

1.25
 1.25 
+ 25mΩ •  1–
= 28.79mΩ

3.3 
3.3
The VIN current during 1MHz with no load is about 22mA,
which includes switching and internal biasing current
loss, transition loss, inductor core loss and other losses
in the application. Therefore, the total power dissipated
by the part is:
PD = IOUT2 • RSW + VIN • IVIN (No Load)
= 36A2 • 28.79mΩ + 3.3V • 22mA = 1.11W
The QFN 3mm × 5mm package junction-to-ambient thermal
resistance, θJA, is around 43°C/W. Therefore, the junction
temperature of the regulator operating in a 25°C ambient
temperature is approximately:
TJ = 1.11W • 43°C/W + 25°C = 73°C
3617fa
15
LTC3617
Applications Information
Remembering that the above junction temperature is
obtained from the RDS(ON) at 25°C, we might recalculate
the junction temperature based on a higher RDS(ON) since
it increases with temperature. Redoing the calculation
assuming that RSW increased 15% at 73°C yields a new
junction temperature of 79°C. Therefore, we can safely assume that the actual junction temperature will not exceed
the absolute maximum junction temperature of 125°C.
Note that for very low input voltage, the junction temperature will be higher due to increased switch resistance,
RDS(ON). It is not recommended to use full load current
with high ambient temperature and low input voltage.
To maximize the thermal performance of the LTC3617 the
exposed pad must be soldered to a ground plane. See the
PCB Layout Board Checklist.
Design Example
As a design example, consider the LTC3617 in an application with the following specifications:
VIN = 2.5V, VOUT = 1.25V, IOUT(MAX) = 6A, IOUT(MIN) =
200mA, f = 2.6MHz.
First, calculate the timing resistor:
RT =
3.8211Hz
– 16k = 130kΩ
2.6MHz
Next, calculate the inductor value for about 33% ripple
current at maximum VIN:
 1.25V   1.25V 
L=
• 1–
= 0.12µH
 2.6MHz • 2A  
2.5V 
Using a standard value of 0.1µH inductor results in a
maximum ripple current of:
CIN should be selected for a maximum current rating of:
IRMS = 6A •
1.25V
 2.5V

• 
– 1 = 3ARMS
 1.25V 
2.5V
Decoupling PVIN with four 10µF to 22µF capacitors is
adequate for most applications. Connecting the VFB pin
directly to VOUT will set the output voltage equal to one-half
of the voltage on the VDDQIN pin. The complete circuit of
this design example is illustrated in Figure 1.
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3617:
1. A ground plane is recommended. If a ground plane layer
is not used, the signal and power grounds should be
segregated with all small-signal components returning
to the SGND pin at one point which is then connected
to the PGND pin close to the LTC3617.
2. Connect the (+) terminal of the input capacitor(s), CIN,
as close as possible to the PVIN pin, and the (–) terminal
as close as possible to the exposed pad, PGND. This
capacitor provides the AC current into the internal power
MOSFETs.
3. Keep the switching node, SW, away from all sensitive
small-signal nodes.
4. Flood all unused areas on all layers with copper. Flooding with copper will reduce the temperature rise of
power components. Connect the copper areas to PGND
(exposed pad) for best performance.
5. Connect the VFB pin directly to VOUT.

  1.25V 
1.25V
∆IL = 
= 2.4A
• 1–
 2.6MHz • 0.1µH 
2.5V 
COUT will be selected based on the ESR that is required
to satisfy the output voltage ripple requirement and the
bulk capacitance needed for loop stability. For this design,
a 100µF ceramic capacitor is used with a X5R or X7R
dielectric.
3617fa
16
LTC3617
Typical Applications
1.25V, ±6A DDR Memory Termination Supply, 2.25MHz
VIN
2.5V TO 5.5V
CIN
22µF
×4
RF
24Ω
CF
1µF
VDDQ
2.5V
RC
20k
CC
470pF
R1
100k
PGOOD
CC1
10pF
PVIN
VTTR
SVIN
RUN
VDDQIN
RT
LTC3617
SW
SGND
PGND
PGOOD
ITH
SYNC
CO1
0.1µF
L1
0.15µH
CO2
100µF
VREF
1.25V
±10mA
VTT
1.25V
±6A
VFB
3617 TA02a
L1: VISHAY IHLP-2525CZ-01 150nH
Efficiency vs Load Current
Load Step Response
100
90
VTT
50mV/DIV
EFFICIENCY (%)
80
70
60
IL
4A/DIV
50
40
30
20
VIN = 2.5V
VIN = 3.3V
VIN = 5V
10
0
0.1
1
LOAD CURRENT (A)
VIN = 3.3V
40µs/DIV
VTT = 1.25V
ILOAD = 100mA TO 6A
3617 TA02c
10
3617 TA02b
3617fa
17
LTC3617
Typical Applications
0.75V, ±6A DDR Termination Using a 1MHz External Clock
VIN
2.5V TO 5.5V
CIN
22µF
×4
RF
24Ω
CF
1µF
VDDQ
1.5V
R2
100k
RC
6k
R1
365k
PGOOD
CC
1.5nF
PVIN
VTTR
SVIN
RUN
VDDQIN
RT
CC1
10pF
L1
0.33µH
LTC3617
PGOOD
ITH
SYNC
VREF
0.75V
CO1 ±10mA
0.1µF
VTT
0.75V
CO2 ±6A
100µF
SW
SGND
PGND
VFB
1MHz CLOCK
3617 TA03a
L1: VISHAY IHLP-2525CZ-01 330nH
External Start-Up
Output Tracking Up/Down
VDDQ
VDDQ
500mV/DIV
500mV/DIV
VREF/VTT
2ms/DIV
VREF/VTT
4ms/DIV
3617 TA03b
3617 TA03c
Package Description
UDD Package
24-Lead Plastic QFN (3mm × 5mm)
(Reference LTC DWG # 05-08-1833 Rev Ø)
3.00 ± 0.10
0.75 ± 0.05
1.50 REF
23
R = 0.05 TYP
0.70 ±0.05
3.50 ± 0.05
2.10 ± 0.05
24
0.40 ± 0.10
PIN 1
TOP MARK
(NOTE 6)
3.65 ± 0.05
1.50 REF
PIN 1 NOTCH
R = 0.20 OR 0.25
× 45° CHAMFER
1.65 ± 0.05
5.00 ± 0.10
1
2
3.65 ± 0.10
3.50 REF
1.65 ± 0.10
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
3.50 REF
4.10 ± 0.05
5.50 ± 0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
(UDD24) QFN 0808 REV Ø
0.200 REF
0.00 – 0.05
R = 0.115
TYP
0.25 ± 0.05
0.50 BSC
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
3617fa
18
LTC3617
Revision History
REV
DATE
DESCRIPTION
PAGE NUMBER
A
7/11
Updated Main Control section
Updated Output Power Good section
Updated Typical Application and scale on graphs
9
14
18, 20
3617fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
19
LTC3617
Typical Application
DDR2 Termination, 1MHz
VIN
2.25V TO 5.5V
22µF
×4
VDDQ
1.8V
R1
365k
R2
100k
RC
6k
PGOOD
CC
2.2nF
SVIN
RUN
VDDQIN
RT
LTC3617
PGOOD
ITH
CC1
10pF
PVIN
VTTR
SYNC
External Start-Up
VDDQ
VREF
0.9V
0.1µF ±10mA
500mV/DIV
L1
0.33µH
SW
100µF
SGND
PGND
VTT
0.9V
47µF ±6A
VFB
VREF/VTT
400µs/DIV
3617 TA04b
3617 TA04a
L1: COILCRAFT D03316T
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5.5V, 7A (IOUT), 1.5MHz, Synchronous Step-Down DC/DC
Converter
95% Efficiency, VIN(MIN) = 2.5V, VIN(MAX) = 5.5V, VOUT(MIN) = 0.6V,
IQ = 450µA, ISD <1µA, 5mm × 7mm QFN-38 Package
LTC3416
5.5V, 4A (IOUT), 4MHz, Synchronous Step-Down DC/DC
Converter
95% Efficiency, VIN(MIN) = 2.25V, VIN(MAX) = 5.5V, VOUT(MIN) = 0.8V,
IQ = 64µA, ISD <1µA, TSSOP20E Package
LTC3413
5.5V, 3A (IOUT Sink/Source), 2MHz, Monolithic Synchronous
Regulator for DDR/QDR Memory Termination
90% Efficiency, VIN(MIN) = 2.25V, VIN(MAX) = 5.5V, VOUT(MIN) = VREF /2,
IQ = 280µA, ISD <1µA, TSSOP16E Package
LTC3412A
5.5V, 2.5A (IOUT), 4MHz, Synchronous Step-Down DC/DC
Converter
95% Efficiency, VIN(MIN) = 2.5V, VIN(MAX) = 5.5V, VOUT(MIN) = 0.8V,
IQ = 60µA, ISD <1µA, 4mm × 4mm QFN-16 TSSOP16E Package
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20 Linear Technology Corporation
LT 0711 REV A • PRINTED IN USA
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