IDT IDT71T75602S150BG 512k x 36, 1m x 18 2.5v synchronous zbtâ ¢ srams 2.5v i/o, burst counter pipelined output Datasheet

512K x 36, 1M x 18
2.5V Synchronous ZBT™ SRAMs
2.5V I/O, Burst Counter
Pipelined Outputs
Features
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IDT71T75602
IDT71T75802
Description
512K x 36, 1M x 18 memory configurations
Supports high performance system speed - 225 MHz
(3.0 ns Clock-to-Data Access)
ZBTTM Feature - No dead cycles between write and read
cycles
Internally synchronized output buffer enable eliminates the
need to control OE
W (READ/WRITE) control pin
Single R/W
Positive clock-edge triggered address, data, and control
signal registers for fully pipelined applications
4-word burst capability (interleaved or linear)
BW 1 - BW 4) control (May tie active)
Individual byte write (BW
Three chip enables for simple depth expansion
2.5V power supply (±5%)
2.5V I/O Supply (VDDQ)
Power down controlled by ZZ input
Boundary Scan JTAG Interface (IEEE 1149.1 Compliant)
Packaged in a JEDEC standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA)
The IDT71T75602/802 are 2.5V high-speed 18,874,368-bit
(18 Megabit) synchronous SRAMs. They are designed to eliminate dead
bus cycles when turning the bus around between reads and writes, or
writes and reads. Thus, they have been given the name ZBTTM, or Zero
Bus Turnaround.
Address and control signals are applied to the SRAM during one
clock cycle, and two cycles later the associated data cycle occurs, be it
read or write.
The IDT71T75602/802 contain data I/O, address and control signal
registers. Output enable is the only asynchronous signal and can be used
to disable the outputs at any given time.
A Clock Enable CEN pin allows operation of the IDT71T75602/802
to be suspended as long as necessary. All synchronous inputs are ignored
when (CEN) is high and the internal device registers will hold their previous
values.
There are three chip enable pins (CE1, CE2, CE2) that allow the
user to deselect the device when desired. If any one of these three is not
asserted when ADV/LD is low, no new memory operation can be initiated.
Pin Description Summary
A0-A19
Address Inputs
Input
Synchronous
CE1, CE2, CE2
Chip Enables
Input
Synchronous
OE
Output Enable
Input
Asynchronous
R/W
Read/Write Signal
Input
Synchronous
CEN
Clock Enable
Input
Synchronous
BW1, BW2, BW3, BW4
Individual Byte Write Selects
Input
Synchronous
CLK
Clock
Input
N/A
ADV/ LD
Advance burst address / Load new address
Input
Synchronous
LBO
Linear / Interleaved Burst Order
Input
Static
TMS
Test Mode Select
Input
N/A
TDI
Test Data Input
Input
N/A
TCK
Test Clock
Input
N/A
TDO
Test Data Input
Output
N/A
TRST
JTAG Reset (Optional)
Input
Asynchronous
ZZ
Sleep Mode
Input
Synchronous
I/O0-I/O31, I/OP1-I/OP4
Data Input / Output
I/O
Synchronous
VDD, VDDQ
Core Power, I/O Power
Supply
Static
VSS
Ground
Supply
Static
5313 tbl 01
APRIL 2004
1
©2004 Integrated Device Technology, Inc.
DSC-5313/08
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Description (cont.)
However, any pending data transfers (reads or writes) will be completed.
The data bus will tri-state two cycles after the chip is deselected or a write
is initiated.
The IDT71T75602/802 have an on-chip burst counter. In the burst
mode, the IDT71T75602/802 can provide four cycles of data for a single
address presented to the SRAM. The order of the burst sequence is
defined by the LBO input pin. The LBO pin selects between linear and
interleaved burst sequence. The ADV/LD signal is used to load a new
external address (ADV/LD = LOW) or increment the internal burst counter
(ADV/LD = HIGH).
The IDT71T75602/802 SRAMs utilize IDT’s latest high-performance
2.5V CMOS process, and are packaged in a JEDEC Standard 14mm x
20mm 100pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid
array (BGA).
Pin Definitions (1)
Symbol
Pin Function
I/O
Active
Description
A0-A19
Address Inputs
I
N/A
Synchronous Address inputs. The address register is triggered by a combination of the rising edge of CLK,
ADV/ LD low, CEN low, and true chip enables.
ADV/ LD
Advance / Load
I
N/A
ADV/ LD is a sync hronous input that is used to load the internal registers with new address and control when it is
sampled lo w at the rising edge of clock with the chip selected. When ADV/LD is low with the chip deselected,
any burst in progress is terminated. When ADV/ LD is sampled high then the internal burst counter is advanced
for any burst that was in progress. The external addresses are ignored when ADV/ LD is sampled high.
R/ W
Read / Write
I
N/A
R/W signal is a synchronous input that identifies whether the current load cycle initiated is a Read or Write access
to the memory array. The data bus activity for the current cycle takes place two clock cycles later.
CEN
Clock Enable
I
LOW
Synchronous Clock Enable Input. When CEN is sampled high, all other synchronous inputs, including clock are
ignored and outputs remain unchanged. The effect of CEN sampled high on the device outputs is as if the low
to high clock transition did not occur. For normal operation, CEN must be sampled low at rising edge of clock.
BW1-BW4
Individual Byte
Write Enables
I
LOW
Synchronous byte write enables. Each 9-bit byte has its own active low byte write enable. On load write cycles
(when R/ W and ADV/ LD are sampled low) the appropriate byte write signal (BW1-BW4) must be valid. The byte
write signal must also be valid on each cycle of a burst write. Byte Write signals are ignored when R/ W is sampled
high. The appropriate byte(s) of data are written into the device two cycles later. BW1-BW4 can all be tied low if
always doing write to the entire 36-bit word.
CE1, CE2
Chip Enables
I
LOW
Synchronous active low chip enable. CE1 and CE2 are used with CE2 to enable the IDT71T75602/802 (CE1 or CE2
sampled high or CE 2 sampled low) and ADV/LD low at the rising edge of clock, initiates a deselect cycle. The
ZBTTM has a two cycle deselect, i.e., the data bus will tri-state two clock cycles after deselect is initiated.
CE 2
Chip Enable
I
HIGH
Synchronous active high chip enable. CE 2 is used with CE1 and CE2 to enable the chip. CE 2 has inverted polarity
but otherwise identical to CE1 and CE2.
CLK
Clock
I
N/A
This is the clock input to the IDT71T75602/802. Except for OE, all timing references for the device are made with
respect to the rising edge of CLK.
I/O0-I/O31
I/OP1-I/OP4
Data Input/Output
I/O
N/A
Synchronous data input/output (I/O) pins. Both the data input path and data output path are registered and triggered
by the rising edge of CLK.
LBO
Linear Burst Order
I
LOW
Burst order selection input. When LBO is high the Interleaved burst sequence is selected. When LBO is low the
Linear burst sequence is selected. LBO is a static input and it must not change during device operation.
OE
Output Enable
I
LOW
Asynchronous output enable. OE must be low to read data from the 71T75602/802. When OE is high the I/O pins
are in a high-impedance state.OE does not need to be actively controlled for read and write cycles. In normal
operation, OE can be tied low.
TMS
Test Mode Select
I
N/A
Gives input command for TAP controller. Sampled on rising edge of TDK. This pin has an internal pullup.
TDI
Test Data Input
I
N/A
Serial input of registers placed between TDI and TDO. Sampled on rising edge of TCK. This pin has an internal
pullup.
TCK
Test Clock
I
N/A
Clock input of TAP controller. Each TAP event is clocked. Test inputs are captured on rising edge of TCK, while
test outputs are driven from the falling edge of TCK. This pin has an internal pullup.
TDO
Test Data Output
O
N/A
Serial output of registers placed between TDI and TDO. This output is active depending on the state of the TAP
controller.
TRST
JTAG Reset
(Optional)
I
LOW
Optional asynchronous JTAG reset. Can be used to reset the TAP controller, but not required. JTAG reset occurs
automatically at power up and also resets using TMS and TCK per IEEE 1149.1. If not used TRST can be left
floating. This pin has an internal pullup. Only available in BGA package.
ZZ
Sleep Mode
I
HIGH
Synchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down the IDT71T75602/802 to its
lowest power consumption level. Data retention is guaranteed in Sleep Mode. This pin has an internal pulldown.
VDD
Power Supply
N/A
N/A
2.5V core power supply.
VDDQ
Power Supply
N/A
N/A
2.5V I/O Supply.
VSS
Ground
N/A
N/A
Ground.
5313 tbl 02
NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
6.42
2
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Functional Block Diagram
LBO
512Kx36 BIT
MEMORY ARRAY
Address A [0:18]
D
Q
Address
D
Q
Control
CE1, CE2, CE2
R/W
Input Register
CEN
ADV/LD
BWx
D
DI
Q
DO
Control Logic
Clk
Mux
Sel
D
Clk
Clock
Output Register
Q
Gate
OE
5313 drw 01
TMS
TDI
TCK
TRST
(optional)
Data I/O [0:31],
I/O P[1:4]
TDO
JTAG
LBO
Address A [0:19]
,,
1Mx18 BIT
MEMORY ARRAY
D
Q
Address
D
Q
Control
CE1, CE2, CE2
R/W
Input Register
CEN
ADV/LD
BWx
D
DI
DO
Control Logic
Q
Clk
Mux
Sel
D
Clk
Clock
Output Register
Q
Gate
OE
5313 drw 01b
TMS
TDI
TCK
TRST
JTAG
TDO
Data I/O [0:15],
I/O P[1:2]
(optional)
6.42
3
,,
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Recommended DC Operating
Conditions
Symbol
Parameter
Recommended Operating
Temperature and Supply Voltage
Min.
Typ.
Max.
Unit
Grade
Ambient
Temperature (1)
VSS
VDD
VDDQ
V
Commercial
0° C to +70° C
OV
2.5V ± 5%
2.5V ± 5%
0
V
Industrial
-40° C to +85° C
OV
2.5V ± 5%
2.5V ± 5%
VDD +0.3
V
V
VDD
Core Supply Voltage
2.375
2.5
2.625
V
V DDQ
I/O Supply Voltage
2.375
2.5
2.625
VSS
Ground
0
0
VIH
Input High Voltage - Inputs
1.7
____
VIH
Input High Voltage - I/O
1.7
____
VDDQ +0.3
____
0.7
VIL
(1)
Input Low Voltage
-0.3
NOTE:
1. VIL (min.) = –0.8V for pulse width less than tCYC/2, once per cycle.
5313 tbl 05
NOTE:
1. During production testing, the case temperature equals the ambient temperature.
V
5313 tbl 03
A18
A17
A8
A9
OE
ADV/LD
VDD
VSS
CLK
R/W
CEN
CE2
BW4
BW3
BW2
BW1
CE2
A7
CE1
A6
Pin Configuration — 512K x 36
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
I/OP3
I/O16
I/O17
VDDQ
VSS
I/O18
I/O19
I/O20
I/O21
VSS
VDDQ
I/O22
I/O23
VDD(1)
VDD
VDD(1)
VSS
I/O24
I/O25
VDDQ
VSS
I/O26
I/O27
I/O28
I/O29
VSS
VDDQ
I/O30
I/O31
I/OP4
1
80
2
79
3
78
77
4
5
6
76
75
7
74
8
73
9
72
71
10
11
70
12
69
13
68
14
67
15
66
16
65
64
17
18
19
63
62
20
61
21
60
22
59
23
24
58
57
25
56
26
55
27
54
28
53
29
52
51
30
I/OP2
I/O15
I/O14
VDDQ
VSS
I/O13
I/O12
I/O11
I/O10
VSS
VDDQ
I/O9
I/O8
VSS
VDD(1)
VDD
ZZ
I/O7
I/O6
VDDQ
VSS
I/O5
I/O4
I/O3
I/O2
VSS
VDDQ
I/O1
I/O0
I/OP1
,
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A16
A10
A11
A12
A13
A14
A15
NC / TMS(2)
NC / TDI(2)
VSS
VDD
NC / TDO(2)
NC / TCK(2,3)
LBO
A5
A4
A3
A2
A1
A0
5313 drw 02
Top View
100 TQFP
NOTES:
1. Pins 14, 16, and 66 do not have to be connected directly to VDD as long as the input voltage is ≥ VIH .
2. Pins 38, 39 and 43 will be pulled internally to V DD if not actively driven. To disable the TAP controller without
interfering with normal operation, several settings are possible. Pins 38, 39 and 43 could be tied to V DD or VSS and pin
42 should be left unconnected. Or all JTAG inputs (TMS, TDI and TCK) pins 38, 39 and 43 could be left unconnected
“NC” and the JTAG circuit will remain disabled from power up.
3. Pin 43 is reserved for the 36M address. JTAG is not offered in the 100-pin TQFP package for the 36M ZBT device.
6.42
4
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Absolute Maximum Ratings(1)
Symbol
A18
A8
A9
A6
A7
CE1
CE2
NC
NC
BW2
BW1
CE2
VDD
VSS
CLK
R/W
CEN
OE
ADV/LD
A19
Pin Configuration — 1Mx 18
(2)
1
80
2
79
3
78
VDDQ
VSS
NC
NC
I/O8
I/O9
VSS
VDDQ
I/O10
I/O11
VDD(1)
VDD
VDD(1)
VSS
I/O12
I/O13
VDDQ
VSS
I/O14
I/O15
I/OP2
NC
VSS
VDDQ
NC
NC
NC
4
77
5
76
6
75
7
74
8
73
9
72
71
10
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
53
28
29
A10
NC
NC
VDDQ
VSS
NC
I/OP1
I/O7
I/O6
VSS
VDDQ
I/O5
I/O4
VSS
VDD(1)
VDD
ZZ
I/O3
I/O2
VDDQ
VSS
I/O1
I/O0
NC
NC
VSS
VDDQ
NC
NC
NC
52
30
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
,
NC / TMS(2)
NC / TDI(2)
VSS
VDD
NC / TDO(2)
NC / TCK(2,3)
A11
A12
A13
A14
A15
A16
A17
LBO
A5
A4
A3
A2
A1
A0
NOTES:
1. Pins 14, 16, and 66 do not have to be connected directly to VDD as long as
the input voltage is ≥ VIH .
2. Pins 38, 39 and 43 will be pulled internally to VDD if not actively driven. To
disable the TAP controller without interfering with normal operation, several
settings are possible. Pins 38, 39 and 43 could be tied to VDD or VSS and
pin 42 should be left unconnected. Or all JTAG inputs (TMS, TDI and TCK)
pins 38, 39 and 43 could be left unconnected “NC” and the JTAG circuit
will remain disabled from power up.
3. Pin 43 is reserved for the 36M address. JTAG is not offered in the 100-pin
TQFP package for the 36M ZBT device.
Terminal Voltage with
Respect to GND
-0.5 to +3.6
-0.5 to +3.6
CIN
Input Capacitance
CI/O
I/O Capacitance
VTERM(3,6)
Terminal Voltage with
Respect to GND
-0.5 to VDD
-0.5 to VDD
VTERM(4,6)
Terminal Voltage with
Respect to GND
-0.5 to VDD +0.5
-0.5 to VDD +0.5
VTERM(5,6)
Terminal Voltage with
Respect to GND
-0.5 to VDDQ +0.5
-0.5 to VDDQ +0.5
TA(7)
Operating Ambient
Temperature
0 to +70
-40 to +85
o
C
TBIAS
Temperature Under Bias
-55 to +125
-55 to +125
o
C
TSTG
Storage Temperature
-55 to +125
-55 to +125
o
C
PT
Power Dissipation
2.0
2.0
IOUT
DC Output Current
50
50
Max.
Unit
Symbol
V IN = 3dV
5
pF
CIN
Input Capacitance
V OUT = 3dV
7
pF
CI/O
I/O Capacitance
Input Capacitance
CI/O
I/O Capacitance
V
V
W
mA
Conditions
Max.
Unit
VIN = 3dV
7
pF
VOUT = 3dV
7
pF
Conditions
Max.
Unit
VIN = 3dV
7
pF
VOUT = 3dV
7
pF
5313 tbl 07b
(T A = +25°C, f = 1.0MHz)
CIN
Parameter(1)
Conditions
119 BGA Capacitance
Parameter(1)
V
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VDD terminals only.
3. VDDQ terminals only.
4. Input terminals only.
5. I/O terminals only.
6. This is a steady-state DC parameter that applies after the power supply has
reached its nominal operating value. Power sequencing is not necessary;
however, the voltage on any input or I/O pin cannot exceed VDDQ during power
supply ramp up.
7. During production testing, the case temperature equals TA.
5313 tbl 07
Symbol
V
(TA = +25°C, f = 1.0MHz)
(TA = +25°C, f = 1.0MHz)
Parameter(1)
Unit
165 fBGA Capacitance
100-Pin TQFP Capacitance
Symbol
Industrial
5313 tbl 06
5313 drw 02a
Top View
100 TQFP
Commercial
VTERM
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
NC
NC
NC
Rating
5313 tbl 07a
NOTE:
1. This parameter is guaranteed by device characterization, but not production tested.
6.42
5
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Pin Configuration — 512K
X
36,3 1194 BGA5 (1,2)
1
2
Top View
A
VDDQ
A
A
A
A
6
4
18
6
7
8
A16
VDDQ
A9
CE2
NC
A3
ADV/ LD
A7
A2
VDD
A12
A15
NC
I/OP3
VSS
NC
VSS
I/OP2
I/O15
I/O18
VSS
CE1
VSS
I/O13
I/O14
VDDQ
I/O19
VSS
OE
VSS
I/O12
VDDQ
G
I/O20
I/O21
BW3
A17
BW2
I/O11
I/O10
H
I/O22
I/O23
VSS
R/W
VSS
I/O9
I/O8
B
NC
CE2
C
NC
D
I/O16
E
I/O17
F
(1)
(1)
J
VDDQ
VDD
VDD
VDD
VDD
VDD
VDDQ
K
I/O24
I/O26
VSS
CLK
VSS
I/O6
I/O7
L
I/O25
I/O27
BW4
NC
BW1
I/O4
I/O5
M
VDDQ
I/O28
VSS
CEN
VSS
I/O3
VDDQ
N
I/O29
I/O30
VSS
A1
VSS
I/O2
I/O1
P
I/O31
I/OP4
VSS
A0
VSS
I/OP1
I/O0
A5
LBO
A13
NC
R
NC
T
NC
NC
U
VDDQ
NC/TMS (2)
(1)
VDD
A10
VDD
A11
(2)
NC/TDI
(3)
A14
NC/TCK
(2)
NC
NC/TDO
(2)
NC/TRST(2,4)
ZZ
VDDQ
5313 tbl 25
Pin Configuration — 1M X 18, 119 BGA (1,2)
1
2
3
4
5
Top View
6
7
A
VDDQ
A6
A4
A19
A8
A16
VDDQ
B
NC
CE2
A3
ADV/LD
A9
CE2
NC
C
NC
A7
A2
VDD
A13
A17
NC
D
I/O8
NC
VSS
NC
VSS
I/OP1
NC
E
NC
I/O9
VSS
CE1
VSS
NC
I/O7
F
VDDQ
NC
VSS
OE
VSS
I/O6
VDDQ
G
NC
I/O10
BW2
A18
VSS
NC
I/O5
H
I/O11
NC
VSS
R/W
VSS
I/O4
NC
J
VDDQ
VDD
VDD (1)
VDD
VDD (1)
VDD
VDDQ
K
NC
I/O12
VSS
CLK
VSS
NC
I/O3
L
I/O13
NC
VSS
NC
BW1
I/O2
NC
M
VDDQ
I/O14
VSS
CEN
VSS
NC
VDDQ
N
I/O15
NC
VSS
A1
VSS
I/O1
NC
P
NC
I/OP2
VSS
A0
VSS
NC
I/O0
A5
LBO
VDD
A12
NC
A15
(3)
R
NC
T
NC
U
VDDQ
A10
NC/TMS
(2)
VDD
NC
(2)
NC/TDI
NC/TCK
(1)
A14
(2)
A11
(2)
NC/TDO
ZZ
NC/TRST
(2,4)
VDDQ
5313 tbl 25a
NOTES:
1. J3, R5, and J5 do not have to be directly connected to VDD as long as the input voltage is ≥ VIH.
2. U2, U3, U4 and U6 will be pulled internally to VDD if not actively driven. To disable the TAP controller without interfering with normal operation, several settings
are possible. U2, U3, U4 and U6 could be tied to VDD or VSS and U5 should be left unconnected. Or all JTAG inputs(TMS, TDI, and TCK and TRST) U2, U3,
U4 and U6 could be left unconnected “NC” and the JTAG circuit will remain disabled from power up.
3. The 36M address will be ball T6 (for the 512K x 36 device) and ball T4 (for the 1M x 18 device).
4. TRST is offered as an optional JTAG reset if required in the application. If not needed, can be left floating and will internally be pulled to VDD.
6.42
6
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Synchronous Truth Table(1)
CEN
R/W
Chip(5)
Enable
ADV/ LD
BWx
ADDRESS
USED
PREVIOUS CYCLE
CURRENT CYCLE
I/O
(2 cycles later)
L
L
Select
L
Valid
External
X
LOAD WRITE
D(7)
L
H
Select
L
X
External
X
LOAD READ
Q(7)
L
X
X
H
Valid
Internal
LOAD WRITE /
BURST WRITE
BURST WRITE
(Advance burst counter)(2)
D(7)
L
X
X
H
X
Internal
LOAD READ /
BURST READ
BURST READ
(Advance burst counter)(2)
Q(7)
L
X
Deselect
L
X
X
X
DESELECT or STOP(3)
HiZ
L
X
X
H
X
X
DESELECT / NOOP
NOOP
HiZ
H
X
X
X
X
X
X
SUSPEND(4)
Previous Value
5313 tbl 08
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. When ADV/LD signal is sampled high, the internal burst counter is incremented. The R/W signal is ignored when the counter is advanced. Therefore the nature of
the burst cycle (Read or Write) is determined by the status of the R/W signal when the first address is loaded at the beginning of the burst cycle.
3. Deselect cycle is initiated when either (CE1, or CE2 is sampled high or CE2 is sampled low) and ADV/LD is sampled low at rising edge of clock. The data bus will
tri-state two cycles after deselect is initiated.
4. When CEN is sampled high at the rising edge of clock, that clock edge is blocked from propogating through the part. The state of all the internal registers and the
I/Os remains unchanged.
5. To select the chip requires CE1 = L, CE2 = L, CE2 = H on these chip enables. Chip is deselected if any one of the chip enables is false.
6. Device Outputs are ensured to be in High-Z after the first rising edge of clock upon power-up.
7. Q - Data read from the device, D - data written to the device.
Partial Truth Table for Writes(1)
R/W
BW1
BW2
BW3(3)
BW4(3)
H
X
X
X
X
L
L
L
L
L
L
L
H
H
H
WRITE BYTE 2 (I/O[8:15], I/OP2)
L
H
L
H
H
WRITE BYTE 3 (I/O[16:23], I/OP3)(2,3)
L
H
H
L
H
WRITE BYTE 4 (I/O[24:31], I/OP4)(2,3)
L
H
H
H
L
NO WRITE
L
H
H
H
H
OPERATION
READ
WRITE ALL BYTES
(2)
WRITE BYTE 1 (I/O[0:7], I/OP1)
(2)
5313 tbl 09
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. Multiple bytes may be selected during the same cycle.
3. N/A for X18 configuration.
6.42
7
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Interleaved Burst Sequence Table (LBO=V DD)
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
A0
A1
A0
A1
A0
A1
A0
First Address
0
0
0
1
1
0
1
1
Second Address
0
1
0
0
1
1
1
0
Third Address
1
0
1
1
0
0
0
1
1
1
1
0
0
1
0
0
Fourth Address
(1)
5313 tbl 10
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.
Linear Burst Sequence Table (LBO=V SS)
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
A0
A1
A0
A1
A0
A1
A0
First Address
0
0
0
1
1
0
1
1
Second Address
0
1
1
0
1
1
0
0
Third Address
1
0
1
1
0
0
0
1
1
1
0
0
0
1
1
0
Fourth Address
(1)
5313 tbl 11
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.
Functional Timing Diagram(1)
CYCLE
n+29
n+30
n+31
n+32
n+33
n+34
n+35
n+36
n+37
A29
A30
A31
A32
A33
A34
A35
A36
A37
C29
C30
C31
C32
C33
C34
C35
C36
C37
D/Q27
D/Q28
D/Q29
D/Q30
D/Q31
D/Q32
D/Q33
D/Q34
D/Q35
CLOCK
ADDRESS
(2)
(A0 - A18)
(2)
CONTROL
(R/W, ADV/LD, BWx)
(2)
DATA
I/O[0:31], I/O P[1:4]
,
5313drw 03
NOTES:
1. This assumes CEN, CE1, CE2, CE2 are all true.
2. All Address, Control and Data_In are only required to meet set-up and hold time with respect to the rising edge of clock. Data_Out is valid after a clock-to-data
delay from the rising edge of clock.
6.42
8
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Device Operation - Showing Mixed Load, Burst,
Deselect and NOOP Cycles(2)
Cycle
Address
R/ W
ADV/LD
CE(1)
CEN
BWx
OE
I/O
Comments
n
A0
H
L
L
L
X
X
X
Load read
n+1
X
X
H
X
L
X
X
X
Burst read
n+2
A1
H
L
L
L
X
L
Q0
Load read
n+3
X
X
L
H
L
X
L
Q0+1
n+4
X
X
H
X
L
X
L
Q1
NOOP
n+5
A2
H
L
L
L
X
X
Z
Load read
n+6
X
X
H
X
L
X
X
Z
Burst read
n+7
X
X
L
H
L
X
L
Q2
Deselect or STOP
n+8
A3
L
L
L
L
L
L
Q2+1
Load write
n+9
X
X
H
X
L
L
X
Z
Burst write
n+10
A4
L
L
L
L
L
X
D3
Load write
n+11
X
X
L
H
L
X
X
D3+1
n+12
X
X
H
X
L
X
X
D4
NOOP
n+13
A5
L
L
L
L
L
X
Z
Load write
n+14
A6
H
L
L
L
X
X
Z
Load read
n+15
A7
L
L
L
L
L
X
D5
Load write
n+16
X
X
H
X
L
L
L
Q6
Burst write
n+17
A8
H
L
L
L
X
X
D7
Load read
n+18
X
X
H
X
L
X
X
D7+1
Burst read
n+19
A9
L
L
L
L
L
L
Q8
Load write
Deselect or STOP
Deselect or STOP
NOTES:
1. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
2. H = High; L = Low; X = Don’t Care; Z = High Impedance.
5313 tbl 12
Read Operation(1)
Cycle
Address
R/ W
ADV/LD
CE(2)
CEN
BWx
OE
I/O
Comments
n
A0
H
L
L
L
X
X
X
Address and Control meet setup
n+1
X
X
X
X
L
X
X
X
Clock Setup Valid
n+2
X
X
X
X
X
X
L
Q0
Contents of Address A0 Read Out
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
6.42
9
5313 tbl 13
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Burst Read Operation(1)
Cycle
Address
R/ W
ADV/LD
CE(2)
CEN
BWx
OE
I/O
Comments
n
A0
H
L
L
L
X
X
X
Address and Control meet setup
n+1
X
X
H
X
L
X
X
X
Clock Setup Valid, Advance Counter
n+2
X
X
H
X
L
X
L
Q0
Address A0 Read Out, Inc. Count
n+3
X
X
H
X
L
X
L
Q0+1
Address A0+1 Read Out, Inc. Count
n+4
X
X
H
X
L
X
L
Q0+2
Address A0+2 Read Out, Inc. Count
n+5
A1
H
L
L
L
X
L
Q0+3
Address A0+3 Read Out, Load A1
n+6
X
X
H
X
L
X
L
Q0
Address A0 Read Out, Inc. Count
n+7
X
X
H
X
L
X
L
Q1
Address A1 Read Out, Inc. Count
n+8
A2
H
L
L
L
X
L
Q1+1
Address A1+1 Read Out, Load A2
5313 tbl 14
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
Write Operation(1)
Cycle
Address
R/ W
ADV/LD
CE(2)
CEN
BWx
OE
I/O
Comments
n
A0
L
L
L
L
L
X
X
Address and Control meet setup
n+1
X
X
X
X
L
X
X
X
Clock Setup Valid
n+2
X
X
X
X
L
X
X
D0
Write to Address A0
5313 tbl 15
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
Burst Write Operation(1)
Cycle
Address
R/ W
ADV/LD
CE(2)
CEN
BWx
OE
I/O
Comments
n
A0
L
L
L
L
L
X
X
Address and Control meet setup
n+1
X
X
H
X
L
L
X
X
Clock Setup Valid, Inc. Count
n+2
X
X
H
X
L
L
X
D0
Address A0 Write, Inc. Count
n+3
X
X
H
X
L
L
X
D0+1
Address A0+1 Write, Inc. Count
n+4
X
X
H
X
L
L
X
D0+2
Address A0+2 Write, Inc. Count
n+5
A1
L
L
L
L
L
X
D0+3
Address A0+3 Write, Load A1
n+6
X
X
H
X
L
L
X
D0
Address A0 Write, Inc. Count
n+7
X
X
H
X
L
L
X
D1
Address A1 Write, Inc. Count
n+8
A2
L
L
L
L
L
X
D1+1
Address A1+1 Write, Load A2
5313 tbl 16
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
6.42
10
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Read Operation with Clock Enable Used(1)
Cycle
Address
R/ W
ADV/LD
CE(2)
CEN
BWx
OE
I/O
Comments
n
A0
H
L
L
L
X
X
X
Address and Control meet setup
n+1
X
X
X
X
H
X
X
X
Clock n+1 Ignored
n+2
A1
H
L
L
L
X
X
X
Clock Valid
n+3
X
X
X
X
H
X
L
Q0
Clock Ignored. Data Q0 is on the bus.
n+4
X
X
X
X
H
X
L
Q0
Clock Ignored. Data Q0 is on the bus.
n+5
A2
H
L
L
L
X
L
Q0
Address A0 Read out (bus trans.)
n+6
A3
H
L
L
L
X
L
Q1
Address A1 Read out (bus trans.)
n+7
A4
H
L
L
L
X
L
Q2
Address A2 Read out (bus trans.)
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
5313 tbl 17
Write Operation with Clock Enable Used(1)
Cycle
Address
R/ W
ADV/LD
CE(2)
CEN
BWx
OE
I/O
Comments
n
A0
L
L
L
L
L
X
X
Address and Control meet setup.
n+1
X
X
X
X
H
X
X
X
Clock n+1 Ignored.
n+2
A1
L
L
L
L
L
X
X
Clock Valid.
n+3
X
X
X
X
H
X
X
X
Clock Ignored.
n+4
X
X
X
X
H
X
X
X
Clock Ignored.
n+5
A2
L
L
L
L
L
X
D0
Write Data D0
n+6
A3
L
L
L
L
L
X
D1
Write Data D1
n+7
A4
L
L
L
L
L
X
D2
Write Data D2
5313 tbl 18
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
6.42
11
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Read Operation with Chip Enable Used(1)
Cycle
Address
R/ W
ADV/LD
CE(2)
CEN
BWx
OE
I/O(3)
Comments
n
X
X
L
H
L
X
X
?
Deselected.
n+1
X
X
L
H
L
X
X
?
Deselected.
n+2
A0
H
L
L
L
X
X
Z
Address and Control meet setup.
n+3
X
X
L
H
L
X
X
Z
Deselected or STOP.
n+4
A1
H
L
L
L
X
L
Q0
Address A0 Read out. Load A 1.
n+5
X
X
L
H
L
X
X
Z
Deselected or STOP.
n+6
X
X
L
H
L
X
L
Q1
Address A1 Read out. Deselected.
n+7
A2
H
L
L
L
X
X
Z
Address and control meet setup.
n+8
X
X
L
H
L
X
X
Z
Deselected or STOP.
n+9
X
X
L
H
L
X
L
Q2
Address A2 Read out. Deselected.
5313 tbl 19
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
3. Device Outputs are ensured to be in High-Z after the first rising edge of clock upon power-up.
Write Operation with Chip Enable Used(1)
Cycle
Address
R/ W
ADV /LD
CE(2)
CEN
BWx
OE
I/O
Comments
n
X
X
L
H
L
X
X
?
Deselected.
n+1
X
X
L
H
L
X
X
?
Deselected.
n+2
A0
L
L
L
L
L
X
Z
Address and Control meet setup.
n+3
X
X
L
H
L
X
X
Z
Deselected or STOP.
n+4
A1
L
L
L
L
L
X
D0
Address D0 Write in. Load A 1.
n+5
X
X
L
H
L
X
X
Z
Deselected or STOP.
n+6
X
X
L
H
L
X
X
D1
Address D1 Write in. Deselected.
n+7
A2
L
L
L
L
L
X
Z
Address and control meet setup.
n+8
X
X
L
H
L
X
X
Z
Deselected or STOP.
n+9
X
X
L
H
L
X
X
D2
Address D2 Write in. Deselected.
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
6.42
12
5313 tbl 20
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 2.5V±5%)
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
VDD = Max., VIN = 0V to V DD
___
5
µA
VDD = Max., VIN = 0V to V DD
___
30
µA
|ILI|
Input Leakage Current
|ILI|
LBO, JTAG and ZZ Input Leakage Current
|ILO|
Output Leakage Current
VOUT = 0V to V DDQ, Device Deselected
___
5
µA
VOL
Output Low Voltage
IOL = +6mA, VDD = Min.
___
0.4
V
2.0
___
V
VOH
(1)
Output High Voltage
IOH = -6mA, VDD = Min.
5313 tbl 21
NOTE:
1. The LBO, TMS, TDI, TCK and TRST pins will be internally pulled to VDD, and the ZZ pin will be internally pulled to VSS if they are not actively driven in the application.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1) (VDD = 2.5V±5%)
225MHz
Symbol
Parameter
200MHz
166MHz
150MHz
133MHz
100MHz
Test Conditions
Unit
Com'l Only Com'l Only
Com'l
Ind
Com'l
Ind
Com'l
Ind
Com'l
Ind
IDD
Operating Power
Supply Current
Device Selected, Outputs Open,
ADV/ LD = X, VDD = Max.,
VIN > VIH or < VIL, f = fMAX(2)
315
275
245
265
215
235
195
215
175
195
mA
ISB1
CMOS Standby Power
Supply Current
Device Deselected, Outputs Open,
VDD = Max., VIN > VHD or < VLD ,
f = 0(2,3)
40
40
40
60
40
60
40
60
40
60
mA
ISB2
Clock Running Power
Supply Current
Device Deselected, Outputs Open,
VDD = Max., VIN > VHD or < VLD ,
f = fMAX(2.3)
90
80
70
90
60
80
50
70
45
65
mA
ISB3
Idle Power
Supply Current
Device Selected, Outputs Open,
CEN > VIH, VDD = Max.,
VIN > VHD or < VLD, f = fMAX(2,3)
60
60
60
80
60
80
60
80
60
80
mA
IZZ
Full Sleep Mode
Supply Current
Device Selected, Outputs Open,
CEN < VIH, VDD = Max.,
VIN > VHD or < VLD, f = fMAX(2,3),ZZ > VHD
40
40
40
60
40
60
40
60
40
60
mA
5313 tbl 22
NOTES:
1. All values are maximum guaranteed values.
2. At f = f MAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC ; f=0 means no input lines are changing.
3. For I/Os V HD = VDDQ – 0.2V, VLD = 0.2V. For other inputs V HD = VDD – 0.2V, VLD = 0.2V.
AC Test Load
AC Test Conditions
VDDQ/2
Input Pulse Levels
50Ω
I/O
Z0 = 50Ω
Input Rise/Fall Times
,
5313 drw 04
Figure 1. AC Test Load
6
5
∆tCD 3
(Typical, ns)
2
1
•
•
20 30 50
200
(VDDQ/2)
Output Timing Reference Levels
(VDDQ/2)
See Figure 1
5313 tbl 23
• •
80 100
Capacitance (pF)
2ns
Input Timing Reference Levels
AC Test Load
•
4
0 to 2.5V
,
5313 drw 05
Figure 2. Lumped Capacitive Load, Typical Derating
6.42
13
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
(VDD = 2.5V +/-5%, Commercial and Industrial
Temperature Ranges)
225MHz
Symbol
166MHz
150MHz
133MHz
100MHz
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Clock Cycle Time
4.4
____
5
____
6
____
6.7
____
7.5
____
10
____
ns
tF(1)
Clock Frequency
____
225
____
200
____
166
____
150
____
133
____
100
MHz
tCH(2)
Clock High Pulse Width
1.8
____
1.8
____
1.8
____
2.0
____
2.2
____
3.2
____
ns
1.8
____
1.8
____
1.8
____
2.0
____
2.2
____
3.2
____
ns
tCYC
(2)
tCL
Parameter
200MHz
Clock Low Pulse Width
Output Parameters
tCD
Clock High to Valid Data
____
3.0
____
3.2
____
3.5
____
3.8
____
4.2
____
5
ns
tCDC
Clock High to Data Change
1.0
____
1.0
____
1.0
____
1.5
____
1.5
____
1.5
____
ns
tCLZ(3,4,5)
Clock High to Output Active
1.0
____
1.0
____
1.0
____
1.5
____
1.5
____
1.5
____
ns
tCHZ(3,4,5)
Clo ck High to Data High-Z
1.0
3
1.0
3
1.0
3
1.5
3
1.5
3
1.5
3.3
ns
tOE
Output Enable Access Time
____
3.0
____
3.2
____
3.5
____
3.8
____
4.2
____
5
ns
tOLZ(3,4)
Output Enable Low to Data Active
0
____
0
____
0
____
0
____
0
____
0
____
ns
tOHZ(3,4)
Output Enab le High to Data High-Z
____
3.0
____
3.2
____
3.5
____
3.8
____
4.2
____
5
ns
1.4
____
1.4
____
1.5
____
1.5
____
1.7
____
2.0
____
ns
1.4
____
1.5
____
1.5
____
1.7
____
2.0
____
ns
Set Up Times
tSE
Clock Enable Setup Time
tSA
Address Setup Time
1.4
____
tSD
Data In Setup Time
1.4
____
1.4
____
1.5
____
1.5
____
1.7
____
2.0
____
ns
tSW
Read/Write (R/W) Setup Time
1.4
____
1.4
____
1.5
____
1.5
____
1.7
____
2.0
____
ns
tSADV
Advance/Load (ADV/LD) Setup Time
1.4
____
1.4
____
1.5
____
1.5
____
1.7
____
2.0
____
ns
tSC
Chip Enable/Select Setup Time
1.4
____
1.4
____
1.5
____
1.5
____
1.7
____
2.0
____
ns
tSB
Byte Write Enable (BWx) Setup Time
1.4
____
1.4
____
1.5
____
1.5
____
1.7
____
2.0
____
ns
tHE
Clock Enable Hold Time
0.4
____
0.4
____
0.5
____
0.5
____
0.5
____
0.5
____
ns
tHA
Address Hold Time
0.4
____
0.4
____
0.5
____
0.5
____
0.5
____
0.5
____
ns
tHD
Data In Hold Time
0.4
____
0.4
____
0.5
____
0.5
____
0.5
____
0.5
____
ns
tHW
Read/Write (R/W) Hold Time
0.4
____
0.4
____
0.5
____
0.5
____
0.5
____
0.5
____
ns
tHADV
Advance/Load (ADV/LD) Hold Time
0.4
____
0.4
____
0.5
____
0.5
____
0.5
____
0.5
____
ns
tHC
Chip Enable/Select Hold Time
0.4
____
0.4
____
0.5
____
0.5
____
0.5
____
0.5
____
ns
tHB
Byte Write Enable (BWx) Hold Time
0.4
____
0.4
____
0.5
____
0.5
____
0.5
____
0.5
____
ns
Hold Times
5313 tbl 24
NOTES:
1. tF = 1/tCYC.
2. Measured as HIGH above 0.6VDDQ and LOW below 0.4VDDQ.
3. Transition is measured ±200mV from steady-state.
4. These parameters are guaranteed with the AC load (Figure 1) by device characterization. They are not production tested.
5. To avoid bus contention, the output buffers are designed such that tCHZ (device turn-off) is faster than tCLZ (device turn-on) at a given temperature and voltage. The specs as shown
do not imply bus contention because tCLZ is a Min. parameter that is worse case at totally different test conditions (0 deg. C, 2.625V) than t CHZ, which is a Max. parameter (worse case
at 70 deg. C, 2.375V).
6.42
14
6.42
15
A1
tSADV
tHA
tHW
tHE
tCLZ
tHC
Pipeline
Read
tSC
A2
tSA
tSW
tSE
tCD
Pipeline
Read
Q(A1)
tHADV
tCH
tCDC
tCL
Q(A2)
,
.
Q(A2+1)
Q(A2+2)
(CEN high, eliminates
current L-H clock edge)
Burst Pipeline Read
tCD
Q(A2+2)
tCDC
Q(A2+3)
tCHZ
Q(A2)
5313 drw 06
(Burst Wraps around
to initial state)
NOTES:
1. Q (A1) represents the first output from the external address A1. Q (A2) represents the first output from the external address A2; Q (A2+1) represents the next output data in the burst sequence
of the base address A2, etc. where address bits A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input.
2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.
3. Burst ends when new address and control are loaded into the SRAM by sampling ADV/LD LOW.
4. R/W is don't care when the SRAM is bursting (ADV/LD sampled HIGH). The nature of the burst access (Read or Write) is fixed by the state of the R/W signal when new address and control are
loaded into the SRAM.
DATAOUT
OE
BW1 - BW4
CE1, CE2
(2)
ADDRESS
R/W
ADV/LD
CEN
CLK
tCYC
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Timing Waveform of Read Cycle(1,2,3,4)
6.42
16
(2)
A1
tSADV
tHW
tHE
tHB
tHC
Pipeline
Write
tSB
tSC
tHA
A2
tSA
tSW
tSE
tHD
Pipeline
Write
D(A1)
tSD
tHADV
tCH
,
.
D(A2)
tCL
D(A2+1)
Burst Pipeline Write
(CEN high, eliminates
current L-H clock edge)
tSD
D(A2+2)
tHD
D(A2)
5313 drw 07
D(A2+3)
(Burst Wraps around
to initial state)
NOTES:
1. D (A1) represents the first input to the external address A1. D (A2) represents the first input to the external address A2; D (A2+1) represents the next input data in the burst sequence of
the base address A2, etc. where address bits A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input.
2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.
3. Burst ends when new address and control are loaded into the SRAM by sampling ADV/LD LOW.
4. R/W is don't care when the SRAM is bursting (ADV/LD sampled HIGH). The nature of the burst access (Read or Write) is fixed by the state of the R/W signal when new address and control are
loaded into the SRAM.
5. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information comes in two
cycles before the actual data is presented to the SRAM.
DATAIN
OE
BW1 - BW4
CE1, CE2
ADDRESS
R/W
ADV/LD
CEN
CLK
tCYC
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Timing Waveform of Write Cycles(1,2,3,4,5)
6.42
17
DATAOUT
DATAIN
OE
BW1 - BW4
CE1, CE2(2)
ADDRESS
R/W
ADV/LD
CEN
CLK
tHW
tCD
tHB
tHC
Read
tSB
tSC
tHA
A2
tSA
tSW
tHE
A3
Q(A1)
tCHZ
Write
tHADV
tCH
tCLZ
Read
D(A2)
tSD tHD
A4
tCL
Q(A3)
tCDC
Write
A5
D(A4)
A6
Read
D(A5)
A7
Q(A6)
A8
5313 drw 08
Q(A7)
A9
NOTES:
1. Q (A1) represents the first output from the external address A1. D (A2) represents the input data to the SRAM corresponding to address A2.
2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.
3. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information comes in two
cycles before the actual data is presented to the SRAM.
A1
tSADV
tSE
tCYC
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Timing Waveform of Combined Read and Write Cycles(1,2,3)
,
,
6.42
18
A1
tSE
tSADV
tHE
tHW
tHC
tCD
tCLZ
tHB
B(A2)
tSB
tSC
tHA
A2
tSA
tSW
tCH
tHADV
Q(A1)
tCL
tCHZ
tCDC
Q(A1)
A3
D(A2)
tSD tHD
A4
,
5313 drw 09
Q(A3)
A5
NOTES:
1. Q (A1) represents the first output from the external address A1. D (A2) represents the input data to the SRAM corresponding to address A2.
2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.
3. CEN when sampled high on the rising edge of clock will block that L-H transition of the clock from propogating into the SRAM. The part will behave as if the L-H clock transition did not
occur. All internal registers in the SRAM will retain their previous state.
4. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information comes in two
cycles before the actual data is presented to the SRAM.
DATAOUT
DATAIN
OE
BW1 - BW4
CE1, CE2(2)
ADDRESS
R/W
ADV/LD
CEN
CLK
tCYC
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Timing Waveform of CEN Operation(1,2,3,4)
6.42
19
A1
tSADV
tHW
tHE
tSC
tCLZ
tCD
tHC
tHA
A2
tSA
tSW
tSE
Q(A1)
tHADV
tCH
tCDC
tCHZ
tHB
Q(A2 )
tSB
A3
tCL
D(A3)
tSD tHD
A4
Q(A4)
A5
5313 drw 10
,
NOTES:
1. Q (A1) represents the first output from the external address A1. D (A3) represents the input data to the SRAM corresponding to address A3.
2 CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.
3. CEN when sampled high on the rising edge of clock will block that L-H transition of the clock from propogating into the SRAM. The part will behave as if the L-H clock transition did not
occur. All internal registers in the SRAM will retain their previous state.
4. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information comes in two
cycles before the actual data is presented to the SRAM.
DATAOUT
DATAIN
OE
BW1 - BW4
CE1, CE2
(2)
ADDRESS
R/W
ADV/LD
CEN
CLK
tCYC
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Timing Waveform of CS Operation(1,2,3,4)
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
JTAG Interface Specification
tJF
tJCL
tJCYC
tJR
tJCH
TCK
Device Inputs(1)/
TDI/TMS
tJS
Device Outputs(2)/
TDO
tJDC
tJH
tJRSR
tJCD
TRST(3)
x
M5313 drw 01
tJRST
NOTES:
1. Device inputs = All device inputs except TDI, TMS and TRST.
2. Device outputs = All device outputs except TDO.
3. During power up, TRST could be driven low or not be used since the JTAG circuit resets automatically. TRST is an optional JTAG reset.
JTAG AC Electrical
Characteristics(1,2,3,4)
Symbol
Parameter
Min.
Max.
Units
tJCYC
JTAG Clock Input Period
100
____
ns
tJCH
JTAG Clock HIGH
40
____
ns
tJCL
JTAG Clock Low
40
____
ns
tJR
JTAG Clock Rise Time
____
5(1)
ns
tJF
JTAG Clock Fall Time
____
5(1)
ns
JTAG Identification (JIDR)
tJRST
JTAG Reset
50
____
ns
Boundary Scan (BSR)
tJRSR
JTAG Reset Recovery
50
____
ns
tJCD
JTAG Data Output
____
20
ns
NOTE:
1. The Boundary Scan Descriptive Language (BSDL) file for this device is available
by contacting your local IDT sales representative.
0
____
ns
ns
ns
tJDC
JTAG Data Output Hold
tJS
JTAG Setup
25
____
tJH
JTAG Hold
25
____
Scan Register Sizes
Register Name
Bit Size
Instruction (IR)
4
Bypass (BYR)
1
32
Note (1)
I5313 tbl 03
I5313 tbl 01
NOTES:
1. Guaranteed by design.
2. AC Test Load (Fig. 1) on external output signals.
3. Refer to AC Test Conditions stated earlier in this document.
4. JTAG operations occur at one speed (10MHz). The base device may run at any speed specified in this datasheet.
6.42
20
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
JTAG Identification Register Definitions
Instruction Field
Value
Revision Number (31:28)
Description
0x2
IDT Device ID (27:12)
0x220, 0x222
IDT JEDEC ID (11:1)
0x33
ID Register Indicator Bit (Bit 0)
Reserved for version number.
Defines IDT part number 71T75602 and 71T75802, respectively.
Allows unique identification of device vendor as IDT.
1
Indicates the presence of an ID register.
I5313 tbl 02
Available JTAG Instructions
Instruction
Description
OPCODE
EXTEST
Forces contents of the boundary scan cells onto the device outputs (1).
Places the boundary scan register (BSR) between TDI and TDO.
0000
SAMPLE/PRELOAD
Places the boundary scan register (BSR) between TDI and TDO.
SAMPLE allows data from device inputs(2) and outputs(1) to be captured
in the boundary scan cells and shifted serially through TDO. PRELOAD
allows data to be input serially into the boundary scan cells via the TDI.
0001
DEVICE_ID
Loads the JTAG ID register (JIDR) with the vendor ID code and places
the register between TDI and TDO.
0010
HIGHZ
Places the bypass register (BYR) between TDI and TDO. Forces all
device o utput drivers to a High-Z state.
0011
RESERVED
RESERVED
RESERVED
0100
Several combinations are reserved. Do not use codes other than those
identified for EXTEST, SAMPLE/PRELOAD, DEVICE_ID, HIGHZ, CLAMP,
VALIDATE and BYPASS instructions.
RESERVED
CLAMP
0101
0110
0111
Uses BYR. Forces contents of the boundary scan cells onto the device
outputs. Places the byp ass registe r (BYR) between TDI and TDO.
RESERVED
1000
1001
RESERVED
1010
Same as above.
RESERVED
1011
RESERVED
1100
VALIDATE
Automatically loaded into the instruction register whenever the TAP
controller passes through the CAPTURE-IR state. The lower two bits '01'
are mand ated by the IEEE std. 1149.1 specification.
1101
RESERVED
Same as above.
1110
BYPASS
The BYPASS instruction is used to truncate the boundary scan register
as a single bit in length.
1111
I5313 tbl 04
NOTES:
1. Device outputs = All device outputs except TDO.
2. Device inputs = All device inputs except TDI, TMS, and TRST.
6.42
21
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
100-Pin Thin Quad Flatpack (TQFP) Package Diagram Outline
6.42
22
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
119 Ball Grid Array (BGA) Package Diagram Outline
6.42
23
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Timing Waveform of OE Operation(1)
OE
tOE
tOHZ
tOLZ
Valid
DATAOUT
5313 drw 11
NOTE:
1. A read operation is assumed to be in progress.
Ordering Information
IDT
XXXX
S
XX
XX
Device
Type
Power
Speed
Package
X
Blank
I
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
PF
BG
100-Pin Plastic Thin Quad Flatpack (TQFP)
119 Ball Grid Array (BGA)
225
200
166
150
133
100
Clock Frequency in Megahertz
IDT71T75602 512Kx36 Pipelined ZBT SRAM
IDT71T75802 1Mx18 Pipelined ZBT SRAM
5313 drw 12
6.42
24
,
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Datasheet Document History
Rev
0
1
Date
04/20/00
05/25/00
2
08/23/01
3
4
10/16/01
10/29/01
12/21/01
5
06/07/02
6
11/19/02
7
05/23/03
8
04/01/04
Pages
Description
Created New Datasheet
Pg.1,14,15,25
Added 166MHz speed grade offering
Pg. 1,2,14
Corrected error in ZZ Sleep Mode
Pg. 23
AddBQ165 Package Diagram Outline
Pg. 24
Corrected 119BGA Package Diagram Outline.
Pg. 25
Corrected topmark on ordering information
Pg. 1,2,24
Removed reference of BQ165 Package
Pg. 7
Removed page of the 165 BGA pin configuration
Pg. 23
Removed page of the 165 BGA package diagram outline
Pg. 6
Corrected 3.3V to 2.5V in Note 2
Pg. 13
Improved DC Electrical characteristics-parameters improved: Icc, ISB2, ISB3, IZZ.
Pg. 4-6
Added clarification to JTAG pins, allow for NC. Added 36M address pin locations.
Pg. 14
Revised 166MHz tCDC(min), tCLZ(min) and tCHZ(min) to 1.0ns
Pg. 1-3,6,13,20,21 Added complete JTAG functionality.
Pg. 2,13
Added notes for ZZ pin internal pulldown and ZZ leakage current.
Pg. 13,14,24
Added 200MHz and 225MHz to DC and AC Electrical Characteristics. Updated supply current for
Idd, ISB1, ISB3 and Izz.
Pg.1-24
Changed datasheet from Advanced Information to final release.
Pg.13
Updated DC Electrical characteristics temperature and voltage range table.
Pg.4,5,13,14,24
Added I-temp to the datasheet.
Pg.5
Updated 165 BGA Capacitance table.
Pg. 1
Updated logo with new design.
Pg. 4,5
Clarified ambient and case operating temperatures.
Pg. 6
Updated pin I/O number order for the 119 BGA.
Pg. 23
Updated 119BGA Package Diagram Drawing.
CORPORATE HEADQUARTERS
2975 Stender Way
Santa Clara, CA 95054
for SALES:
800-345-7015 or 408-727-6116
fax: 408-492-8674
www.idt.com
for Tech Support:
[email protected]
800-544-7726
The IDT logo is a registered trademark of Integrated Device Technology, Inc. All brands or products are the trademarks or registered trademarks of their respective owners.
ZBT® and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola Inc.
6.42
25