Cypress CY62157ELL-55BVXE 8-mbit (512k x 16) static ram Datasheet

CY62157E MoBL®
8-Mbit (512K x 16) Static RAM
Features
also has an automatic power-down feature that significantly
reduces power consumption when addresses are not toggling.
The device can also be put into standby mode when
deselected (CE1 HIGH or CE2 LOW or both BHE and BLE are
HIGH). The input/output pins (IO0 through IO15) are placed in
a high-impedance state when: deselected (CE1HIGH or CE2
LOW), outputs are disabled (OE HIGH), both Byte High
Enable and Byte Low Enable are disabled (BHE, BLE HIGH),
or during a write operation (CE1 LOW, CE2 HIGH and WE
LOW).
• Very high speed: 45 ns
• Wide voltage range: 4.5V–5.5V
• Ultra-low standby power
—Typical Standby current: 2 µA
—Maximum Standby current: 8 µA (Industrial)
• Ultra-low active power
— Typical active current: 1.8 mA @ f = 1 MHz
Writing to the device is accomplished by taking Chip Enable
(CE1 LOW and CE2 HIGH) and Write Enable (WE) input LOW.
If Byte Low Enable (BLE) is LOW, then data from IO pins (IO0
through IO7), is written into the location specified on the
address pins (A0 through A18). If Byte High Enable (BHE) is
LOW, then data from IO pins (IO8 through IO15) is written into
the location specified on the address pins (A0 through A18).
• Ultra-low standby power
• Easy memory expansion with CE1, CE2 and OE features
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Available in Pb-free 44-pin TSOP II and 48-ball VFBGA
package
Reading from the device is accomplished by taking Chip
Enable (CE1 LOW and CE2 HIGH) and Output Enable (OE)
LOW while forcing the Write Enable (WE) HIGH. If Byte Low
Enable (BLE) is LOW, then data from the memory location
specified by the address pins will appear on IO0 to IO7. If Byte
High Enable (BHE) is LOW, then data from memory will appear
on IO8 to IO15. See the truth table at the back of this data sheet
for a complete description of read and write modes.
Functional Description[1]
The CY62157E is a high-performance CMOS static RAM
organized as 512K words by 16 bits. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life™ (MoBL®) in
portable applications such as cellular telephones. The device
Logic Block Diagram
SENSE AMPS
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
ROW DECODER
DATA IN DRIVERS
512K x 16
RAM Array
IO0–IO7
IO8–IO15
COLUMN DECODER
A17
A18
A15
A16
A14
A11
A12
A13
BHE
WE
CE2
OE
BLE
CE1
POWER-DOWN
CIRCUIT
BHE
CE2
BLE
CE1
Note:
1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05695 Rev. *C
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised November 21, 2006
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CY62157E MoBL®
Pin Configuration[2, 3]
TSOP II
Top View
A4
A3
A2
A1
A0
CE
IO0
IO1
IO2
IO3
VCC
VSS
IO4
IO5
IO6
IO7
WE
A18
A17
A16
A15
A14
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
VFBGA
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
BHE
BLE
IO15
IO14
IO13
IO12
VSS
VCC
IO11
IO10
IO9
IO8
A8
A9
A10
A11
A12
A13
Top View
4
3
1
2
BLE
OE
A0
IO 8
BHE
IO 9
5
6
A1
A2
CE2
A
A3
A4
CE1
IO 0
B
IO 10
A5
A6
IO 1
IO 2
C
VSS
IO11
A17
A7
IO3
Vcc
D
VCC
IO 12
NC
A16
IO 4
Vss
E
IO 14
IO 13
A14
A15
IO 5
IO 6
F
IO 15
NC
A12
A13
WE
IO 7
G
A18
A8
A9
A10
A11
NC
H
Product Portfolio
Power Dissipation
Speed
(ns)
VCC Range (V)
Product
Range
Min
Typ[4]
Max
Operating ICC, (mA)
f = 1MHz
f = fmax
Standby, ISB2
(µA)
Typ[4]
Max
Typ[4]
Max
Typ[4]
Max
CY62157E-45
Ind’l
4.5
5.0
5.5
45
1.8
3
18
25
2
8
CY62157E-55[5]
Auto
4.5
5.0
5.5
55
1.8
4
18
35
2
30
Notes:
2. NC pins are not connected on the die.
3. The 44-pin TSOP II package has only one chip enable (CE) pin.
4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25°C.
5. Automotive product information is Preliminary.
Document #: 38-05695 Rev. *C
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CY62157E MoBL®
DC Input Voltage[6, 7] ........................................–0.5V to 6.0V
Maximum Ratings
Output Current into Outputs (LOW) ............................ 20 mA
(Above which the useful life may be impaired. For user guidelines, not tested.)
Static Discharge Voltage .......................................... > 2001V
(per MIL-STD-883, Method 3015)
Storage Temperature ................................ –65°C to + 150°C
Latch-Up Current ................................................... > 200 mA
Ambient Temperature with
Power Applied ........................................... –55°C to + 125°C
Operating Range
Supply Voltage to Ground
Potential .......................................................... –0.5V to 6.0V
Device
DC Voltage Applied to Outputs
in High Z State[6, 7] ........................................... –0.5V to 6.0V
CY62157E
Range
Ambient
Temperature
VCC[8]
Industrial
–40°C to +85°C
4.5V to 5.5V
Automotive –40°C to +125°C
Electrical Characteristics (Over the Operating Range)
45 ns (Industrial)
Parameter
Description
Test Conditions
Min
[4]
Typ
Max
VOH
Output HIGH
Voltage
IOH = –1 mA
VCC = 4.5V
2.4
VOL
Output LOW
Voltage
IOL = 2.1 mA
VCC = 4.5V
VIH
Input HIGH
Voltage
VCC = 4.5V to 5.5V
2.2
VCC + 0.5
VIL
Input LOW
Voltage
VCC = 4.5V to 5.5V
–0.5
IIX
Input Leakage
Current
GND < VI < VCC
IOZ
Output Leakage GND < VO < VCC, Output Disabled
Current
ICC
VCC Operating
Supply
Current
f = fmax = 1/tRC VCC = VCCmax
IOUT = 0 mA
f = 1 MHz
CMOS levels
ISB1
Automatic CE
Power-Down
Current —
CMOS Inputs
ISB2
Automatic CE
Power-Down
Current —
CMOS Inputs
55 ns (Automotive)
Min
Typ[4]
Max
2.4
Unit
V
0.4
0.4
V
2.2
VCC + 0.5
V
0.8
–0.5
0.8
V
–1
+1
–1
+1
µA
–1
+1
–1
+1
µA
18
25
18
35
1.8
3
1.8
4
CE1 > VCC − 0.2V, CE2 < 0.2V,
VIN > VCC – 0.2V, VIN < 0.2V,
f = fmax (Address and Data Only),
f = 0 (OE, BHE, BLE and WE),
VCC = 3.60V
2
8
2
30
µA
CE1 > VCC – 0.2V or CE2 < 0.2V,
VIN > VCC – 0.2V or VIN < 0.2V,
f = 0, VCC = 3.60V
2
8
2
30
µA
mA
Capacitance[9]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz, VCC = VCC(typ)
Max
Unit
10
pF
10
pF
Notes:
6. VIL(min) = –2.0V for pulse durations less than 20 ns for I < 30 mA.
7. VIH(max) = VCC + 0.75V for pulse durations less than 20 ns.
8. Full device AC operation assumes a 100 µs ramp time from 0 to VCC(min) and 200 µs wait time after VCC stabilization.
9. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05695 Rev. *C
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CY62157E MoBL®
Thermal Resistance[9]
Parameter
Description
ΘJA
Thermal Resistance
(Junction to Ambient)
ΘJC
Thermal Resistance
(Junction to Case)
Test Conditions
TSOP II VFBGA
Still Air, soldered on a 3 × 4.5 inch,
two-layer printed circuit board
Unit
77
72
°C/W
13
8.86
°C/W
AC Test Loads and Waveforms
R1
VCC
OUTPUT
3V
30 pF
10%
GND
Rise Time = 1 V/ns
R2
ALL INPUT PULSES
90%
90%
10%
Fall Time = 1 V/ns
INCLUDING
JIG AND
SCOPE
Equivalent to:
THEVENIN EQUIVALENT
RTH
OUTPUT
V
Parameters
Values
Unit
R1
1800
Ω
R2
990
Ω
RTH
639
Ω
VTH
1.77
V
Data Retention Characteristics (Over the Operating Range)
Parameter
Description
VDR
VCC for Data Retention
ICCDR
Data Retention Current
tCDR
[9]
tR[10]
Conditions
Min
Typ[4]
Max
2
Industrial
VCC=2V, CE1> VCC – 0.2V,
CE2 < 0.2V, VIN > VCC – 0.2V or VIN < 0.2V
Automotive
V
8
µA
30
Chip Deselect to Data
Retention Time
Operation Recovery Time
Unit
0
ns
tRC
ns
Data Retention Waveform[11]
DATA RETENTION MODE
VCC
VCC(min)
tCDR
VDR > 2 V
VCC(min)
tR
CE1or
BHE.BLE
CE2
Notes:
10. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 µs or stable at VCC(min) > 100 µs.
11. BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE.
Document #: 38-05695 Rev. *C
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CY62157E MoBL®
Switching Characteristics Over the Operating Range [12]
45 ns
Parameter
Description
Min
55 ns
Max
Min
Max
Unit
Read Cycle
tRC
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
CE1 LOW and CE2 HIGH to Data Valid
tDOE
OE LOW to Data Valid
tLZOE
OE LOW to LOW Z[13]
45
22
5
OE HIGH to High Z
tLZCE
CE1 LOW and CE2 HIGH to Low Z
CE1 HIGH and CE2 LOW to High Z[13, 14]
tPU
CE1 LOW and CE2 HIGH to Power-Up
tPD
CE1 HIGH and CE2 LOW to Power-Down
tDBE
BLE/BHE LOW to Data Valid
tLZBE
BLE/BHE LOW to Low Z[13]
BLE/BHE HIGH to HIGH
10
0
ns
25
ns
ns
20
ns
20
ns
ns
0
45
45
10
Z[13, 14]
55
10
18
ns
55
ns
55
ns
10
18
ns
ns
5
18
[13]
tHZCE
tHZBE
10
10
[13, 14]
ns
55
45
tAA
tHZOE
55
45
Read Cycle Time
ns
20
ns
Write Cycle[15]
tWC
Write Cycle Time
45
55
ns
tSCE
CE1 LOW and CE2 HIGH to Write End
35
40
ns
tAW
Address Set-Up to Write End
35
40
ns
tHA
Address Hold from Write End
0
0
ns
tSA
Address Set-Up to Write Start
0
0
ns
tPWE
WE Pulse Width
35
40
ns
tBW
BLE/BHE LOW to Write End
35
40
ns
tSD
Data Set-Up to Write End
25
25
ns
tHD
Data Hold from Write End
0
0
ns
High-Z[13, 14]
tHZWE
WE LOW to
tLZWE
WE HIGH to Low-Z[13]
18
10
20
10
ns
ns
Notes:
12. Test conditions for all parameters other than Tri-state parameters assume signal transition time of 3 ns or less, timing reference levels of VCC(typ)/2, input pulse
levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in the “AC Test Loads and Waveforms” section.
13. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any
given device.
14. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high-impedance state.
15. The internal Write time of the memory is defined by the overlap of WE, CE1 = VIL, BHE and/or BLE = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate
a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal
that terminates the Write.
Document #: 38-05695 Rev. *C
Page 5 of 12
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CY62157E MoBL®
Switching Waveforms
Read Cycle 1 (Address Transition Controlled)[16, 17]
tRC
ADDRESS
tOHA
DATA OUT
tAA
PREVIOUS DATA VALID
DATA VALID
Read Cycle 2 (OE Controlled)[17, 18]
ADDRESS
tRC
CE1
tPD
tHZCE
CE2
tACE
BHE/BLE
tLZBE
OE
tDBE
tHZBE
tHZOE
tDOE
DATA OUT
tLZOE
HIGH IMPEDANCE
HIGH
IMPEDANCE
DATA VALID
tLZCE
VCC
SUPPLY
CURRENT
tPU
50%
50%
ICC
ISB
Notes:
16. The device is continuously selected. OE, CE1 = VIL, BHE and/or BLE = VIL, and CE2 = VIH.
17. WE is HIGH for read cycle.
18. Address valid prior to or coincident with CE1, BHE, BLE transition LOW and CE2 transition HIGH.
Document #: 38-05695 Rev. *C
Page 6 of 12
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CY62157E MoBL®
Switching Waveforms (continued)
Write Cycle 1 (WE Controlled)[15, 19, 20, 21]
tWC
ADDRESS
tSCE
CE1
CE2
tAW
tHA
tSA
tPWE
WE
tBW
BHE/BLE
OE
tSD
DATA IO
tHD
VALID DATA
See Note 21
tHZOE
Write Cycle 2 (CE1 or CE2 Controlled)[15, 19, 20, 21]
tWC
ADDRESS
tSCE
CE1
CE2
tSA
tAW
tHA
tPWE
WE
tBW
BHE/BLE
OE
tSD
DATA IO
tHD
VALID DATA
See Note 21
tHZOE
Notes:
19. Data IO is high impedance if OE = VIH.
20. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high-impedance state.
21. During this period, the IOs are in output state and input signals should not be applied.
Document #: 38-05695 Rev. *C
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CY62157E MoBL®
Switching Waveforms (continued)
Write Cycle 3 (WE Controlled, OE LOW)[20, 21]
tWC
ADDRESS
tSCE
CE1
CE2
tBW
BHE/BLE
tAW
WE
tHA
tSA
tPWE
tHD
tSD
DATA IO
See Note 21
VALID DATA
tLZWE
tHZWE
Write Cycle 4 (BHE/BLE Controlled, OE LOW)[20, 21]
tWC
ADDRESS
CE1
CE2
tSCE
tAW
tHA
tBW
BHE/BLE
tSA
tPWE
WE
tSD
DATA IO
See Note 21
Document #: 38-05695 Rev. *C
tHD
VALID DATA
Page 8 of 12
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CY62157E MoBL®
Truth Table
CE1
CE2
WE
OE
BHE
BLE
H
X
X
X
X
X
X
L
X
X
X
X
X
X
X
L
H
H
L
H
L
Inputs/Outputs
Mode
Power
High Z
Deselect/Power-Down
Standby (ISB)
X
High Z
Deselect/Power-Down
Standby (ISB)
H
H
High Z
Deselect/Power-Down
Standby (ISB)
L
L
L
Data Out (IO0–IO15)
Read
Active (ICC)
H
L
H
L
Data Out (IO0–IO7);
High Z (IO8–IO15)
Read
Active (ICC)
H
H
L
L
H
High Z (IO0–IO7);
Data Out (IO8–IO15)
Read
Active (ICC)
L
H
H
H
L
H
High Z
Output Disabled
Active (ICC)
L
H
H
H
H
L
High Z
Output Disabled
Active (ICC)
L
H
H
H
L
L
High Z
Output Disabled
Active (ICC)
L
H
L
X
L
L
Data In (IO0–IO15)
Write
Active (ICC)
L
H
L
X
H
L
Data In (IO0–IO7);
High Z (IO8–IO15)
Write
Active (ICC)
L
H
L
X
L
H
High Z (IO0–IO7);
Data In (IO8–IO15)
Write
Active (ICC)
Ordering Information
Speed
(ns)
Ordering Code
Package
Diagram
Package Type
Operating
Range
45
CY62157ELL-45ZSXI
51-85087
44-pin Thin Small Outline Package Type II (Pb-free)
Industrial
55
CY62157ELL-55ZSXE
51-85087
44-pin Thin Small Outline Package Type II (Pb-free)
Automotive
CY62157ELL-55BVXE
51-85150
48-ball Very Fine Pitch Ball Grid Array (Pb-free)
Document #: 38-05695 Rev. *C
Page 9 of 12
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CY62157E MoBL®
Package Diagrams
44-pin TSOP II (51-85087)
51-85087-*A
Document #: 38-05695 Rev. *C
Page 10 of 12
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CY62157E MoBL®
Package Diagrams (continued)
48-ball VFBGA (6 x 8 x 1 mm) (51-85150)
BOTTOM VIEW
TOP VIEW
A1 CORNER
Ø0.05 M C
Ø0.25 M C A B
A1 CORNER
Ø0.30±0.05(48X)
2
3
4
5
6
6
5
4
3
2
1
C
C
E
F
G
D
E
2.625
D
0.75
A
B
5.25
A
B
8.00±0.10
8.00±0.10
1
F
G
H
H
A
1.875
A
B
0.75
6.00±0.10
3.75
6.00±0.10
0.10 C
0.21±0.05
0.25 C
0.55 MAX.
B
0.15(4X)
51-85150-*D
C
1.00 MAX
0.26 MAX.
SEATING PLANE
MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor Corporation. All product and
company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05695 Rev. *C
Page 11 of 12
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CY62157E MoBL®
Document History Page
Document Title: CY62157E MoBL®, 8-Mbit (512K x 16) Static RAM
Document Number: 38-05695
REV.
ECN NO. Issue Date
Orig. of
Change
Description of Change
**
291273
See ECN
PCI
New data sheet
*A
457689
See ECN
NXR
Added Automotive Product
Removed Industrial Product
Removed 35 ns and 45 ns speed bins
Removed “L” bin
Updated AC Test Loads table
Corrected tR in Data Retention Characteristics from 100 µs to tRC ns
Updated the Ordering Information and replaced the Package Name column
with Package Diagram
*B
467033
See ECN
NXR
Added Industrial Product (Final Information)
Removed 48 ball VFBGA package and its relevant information
Changed the ICC(typ) value of Automotive from 2 mA to 1.8 mA for f = 1MHz
Changed the ISB2(typ) value of Automotive from 5 µA to 1.8 µA
Modified footnote #4 to include current limit
Updated the Ordering Information table
*C
569114
See ECN
VKN
Added 48 ball VFBGA package
Updated Logic Block Diagram
Added footnote #3
Updated the Ordering Information table
Document #: 38-05695 Rev. *C
Page 12 of 12
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