SILABS C8051F523A-IM 8/4/2 kb isp flash mcu family Datasheet

C8051F52x/F53x
8/4/2 kB ISP Flash MCU Family
Analog Peripherals
- 12-Bit ADC
• Programmable throughput up to 200 ksps
• Up to 6/16 external inputs
• Data dependent windowed interrupt generator
• Built-in temperature sensor
- Comparator
• Programmable hysteresis and response time
• Configurable as wake-up or reset source
• Low current
- POR/Brownout Detector
- Voltage Reference—1.5 and 2.2 V 
Memory
- 8/4/2 kB Flash; In-system byte programmable in
512 byte sectors
- 256 bytes internal data RAM
Digital Peripherals
- 16/6 port I/O; push-pull or open-drain, 5 V tolerant
- Hardware SPI™, and UART serial port
- LIN 2.1 Controller (Master and Slave capable); no
-
intrusive in-system debug (No emulator required)
- Provides breakpoints, single stepping
- Inspect/modify memory and registers
- Complete development kit
Supply Voltage 2.0 to 5.25 V
- Built-in LDO regulator
High-Speed 8051 µC Core
- Pipelined instruction architecture; executes 70% of
-
instructions in 1 or 2 system clocks
Up to 25 MIPS throughput with
25 MHz system clock
Expanded interrupt handler
ANALOG
PERIPHERALS
A
M
U
X
12-bit
200 ksps
ADC
TEMP
SENSOR
+
VOLTAGE
COMPARATOR
VREF
Clock Sources
- Internal oscillators: 24.5 MHz ±0.5% accuracy sup-
ports UART and LIN-Master operation
External oscillator: Crystal, RC, C, or Clock
(1 or 2 pin modes)
Can switch between clock sources on-the-fly
Packages
- 10-Pin DFN (3 x 3 mm)
- 20-pin QFN (4 x 4 mm)
- 20-pin TSSOP
Automotive Qualified
- Temperature Range: –40 to +125 °C
- Compliant to AEC-Q100
DIGITAL I/O
UART
SPI
PCA
Timer 0
Timer 1
Timer 2
Port 0
CROSSBAR
(programmable)
On-Chip Debug
- On-chip debug circuitry facilitates full-speed, non-
crystal required
Three general purpose 16-bit counter/timers
Programmable 16-bit counter/timer array with three
capture/compare modules, WDT
Port 1
LIN
VREG
24.5 MHz High Precision (±0.5%) Internal Oscillator
HIGH-SPEED CONTROLLER CORE
8/4/2 kB
ISP FLASH
FLEXIBLE
INTERRUPTS
Rev. 1.4 4/12
8051 CPU
(25 MIPS)
DEBUG
CIRCUITRY
256 B SRAM
POR
Copyright © 2012 by Silicon Laboratories
WDT
C8051F52x/F53x
C8051F52x/F53x
2
Rev. 1.4
C8051F52x/F53x
Table of Contents
1. System Overview ..................................................................................................... 13
1.1. Ordering Information.......................................................................................... 14
1.2. CIP-51™ Microcontroller ................................................................................... 18
1.2.1. Fully 8051 Compatible Instruction Set ...................................................... 18
1.2.2. Improved Throughput................................................................................ 18
1.2.3. Additional Features ................................................................................... 18
1.2.4. On-Chip Debug Circuitry ........................................................................... 18
1.3. On-Chip Memory ............................................................................................... 20
1.4. Operating Modes ............................................................................................... 21
1.5. 12-Bit Analog to Digital Converter ..................................................................... 22
1.6. Programmable Comparator ............................................................................... 23
1.7. Voltage Regulator.............................................................................................. 23
1.8. Serial Port.......................................................................................................... 23
1.9. Port Input/Output ............................................................................................... 24
2. Electrical Characteristics ........................................................................................ 25
2.1. Absolute Maximum Ratings............................................................................... 25
2.2. Electrical Characteristics ................................................................................... 26
3. Pinout and Package Definitions ............................................................................. 35
4. 12-Bit ADC (ADC0) ................................................................................................... 52
4.1. Analog Multiplexer ............................................................................................. 52
4.2. Temperature Sensor.......................................................................................... 53
4.3. ADC0 Operation ................................................................................................ 54
4.3.1. Starting a Conversion................................................................................ 54
4.3.2. Tracking Modes......................................................................................... 54
4.3.3. Timing ....................................................................................................... 55
4.3.4. Burst Mode................................................................................................ 57
4.3.5. Output Conversion Code........................................................................... 59
4.3.6. Settling Time Requirements...................................................................... 60
4.4. Selectable Gain ................................................................................................. 60
4.4.1. Calculating the Gain Value........................................................................ 61
4.4.2. Setting the Gain Value .............................................................................. 62
4.5. Programmable Window Detector....................................................................... 69
4.5.1. Window Detector In Single-Ended Mode .................................................. 71
5. Voltage Reference.................................................................................................... 72
6. Voltage Regulator (REG0) ....................................................................................... 74
7. Comparator ............................................................................................................. 76
8. CIP-51 Microcontroller............................................................................................. 81
8.1. Instruction Set.................................................................................................... 82
8.1.1. Instruction and CPU Timing ...................................................................... 82
8.1.2. MOVX Instruction and Program Memory .................................................. 83
8.2. Register Descriptions ........................................................................................ 86
8.3. Power Management Modes............................................................................... 89
8.3.1. Idle Mode .................................................................................................. 90
Rev. 1.4
3
C8051F52x/F53x
8.3.2. Stop Mode................................................................................................. 90
8.3.3. Suspend Mode .......................................................................................... 90
9. Memory Organization and SFRs............................................................................. 92
9.1. Program Memory............................................................................................... 92
9.2. Data Memory ..................................................................................................... 93
9.3. General Purpose Registers ............................................................................... 93
9.4. Bit Addressable Locations ................................................................................. 93
9.5. Stack
............................................................................................................ 93
9.6. Special Function Registers................................................................................ 93
10. Interrupt Handler.................................................................................................... 98
10.1. MCU Interrupt Sources and Vectors................................................................ 98
10.2. Interrupt Priorities ............................................................................................ 98
10.3. Interrupt Latency.............................................................................................. 98
10.4. Interrupt Register Descriptions ...................................................................... 100
10.5. External Interrupts ......................................................................................... 104
11. Reset Sources ...................................................................................................... 106
11.1. Power-On Reset ............................................................................................ 107
11.2. Power-Fail Reset / VDD Monitors (VDDMON0 and VDDMON1) .................. 108
11.2.1. VDD Monitor Thresholds and Minimum VDD........................................ 108
11.3. External Reset ............................................................................................... 110
11.4. Missing Clock Detector Reset ....................................................................... 110
11.5. Comparator Reset ......................................................................................... 110
11.6. PCA Watchdog Timer Reset ......................................................................... 110
11.7. Flash Error Reset .......................................................................................... 110
11.8. Software Reset .............................................................................................. 111
12. Flash Memory....................................................................................................... 113
12.1. Programming The Flash Memory .................................................................. 113
12.1.1. Flash Lock and Key Functions .............................................................. 113
12.1.2. Flash Erase Procedure ......................................................................... 114
12.1.3. Flash Write Procedure .......................................................................... 114
12.2. Flash Write and Erase Guidelines ................................................................. 115
12.2.1. VDD Maintenance and the VDD monitor ................................................ 115
12.2.2. PSWE Maintenance .............................................................................. 115
12.2.3. System Clock ........................................................................................ 116
12.3. Non-volatile Data Storage ............................................................................. 117
12.4. Security Options ............................................................................................ 117
13. Port Input/Output ................................................................................................. 120
13.1. Priority Crossbar Decoder ............................................................................. 122
13.2. Port I/O Initialization ...................................................................................... 126
13.3. General Purpose Port I/O .............................................................................. 128
14. Oscillators ............................................................................................................ 135
14.1. Programmable Internal Oscillator .................................................................. 135
14.1.1. Internal Oscillator Suspend Mode ......................................................... 136
14.2. External Oscillator Drive Circuit..................................................................... 139
14.2.1. Clocking Timers Directly Through the External Oscillator..................... 139
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C8051F52x/F53x
14.2.2. External Crystal Example...................................................................... 139
14.2.3. External RC Example............................................................................ 141
14.2.4. External Capacitor Example.................................................................. 141
14.3. System Clock Selection................................................................................. 143
15. UART0 ................................................................................................................... 144
15.1. Enhanced Baud Rate Generation.................................................................. 145
15.2. Operational Modes ........................................................................................ 146
15.2.1. 8-Bit UART ............................................................................................ 146
15.2.2. 9-Bit UART ............................................................................................ 147
15.3. Multiprocessor Communications ................................................................... 148
16. Enhanced Serial Peripheral Interface (SPI0) ..................................................... 151
16.1. Signal Descriptions........................................................................................ 152
16.1.1. Master Out, Slave In (MOSI)................................................................. 152
16.1.2. Master In, Slave Out (MISO)................................................................. 152
16.1.3. Serial Clock (SCK) ................................................................................ 152
16.1.4. Slave Select (NSS) ............................................................................... 152
16.2. SPI0 Master Mode Operation ........................................................................ 153
16.3. SPI0 Slave Mode Operation .......................................................................... 154
16.4. SPI0 Interrupt Sources .................................................................................. 155
16.5. Serial Clock Timing........................................................................................ 156
16.6. SPI Special Function Registers ..................................................................... 156
17. LIN (C8051F520/0A/3/3A/6/6A and C8051F530/0A/3/3A/6/6A) .......................... 164
17.1. Software Interface with the LIN Peripheral .................................................... 165
17.2. LIN Interface Setup and Operation................................................................ 165
17.2.1. Mode Definition ..................................................................................... 165
17.2.2. Baud Rate Options: Manual or Autobaud ............................................. 165
17.2.3. Baud Rate Calculations—Manual Mode ............................................... 165
17.2.4. Baud Rate Calculations—Automatic Mode ........................................... 168
17.3. LIN Master Mode Operation .......................................................................... 169
17.4. LIN Slave Mode Operation ............................................................................ 170
17.5. Sleep Mode and Wake-Up ............................................................................ 171
17.6. Error Detection and Handling ........................................................................ 171
17.7. LIN Registers................................................................................................. 172
17.7.1. LIN Direct Access SFR Registers Definition ......................................... 172
17.7.2. LIN Indirect Access SFR Registers Definition....................................... 174
18. Timers ................................................................................................................... 182
18.1. Timer 0 and Timer 1 ...................................................................................... 182
18.1.1. Mode 0: 13-bit Counter/Timer ............................................................... 182
18.1.2. Mode 1: 16-bit Counter/Timer ............................................................... 184
18.1.3. Mode 2: 8-bit Counter/Timer with Auto-Reload..................................... 184
18.1.4. Mode 3: Two 8-bit Counter/Timers (Timer 0 Only)................................ 185
18.2. Timer 2 .......................................................................................................... 190
18.2.1. 16-bit Timer with Auto-Reload............................................................... 190
18.2.2. 8-bit Timers with Auto-Reload............................................................... 191
18.2.3. External Capture Mode ......................................................................... 192
Rev. 1.4
5
C8051F52x/F53x
19. Programmable Counter Array (PCA0)................................................................ 195
19.1. PCA Counter/Timer ....................................................................................... 196
19.2. Capture/Compare Modules ........................................................................... 197
19.2.1. Edge-triggered Capture Mode............................................................... 198
19.2.2. Software Timer (Compare) Mode.......................................................... 199
19.2.3. High Speed Output Mode...................................................................... 200
19.2.4. Frequency Output Mode ....................................................................... 201
19.2.5. 8-Bit Pulse Width Modulator Mode........................................................ 202
19.2.6. 16-Bit Pulse Width Modulator Mode...................................................... 203
19.3. Watchdog Timer Mode .................................................................................. 203
19.3.1. Watchdog Timer Operation ................................................................... 204
19.3.2. Watchdog Timer Usage ........................................................................ 205
19.4. Register Descriptions for PCA....................................................................... 206
20. Device Specific Behavior .................................................................................... 210
20.1. Device Identification ...................................................................................... 210
20.2. Reset Pin Behavior........................................................................................ 211
20.3. Reset Time Delay .......................................................................................... 211
20.4. VDD Monitors and VDD Ramp Time ............................................................. 211
20.5. VDD Monitor (VDDMON0) High Threshold Setting ....................................... 212
20.6. Reset Low Time............................................................................................. 212
20.7. Internal Oscillator Suspend Mode ................................................................. 212
20.8. UART Pins..................................................................................................... 213
20.9. LIN ................................................................................................................. 213
20.9.1. Stop Bit Check ...................................................................................... 213
20.9.2. Synch Break and Synch Field Length Check........................................ 213
21. C2 Interface .......................................................................................................... 214
21.1. C2 Interface Registers................................................................................... 214
21.2. C2 Pin Sharing .............................................................................................. 216
Document Change List.............................................................................................. 217
Contact Information................................................................................................... 220
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Rev. 1.4
C8051F52x/F53x
List of Figures
Figure 1.1. C8051F53xA/F53x-C Block Diagram .................................................... 16
Figure 1.2. C8051F52xA/F52x-C Block Diagram .................................................... 16
Figure 1.3. C8051F53x Block Diagram (Silicon Revision A) ................................... 17
Figure 1.4. C8051F52x Block Diagram (Silicon Revision A) ................................... 17
Figure 1.5. Development/In-System Debug Diagram .............................................. 19
Figure 1.6. Memory Map ......................................................................................... 20
Figure 1.7. 12-Bit ADC Block Diagram .................................................................... 22
Figure 1.8. Comparator Block Diagram ................................................................... 23
Figure 1.9. Port I/O Functional Block Diagram ........................................................ 24
Figure 3.1. DFN-10 Pinout Diagram (Top View) ...................................................... 35
Figure 3.2. DFN-10 Package Diagram .................................................................... 38
Figure 3.3. DFN-10 Landing Diagram ..................................................................... 39
Figure 3.4. TSSOP-20 Pinout Diagram (Top View) ................................................. 40
Figure 3.5. TSSOP-20 Package Diagram ............................................................... 43
Figure 3.6. TSSOP-20 Landing Diagram ................................................................. 44
Figure 3.7. QFN-20 Pinout Diagram (Top View) ..................................................... 45
Figure 3.8. QFN-20 Package Diagram* ................................................................... 48
Figure 3.9. QFN-20 Landing Diagram* .................................................................... 50
Figure 4.1. ADC0 Functional Block Diagram ........................................................... 52
Figure 4.2. Typical Temperature Sensor Transfer Function .................................... 53
Figure 4.3. ADC0 Tracking Modes .......................................................................... 55
Figure 4.4. 12-Bit ADC Tracking Mode Example ..................................................... 56
Figure 4.5. 12-Bit ADC Burst Mode Example with Repeat Count Set to 4 .............. 58
Figure 4.6. ADC0 Equivalent Input Circuits ............................................................. 60
Figure 4.7. ADC Window Compare Example: 
Right-Justified Single-Ended Data ........................................................ 71
Figure 4.8. ADC Window Compare Example: 
Left-Justified Single-Ended Data .......................................................... 71
Figure 5.1. Voltage Reference Functional Block Diagram ....................................... 72
Figure 6.1. External Capacitors for Voltage Regulator Input/Output ....................... 74
Figure 7.1. Comparator Functional Block Diagram ................................................. 76
Figure 7.2. Comparator Hysteresis Plot .................................................................. 77
Figure 8.1. CIP-51 Block Diagram ........................................................................... 81
Figure 9.1. Memory Map ......................................................................................... 92
Figure 11.1. Reset Sources ................................................................................... 106
Figure 11.2. Power-On and VDD Monitor Reset Timing ........................................ 107
Figure 12.1. Flash Program Memory Map ............................................................. 117
Figure 13.1. Port I/O Functional Block Diagram .................................................... 120
Figure 13.2. Port I/O Cell Block Diagram .............................................................. 121
Figure 13.3. Crossbar Priority Decoder with No Pins Skipped 
(TSSOP 20 and QFN 20) .................................................................. 122
Figure 13.4. Crossbar Priority Decoder with Crystal Pins Skipped
(TSSOP 20 and QFN 20) .................................................................. 123
Rev. 1.4
7
C8051F52x/F53x
Figure 13.5. Crossbar Priority Decoder with No Pins Skipped (DFN 10) .............. 124
Figure 13.6. Crossbar Priority Decoder with Some Pins Skipped (DFN 10) ......... 125
Figure 14.1. Oscillator Diagram ............................................................................. 135
Figure 14.2. 32 kHz External Crystal Example ...................................................... 140
Figure 15.1. UART0 Block Diagram ...................................................................... 144
Figure 15.2. UART0 Baud Rate Logic ................................................................... 145
Figure 15.3. UART Interconnect Diagram ............................................................. 146
Figure 15.4. 8-Bit UART Timing Diagram .............................................................. 146
Figure 15.5. 9-Bit UART Timing Diagram .............................................................. 147
Figure 15.6. UART Multi-Processor Mode Interconnect Diagram ......................... 148
Figure 16.1. SPI Block Diagram ............................................................................ 151
Figure 16.2. Multiple-Master Mode Connection Diagram ...................................... 154
Figure 16.3. 3-Wire Single Master and Slave Mode Connection Diagram ............ 154
Figure 16.4. 4-Wire Single Master and Slave Mode Connection Diagram ............ 154
Figure 16.5. Data/Clock Timing Relationship ........................................................ 156
Figure 16.6. SPI Master Timing (CKPHA = 0) ....................................................... 161
Figure 16.7. SPI Master Timing (CKPHA = 1) ....................................................... 161
Figure 16.8. SPI Slave Timing (CKPHA = 0) ......................................................... 162
Figure 16.9. SPI Slave Timing (CKPHA = 1) ......................................................... 162
Figure 17.1. LIN Block Diagram ............................................................................ 164
Figure 18.1. T0 Mode 0 Block Diagram ................................................................. 183
Figure 18.2. T0 Mode 2 Block Diagram ................................................................. 184
Figure 18.3. T0 Mode 3 Block Diagram ................................................................. 185
Figure 18.4. Timer 2 16-Bit Mode Block Diagram ................................................. 190
Figure 18.5. Timer 2 8-Bit Mode Block Diagram ................................................... 191
Figure 18.6. Timer 2 Capture Mode Block Diagram .............................................. 192
Figure 19.1. PCA Block Diagram ........................................................................... 195
Figure 19.2. PCA Counter/Timer Block Diagram ................................................... 196
Figure 19.3. PCA Interrupt Block Diagram ............................................................ 197
Figure 19.4. PCA Capture Mode Diagram ............................................................. 198
Figure 19.5. PCA Software Timer Mode Diagram ................................................. 199
Figure 19.6. PCA High-Speed Output Mode Diagram ........................................... 200
Figure 19.7. PCA Frequency Output Mode ........................................................... 201
Figure 19.8. PCA 8-Bit PWM Mode Diagram ........................................................ 202
Figure 19.9. PCA 16-Bit PWM Mode ..................................................................... 203
Figure 19.10. PCA Module 2 with Watchdog Timer Enabled ................................ 204
Figure 20.1. Device Package—TSSOP 20 ............................................................ 210
Figure 20.2. Device Package—QFN 20 ................................................................ 210
Figure 20.3. Device Package—DFN 10 ................................................................ 211
Figure 21.1. Typical C2 Pin Sharing ...................................................................... 216
8
Rev. 1.4
C8051F52x/F53x
List of Tables
Table 1.1. Product Selection Guide (Recommended for New Designs) .................. 14
Table 1.2. Product Selection Guide (Not Recommended for New Designs) ........... 15
Table 1.3. Operating Modes Summary .................................................................... 21
Table 2.1. Absolute Maximum Ratings .................................................................... 25
Table 2.2. Global DC Electrical Characteristics ....................................................... 26
Table 2.3. ADC0 Electrical Characteristics .............................................................. 28
Table 2.4. Temperature Sensor Electrical Characteristics ...................................... 29
Table 2.5. Voltage Reference Electrical Characteristics ......................................... 29
Table 2.6. Voltage Regulator Electrical Specifications ............................................ 30
Table 2.7. Comparator Electrical Characteristics .................................................... 31
Table 2.8. Reset Electrical Characteristics .............................................................. 32
Table 2.9. Flash Electrical Characteristics .............................................................. 33
Table 2.10. Port I/O DC Electrical Characteristics ................................................... 33
Table 2.11. Internal Oscillator Electrical Characteristics ......................................... 34
Table 3.1. Pin Definitions for the C8051F52x and C8051F52xA (DFN 10) ............. 36
Table 3.2. DFN-10 Package Diagram Dimensions .................................................. 38
Table 3.3. DFN-10 Landing Diagram Dimensions ................................................... 39
Table 3.4. Pin Definitions for the C8051F53x and C805153xA (TSSOP 20) .......... 40
Table 3.5. TSSOP-20 Package Diagram Dimensions ............................................. 43
Table 3.6. TSSOP-20 Landing Diagram Dimensions .............................................. 44
Table 3.7. Pin Definitions for the C8051F53x and C805153xA (QFN 20) ............... 46
Table 3.8. QFN-20 Package Diagram Dimensions ................................................. 49
Table 3.9. QFN-20 Landing Diagram Dimensions ................................................... 51
Table 8.1. CIP-51 Instruction Set Summary ............................................................ 83
Table 9.1. Special Function Register (SFR) Memory Map ...................................... 94
Table 9.2. Special Function Registers ..................................................................... 95
Table 10.1. Interrupt Summary ................................................................................ 99
Table 12.1. Flash Security Summary .................................................................... 118
Table 15.1. Timer Settings for Standard Baud Rates 
Using the Internal Oscillator ............................................................... 150
Table 16.1. SPI Slave Timing Parameters ............................................................ 163
Table 17.1. Baud-Rate Calculation Variable Ranges ............................................ 166
Table 17.2. Manual Baud Rate Parameters Examples ......................................... 167
Table 17.3. Autobaud Parameters Examples ........................................................ 168
Table 17.4. LIN Registers* (Indirectly Addressable) .............................................. 174
Table 19.1. PCA Timebase Input Options ............................................................. 196
Table 19.2. PCA0CPM Register Settings for PCA Capture/Compare Modules .... 197
Table 19.3. Watchdog Timer Timeout Intervals1 ................................................... 205
Rev. 1.4
9
C8051F52x/F53x
List of Registers
SFR Definition 4.4. ADC0MX: ADC0 Channel Select ................................................... 64
SFR Definition 4.5. ADC0CF: ADC0 Configuration ..................................................... 65
SFR Definition 4.6. ADC0H: ADC0 Data Word MSB .................................................... 66
SFR Definition 4.7. ADC0L: ADC0 Data Word LSB ..................................................... 66
SFR Definition 4.8. ADC0CN: ADC0 Control ............................................................... 67
SFR Definition 4.9. ADC0TK: ADC0 Tracking Mode Select ........................................ 68
SFR Definition 4.10. ADC0GTH: ADC0 Greater-Than Data High Byte ........................ 69
SFR Definition 4.11. ADC0GTL: ADC0 Greater-Than Data Low Byte ......................... 69
SFR Definition 4.12. ADC0LTH: ADC0 Less-Than Data High Byte .............................. 70
SFR Definition 4.13. ADC0LTL: ADC0 Less-Than Data Low Byte ............................... 70
SFR Definition 5.1. REF0CN: Reference Control ......................................................... 73
SFR Definition 6.1. REG0CN: Regulator Control .......................................................... 75
SFR Definition 7.1. CPT0CN: Comparator0 Control ..................................................... 78
SFR Definition 7.2. CPT0MX: Comparator0 MUX Selection ........................................ 79
SFR Definition 7.3. CPT0MD: Comparator0 Mode Selection ....................................... 80
SFR Definition 8.1. SP: Stack Pointer ........................................................................... 87
SFR Definition 8.2. DPL: Data Pointer Low Byte .......................................................... 87
SFR Definition 8.3. DPH: Data Pointer High Byte ......................................................... 87
SFR Definition 8.4. PSW: Program Status Word .......................................................... 88
SFR Definition 8.5. ACC: Accumulator ......................................................................... 89
SFR Definition 8.6. B: B Register .................................................................................. 89
SFR Definition 8.7. PCON: Power Control .................................................................... 91
SFR Definition 10.1. IE: Interrupt Enable .................................................................... 100
SFR Definition 10.2. IP: Interrupt Priority .................................................................... 101
SFR Definition 10.3. EIE1: Extended Interrupt Enable 1 ............................................ 102
SFR Definition 10.4. EIP1: Extended Interrupt Priority 1 ............................................ 103
SFR Definition 10.5. IT01CF: INT0/INT1 Configuration .............................................. 105
SFR Definition 11.1. VDDMON: VDD Monitor Control ................................................ 109
SFR Definition 11.2. RSTSRC: Reset Source ............................................................ 112
SFR Definition 12.1. PSCTL: Program Store R/W Control ......................................... 119
SFR Definition 12.2. FLKEY: Flash Lock and Key ...................................................... 119
SFR Definition 13.1. XBR0: Port I/O Crossbar Register 0 .......................................... 127
SFR Definition 13.2. XBR1: Port I/O Crossbar Register 1 .......................................... 128
SFR Definition 13.3. P0: Port0 .................................................................................... 129
SFR Definition 13.4. P0MDIN: Port0 Input Mode ........................................................ 129
SFR Definition 13.5. P0MDOUT: Port0 Output Mode ................................................. 130
SFR Definition 13.6. P0SKIP: Port0 Skip .................................................................... 130
SFR Definition 13.7. P0MAT: Port0 Match ................................................................. 131
SFR Definition 13.8. P0MASK: Port0 Mask ................................................................ 131
SFR Definition 13.9. P1: Port1 .................................................................................... 132
SFR Definition 13.10. P1MDIN: Port1 Input Mode ...................................................... 132
SFR Definition 13.11. P1MDOUT: Port1 Output Mode ............................................... 133
SFR Definition 13.12. P1SKIP: Port1 Skip .................................................................. 133
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Rev. 1.4
C8051F52x/F53x
SFR Definition 13.13. P0SKIP: Port0 Skip .................................................................. 134
SFR Definition 13.14. P1MAT: Port1 Match ............................................................... 134
SFR Definition 13.15. P1MASK: Port1 Mask .............................................................. 134
SFR Definition 14.1. OSCICN: Internal Oscillator Control .......................................... 137
SFR Definition 14.2. OSCICL: Internal Oscillator Calibration ..................................... 138
SFR Definition 14.3. OSCIFIN: Internal Fine Oscillator Calibration ............................ 138
SFR Definition 14.4. OSCXCN: External Oscillator Control ........................................ 142
SFR Definition 14.5. CLKSEL: Clock Select ............................................................... 143
SFR Definition 15.1. SCON0: Serial Port 0 Control .................................................... 149
SFR Definition 15.2. SBUF0: Serial (UART0) Port Data Buffer .................................. 150
SFR Definition 16.1. SPI0CFG: SPI0 Configuration ................................................... 157
SFR Definition 16.2. SPI0CN: SPI0 Control ............................................................... 158
SFR Definition 16.3. SPI0CKR: SPI0 Clock Rate ....................................................... 159
SFR Definition 16.4. SPI0DAT: SPI0 Data ................................................................. 160
SFR Definition 17.1. LINADDR: Indirect Address Register ......................................... 172
SFR Definition 17.2. LINDATA: LIN Data Register ..................................................... 172
SFR Definition 17.3. LINCF Control Mode Register ................................................... 173
SFR Definition 17.4. LIN0DT1: LIN0 Data Byte 1 ....................................................... 174
SFR Definition 17.5. LIN0DT2: LIN0 Data Byte 2 ....................................................... 175
SFR Definition 17.6. LIN0DT3: LIN0 Data Byte 3 ....................................................... 175
SFR Definition 17.7. LIN0DT4: LIN0 Data Byte 4 ....................................................... 175
SFR Definition 17.8. LIN0DT5: LIN0 Data Byte 5 ....................................................... 176
SFR Definition 17.9. LIN0DT6: LIN0 Data Byte 6 ....................................................... 176
SFR Definition 17.10. LIN0DT7: LIN0 Data Byte 7 ..................................................... 176
SFR Definition 17.11. LIN0DT8: LIN0 Data Byte 8 ..................................................... 176
SFR Definition 17.12. LIN0CTRL: LIN0 Control Register ........................................... 177
SFR Definition 17.13. LIN0ST: LIN0 STATUS Register ............................................. 178
SFR Definition 17.14. LIN0ERR: LIN0 ERROR Register ............................................ 179
SFR Definition 17.15. LIN0SIZE: LIN0 Message Size Register .................................. 180
SFR Definition 17.16. LIN0DIV: LIN0 Divider Register ............................................... 180
SFR Definition 17.17. LIN0MUL: LIN0 Multiplier Register .......................................... 181
SFR Definition 17.18. LIN0ID: LIN0 ID Register ......................................................... 181
SFR Definition 18.1. TCON: Timer Control ................................................................. 186
SFR Definition 18.2. TMOD: Timer Mode ................................................................... 187
SFR Definition 18.3. CKCON: Clock Control .............................................................. 188
SFR Definition 18.4. TL0: Timer 0 Low Byte ............................................................... 189
SFR Definition 18.5. TL1: Timer 1 Low Byte ............................................................... 189
SFR Definition 18.6. TH0: Timer 0 High Byte ............................................................. 189
SFR Definition 18.7. TH1: Timer 1 High Byte ............................................................. 189
SFR Definition 18.8. TMR2CN: Timer 2 Control ......................................................... 193
SFR Definition 18.9. TMR2RLL: Timer 2 Reload Register Low Byte .......................... 194
SFR Definition 18.10. TMR2RLH: Timer 2 Reload Register High Byte ...................... 194
SFR Definition 18.11. TMR2L: Timer 2 Low Byte ....................................................... 194
SFR Definition 18.12. TMR2H Timer 2 High Byte ....................................................... 194
SFR Definition 19.1. PCA0CN: PCA Control .............................................................. 206
Rev. 1.4
11
C8051F52x/F53x
SFR Definition 19.2. PCA0MD: PCA Mode ................................................................ 207
SFR Definition 19.3. PCA0CPMn: PCA Capture/Compare Mode .............................. 208
SFR Definition 19.4. PCA0L: PCA Counter/Timer Low Byte ...................................... 209
SFR Definition 19.5. PCA0H: PCA Counter/Timer High Byte ..................................... 209
SFR Definition 19.6. PCA0CPLn: PCA Capture Module Low Byte ............................. 209
SFR Definition 19.7. PCA0CPHn: PCA Capture Module High Byte ........................... 209
C2 Register Definition 21.1. C2ADD: C2 Address ...................................................... 214
C2 Register Definition 21.2. DEVICEID: C2 Device ID ............................................... 214
C2 Register Definition 21.3. REVID: C2 Revision ID .................................................. 215
C2 Register Definition 21.4. FPCTL: C2 Flash Programming Control ........................ 215
C2 Register Definition 21.5. FPDAT: C2 Flash Programming Data ............................ 215
12
Rev. 1.4
C8051F52x/F53x
1. System Overview
The C8051F52x/F52xA/F53x/F53xA family of devices are fully integrated, low power, mixed-signal systemon-a-chip MCUs. Highlighted features are listed below. Refer to Table 1.1 for specific product feature
selection.











High-speed pipelined 8051-compatible microcontroller core (up to 25 MIPS)
In-system, full-speed, non-intrusive debug interface (on-chip)
True 12-bit 200 ksps ADC with analog multiplexer and up to 16 analog inputs
Precision programmable 24.5 MHz internal oscillator that is within ±0.5% across the temperature range
and for VDD voltages greater than or equal to the on-chip voltage regulator minimum output at the low
setting. The oscillator is within +1.0% for VDD voltages below this minimum output setting.
Up to 7680 bytes of on-chip Flash memory
256 bytes of on-chip RAM
Enhanced UART, and SPI serial interfaces implemented in hardware
LIN 2.1 peripheral (fully backwards compatible, master and slave modes)
Three general-purpose 16-bit timers
Programmable Counter/Timer Array (PCA) with three capture/compare modules and Watchdog Timer
function
On-chip Power-On Reset, VDD Monitor, and Temperature Sensor

On-chip Voltage Comparator
 Up to 16 Port I/O
With on-chip Power-On Reset, VDD monitor, Watchdog Timer, and clock oscillator, the
C8051F52x/F52xA/F53x/F53xA devices are truly standalone system-on-a-chip solutions. The Flash memory is byte writable and can be reprogrammed in-circuit, providing non-volatile data storage, and also
allowing field upgrades of the 8051 firmware. User software has complete control of all peripherals, and
may individually shut down any or all peripherals for power savings.
The on-chip Silicon Laboratories 2-Wire (C2) Development Interface allows non-intrusive (uses no on-chip
resources), full speed, in-circuit debugging using the production MCU installed in the final application. This
debug logic supports inspection and modification of memory and registers, setting breakpoints, single
stepping, run and halt commands. All analog and digital peripherals are fully functional while debugging
using C2. The two C2 interface pins can be shared with user functions, allowing in-system programming
and debugging without occupying package pins.
Each device is specified for 2.0 to 5.25 V operation (supply voltage can be up to 5.25 V using on-chip regulator) over the automotive temperature range (–40 to +125 °C). The F52x/F52xA is available in the
DFN10 (3 x 3 mm) package. The F53x/F53xA is available in the QFN20 (4 x 4 mm) or the TSSOP20 package.
Rev. 1.4
13
C8051F52x/F53x
1.1. Ordering Information
The following features are common to all devices in this family:











25 MHz system clock and 25 MIPS throughput (peak)
256 bytes of internal RAM
Enhanced SPI peripheral
Enhanced UART peripheral
Three Timers
Three Programmable Counter Array channels
Internal 24.5 MHz oscillator
Internal Voltage Regulator
12-bit, 200 ksps ADC
Internal Voltage Reference and Temperature Sensor
One Analog Comparator

Table 1.1 shows the features that differentiate the devices in this family.

DFN-10
C8051F534-C-IM 4
16
—
QFN-20
C8051F521-C-IM
8
6
—
DFN-10
C8051F536-C-IM 2
16

QFN-20
C8051F523-C-IM
4
6

DFN-10
C8051F537-C-IM 2
16
—
QFN-20
TSSOP-20
Package
6
LIN
8
Port I/Os
Flash Memory (kB)
LIN
Ordering Part Number
Port I/Os
C8051F520-C-IM
Package
Flash Memory (kB)
Ordering Part Number
Table 1.1. Product Selection Guide (Recommended for New Designs)
C8051F524-C-IM
4
6
—
DFN-10
C8051F530-C-IT 8
16

C8051F526-C-IM
2
6

DFN-10
C8051F531-C-IT 8
16
— TSSOP-20
C8051F527-C-IM
2
6
—
DFN-10
C8051F533-C-IT 4
16

C8051F530-C-IM
8
16

QFN-20
C8051F534-C-IT 4
16
— TSSOP-20
TSSOP-20
C8051F531-C-IM
8
16
—
QFN-20
C8051F536-C-IT 2
16

C8051F533-C-IM
4
16

QFN-20
C8051F537-C-IT 2
16
— TSSOP-20
TSSOP-20
All devices in Table 1.1 are also available in an automotive version. For the automotive version, the -I in the
ordering part number is replaced with -A. For example, the automotive version of the C8051F520-C-IM is
the C8051F520-C-AM.
The -AM and -AT devices receive full automotive quality production status, including AEC-Q100 qualification (fault coverage report available upon request), registration with International Material Data System
(IMDS) and Part Production Approval Process (PPAP) documentation. PPAP documentation is available at
www.silabs.com with a registered NDA and approved user account. The -AM and -AT devices enable high
volume automotive OEM applications with their enhanced testing and processing. Please contact Silicon
Labs sales for more information regarding -AM and -AT devices for your automotive project.
14
Rev. 1.4
C8051F52x/F53x

DFN-10
C8051F534-IM 4
C8051F534A-IM
16
—
QFN-20
C8051F521-IM
C8051F521A-IM
8
6
—
DFN-10
C8051F536-IM 2
C8051F536A-IM
16

QFN-20
C8051F523-IM
C8051F523A-IM
4
6

DFN-10
C8051F537-IM 2
C8051F537A-IM
16
—
QFN-20
C8051F524-IM
C8051F524A-IM
4
6
—
DFN-10
C8051F530-IT
C8051F530A-IT
8
16

TSSOP-20
C8051F526-IM
C8051F526A-IM
2
6

DFN-10
C8051F531-IT
C8051F531A-IT
8
16
— TSSOP-20
C8051F527-IM
C8051F527A-IM
2
6
—
DFN-10
C8051F533-IT
C8051F533A-IT
4
16

C8051F530-IM
C8051F530A-IM
8
16

QFN-20
C8051F534-IT
C8051F534A-IT
4
16
— TSSOP-20
C8051F531-IM
C8051F531A-IM
8
16
—
QFN-20
C8051F536-IT
C8051F536A-IT
2
16

C8051F533-IM
C8051F533A-IM
4
16

QFN-20
C8051F537-IT
C8051F537A-IT
2
16
— TSSOP-20
Package
6
LIN
8
Port I/Os
Flash Memory (kB)
LIN
Ordering Part Number
Port I/Os
C8051F520-IM
C8051F520A-IM
Package
Flash Memory (kB)
Ordering Part Number
Table 1.2. Product Selection Guide (Not Recommended for New Designs)
TSSOP-20
TSSOP-20
The part numbers in Table 1.2 are not recommended for new designs. Instead, select the corresponding
part number from Table 1.1 (silicon revision C) for your design. In Table 1.2, the part numbers in the format
similar to C8051F520-IM are silicon revision A devices. The part numbers in the format similar to
C8051F520A-IM are silicon revision B devices.
Rev. 1.4
15
C8051F52x/F53x
Power On
Reset
Reset
C2CK/RST
Port I/O Configuration
CIP-51 8051
Controller Core
Digital Peripherals
up to 8k Byte Flash
Program Memory
Debug /
Programming
Hardware
VREGIN
Port 0
Drivers
P0.0/VREF
P0.1
P0.2
P0.3
P0.4/TX
P0.5/RX
P0.6/C2D
P0.7/XTAL1
Port 1
Drivers
P1.0/XTAL2
P1.1
P1.2/CNVSTR
P1.3
P1.4
P1.5
P1.6
P1.7
UART0
Timers 0,
1, 2, 3
256 Byte SRAM
Priority
Crossbar
Decoder
PCA/
WDT
C2D
LIN 2.1
VREGIN
Voltage Regulator
(LDO)
SPI
Crossbar Control
SFR
Bus
VDD
GND
Analog Peripherals
Voltage
Reference
System Clock Setup
VDD
XTAL1
XTAL2
VREF
VREF
External Oscillator
12-bit
200ksps
ADC
Internal Oscillator
VDD
VREF
A
M
U
X
Temp
Sensor
GND
CP0, CP0A
+
-
Comparator
Figure 1.1. C8051F53xA/F53x-C Block Diagram
Power On
Reset
Reset
C2CK/RST
Port I/O Configuration
CIP-51 8051
Controller Core
Digital Peripherals
up to 8k Byte Flash
Program Memory
Debug /
Programming
Hardware
VREGIN
UART0
Timers 0,
1, 2, 3
256 Byte SRAM
Priority
Crossbar
Decoder
PCA/
WDT
C2D
Port 0
Drivers
LIN 2.1
VREGIN
Voltage Regulator
(LDO)
SPI
Crossbar Control
SFR
Bus
VDD
GND
Analog Peripherals
Voltage
Reference
System Clock Setup
XTAL1
XTAL2
VDD
VREF
VREF
External Oscillator
Internal Oscillator
A
M
U
X
12-bit
200ksps
ADC
VDD
VREF
Temp
Sensor
GND
CP0, CP0A
+
-
Comparator
Figure 1.2. C8051F52xA/F52x-C Block Diagram
16
Rev. 1.4
P0.0/VREF
P0.1/C2D
P0.2/XTAL1
P0.3/XTAL2
P0.4/TX
P0.5/RX/
CNVSTR
C8051F52x/F53x
Power On
Reset
Reset
C2CK/RST
Port I/O Configuration
CIP-51 8051
Controller Core
Digital Peripherals
up to 8k Byte Flash
Program Memory
Debug /
Programming
Hardware
VREGIN
Port 0
Drivers
P0.0/VREF
P0.1
P0.2
P0.3/TX
P0.4/RX
P0.5
P0.6/C2D
P0.7/XTAL1
Port 1
Drivers
P1.0/XTAL2
P1.1
P1.2/CNVSTR
P1.3
P1.4
P1.5
P1.6
P1.7
UART0
Timers 0,
1, 2, 3
256 Byte SRAM
Priority
Crossbar
Decoder
PCA/
WDT
C2D
LIN 2.1
VREGIN
Voltage Regulator
(LDO)
SPI
Crossbar Control
SFR
Bus
VDD
GND
Analog Peripherals
Voltage
Reference
System Clock Setup
VDD
XTAL1
XTAL2
VREF
VREF
External Oscillator
12-bit
200ksps
ADC
Internal Oscillator
VDD
VREF
A
M
U
X
Temp
Sensor
GND
CP0, CP0A
+
-
Comparator
Figure 1.3. C8051F53x Block Diagram (Silicon Revision A)
Power On
Reset
Reset
C2CK/RST
Port I/O Configuration
CIP-51 8051
Controller Core
Digital Peripherals
up to 8k Byte Flash
Program Memory
Debug /
Programming
Hardware
VREGIN
UART0
Timers 0,
1, 2, 3
256 Byte SRAM
Priority
Crossbar
Decoder
PCA/
WDT
C2D
Port 0
Drivers
P0.0/VREF
P0.1/C2D
P0.2/XTAL1
P0.3/XTAL2/TX
P0.4/RX
P0.5/CNVSTR
LIN 2.1
VREGIN
Voltage Regulator
(LDO)
SPI
Crossbar Control
SFR
Bus
VDD
GND
Analog Peripherals
Voltage
Reference
System Clock Setup
XTAL1
XTAL2
VDD
VREF
VREF
External Oscillator
Internal Oscillator
A
M
U
X
12-bit
200ksps
ADC
VDD
VREF
Temp
Sensor
GND
CP0, CP0A
+
-
Comparator
Figure 1.4. C8051F52x Block Diagram (Silicon Revision A)
Rev. 1.4
17
C8051F52x/F53x
1.2. CIP-51™ Microcontroller
1.2.1. Fully 8051 Compatible Instruction Set
The C8051F52x/F52xA/F53x/F53xA devices use Silicon Laboratories’ proprietary CIP-51 microcontroller
core. The CIP-51 is fully compatible with the MCS-51™ instruction set. Standard 803x/805x assemblers
and compilers can be used to develop software. The C8051F52x/F52xA/F53x/F53xA family has a superset
of all the peripherals included with a standard 8052.
1.2.2. Improved Throughput
The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the standard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system
clock cycles to execute, and usually have a maximum system clock of 12-to-24 MHz. By contrast, the CIP51 core executes 70% of its instructions in one or two system clock cycles, with no instructions taking more
than eight system clock cycles.
With the CIP-51's system clock running at 25 MHz, it has a peak throughput of 25 MIPS. The CIP-51 has a
total of 109 instructions. The table below shows the total number of instructions that require each execution
time.
Clocks to Execute
1
2
2/3
3
3/4
4
4/5
5
8
Number of Instructions
26
50
5
14
7
3
1
2
1
1.2.3. Additional Features
The C8051F52x/F52xA/F53x/F53xA family includes several key enhancements to the CIP-51 core and
peripherals to improve performance and ease of use in end applications.
An extended interrupt handler allows the numerous analog and digital peripherals to operate independently of the controller core and interrupt the controller only when necessary. By requiring less intervention
from the microcontroller core, an interrupt-driven system is more efficient and allows for easier implementation of multi-tasking, real-time systems.
Eight reset sources are available: power-on reset circuitry (POR), an on-chip VDD monitor, a Watchdog
Timer, a Missing Clock Detector, a voltage level detection from Comparator, a forced software reset, an
external reset pin, and an illegal Flash access protection circuit. Each reset source except for the POR,
Reset Input Pin, or Flash error may be disabled by the user in software. The WDT may be permanently
enabled in software after a power-on reset during MCU initialization.
The internal oscillator is factory calibrated to 24.5 MHz ±0.5% across the entire operating temperature and
voltage range. An external oscillator drive circuit is also included, allowing an external crystal, ceramic resonator, capacitor, RC, or CMOS clock source to generate the system clock.
1.2.4. On-Chip Debug Circuitry
The C8051F52x/F52xA/F53x/F53xA devices include on-chip Silicon Laboratories 2-Wire (C2) debug circuitry that provides non-intrusive, full speed, in-circuit debugging of the production part installed in the end
application.
Silicon Laboratories’ debugging system supports inspection and modification of memory and registers,
breakpoints, and single stepping. No additional target RAM, program memory, timers, or communications
channels are required. All the digital and analog peripherals are functional and work correctly while debugging. All the peripherals (except for the ADC) are stalled when the MCU is halted, during single stepping,
or at a breakpoint in order to keep them synchronized.
The C8051F530DK development kit provides all the hardware and software necessary to develop application code and perform in-circuit debugging with the C8051F52x/F52xA/F53x/F53xA MCUs. The kit
18
Rev. 1.4
C8051F52x/F53x
includes software with a developer's studio and debugger, a USB debug adapter, a target application
board with the associated MCU installed, and the required cables and wall-mount power supply. The
development kit requires a computer with Windows installed. As shown in Figure 1.5, the PC is connected
to the USB debug adapter. A six-inch ribbon cable connects the USB debug adapter to the user's application board, picking up the two C2 pins and GND.
The Silicon Laboratories IDE interface is a vastly superior developing and debugging configuration, compared to standard MCU emulators that use on-board "ICE Chips" and require the MCU in the application
board to be socketed. Silicon Laboratories’ debug paradigm increases ease of use and preserves the performance of the precision analog peripherals.
Target Board
J8
D2
J6
PC
D1
P1.4_B
J14
C8051F530A TB
U1
HDR3
P5
DEBUG_B
T1
PWR
U2
J13
U3
T2
SILICON
LABORATORIES
“B” Side
HDR2
Reset_A
P1
J4 J3 J5
“A” Side
P1.6_B
P1.7_B
DEBUG_A
P0.0_B
Run
Stop
Silicon Laboratories
USB DEBUG ADAPTER
Power
USB
Cable
P1.4_A
HDR4
USB Debug Adapter
HDR1
Reset_B
AC/DC
Adapter
Figure 1.5. Development/In-System Debug Diagram
Rev. 1.4
19
C8051F52x/F53x
1.3. On-Chip Memory
The CIP-51 has a standard 8051 program and data address configuration. It includes 256 bytes of data
RAM, with the upper 128 bytes dual-mapped. Indirect addressing accesses the upper 128 bytes of general
purpose RAM, and direct addressing accesses the 128 byte SFR address space. The lower 128 bytes of
RAM are accessible via direct and indirect addressing. The first 32 bytes are addressable as four banks of
general purpose registers, and the next 16 bytes can be byte addressable or bit addressable.
Program memory consists of 7680 bytes (’F520/0A/1/1A and ’F530/0A/1/1A), 4 kB (’F523/3A/4/4A and
C8051F53x/53xA), or 2 kB (’F526/6A/7/7A and ’F536/6A/7/7A) of Flash. This memory is byte writable and
erased in 512-byte sectors, and requires no special off-chip programming voltage.
PROGRAM/DATA MEMORY
(Flash)
'F520/0A/1/1A and 'F530/0A/1/1A
0x1E00
0x1DFF
0xFF
RESERVED
8 kB Flash
(In-System
Programmable in 512
Byte Sectors)
0x0000
'F523/3A/4/4A and 'F533/3A/4/4A
0x1000
0x0FFF
DATA MEMORY (RAM)
INTERNAL DATA ADDRESS SPACE
0x80
0x7F
Upper 128 RAM
(Indirect Addressing
Only)
(Direct and Indirect
Addressing)
0x30
0x2F
0x20
0x1F
0x00
Bit Addressable
General Purpose
Registers
RESERVED
4 kB Flash
0x0000
(In-System
Programmable in 512
Byte Sectors)
'F526/6A/7/7A and 'F536/6A/7/7A
0x0800
0x07FF
RESERVED
2 kB Flash
(In-System
Programmable in 512
Byte Sectors)
0x0000
Figure 1.6. Memory Map
20
Rev. 1.4
Special Function
Register's
(Direct Addressing Only)
Lower 128 RAM
(Direct and Indirect
Addressing)
C8051F52x/F53x
1.4. Operating Modes
The C8051F52x/F52xA/F53x/F53xA devices have four operating modes: Active (Normal), Idle, Suspend,
and Stop. Active mode occurs during normal operation when the oscillator and peripherals are active. Idle
mode halts the CPU while leaving the peripherals and internal clocks active. In Suspend and Stop mode,
the CPU is halted, all interrupts and timers are inactive, and the internal oscillator is stopped. The various
operating modes are described in Table 1.3 below:
Table 1.3. Operating Modes Summary
Properties
Active

SYSCLK active
CPU active (accessing Flash)
 Peripherals active or inactive
depending on user settings
Power
Consumption
Full
How
Entered?
—
How Exited?
—

Idle

Less than Full
IDLE
(PCON.0)
Any enabled interrupt
or device reset
Suspend

Low
SUSPEND
(OSCICN.5)
Port 0 event match
Port 1 event match
Comparator 0 enabled
and output is logic 0
Stop

Very low
STOP
(PCON.1)
Device Reset
SYSCLK active
 CPU inactive (not accessing
Flash)
 Peripherals active or inactive
depending on user settings
Internal oscillator inactive
 If SYSCLK is derived from the
internal oscillator, the peripherals
and the CIP-51 will be stopped
SYSCLK inactive
CPU inactive (not accessing
Flash)
 Digital peripherals inactive;
analog peripherals active or
inactive depending on user
settings

See Section “8.3. Power Management Modes” on page 89 for Idle and Stop mode details. See Section
“14.1.1. Internal Oscillator Suspend Mode” on page 136 for more information on Suspend mode.
Rev. 1.4
21
C8051F52x/F53x
1.5. 12-Bit Analog to Digital Converter
The C8051F52x/F52xA/F53x/F53xA devices include an on-chip 12-bit SAR ADC with a maximum throughput of 200 ksps. The ADC system includes a configurable analog multiplexer that selects the positive ADC
input, which is measured with respect to GND. Ports 0 and 1 are available as ADC inputs; additionally, the
ADC includes an innovative programmable gain stage which allows the ADC to sample inputs sources
greater than the VREF voltage. The on-chip Temperature Sensor output and the core supply voltage (VDD)
are also available as ADC inputs. User firmware may shut down the ADC or use it in Burst Mode to save
power.
Conversions can be initiated in four ways: a software command, an overflow of Timer 1, an overflow of
Timer 2, or an external convert start signal. This flexibility allows the start of conversion to be triggered by
software events, a periodic signal (timer overflows), or external HW signals. Conversion completions are
indicated by a status bit and an interrupt (if enabled) and occur after 1, 4, 8, or 16 samples have been
accumulated by a hardware accumulator. The resulting 12-bit to 16-bit data word is latched into the ADC
data SFRs upon completion of a conversion. When the system clock is slow, Burst Mode allows ADC0 to
automatically wake from a low power shutdown state, acquire and accumulate samples, then re-enter the
low power shutdown state without CPU intervention.
Window compare registers for the ADC data can be configured to interrupt the controller when ADC data is
either within or outside of a specified range. The ADC can monitor a key voltage continuously in background mode, but not interrupt the controller unless the converted data is within/outside the specified
range.
Analog Multiplexer
Configuration, Control, and Data Registers
P0.0
P0.6*
P0.7*
P1.0*
P1.7*
* Available on ‘F53x/
’F53xA devices
Burst Mode
Logic
Timer 2 Overflow
19-to-1
AMUX
12-Bit
SAR
Selectable
Gain
VDD
GND
End of
Conversion
Interrupt
Figure 1.7. 12-Bit ADC Block Diagram
22
Timer 1 Overflow
CNVSTR Rising Edge
ADC
Temp
Sensor
AD0BUSY (W)
Start
Conversion
Rev. 1.4
ADC Data
Registers
16
Accumulator
Window Compare
Logic
Window
Compare
Interrupt
C8051F52x/F53x
1.6. Programmable Comparator
C8051F52x/F52xA/F53x/F53xA devices include a software-configurable voltage comparator with an input
multiplexer. The comparator offers programmable response time and hysteresis and an output that is
optionally available at the Port pins: a synchronous “latched” output (CP0). The comparator interrupt may
be generated on rising, falling, or both edges. When in IDLE or SUSPEND mode, these interrupts may be
used as a “wake-up” source for the processor. The Comparator may also be configured as a reset source.
A block diagram of the comparator is shown in Figure 1.8.
VDD
Port I/O
Pins
Multiplexer
Interrupt
Logic
+
D
-
SET
CLR
Q
Q
D
SET
CLR
Q
CP0
(synchronous output)
Q
(SYNCHRONIZER)
CP0A
(asynchronous output)
GND
Reset
Decision
Tree
Figure 1.8. Comparator Block Diagram
1.7. Voltage Regulator
C8051F52x/F52xA/F53x/F53xA devices include an on-chip low dropout voltage regulator (REG0). The
input to REG0 at the VREGIN pin can be as high as 5.25 V. The output can be selected by software to 2.1 or
2.6 V. When enabled, the output of REG0 powers the device and drives the VDD pin. The voltage regulator
can be used to power external devices connected to VDD.
1.8. Serial Port
The C8051F52x/F52xA/F53x/F53xA family includes a full-duplex UART with enhanced baud rate configuration, and an Enhanced SPI interface. Each of the serial buses is fully implemented in hardware and
makes extensive use of the CIP-51's interrupts, thus requiring very little CPU intervention.
Rev. 1.4
23
C8051F52x/F53x
1.9. Port Input/Output
C8051F52x/F52xA/F53x/F53xA devices include up to 16 I/O pins. Port pins are organized as two bytewide ports. The port pins behave like typical 8051 ports with a few enhancements. Each port pin can be
configured as a digital or analog I/O pin. Pins selected as digital I/O can be configured for push-pull or
open-drain operation. The “weak pullups” that are fixed on typical 8051 devices may be globally disabled
to save power.
The Digital Crossbar allows mapping of internal digital system resources to port I/O pins. On-chip counter/timers, serial buses, hardware interrupts, and other digital signals can be configured to appear on the
port pins using the Crossbar control registers. This allows the user to select the exact mix of general-purpose port I/O, digital, and analog resources needed for the application.
P0MASK, P0MATCH
P1MASK, P1MATCH
Registers
XBR0, XBR1,
PnSKIP Registers
PnMDOUT,
PnMDIN Registers
Priority
Decoder
Highest
Priority
2
UART
4
(Internal Digital Signals)
SPI
2
LIN
CP0
Outputs
8
7
T0, T1
(Port Latches)
P0
I/O
Cells
P1
I/O
Cells
2
8
P0
8
2
SYSCLK
PCA
Lowest
Priority
Digital
Crossbar
*Available in 'F53x/'F53xA
devices
(P0.0-P0.7)
8
P1
(P1.0-P1.7*)
Figure 1.9. Port I/O Functional Block Diagram
24
Rev. 1.4
P0.0
P0.7
P1.0*
P1.7*
C8051F52x/F53x
2. Electrical Characteristics
2.1. Absolute Maximum Ratings
Table 2.1. Absolute Maximum Ratings
Parameter
Conditions
Min
Typ
Max
Units
Ambient temperature under Bias
–55
—
135
°C
Storage Temperature
–65
—
150
°C
Voltage on VREGIN with Respect to GND
–0.3
—
5.5
V
Voltage on VDD with Respect to GND
–0.3
—
2.8
V
Voltage on XTAL1 with Respect to GND
–0.3
—
VREGIN + 0.3
V
Voltage on XTAL2 with Respect to GND
–0.3
—
VREGIN + 0.3
V
Voltage on any Port I/O Pin or RST with Respect to
GND
–0.3
—
VREGIN + 0.3
V
Maximum Output Current Sunk by any Port Pin
—
—
100
mA
Maximum Output Current Sourced by any Port Pin
—
—
100
mA
Maximum Total Current through VREGIN, and GND
—
—
500
mA
Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the devices at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
Rev. 1.4
25
C8051F52x/F53x
2.2. Electrical Characteristics
Table 2.2. Global DC Electrical Characteristics
–40 to +125 °C, 25 MHz System Clock unless otherwise specified. Typical values are given at 25 °C
Parameter
Min
Typ
Max
Units
Output Current < 1 mA
C8051F52x/53x
C8051F52xA/53xA
C8051F52x-C/53x-C
2.7
1.81
2.01
—
—
—
5.25
5.25
5.25
V
V
V
C8051F52x/53x
C8051F52xA/53xA
C8051F52x-C/53x-C
2.0
1.8
2.0
—
—
—
2.7
2.7
2.75
V
V
V
Core Supply RAM Data Retention
Voltage
—
1.5
—
SYSCLK (System Clock)2
0
—
25
MHz
–40
—
+125
°C
Supply Input Voltage (VREGIN)1
Digital Supply Voltage (VDD)
Conditions
Specified Operating Temperature Range
V
Digital Supply Current—CPU Active (Normal Mode, fetching instructions from Flash)
IDD3,4
IDD Frequency Sensitivity3,5
VDD = 2.1 V:
Clock = 32 kHz
Clock = 200 kHz
Clock = 1 MHz
Clock = 25 MHz
VDD = 2.6 V:
Clock = 32 kHz
Clock = 200 kHz
Clock = 1 MHz
Clock = 25 MHz
T = 25 °C:
VDD = 2.1 V, F < 12 MHz
VDD = 2.1 V, F > 12 MHz
VDD = 2.6 V, F < 12 MHz
VDD = 2.6 V, F > 12 MHz
—
—
—
—
13
60
0.28
5.1
—
—
—
9
µA
µA
mA
mA
—
—
—
—
22
105
0.5
7.3
—
—
—
13
µA
µA
mA
mA
—
—
—
—
0.276
0.140
0.424
0.184
—
—
—
—
mA/MHz
mA/MHz
mA/MHz
mA/MHz
Notes:
1.
2.
3.
4.
5.
For more information on VREGIN characteristics, see Table 2.6 on page 30.
SYSCLK must be at least 32 kHz to enable debugging.
Based on device characterization data; Not production tested.
Does not include internal oscillator or internal regulator supply current.
IDD can be estimated for frequencies <= 12 MHz by multiplying the frequency of interest by the frequency
sensitivity number for that range. When using these numbers to estimate IDD > 12 MHz, the estimate should be
the current at 25 MHz minus the difference in current indicated by the frequency sensitivity number. For
example: VDD = 2.6 V; F= 20 MHz, IDD = 7.3 mA – (25 MHz – 20 MHz) x 0.184 mA/MHz = 6.38 mA.
6. Idle IDD can be estimated for frequencies <= 1 MHz by multiplying the frequency of interest by the frequency
sensitivity number for that range. When using these numbers to estimate IDD > 1 MHz, the estimate should be
the current at 25 MHz minus the difference in current indicated by the frequency sensitivity number. For
example: VDD = 2.6 V; F= 5 MHz, Idle IDD = 3 mA – (25 MHz– 5 MHz) x 118 µA/MHz = 0.64 mA.
26
Rev. 1.4
C8051F52x/F53x
Table 2.2. Global DC Electrical Characteristics
–40 to +125 °C, 25 MHz System Clock unless otherwise specified. Typical values are given at 25 °C
Parameter
Conditions
Min
Typ
Max
Units
Digital Supply Current—CPU Inactive (Idle Mode, not fetching instructions from Flash)
Idle IDD3,4
Idle IDD Frequency Sensitivity3,6
Digital Supply Current3
(Stop or Suspend Mode)
VDD = 2.1 V:
Clock = 32 kHz
Clock = 200 kHz
Clock = 1 MHz
Clock = 25 MHz
VDD = 2.6 V:
Clock = 32 kHz
Clock = 200 kHz
Clock = 1 MHz
Clock = 25 MHz
T = 25 °C:
VDD = 2.1 V, F < 1 MHz
VDD = 2.1 V, F > 1 MHz
VDD = 2.6 V, F < 1 MHz
VDD = 2.6 V, F > 1 MHz
Oscillator not running,
VDD Monitor Disabled.
T = 25 °C
T = 60 °C
T = 125 °C
—
—
—
—
8
22
0.09
2.2
—
—
—
5
µA
µA
mA
mA
—
—
—
—
9
30
0.13
3
—
—
—
6.5
µA
µA
mA
mA
—
—
—
—
90
90
118
118
—
—
—
—
µA/MHz
µA/MHz
µA/MHz
µA/MHz
—
—
—
2
3
50
—
—
—
µA
µA
µA
Notes:
1.
2.
3.
4.
5.
For more information on VREGIN characteristics, see Table 2.6 on page 30.
SYSCLK must be at least 32 kHz to enable debugging.
Based on device characterization data; Not production tested.
Does not include internal oscillator or internal regulator supply current.
IDD can be estimated for frequencies <= 12 MHz by multiplying the frequency of interest by the frequency
sensitivity number for that range. When using these numbers to estimate IDD > 12 MHz, the estimate should be
the current at 25 MHz minus the difference in current indicated by the frequency sensitivity number. For
example: VDD = 2.6 V; F= 20 MHz, IDD = 7.3 mA – (25 MHz – 20 MHz) x 0.184 mA/MHz = 6.38 mA.
6. Idle IDD can be estimated for frequencies <= 1 MHz by multiplying the frequency of interest by the frequency
sensitivity number for that range. When using these numbers to estimate IDD > 1 MHz, the estimate should be
the current at 25 MHz minus the difference in current indicated by the frequency sensitivity number. For
example: VDD = 2.6 V; F= 5 MHz, Idle IDD = 3 mA – (25 MHz– 5 MHz) x 118 µA/MHz = 0.64 mA.
Rev. 1.4
27
C8051F52x/F53x
Table 2.3. ADC0 Electrical Characteristics
VDD = 2.1 V, VREF = 1.5 V (REFSL=0), –40 to +125 °C unless otherwise specified.
Parameter
Conditions
Min
Typ
Max
Units
DC Accuracy
Resolution
12
bits
Integral Nonlinearity
—
—
±3
LSB
Differential Nonlinearity
Guaranteed Monotonic
—
—
±1
LSB
1
–10
±1
+10
LSB
Offset Error
Full Scale Error
–20
±1
+20
LSB
Dynamic Performance (10 kHz sine-wave Single-ended input, 0 to 1 dB below Full Scale, 200 ksps)
Signal-to-Noise Plus Distortion
60
66
—
dB
th
—
74
—
dB
Total Harmonic Distortion
Up to the 5 harmonic
Spurious-Free Dynamic Range
—
88
—
dB
Conversion Rate
SAR Conversion Clock
Burst Mode Oscillator
Conversion Time in SAR Clocks2
Track/Hold Acquisition Time3,6
Throughput Rate4
—
—
—
1
—
—
—
13
—
—
3
27
—
—
200
MHz
MHz
clocks
µs
ksps
0
0
—
—
VREF
VREF / n
V
0
—
—
—
24
1.5
VREGIN
—
—
V
pF
k
—
—
—
—
1050
930
5
1
1400
—
—
—
µA
µA
µs
mV/V
Analog Inputs
ADC Input Voltage Range5
gain = 1.0 (default)
gain = n
Absolute Pin Voltage wrt to GND
Sampling Capacitance
Input Multiplexer Impedance
Power Specifications
Power Supply Current (from VDD)
Burst Mode (Idle)
Power-on Time
Power Supply Rejection
Operating Mode, 200 ksps
Notes:
1. Represents one standard deviation from the mean. Offset and full-scale error can be removed through
calibration.
2. An additional 2 FCLK cycles are required to start and complete a conversion.
3. Additional tracking time may be required depending on the output impedance connected to the ADC input.
See Section “4.3.6. Settling Time Requirements” on page 60.
4. An increase in tracking time will decrease the ADC throughput.
5. See Section “4.4. Selectable Gain” on page 60 for more information about setting the gain.
6. Additional tracking time might be needed ifVDD < 2.0 V; See Section “11.2.1. VDD Monitor Thresholds and
Minimum VDD” on page 108 for minimum VDD requirements.
28
Rev. 1.4
C8051F52x/F53x
Table 2.4. Temperature Sensor Electrical Characteristics
VDD = 2.1 V, VREF = 1.5 V (REFSL=0), –40 to +125 °C unless otherwise specified.
Parameter
Min
Typ
Max
Units
Linearity1
—
0.1
—
°C
1
—
3.33
—
mV/°C
—
±100
—
µV/°C
Temp = 0 °C
—
890
—
mV
Temp = 0 °C
—
±15
—
mV
Tracking Time
12
—
—
µs
Power Supply Current
—
17
—
µA
Conditions
Min
Typ
Max
Units
IDD  1 mA; No load on VREF pin and all
other GPIO pins.
25 °C ambient (REFLV = 0)
25 °C ambient (REFLV = 1), VDD = 2.6 V
1.45
2.15
1.5
2.2
1.55
2.25
V
VREF Short-Circuit Current
—
2.5
—
mA
VREF Temperature Coefficient
—
33
—
ppm/°C
Gain
Gain
Conditions
Error2
Offset
1
Offset Error
2
Notes:
1. Includes ADC offset, gain, and linearity variations.
2. Represents one standard deviation from the mean.
Table 2.5. Voltage Reference Electrical Characteristics
VDD = 2.1 V; –40 to +125 °C unless otherwise specified.
Parameter
Internal Reference (REFBE = 1)
Output Voltage
Load Regulation
Load = 0 to 200 µA to GND
—
10
—
ppm/µA
VREF Turn-on Time 1
4.7 µF, 0.1 µF bypass
—
21
—
ms
VREF Turn-on Time 2
0.1 µF bypass
—
230
—
µs
—
2.1
—
mV/V
0
—
VDD
V
Sample Rate = 200 ksps; VREF = 1.5 V
—
2.4
—
µA
BIASE = 1
—
22
—
µA
—
35
—
µA
Power Supply Rejection
External Reference (REFBE = 0)
Input Voltage Range
Input Current
Bias Generators
ADC Bias Generator
Power Consumption (Internal)
Rev. 1.4
29
C8051F52x/F53x
Table 2.6. Voltage Regulator Electrical Specifications
VDD = 2.1 or 2.6 V; –40 to +125 °C unless otherwise specified.
Parameter
Input Voltage Range (VREGIN)
Dropout Voltage (VDO)
Output Voltage (VDD)
Bias Current
Dropout Indicator Detection
Threshold
Output Voltage Temperature
Coefficient
VREG Settling Time
Conditions
C8051F52x/53x
C8051F52xA/53xA
VDD connected to VREGIN
VDD not connected to VREGIN
C8051F52x-C/53x-C
VDD connected to VREGIN
VDD not connected to VREGIN
Output Current = 1-50 mA
Output Current = 1 to 50 mA
REG0MD = 0
REG0MD = 1
2.1 V operation 
(REG0MD = 0; T = 25 °C)
2.6 V operation 
(REG0MD = 1; T = 25 °C)
50 mA load with VREGIN = 2.4 V and
VDD load capacitor of 4.8 µF
Min
Typ
Max
Units
1
2.7
—
5.25
V
1.8
2.22
—
—
2.7
5.25
2.0
2.22
—
—
—
10
2.75
5.25
—
2.0
2.5
—
2.1
2.6
1
2.25
2.75
5
—
1
5
—
75
—
mV
—
0.25
—
mV/ºC
—
250
—
µs
Notes:
1. The minimum input voltage is 2.7 V or VDD + VDO(max load), whichever is greater.
2. The minimum input voltage is 2.2 V or VDD + VDO(max load), whichever is greater.
30
Rev. 1.4
mV/mA
V
µA
C8051F52x/F53x
Table 2.7. Comparator Electrical Characteristics
VREGIN = 2.7–5.25 V, –40 to +125 °C unless otherwise noted. 
All specifications apply to both Comparator0 and Comparator1 unless otherwise noted.
Parameter
Conditions
Min
Typ
Max
Units
Response Time:
Mode 0, Vcm1 = 1.5 V
CP0+ – CP0– = 100 mV
—
780
—
ns
CP0+ – CP0– = –100 mV
—
980
—
ns
Response Time:
Mode 1, Vcm1 = 1.5 V
CP0+ – CP0– = 100 mV
—
850
—
ns
CP0+ – CP0– = –100 mV
—
1120
—
ns
Response Time:
Mode 2, Vcm1 = 1.5 V
CP0+ – CP0– = 100 mV
—
870
—
ns
CP0+ – CP0– = –100 mV
—
1310
—
ns
Response Time:
Mode 3, Vcm1 = 1.5 V
CP0+ – CP0– = 100 mV
—
1980
—
ns
CP0+ – CP0– = –100 mV
—
4770
—
ns
—
3
9
mV/V
0.7
2
mV
Common-Mode Rejection
Ratio
Positive Hysteresis 1
CP0HYP1-0 = 00
—
Positive Hysteresis 2
CP0HYP1-0 = 01
2
5
10
mV
Positive Hysteresis 3
CP0HYP1-0 = 10
5
10
20
mV
Positive Hysteresis 4
CP0HYP1-0 = 11
13
20
40
mV
Negative Hysteresis 1
CP0HYN1-0 = 00
—
0.7
2
mV
Negative Hysteresis 2
CP0HYN1-0 = 01
2
5
10
mV
Negative Hysteresis 3
CP0HYN1-0 = 10
5
10
20
mV
Negative Hysteresis 4
CP0HYN1-0 = 11
13
20
40
mV
–0.25
—
VDD + 0.25
V
Inverting or Non-Inverting
Input Voltage Range2
Input Capacitance2
—
4
—
pF
Input Bias Current
—
0.5
—
nA
–15
—
15
mV
—
1.5
—
k
Power Supply Rejection2
—
0.2
4
mV/V
Power-up Time
—
2.3
—
µs
—
6
30
µA
Input Offset Voltage
Input Impedance
Power Supply
Mode 0
Supply Current at DC
Mode 1
—
3
15
µA
Mode 2
—
2
7.5
µA
Mode 3
—
0.3
3.8
µA
Notes:
1. Vcm is the common-mode voltage on CP0+ and CP0–.
2. Guaranteed by design and/or characterization.
Rev. 1.4
31
C8051F52x/F53x
Table 2.8. Reset Electrical Characteristics
–40 to +125 °C unless otherwise specified.
Parameter
RST Output Low Voltage
Conditions
IOL = 8.5 mA, VDD =
2.1 V
RST Input High Voltage
RST Input Low Voltage
Min
Typ
Max
Units
—
—
0.8
V
0.7 x
VREGIN
—
—
V
—
—
0.3 x
VREGIN
V
—
—
—
—
330
160
130
80
—
—
—
—
k
k
k
k
RST Input Pullup Impedance
VREGIN = 1.8 V
VREGIN = 2.7 V
VREGIN = 3.3 V
VREGIN = 5 V
Missing Clock Detector Timeout
Time from last system
clock rising edge to reset
initiation
100
350
650
µs
Delay between release
of any reset source and
code execution at location 0x0000
—
—
350
µs
10
—
—
µs
Reset Time Delay (TPORDelay)1
Minimum RST Low Time to Generate a
System Reset
VDD Monitor (VDDMON0)
Low Threshold (VRST-LOW)1,2,3
C8051F52x/53x
C8051F52xA/53xA
C8051F52x-C/53x-C
1.8
1.65
1.65
1.9
1.75
1.75
2.0
1.8
1.8
V
V
V
High Threshold (VRST-HIGH)3
C8051F52x/53x
C8051F52xA/53xA
C8051F52x-C/53x-C
2.1
2.25
2.25
2.2
2.3
2.3
2.3
2.4
2.45
V
V
V
—
83
—
µs
—
1
2
µA
Turn-on Time
Supply Current
VDD = 2.1 V
Level-Sensitive VDD Monitor (VDDMON1)
1
Threshold (VRST1)1,2,3
C8051F52x-C/53x-C
1.6
1.75
1.9
V
Supply Current
C8051F52x-C/53x-C
—
3
6
µA
Notes:
1. Refer to Section “20. Device Specific Behavior” on page 210.
2. The POR threshold (VRST) is VRST-LOW or VRST1, whichever is higher.
3. The VRSTthreshold for power fail / brownout is the higher of VDDMON0 and VDDMON1 thresholds, if both are
enabled.
32
Rev. 1.4
C8051F52x/F53x
Table 2.9. Flash Electrical Characteristics
VDD = 1.8 to 2.75 V; –40 to +125 ºC unless otherwise specified
Parameter
Conditions
Min
Typ
Max
Units
Flash Size
’F520/0A/1/1A and ’F530/0A/1/1A
’F523/3A/4/4A and ’F533/3A/4/4A
’F526/6A/7/7A and ’F536/6A/7/7A
7680
4096
2048
—
—
bytes
Endurance2
VDD  VRST-HIGH1
20 k
150 k
—
Erase/Write
27
32
38
ms
57
65
74
µs
VRST-HIGH1
—
—
V
Erase Cycle Time
Write Cycle Time
VDD
Write/Erase Operations
Notes:
1. See Table 2.8 on page 32 for the VRST-HIGH specification.
2. For –I (industrial Grade) parts, flash should be programmed (erase/write) at a minimum temperature of 0 °C
for reliable flash operation across the entire temperature range of –40 to +125 °C. This minimum
programming temperature does not apply to –A (Automotive Grade) parts.
Table 2.10. Port I/O DC Electrical Characteristics
VREGIN = 2.7 to 5.25 V, –40 to +125 °C unless otherwise specified
Parameters
Conditions
Min
Output High IOH = –3 mA, Port I/O push-pull
Voltage
IOH = –10 µA, Port I/O push-pull
IOH = –10 mA, Port I/O push-pull
Typ
—
VREGIN – 0.4
VREGIN – 0.02
—
—
VREGIN – 0.7
Output Low VREGIN = 2.7 V:
Voltage
IOL = 70 µA
IOL = 8.5 mA
VREGIN = 5.25 V:
IOL = 70 µA
IOL = 8.5 mA
Max
Units
—
—
—
V
—
—
—
—
45
550
—
—
—
—
40
400
Input High
Voltage
VREGIN x 0.7
—
—
V
Input Low 
Voltage
—
—
VREGIN x
0.3
V
Weak Pullup Off
—
—
±2
C8051F52xA/53xA:
Weak Pullup On, VIN = 0 V; VREGIN = 1.8 V
—
5
15
C8051F52x/52xA/53x/53xA:
Weak Pullup On, VIN = 0 V; VREGIN = 2.7 V
Weak Pullup On, VIN = 0 V; VREGIN = 5.25 V
—
—
20
65
50
115
Input
Leakage 
Current
Rev. 1.4
mV
µA
33
C8051F52x/F53x
Table 2.11. Internal Oscillator Electrical Characteristics
VDD = 1.8 to 2.75 V, –40 to +125 °C unless otherwise specified; Using factory-calibrated settings.
Parameter
Conditions
1
Oscillator Frequency
Min
Typ
Max
Units
3
24.5 + 0.5%
MHz
IFCN = 111b
VDD > VREGMIN2
24.5 – 0.5%
24.5
IFCN = 111b
VDD < VREGMIN2
24.5 – 1.0%
24.53
24.5 + 1.0%
Oscillator On
OSCICN[7:6] = 11b
—
800
1100
µA
—
—
—
67
77
117
—
—
300
µA
µA
µA
T = 25 °C
T = 85 °C
T = 125 °C
—
—
—
2
3
50
—
—
—
µA
µA
µA
OSCICN[7:6] = 00b
ZTCEN = 04
—
—
1
µs
OSCICN[7:6] = 00b
ZTCEN = 1
—
5
—
Instruction
Cycles
Constant Temperature
—
0.10
—
%/V
Constant Supply
TC1
TC2
—
—
5.0
–0.65
—
—
ppm/°C
ppm/°C2
Oscillator Suspend
OSCICN[7:6] = 00b
ZTCEN = 1
Oscillator Supply Current
(from VDD)
T = 25 °C
T = 85 °C
T = 125 °C
Oscillator Suspend
OSCICN[7:6] = 00b
ZTCEN = 0
Wake-Up Time From Suspend
Power Supply Sensitivity
Temperature
Sensitivity5
Notes:
1. See Section “11.2.1. VDD Monitor Thresholds and Minimum VDD” on page 108 for minimum VDD
requirements.
2. VREGMIN is the minimum output of the voltage regulator for its low setting (REG0CN: REG0MD = 0b). See
Table 2.6, “Voltage Regulator Electrical Specifications,” on page 30.
3. This is the average frequency across the operating temperature range.
4. See “20.7. Internal Oscillator Suspend Mode” on page 212 for ZTCEN setting in older silicon revisions.
5. Use temperature coefficients TC1 and TC2 to calculate the new internal oscillator frequency using the
following equation:
f(T) = f0 x (1 + TC1 x (T – T0) + TC2 x (T – T0)2)
where f0 is the internal oscillator frequency at 25 °C and T0 is 25 °C.
34
Rev. 1.4
C8051F52x/F53x
3. Pinout and Package Definitions
RST/C2CK
1
10
P0.1/C2D
P0.0/VREF
2
9
P0.2/XTAL1
GND
3
8
P0.3/XTAL2
VDD
4
7
P0.4/TX
VREGIN
5
6
P0.5/CNVSTR/RX
RST/C2CK
1
10
P0.1/C2D
P0.0/VREF
2
9
P0.2/XTAL1
GND
3
8
P0.3/XTAL2/TX
VDD
4
7
P0.4/RX
VREGIN
5
6
P0.5/CNVSTR
C8051F52xA/52x-C
Top View
GND
C8051F52x
Top View
GND
Figure 3.1. DFN-10 Pinout Diagram (Top View)
Rev. 1.4
35
C8051F52x/F53x
Table 3.1. Pin Definitions for the C8051F52x and C8051F52xA (DFN 10)
Name
Pin Numbers
Type
Description
D I/O
Device Reset. Open-drain output of internal POR or VDD monitor.
An external source can initiate a system reset by driving this pin
low for at least the minimum RST low time to generate a system
reset, as defined in Table 2.8 on page 32. A 1 k pullup to VREGIN is recommended. See Reset Sources Section for a complete
description.
‘F52xA ‘F52x
‘F52x-C
RST/
1
1
C2CK
D I/O
Clock signal for the C2 Debug Interface.
P0.0/
2
2
D I/O or Port 0.0. See Port I/O Section for a complete description.
A In
A O or
D In
VREF
External VREF Input. See VREF Section.
GND
3
3
Ground.
VDD
4
4
Core Supply Voltage.
VREGIN
5
5
On-Chip Voltage Regulator Input.
P0.5/RX*/
6
—
D In
CNVSTR
P0.5/
D I/O or Port 0.5. See Port I/O Section for a complete description.
A In
—
6
D I/O or Port 0.5. See Port I/O Section for a complete description.
A In
D In
CNVSTR
External Converter start input for the ADC0, see Section “4. 12Bit ADC (ADC0)” on page 52 for a complete description.
External Converter start input for the ADC0, see Section “4. 12Bit ADC (ADC0)” on page 52 for a complete description.
P0.4/TX*
7
—
D I/O or Port 0.4. See Port I/O Section for a complete description.
A In
P0.4/RX*
—
7
D I/O or Port 0.4. See Port I/O Section for a complete description.
A In
P0.3
8
—
D I/O or Port 0.3. See Port I/O Section for a complete description.
A In
XTAL2
D I/O
External Clock Output. For an external crystal or resonator, this
pin is the excitation driver. This pin is the external clock input for
CMOS, capacitor, or RC oscillator configurations. See Section
“14. Oscillators” on page 135.
Note: Please refer to Section “20. Device Specific Behavior” on page 210.
36
Rev. 1.4
C8051F52x/F53x
Table 3.1. Pin Definitions for the C8051F52x and C8051F52xA (DFN 10) (Continued)
Name
Pin Numbers
Type
Description
‘F52xA ‘F52x
‘F52x-C
P0.3/TX*/
—
8
D I/O
XTAL2
P0.2
9
9
XTAL1
P0.1/
C2D
D I/O or Port 0.3. See Port I/O Section for a complete description.
A In
D I/O or Port 0.2. See Port I/O Section for a complete description.
A In
10
10
External Clock Output. For an external crystal or resonator, this
pin is the excitation driver. This pin is the external clock input for
CMOS, capacitor, or RC oscillator configurations. See Section
“14. Oscillators” on page 135.
External Clock Input. This pin is the external oscillator return for a
crystal or resonator. Section “14. Oscillators” on page 135.
D I/O or Port 0.1. See Port I/O Section for a complete description.
A In
D I/O
Bi-directional data signal for the C2 Debug Interface
Note: Please refer to Section “20. Device Specific Behavior” on page 210.
Rev. 1.4
37
C8051F52x/F53x
Figure 3.2. DFN-10 Package Diagram
Table 3.2. DFN-10 Package Diagram Dimensions
Dimension
Min
Nom
Max
A
A1
b
D
D2
e
E
E2
L
L1
aaa
bbb
ddd
eee
0.80
0.00
0.18
0.90
0.02
0.25
3.00 BSC.
1.65
0.50 BSC.
3.00 BSC.
2.38
0.40
—
—
—
—
—
1.00
0.05
0.30
1.50
2.23
0.30
0.00
—
—
—
—
1.80
2.53
0.50
0.15
0.15
0.15
0.05
0.08
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC outline MO-220, variation VEED except for
custom features D2, E2, and L, which are toleranced per supplier designation.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification
for Small Body Components.
38
Rev. 1.4
C8051F52x/F53x
Figure 3.3. DFN-10 Landing Diagram
Table 3.3. DFN-10 Landing Diagram Dimensions
Dimension
Min
Max
C1
E
X1
X2
Y1
Y2
2.90
3.00
0.50 BSC.
0.20
1.70
0.70
2.45
0.30
1.80
0.80
2.55
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This land pattern design is based on the IPC-7351 guidelines.
Solder Mask Design
3. All metal pads are to be non-solder mask defined (NSMD). Clearance
between the solder mask and the metal pad is to be 60 µm minimum, all the
way around the pad.
Stencil Design
4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls
should be used to assure good solder paste release.
5. The stencil thickness should be 0.125 mm (5 mils).
6. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter
pads.
7. A 4x1 array of 1.60 x 0.45 mm openings on 0.65 mm pitch should be used for
the center ground pad.
Card Assembly
8. A No-Clean, Type-3 solder paste is recommended.
9. The recommended card reflow profile is per the JEDEC/IPC J-STD-020
specification for Small Body Components.
Rev. 1.4
39
C8051F52x/F53x
20
P0.3
P0.2
1
20
P0.3/TX
P0.1
2
19
P0.4/TX
P0.1
2
19
P0.4/RX
RST/C2CK
3
18
P0.5/RX
RST/C2CK
3
18
P0.5
P0.0/VREF
4
17
P0.6/C2D
P0.0/VREF
4
17
P0.6/C2D
GND
5
16
P0.7/XTAL1
GND
5
16
P0.7/XTAL1
VDD
6
15
P1.0/XTAL2
VDD
6
15
P1.0/XTAL2
VREGIN
7
14
P1.1
VREGIN
7
14
P1.1
P1.7
8
13
P1.2/CNVSTR
P1.7
8
13
P1.2/CNVSTR
P1.6
9
12
P1.3
P1.6
9
12
P1.3
P1.5
10
11
P1.4
P1.5
10
11
P1.4
C8051F53x
1
C8051F53xA/53x-C
P0.2
Figure 3.4. TSSOP-20 Pinout Diagram (Top View)
Table 3.4. Pin Definitions for the C8051F53x and C805153xA (TSSOP 20)
Name
Pin Numbers
Type
Description
‘F53xA ‘F53x
‘F53x-C
P0.2
1
1
D I/O or Port 0.2. See Port I/O Section for a complete description.
A In
P0.1
2
2
D I/O or Port 0.1. See Port I/O Section for a complete description.
A In
RST/
3
3
C2CK
D I/O
D I/O
Device Reset. Open-drain output of internal POR or VDD monitor.
An external source can initiate a system reset by driving this pin
low for at least the minimum RST low time to generate a system
reset, as defined in Table 2.8 on page 32. A 1 k pullup to VREGIN is recommended. See Reset Sources Section for a complete
description.
Clock signal for the C2 Debug Interface.
P0.0/
4
4
D I/O or Port 0.0. See Port I/O Section for a complete description.
A In
A O or
D In
VREF
External VREF Input. See VREF Section.
GND
5
5
Ground.
VDD
6
6
Core Supply Voltage.
*Note: Please refer to Section “20. Device Specific Behavior” on page 210.
40
Rev. 1.4
C8051F52x/F53x
Table 3.4. Pin Definitions for the C8051F53x and C805153xA (TSSOP 20) (Continued)
Name
Pin Numbers
Type
Description
‘F53xA ‘F53x
‘F53x-C
VREGIN
7
7
On-Chip Voltage Regulator Input.
P1.7
8
8
D I/O or Port 1.7. See Port I/O Section for a complete description.
A In
P1.6
9
9
D I/O or Port 1.6. See Port I/O Section for a complete description.
A In
P1.5
10
10
D I/O or Port 1.5. See Port I/O Section for a complete description.
A In
P1.4
11
11
D I/O or Port 1.4. See Port I/O Section for a complete description.
A In
P1.3
12
12
D I/O or Port 1.3. See Port I/O Section for a complete description.
A In
P1.2/
13
13
D I/O or Port 1.2. See Port I/O Section for a complete description.
A In
D In
CNVSTR
External Converter start input for the ADC0, see Section “4. 12Bit ADC (ADC0)” on page 52 for a complete description.
P1.1
14
14
D I/O or Port 1.1. See Port I/O Section for a complete description.
A In
P1.0/
15
15
D I/O or Port 1.0. See Port I/O Section for a complete description.
A In
D I/O
XTAL2
P0.7/
16
16
D I/O or Port 0.7. See Port I/O Section for a complete description.
A In
External Clock Input. This pin is the external oscillator return for
A In
a crystal or resonator. Section “14. Oscillators” on page 135.
17
17
D I/O or Port 0.6. See Port I/O Section for a complete description.
A In
XTAL1
P0.6/
External Clock Output. For an external crystal or resonator, this
pin is the excitation driver. This pin is the external clock input for
CMOS, capacitor, or RC oscillator configurations. See Section
“14. Oscillators” on page 135.
D I/O
C2D
Bi-directional data signal for the C2 Debug Interface.
P0.5/RX*
18
—
D I/O or Port 0.5. See Port I/O Section for a complete description.
A In
P0.5
—
18
D I/O or Port 0.5. See Port I/O Section for a complete description.
A In
*Note: Please refer to Section “20. Device Specific Behavior” on page 210.
Rev. 1.4
41
C8051F52x/F53x
Table 3.4. Pin Definitions for the C8051F53x and C805153xA (TSSOP 20) (Continued)
Name
Pin Numbers
Type
Description
‘F53xA ‘F53x
‘F53x-C
P0.4/TX*
19
—
D I/O or Port 0.4. See Port I/O Section for a complete description.
A In
P0.4/RX*
—
19
D I/O or Port 0.4. See Port I/O Section for a complete description.
A In
P0.3
20
—
D I/O or Port 0.3. See Port I/O Section for a complete description.
A In
P0.3/TX*
—
20
D I/O or Port 0.3. See Port I/O Section for a complete description.
A In
*Note: Please refer to Section “20. Device Specific Behavior” on page 210.
42
Rev. 1.4
C8051F52x/F53x

Figure 3.5. TSSOP-20 Package Diagram
Table 3.5. TSSOP-20 Package Diagram Dimensions
Symbol
Min
A
A1
A2
b
c
D
e
E
E1
L
1
aaa
bbb
ddd
—
0.05
0.80
0.19
0.09
6.40
4.30
0.45
0°
Nom
—
—
1.00
—
—
6.50
0.65 BSC.
6.40 BSC.
4.40
0.60
—
0.10
0.10
0.20
Max
1.20
0.15
1.05
0.30
0.20
6.60
4.50
0.75
8°
Notes:
1. All dimensions shown are in millimeters (mm).
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC outline MO-153, variation AC.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020
specification for Small Body Components.
Rev. 1.4
43
C8051F52x/F53x
Figure 3.6. TSSOP-20 Landing Diagram
Table 3.6. TSSOP-20 Landing Diagram Dimensions
Symbol
Min
C
E
X1
Y1
5.80
Max
5.90
0.65 BSC.
0.35
1.35
0.45
1.45
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This land pattern design is based on the IPC-7351 guidelines.
Solder Mask Design
3. All metal pads are to be non-solder mask defined (NSMD). Clearance
between the solder mask and the metal pad is to be 60 µm minimum,
all the way around the pad.
Stencil Design
4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal
walls should be used to assure good solder paste release.
5. The stencil thickness should be 0.125 mm (5 mils).
6. The ratio of stencil aperture to land pad size should be 1:1 for all
perimeter pads.
Card Assembly
7. A No-Clean, Type-3 solder paste is recommended.
8. The recommended card reflow profile is per the JEDEC/IPC J-STD020 specification for Small Body Components.
44
Rev. 1.4
P0.1
P0.2
P0.3
P0.4/TX
P0.5/RX
20
19
18
17
16
C8051F52x/F53x
RST/C2CK
1
15
P0.6/C2D
P0.0/VREF
2
14
P0.7/XTAL1
GND
3
13
P1.0/XTAL2
VDD
4
12
P1.1
VREGIN
5
11
P1.2/CNVSTR
RST/C2CK
1
15
P0.6/C2D
P0.0/VREF
2
14
P0.7/XTAL1
GND
3
13
P1.0/XTAL2
VDD
4
12
P1.1
VREGIN
5
11
P1.2/CNVSTR
C8051F53xA/53x-C
Top View
10
P1.3
P0.5
16
9
P1.4
P0.4/RX
17
8
P1.5
P0.3/TX
18
7
P1.6
P0.2
19
6
P0.1
20
P1.7
GND
C8051F53x
Top View
8
9
10
P1.4
P1.3
7
P1.6
P1.5
6
P1.7
GND
Figure 3.7. QFN-20 Pinout Diagram (Top View)
Rev. 1.4
45
C8051F52x/F53x
Table 3.7. Pin Definitions for the C8051F53x and C805153xA (QFN 20)
Name
Pin Numbers
Type
Description
D I/O
Device Reset. Open-drain output of internal POR or VDD monitor.
An external source can initiate a system reset by driving this pin
low for at least the minimum RST low time to generate a system
reset, as defined in Table 2.8 on page 32. A 1 k pullup to VREGIN is recommended. See Reset Sources Section for a complete
description.
‘F53xA ‘F53x
‘F53x-C
RST/
1
1
C2CK
D I/O
Clock signal for the C2 Debug Interface.
P0.0/
2
2
D I/O or Port 0.0. See Port I/O Section for a complete description.
A In
A O or
D In
VREF
External VREF Input. See VREF Section.
GND
3
3
Ground.
VDD
4
4
Core Supply Voltage.
VREGIN
5
5
On-Chip Voltage Regulator Input.
P1.7
6
6
D I/O or Port 1.7. See Port I/O Section for a complete description.
A In
P1.6
7
7
D I/O or Port 1.6. See Port I/O Section for a complete description.
A In
P1.5
8
8
D I/O or Port 1.5. See Port I/O Section for a complete description.
A In
P1.4
9
9
D I/O or Port 1.4. See Port I/O Section for a complete description.
A In
P1.3
10
10
D I/O or Port 1.3. See Port I/O Section for a complete description.
A In
P1.2/
11
11
D I/O or Port 1.2. See Port I/O Section for a complete description.
A In
D In
CNVSTR
P1.1
12
12
External Converter start input for the ADC0, see Section “4. 12Bit ADC (ADC0)” on page 52 for a complete description.
D I/O or Port 1.1. See Port I/O Section for a complete description.
A In
Note: Please refer to Section “20. Device Specific Behavior” on page 210.
46
Rev. 1.4
C8051F52x/F53x
Table 3.7. Pin Definitions for the C8051F53x and C805153xA (QFN 20) (Continued)
Name
Pin Numbers
Type
Description
‘F53xA ‘F53x
‘F53x-C
P1.0/
13
13
D I/O
XTAL2
P0.7/
14
14
XTAL1
P0.6/
D I/O or Port 1.0. See Port I/O Section for a complete description.
A In
D I/O or Port 0.7. See Port I/O Section for a complete description.
A In
15
15
External Clock Input. This pin is the external oscillator return for
a crystal or resonator. See Oscillator Section.
D I/O or Port 0.6. See Port I/O Section for a complete description.
A In
D I/O
C2D
External Clock Output. For an external crystal or resonator, this
pin is the excitation driver. This pin is the external clock input for
CMOS, capacitor, or RC oscillator configurations. Section
“14. Oscillators” on page 135.
Bi-directional data signal for the C2 Debug Interface.
P0.5/RX*
16
—
D I/O or Port 0.5. See Port I/O Section for a complete description.
A In
P0.5
—
16
D I/O or Port 0.5. See Port I/O Section for a complete description.
A In
P0.4/TX*
17
—
D I/O or Port 0.4. See Port I/O Section for a complete description.
A In
P0.4/RX*
—
17
D I/O or Port 0.4. See Port I/O Section for a complete description.
A In
P0.3
18
—
D I/O or Port 0.3. See Port I/O Section for a complete description.
A In
P0.3/TX*
—
18
D I/O or Port 0.3. See Port I/O Section for a complete description.
A In
P0.2
19
19
D I/O or Port 0.2. See Port I/O Section for a complete description.
A In
P0.1
20
20
D I/O or Port 0.1. See Port I/O Section for a complete description.
A In
Note: Please refer to Section “20. Device Specific Behavior” on page 210.
Rev. 1.4
47
C8051F52x/F53x
Figure 3.8. QFN-20 Package Diagram*
*Note: The Package Dimensions are given in Table 3.8, “QFN-20 Package Diagram Dimensions,” on page 49.
48
Rev. 1.4
C8051F52x/F53x
Table 3.8. QFN-20 Package Diagram Dimensions
Dimension
MIN
NOM
MAX
A
A1
b
D
D2
e
E
E2
L
L1
aaa
bbb
ddd
eee
Z
Y
0.80
0.00
0.18
0.90
0.02
0.25
4.00 BSC.
2.70
0.50 BSC.
4.00 BSC.
2.70
0.40
—
—
—
—
—
0.43
0.18
1.00
0.05
0.30
2.55
2.55
0.30
0.00
—
—
—
—
—
—
2.85
2.85
0.50
0.15
0.15
0.10
0.05
0.08
—
—
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC outline MO-220, variation VGGD except for
custom features D2, E2, Z, Y, L, and L1, which are toleranced per supplier
designation.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification
for Small Body Components.
Rev. 1.4
49
C8051F52x/F53x
Figure 3.9. QFN-20 Landing Diagram*
Note: The Landing Dimensions are given in Table 3.9, “QFN-20 Landing Diagram Dimensions,” on page 51.
50
Rev. 1.4
C8051F52x/F53x
Table 3.9. QFN-20 Landing Diagram Dimensions
Symbol
Min
Max
C1
C2
E
X1
X2
Y1
Y2
3.90
3.90
4.00
4.00
0.50 BSC.
0.20
2.75
0.65
2.75
0.30
2.85
0.75
2.85
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise
noted.
2. This land pattern design is based on the IPC-7351 guidelines.
Solder Mask Design
3. All metal pads are to be non-solder mask defined (NSMD).
Clearance between the solder mask and the metal pad is to be
60 µm minimum, all the way around the pad.
Stencil Design
4. A stainless steel, laser-cut and electro-polished stencil with
trapezoidal walls should be used to assure good solder paste
release.
5. The stencil thickness should be 0.125 mm (5 mils).
6. The ratio of stencil aperture to land pad size should be 1:1 for all
perimeter pads.
7. A 2x2 array of 1.10 x 1.10 mm openings on 1.30 mm pitch should be
used for the center ground pad.
Card Assembly
8. A No-Clean, Type-3 solder paste is recommended.
9. The recommended card reflow profile is per the JEDEC/IPC J-STD020 specification for Small Body Components.
Rev. 1.4
51
C8051F52x/F53x
4. 12-Bit ADC (ADC0)
ADC0TK
ADC0CN
AD0PWR3
AD0PWR2
AD0PWR1
AD0PWR0
AD0TM1
AD0TM0
AD0TK1
AD0TK0
AD0EN
BURSTEN
AD0INT
AD0BUSY
AD0WINT
AD0LJST
AD0CM1
AD0CM0
The ADC0 on the C8051F52x/F52xA/F53x/F53xA Family consists of an analog multiplexer (AMUX0) with
16/6 total input selections, and a 200 ksps, 12-bit successive-approximation-register (SAR) ADC with integrated track-and-hold, programmable window detector, programmable gain, and hardware accumulator.
The ADC0 subsystem has a special Burst Mode which can automatically enable ADC0, capture and accumulate samples, then place ADC0 in a low power shutdown mode without CPU intervention. The AMUX0,
data conversion modes, and window detector are all configurable under software control via the Special
Function Registers shown in Figure 4.1. ADC0 inputs are single-ended and may be configured to measure
P0.0-P1.7, the Temperature Sensor output, VDD, or GND with respect to GND. The voltage reference for
the ADC is selected as described in Section “5. Voltage Reference” on page 72. ADC0 is enabled when
the AD0EN bit in the ADC0 Control register (ADC0CN) is set to logic 1, or when performing conversions in
Burst Mode. ADC0 is in low power shutdown when AD0EN is logic 0 and no Burst Mode conversions are
taking place.
Start
Conversion
Burst Mode
Oscillator
25 MHz Max
*Available on ‘F53x/’F53xA
devices
19-to-1
AMUX0
Burst Mode
Logic
12-Bit
SAR
Selectable
Gain
ADC
VDD
ADC0GNH ADC0GNL ADC0GNA
Temp Sensor
00
AD0BUSY (W)
01
Timer 1 Overflow
10
CNVSTR Input
11
Timer 2 Overflow
Accumulator
AD0TM1:0
AD0PRE
AD0POST
FCLK
REF
P1.7*
Start
Conversion
ADC0L
SYSCLK
P0.6*
P0.7*
P1.0*
VDD
FCLK
P0.0
ADC0H
ADC0MX4
ADC0MX3
ADC0MX2
ADC0MX1
ADC0MX0
ADC0MX
AD0WINT
AD0SC4
AD0SC3
AD0SC2
AD0SC1
AD0SC0
AD0RPT1
AD0RPT0
GAINEN
GND
ADC0LTH ADC0LTL
ADC0CF
ADC0GTH ADC0GTL
32
Window
Compare
Logic
Figure 4.1. ADC0 Functional Block Diagram
4.1. Analog Multiplexer
AMUX0 selects the input channel to the ADC. Any of the following may be selected as an input: P0.0–
P1.7, the on-chip temperature sensor, the core power supply (VDD), or ground (GND). ADC0 is singleended and all signals measured are with respect to GND. The ADC0 input channels are selected using
the ADC0MX register as described in SFR Definition 4.4.
Important Note About ADC0 Input Configuration: Port pins selected as ADC0 inputs should be configured as analog inputs, and should be skipped by the Digital Crossbar. To configure a Port pin for analog
input, set to 0 the corresponding bit in register PnMDIN (for n = 0,1). To force the Crossbar to skip a Port
pin, set to 1 the corresponding bit in register PnSKIP (for n = 0,1). See Section “13. Port Input/Output” on
page 120 for more Port I/O configuration details.
52
Rev. 1.4
C8051F52x/F53x
4.2. Temperature Sensor
An on-chip temperature sensor is included on the C8051F52x/F52xA/F53x/F53xA devices which can be
directly accessed via the ADC0 multiplexer. To use ADC0 to measure the temperature sensor, the ADC
multiplexer channel should be configured to connect to the temperature sensor. The temperature sensor
transfer function is shown in Figure 5.2. The output voltage (VTEMP) is the positive ADC input selected by
bits AD0MX[4:0] in register ADC0MX. The TEMPE bit in register REF0CN enables/disables the temperature sensor, as described in SFR Definition 5.1. While disabled, the temperature sensor defaults to a high
impedance state and any ADC measurements performed on the sensor will result in meaningless data.
Refer to Table 5.1 for the slope and offset parameters of the temperature sensor.
VTEMP = (Slope x TempC) + Offset
TempC = (VTEMP - Offset) / Slope
Voltage
Slope ( V / deg C)
Offset ( V at 0 Celsius)
Temperature
Figure 4.2. Typical Temperature Sensor Transfer Function
Rev. 1.4
53
C8051F52x/F53x
4.3. ADC0 Operation
In a typical system, ADC0 is configured using the following steps:
1. If a gain adjustment is required, refer to Section “4.4. Selectable Gain” on page 60.
2. Choose the start of conversion source.
3. Choose Normal Mode or Burst Mode operation.
4. If Burst Mode, choose the ADC0 Idle Power State and set the Power-Up Time.
5. Choose the tracking mode. Note that Pre-Tracking Mode can only be used with Normal Mode.
6. Calculate required settling time and set the post convert-start tracking time using the AD0TK bits.
7. Choose the repeat count.
8. Choose the output word justification (Right-Justified or Left-Justified).
9. Enable or disable the End of Conversion and Window Comparator Interrupts.
4.3.1. Starting a Conversion
A conversion can be initiated in one of four ways, depending on the programmed states of the ADC0 Start
of Conversion Mode bits (AD0CM1–0) in register ADC0CN. Conversions may be initiated by one of the following:

Writing a 1 to the AD0BUSY bit of register ADC0CN
A rising edge on the CNVSTR input signal (pin P0.6)
 A Timer 1 overflow (i.e., timed continuous conversions)
 A Timer 2 overflow (i.e., timed continuous conversions)

Writing a 1 to AD0BUSY provides software control of ADC0 whereby conversions are performed "ondemand.” During conversion, the AD0BUSY bit is set to logic 1 and reset to logic 0 when the conversion is
complete. The falling edge of AD0BUSY triggers an interrupt (when enabled) and sets the ADC0 interrupt
flag (AD0INT). Note: When polling for ADC conversion completions, the ADC0 interrupt flag (AD0INT)
should be used. Converted data is available in the ADC0 data registers, ADC0H:ADC0L, when bit AD0INT
is logic 1. Note that when Timer 2 overflows are used as the conversion source, Low Byte overflows are
used if Timer2 is in 8-bit mode; High byte overflows are used if Timer 2 is in 16-bit mode. See Section
“18. Timers” on page 182 for timer configuration.
Important Note: The CNVSTR input pin also functions as Port pin P0.5 on C8051F52x/52xA devices and
P1.2 on C8051F53x/53xA devices. When the CNVSTR input is used as the ADC0 conversion source, Port
pin P0.5 or P1.2 should be skipped by the Digital Crossbar. To configure the Crossbar to skip P0.5 or P1.2,
set to 1 to the appropriate bit in the PnSKIP register. See Section “13. Port Input/Output” on page 120 for
details on Port I/O configuration.
4.3.2. Tracking Modes
Each ADC0 conversion must be preceded by a minimum tracking time for the converted result to be accurate, as shown in Table 2.3 on page 28. ADC0 has three tracking modes: Pre-Tracking, Post-Tracking, and
Dual-Tracking. Pre-Tracking Mode provides the minimum delay between the convert start signal and end
of conversion by tracking continuously before the convert start signal. This mode requires software management in order to meet minimum tracking requirements. In Post-Tracking Mode, a programmable tracking time starts after the convert start signal and is managed by hardware. Dual-Tracking Mode maximizes
tracking time by tracking before and after the convert start signal. Figure 4.3 shows examples of the three
tracking modes.
Pre-Tracking Mode is selected when AD0TM is set to 10b. Conversions are started immediately following
the convert start signal. ADC0 is tracking continuously when not performing a conversion. Software must
allow at least the minimum tracking time between each end of conversion and the next convert start signal.
The minimum tracking time must also be met prior to the first convert start signal after ADC0 is enabled.
54
Rev. 1.4
C8051F52x/F53x
Post-Tracking Mode is selected when AD0TM is set to 01b. A programmable tracking time based on
AD0TK is started immediately following the convert start signal. Conversions are started after the programmed tracking time ends. After a conversion is complete, ADC0 does not track the input. Rather, the
sampling capacitor remains disconnected from the input making the input pin high-impedance until the
next convert start signal.
Dual-Tracking Mode is selected when AD0TM is set to 11b. A programmable tracking time based on
AD0TK is started immediately following the convert start signal. Conversions are started after the programmed tracking time ends. After a conversion is complete, ADC0 tracks continuously until the next conversion is started.
Depending on the output connected to the ADC input, additional tracking time, more than is specified in
Table 2.3 on page 28, may be required after changing MUX settings. See the settling time requirements
described in Section “4.3.6. Settling Time Requirements” on page 60.
Convert Start
Pre-Tracking
AD0TM = 10
Track
Post-Tracking
AD0TM= 01
Idle
Track
Convert
Idle
Track
Convert..
Dual-Tracking
AD0TM = 11
Track
Track
Convert
Track
Track
Convert..
Convert
Track
Convert ...
Figure 4.3. ADC0 Tracking Modes
4.3.3. Timing
ADC0 has a maximum conversion speed specified in Table 2.3 on page 28. ADC0 is clocked from the
ADC0 Subsystem Clock (FCLK). The source of FCLK is selected based on the BURSTEN bit. When
BURSTEN is logic 0, FCLK is derived from the current system clock. When BURSTEN is logic 1, FCLK is
derived from the Burst Mode Oscillator, which is an independent clock source whose maximum frequency
is specified in Table 2.3 on page 28.
When ADC0 is performing a conversion, it requires a clock source that is typically slower than FCLK. The
ADC0 SAR conversion clock (SAR clock) is a divided version of FCLK. The divide ratio can be configured
using the AD0SC bits in the ADC0CF register. The maximum SAR clock frequency is listed in Table 2.3 on
page 28.
ADC0 can be in one of three states at any given time: tracking, converting, or idle. Tracking time depends
on the tracking mode selected. For Pre-Tracking Mode, tracking is managed by software and ADC0 starts
conversions immediately following the convert start signal. For Post-Tracking and Dual-Tracking Modes,
the tracking time after the convert start signal is equal to the value determined by the AD0TK bits plus 2
FCLK cycles. Tracking is immediately followed by a conversion. The ADC0 conversion time is always 13
SAR clock cycles plus an additional 2 FCLK cycles to start and complete a conversion. Figure 4.4 shows
timing diagrams for a conversion in Pre-Tracking Mode and tracking plus conversion in Post-Tracking or
Dual-Tracking Mode. In this example, repeat count is set to one.
Rev. 1.4
55
C8051F52x/F53x
Convert Start
Pre-Tracking Mode
Time
F
S1
S2
ADC0 State
...
S12
S13
F
Convert
AD0INT Flag
Post-Tracking or Dual-Tracking Modes (AD0TK = ‘00')
Time
F
S1
ADC0 State
S2
F F
S1
Track
...
S2
S12
S13
F
Convert
AD0INT Flag
Key
F
Sn
Equal to one period of FCLK.
Each Sn is equal to one period of the SAR clock.
Figure 4.4. 12-Bit ADC Tracking Mode Example
56
Rev. 1.4
C8051F52x/F53x
4.3.4. Burst Mode
Burst Mode is a power saving feature that allows ADC0 to remain in a very low power state between conversions. When Burst Mode is enabled, ADC0 wakes from a very low power state, accumulates 1, 4, 8, or
16 samples using an internal Burst Mode Oscillator, then re-enters a very low power state. Since the Burst
Mode clock is independent of the system clock, ADC0 can perform multiple conversions then enter a very
low power state within a single system clock cycle, even if the system clock is slow (e.g. 32.768 kHz), or
suspended.
Burst Mode is enabled by setting BURSTEN to logic 1. When in Burst Mode, AD0EN controls the ADC0
idle power state (i.e., the state ADC0 enters when not tracking or performing conversions). If AD0EN is set
to logic 0, ADC0 is powered down after each burst. If AD0EN is set to logic 1, ADC0 remains enabled after
each burst. On each convert start signal, ADC0 is awakened from its Idle Power State. If ADC0 is powered
down, it will automatically power up and wait the programmable Power-Up Time controlled by the
AD0PWR bits. Otherwise, ADC0 will start tracking and converting immediately. Figure 4.5 shows an example of Burst Mode Operation with a slow system clock and a repeat count of 4.
Important Note: When Burst Mode is enabled, only Post-Tracking and Dual-Tracking modes can be used.
When Burst Mode is enabled, a single convert start will initiate a number of conversions equal to the repeat
count. When Burst Mode is disabled, a convert start is required to initiate each conversion. In both modes,
the ADC0 End of Conversion Interrupt Flag (AD0INT) will be set after “repeat count” conversions have
been accumulated. Similarly, the Window Comparator will not compare the result to the greater-than and
less-than registers until “repeat count” conversions have been accumulated.
Note: When using Burst Mode, care must be taken to issue a convert start signal no faster than once every
four SYSCLK periods. This includes external convert start signals.
Rev. 1.4
57
C8051F52x/F53x
System Clock
Convert Start
(AD0BUSY or Timer
Overflow)
Post-Tracking
AD0TM = 01
AD0EN = 0
Powered
Down
Power-Up
and Idle
T C T C T C T C
Powered
Down
Power-Up
and Idle
T C..
Dual-Tracking
AD0TM = 11
AD0EN = 0
Powered
Down
Power-Up
and Track
T C T C T C T C
Powered
Down
Power-Up
and Track
T C..
AD0PWR
Post-Tracking
AD0TM = 01
AD0EN = 1
Idle
T C T C T C T C
Idle
T C T C T C..
Dual-Tracking
AD0TM = 11
AD0EN = 1
Track
T C T C T C T C
Track
T C T C T C..
T = Tracking
C = Converting
Convert Start
(CNVSTR)
Post-Tracking
AD0TM = 01
AD0EN = 0
Powered
Down
Power-Up
and Idle
T C
Powered
Down
Power-Up
and Idle
T C..
Dual-Tracking
AD0TM = 11
AD0EN = 0
Powered
Down
Power-Up
and Track
T C
Powered
Down
Power-Up
and Track
T C..
AD0PWR
Post-Tracking
AD0TM = 01
AD0EN = 1
Idle
T C
Idle
T C
Idle..
Dual-Tracking
AD0TM = 11
AD0EN = 1
Track
T C
Track
T C
Track..
T = Tracking
C = Converting
Figure 4.5. 12-Bit ADC Burst Mode Example with Repeat Count Set to 4
58
Rev. 1.4
C8051F52x/F53x
4.3.5. Output Conversion Code
The registers ADC0H and ADC0L contain the high and low bytes of the output conversion code. When the
repeat count is set to 1, conversion codes are represented in 12-bit unsigned integer format and the output
conversion code is updated after each conversion. Inputs are measured from 0 to VREF x 4095/4096. Data
can be right-justified or left-justified, depending on the setting of the AD0LJST bit (ADC0CN.2). Unused
bits in the ADC0H and ADC0L registers are set to 0. Example codes are shown below for both right-justified and left-justified data.
Input Voltage
Right-Justified ADC0H:ADC0L
(AD0LJST = 0)
Left-Justified ADC0H:ADC0L
(AD0LJST = 1)
VREF x 4095/4096
VREF x 2048/4096
VREF x 2047/4096
0
0x0FFF
0x0800
0x07FF
0x0000
0xFFF0
0x8000
0x7FF0
0x0000
When the ADC0 Repeat Count is greater than 1, the output conversion code represents the accumulated
result of the conversions performed and is updated after the last conversion in the series is finished. Sets
of 4, 8, or 16 consecutive samples can be accumulated and represented in unsigned integer format. The
repeat count can be selected using the AD0RPT bits in the ADC0CF register. The value must be right-justified (AD0LJST = “0”), and unused bits in the ADC0H and ADC0L registers are set to '0'. The following
example shows right-justified codes for repeat counts greater than 1. Notice that accumulating 2n samples
is equivalent to left-shifting by n bit positions when all samples returned from the ADC have the same
value.
Input Voltage
Repeat Count = 4
Repeat Count = 8
Repeat Count = 16
VREF x 4095/4096
VREF x 2048/4096
VREF x 2047/4096
0
0x3FFC
0x2000
0x1FFC
0x0000
0x7FF8
0x4000
0x3FF8
0x0000
0xFFF0
0x8000
0x7FF0
0x0000
Rev. 1.4
59
C8051F52x/F53x
4.3.6. Settling Time Requirements
A minimum tracking time is required before an accurate conversion can be performed. This tracking time is
determined by the AMUX0 resistance, the ADC0 sampling capacitance, any external source resistance,
and the accuracy required for the conversion.
Figure 4.6 shows the equivalent ADC0 input circuit. The required ADC0 settling time for a given settling
accuracy (SA) may be approximated by Equation 4.1. When measuring the Temperature Sensor output,
use the settling time specified in Table 2.3 on page 28. See Table 2.3 on page 28 for ADC0 minimum settling time requirements.
n
2
t = ln  -------  R TOTAL C SAMPLE
 SA
Equation 4.1. ADC0 Settling Time Requirements
Where:
SA is the settling accuracy, given as a fraction of an LSB (for example, 0.25 to settle within 1/4 LSB)
t is the required settling time in seconds
RTOTAL is the sum of the AMUX0 resistance and any external source resistance.
n is the ADC resolution in bits (12).
M U X S elect
Px.x
R MUX
C S A M P LE
R C Inp u t = R M U X * C S A M P L E
Figure 4.6. ADC0 Equivalent Input Circuits
4.4. Selectable Gain
ADC0 on the C8051F52x/52xA/53x/53xA family of devices implements a selectable gain adjustment
option. By writing a value to the gain adjust address range, the user can select gain values between 0 and
1.016.
For example, three analog sources to be measured have full-scale outputs of 5.0 V, 4.0 V, and 3.0 V,
respectively. Each ADC measurement would ideally use the full dynamic range of the ADC with an internal
voltage reference of 1.5 V or 2.2 V (set to 2.2 V for this example). When selecting signal one (5.0 V fullscale), a gain value of 0.44 (5 V full scale * 0.44 = 2.2 V full scale) provides a full-scale signal of 2.2 V
when the input signal is 5.0 V. Likewise, a gain value of 0.55 (4 V full scale * 0.55 = 2.2 V full scale) for the
second source and 0.73 (3 V full scale * 0.73 = 2.2 V full scale) for the third source provide full-scale ADC0
measurements when the input signal is full-scale.
Additionally, some sensors or other input sources have small part-to-part variations that must be
accounted for to achieve accurate results. In this case, the programmable gain value could be used as a
calibration value to eliminate these part-to-part variations.
60
Rev. 1.4
C8051F52x/F53x
4.4.1. Calculating the Gain Value
The ADC0 selectable gain feature is controlled by 13 bits in three registers. ADC0GNH contains the 8
upper bits of the gain value and ADC0GNL contains the 4 lower bits of the gain value. The final GAINADD
bit (ADC0GNA.0) controls an optional extra 1/64 (0.016) of gain that can be added in addition to the
ADC0GNH and ADC0GNL gain. The ADC0GNA.0 bit is set to 1 after a power-on reset.
The equivalent gain for the ADC0GNH, ADC0GNL and ADC0GNA registers is:
GAIN
1
gain =  --------------- + GAINADD   ------
 4096 
 64
Equation 4.2. Equivalent Gain from the ADC0GNH and ADC0GNL Registers
Where:
GAIN is the 12-bit word of ADC0GNH[7:0] and ADC0GNL[7:4]
GAINADD is the value of the GAINADD bit (ADC0GNA.0)
gain is the equivalent gain value from 0 to 1.016
For example, if ADC0GNH = 0xFC, ADC0GNL = 0x00, and GAINADD = '1', GAIN = 0xFC0 = 4032, and
the resulting equation is:
4032
1
gain =  ------------ + 1   ------ = 0.984 + 0.016 = 1.0
 4096
 64
The table below equates values in the ADC0GNH, ADC0GNL, and ADC0GNA registers to the equivalent
gain using this equation.
ADC0GNH Value
ADC0GNL Value
GAINADD Value
GAIN Value
Equivalent Gain
0xFC (default)
0x00 (default)
1 (default)
4032 + 64
1.0 (default)
0x7C
0x00
1
1984 + 64
0.5
0xBC
0x00
1
3008 + 64
0.75
0x3C
0x00
1
960 + 64
0.25
0xFF
0xF0
0
4095 + 0
~1.0
0xFF
0xF0
1
4095 + 64
1.016
For any desired gain value, the GAIN registers can be calculated by:
1
GAIN =  gain – GAINADD   ------   4096

 64 
Equation 4.3. Calculating the ADC0GNH and ADC0GNL Values from the Desired Gain
Where:
GAIN is the 12-bit word of ADC0GNH[7:0] and ADC0GNL[7:4]
GAINADD is the value of the GAINADD bit (ADC0GNA.0)
gain is the equivalent gain value from 0 to 1.016
When calculating the value of GAIN to load into the ADC0GNH and ADC0GNL registers, the GAINADD bit
can be turned on or off to reach a value closer to the desired gain value.
Rev. 1.4
61
C8051F52x/F53x
For example, the initial example in this section requires a gain of 0.44 to convert 5 V full scale to 2.2 V full
scale. Using Equation 4.3:
1
GAIN =  0.44 – GAINADD   ------   4096
64
If GAINADD is set to 1, this makes the equation:
1
GAIN =  0.44 – 1   ------   4096 = 0.424  4096 = 1738 = 0x06CA
64
The actual gain from setting GAINADD to 1 and ADC0GNH and ADC0GNL to 0x6CA is 0.4399. A similar
gain can be achieved if GAINADD is set to 0 with a different value for ADC0GNH and ADC0GNL.
4.4.2. Setting the Gain Value
The three programmable gain registers are accessed indirectly using the ADC0H and ADC0L registers
when the GAINEN bit (ADC0CF.0) bit is set. ADC0H acts as the address register, and ADC0L is the data
register. The programmable gain registers can only be written to and cannot be read. See Gain Register
Definition 4.1, Gain Register Definition 4.2, and Gain Register Definition 4.3 for more information.
The gain is programmed using the following steps:
1. Set the GAINEN bit (ADC0CF.0)
2. Load the ADC0H with the ADC0GNH, ADC0GNL, or ADC0GNA address.
3. Load ADC0L with the desired value for the selected gain register.
4. Reset the GAINEN bit (ADC0CF.0)
Notes:
1. An ADC conversion should not be performed while the GAINEN bit is set.
2. Even with gain enabled, the maximum input voltage must be less than VREGIN and the maximum
voltage of the signal after gain must be less than or equal to VREF.
In code, changing the value to 0.44 gain from the previous example looks like:
// in ‘C’:
ADC0CF |= 0x01;// GAINEN = 1
ADC0H = 0x04;// Load the ADC0GNH address
ADC0L = 0x6C;// Load the upper byte of 0x6CA to ADC0GNH
ADC0H = 0x07;// Load the ADC0GNL address
ADC0L = 0xA0;// Load the lower nibble of 0x6CA to ADC0GNL
ADC0H = 0x08;// Load the ADC0GNA address
ADC0L = 0x01;// Set the GAINADD bit
ADC0CF &= ~0x01;// GAINEN = 0
; in assembly
ORL ADC0CF,#01H ; GAINEN = 1
MOV ADC0H,#04H; Load the ADC0GNH address
MOV ADC0L,#06CH ; Load the upper byte of 0x6CA to ADC0GNH
MOV ADC0H,#07H; Load the ADC0GNL address
MOV ADC0L,#0A0H ; Load the lower nibble of 0x6CA to ADC0GNL
MOV ADC0H,#08H; Load the ADC0GNA address
MOV ADC0L,#01H ; Set the GAINADD bit
ANL ADC0CF,#0FEH ; GAINEN = 0
62
Rev. 1.4
C8051F52x/F53x
Gain Register Definition 4.1. ADC0GNH: ADC0 Selectable Gain High Byte
R/W
R/W
R/W
R/W
Bit7
Bit6
Bit5
Bit4
R/W
R/W
R/W
R/W
Bit2
Bit1
Bit0
GAINH[7:0]
Bit3
Reset Value
11111100
Address:
0x04
Bits7–0: High byte of Selectable Gain Word.
Gain Register Definition 4.2. ADC0GNL: ADC0 Selectable Gain Low Byte
R/W
R/W
R/W
R/W
GAINL[3:0]
Bit7
Bit6
Bit5
R/W
R/W
R/W
R/W
Reset Value
Reserved Reserved Reserved Reserved 00000000
Bit4
Bit3
Bit2
Bit1
Bit0
Address:
0x07
Bits7–4: Lower 4 bits of the Selectable Gain Word.
Bits3–0: Reserved. Must Write 0000b.
Gain Register Definition 4.3. ADC0GNA: ADC0 Additional Selectable Gain
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
Reserved Reserved Reserved Reserved Reserved Reserved Reserved GAINADD 00000001
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Address:
0x08
Bits7–1: Reserved. Must Write 0000000b.
Bit0:
GAINADD: Additional Gain Bit.
Setting this bit adds 1/64 (0.016) gain to the gain value in the ADC0GNH and ADC0GNL
registers.
Rev. 1.4
63
C8051F52x/F53x
SFR Definition 4.4. ADC0MX: ADC0 Channel Select
R/W
R/W
R/W
-
-
-
Bit7
Bit6
Bit5
R/W
R/W
R/W
R/W
R/W
Reset Value
Bit1
Bit0
SFR Address:
AD0MX
Bit4
Bit3
Bit2
00011111
0xBB
Bits7–5: UNUSED. Read = 000b; Write = don’t care.
Bits4–0: AD0MX4–0: AMUX0 Positive Input Selection
AD0MX4–0
ADC0 Input Channel
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
11000
11001
11010 - 11111
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6*
P0.7*
P1.0*
P1.1*
P1.2*
P1.3*
P1.4*
P1.5*
P1.6*
P1.7*
Temp Sensor
VDD
GND
Note: Only applies to C8051F53x/C8051F53xA parts.
64
Rev. 1.4
C8051F52x/F53x
SFR Definition 4.5. ADC0CF: ADC0 Configuration
R/W
R/W
R/W
R/W
R/W
AD0SC
Bit7
Bit6
Bit5
R/W
R/W
AD0RPT
Bit4
Bit3
Bit2
Bit1
R/W
Reset Value
GAINEN
11111000
Bit0
SFR Address:
0xBC
Bits7–3: AD0SC4–0: ADC0 SAR Conversion Clock Period Bits.
SAR Conversion clock is derived from FCLK by the following equation, where AD0SC refers
to the 5-bit value held in bits AD0SC4–0. SAR Conversion clock requirements are given in
Table 2.3 on page 28.
BURSTEN = 0: FCLK is the current system clock.
BURSTEN = 1: FCLK is the Burst Mode Oscillator, specified in Table 2.3.
FCLK
AD0SC = -------------------- – 1 *
CLK SAR
or
FCLK
CLK SAR = ---------------------------AD0SC + 1
Note: Round the result up.
Bits2–1: AD0RPT1–0: ADC0 Repeat Count.
Controls the number of conversions taken and accumulated between ADC0 End of
Conversion (ADCINT) and ADC0 Window Comparator (ADCWINT) interrupts. A convert
start is required for each conversion unless Burst Mode is enabled. In Burst Mode, a single
convert start can initiate multiple self-timed conversions. Results in both modes are
accumulated in the ADC0H:ADC0L register. When AD0RPT1–0 are set to a value other
than '00', the AD0LJST bit in the ADC0CN register must be set to '0' (right justified).
00: 1 conversion is performed.
01: 4 conversions are performed and accumulated.
10: 8 conversions are performed and accumulated.
11: 16 conversions are performed and accumulated.
Bit0:
GAINEN: Gain Enable Bit.
Controls the gain programming. For more information of the usage, refer to the following
chapter: Section “4.4. Selectable Gain” on page 60.
Rev. 1.4
65
C8051F52x/F53x
SFR Definition 4.6. ADC0H: ADC0 Data Word MSB
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
0xBE
Bits7–0: ADC0 Data Word High-Order Bits.
For AD0LJST = 0 and AD0RPT as follows:
00: Bits 3–0 are the upper 4 bits of the 12-bit result. Bits 7–4 are 0000b.
01: Bits 4–0 are the upper 5 bits of the 14-bit result. Bits 7–5 are 000b.
10: Bits 5–0 are the upper 6 bits of the 15-bit result. Bits 7–6 are 00b.
11: Bits 7–0 are the upper 8 bits of the 16-bit result.
For AD0LJST = 1 (AD0RPT must be '00'): Bits 7–0 are the most-significant bits of the ADC0
12-bit result.
SFR Definition 4.7. ADC0L: ADC0 Data Word LSB
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
0xBD
Bits7–0: ADC0 Data Word Low-Order Bits.
For AD0LJST = 0: Bits 7–0 are the lower 8 bits of the ADC0 Accumulated Result.
For AD0LJST = 1 (AD0RPT must be '00'): Bits 7–4 are the lower 4 bits of the 12-bit result.
Bits 3–0 are 0000b.
66
Rev. 1.4
C8051F52x/F53x
SFR Definition 4.8. ADC0CN: ADC0 Control
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
AD0EN BURSTEN AD0INT AD0BUSY AD0WINT AD0LJST AD0CM1
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Reset Value
AD0CM0 00000000
Bit0
(bit addressable)
SFR Address:
0xE8
Bit7:
AD0EN: ADC0 Enable Bit.
0: ADC0 Disabled. ADC0 is in low-power shutdown.
1: ADC0 Enabled. ADC0 is active and ready for data conversions.
Bit6:
BURSTEN: ADC0 Burst Mode Enable Bit.
0: ADC0 Burst Mode Disabled.
1: ADC0 Burst Mode Enabled.
Bit5:
AD0INT: ADC0 Conversion Complete Interrupt Flag.
0: ADC0 has not completed a data conversion since the last time AD0INT was cleared.
1: ADC0 has completed a data conversion.
Bit4:
AD0BUSY: ADC0 Busy Bit.
Read:
0: ADC0 conversion is complete or a conversion is not currently in progress. AD0INT is set
to logic 1 on the falling edge of AD0BUSY.
1: ADC0 conversion is in progress.
Write:
0: No Effect.
1: Initiates ADC0 Conversion if AD0CM1–0 = 00b
Bit3:
AD0WINT: ADC0 Window Compare Interrupt Flag.
This bit must be cleared by software.
0: ADC0 Window Comparison Data match has not occurred since this flag was last cleared.
1: ADC0 Window Comparison Data match has occurred.
Bit2:
AD0LJST: ADC0 Left Justify Select
0: Data in ADC0H:ADC0L registers is right justified.
1: Data in ADC0H:ADC0L registers is left justified. This option should not be used with a
repeat count greater than 1 (when AD0RPT1–0 is 01b, 10b, or 11b).
Bits1–0: AD0CM1–0: ADC0 Start of Conversion Mode Select.
00: ADC0 conversion initiated on every write of 1 to AD0BUSY.
01: ADC0 conversion initiated on overflow of Timer 1.
10: ADC0 conversion initiated on rising edge of external CNVSTR.
11: ADC0 conversion initiated on overflow of Timer 2.
Rev. 1.4
67
C8051F52x/F53x
SFR Definition 4.9. ADC0TK: ADC0 Tracking Mode Select
R/W
R/W
R/W
R/W
R/W
AD0PWR
Bit7
Bit6
Bit5
R/W
R/W
AD0TM
Bit4
Bit3
R/W
Reset Value
Bit0
SFR Address:
AD0TK
Bit2
Bit1
11111111
(bit addressable)
0xBA
Bits7–4: AD0PWR3–0: ADC0 Burst Power-Up Time.
For BURSTEN = 0:
ADC0 power state controlled by AD0EN.
For BURSTEN = 1 and AD0EN = 1;
ADC0 remains enabled and does not enter the very low power state.
For BURSTEN = 1 and AD0EN = 0:
ADC0 enters the very low power state as specified in Table 2.3 on page 28 and is enabled
after each convert start signal. The Power Up time is programmed according to the following
equation:
Tstartup
AD0PWR = ---------------------- – 1
200ns
or
Tstartup =  AD0PWR + 1 200ns
Bits3–2: AD0TM1–0: ADC0 Tracking Mode Select Bits.
00: Reserved.
01: ADC0 is configured to Post-Tracking Mode.
10: ADC0 is configured to Pre-Tracking Mode.
11: ADC0 is configured to Dual-Tracking Mode (default).
Bits1–0: AD0TK1–0: ADC0 Post-Track Time.
Post-Tracking time is controlled by AD0TK as follows:
00: Post-Tracking time is equal to 2 SAR clock cycles + 2 FCLK cycles.
01: Post-Tracking time is equal to 4 SAR clock cycles + 2 FCLK cycles.
10: Post-Tracking time is equal to 8 SAR clock cycles + 2 FCLK cycles.
11: Post-Tracking time is equal to 16 SAR clock cycles + 2 FCLK cycles.
68
Rev. 1.4
C8051F52x/F53x
4.5. Programmable Window Detector
The ADC Programmable Window Detector continuously compares the ADC0 output registers to user-programmed limits, and notifies the system when a desired condition is detected. This is especially effective in
an interrupt-driven system, saving code space and CPU bandwidth while delivering faster system
response times. The window detector interrupt flag (AD0WINT in register ADC0CN) can also be used in
polled mode. The ADC0 Greater-Than (ADC0GTH, ADC0GTL) and Less-Than (ADC0LTH, ADC0LTL)
registers hold the comparison values. The window detector flag can be programmed to indicate when measured data is inside or outside of the user-programmed limits, depending on the contents of the ADC0
Less-Than and ADC0 Greater-Than registers.
SFR Definition 4.10. ADC0GTH: ADC0 Greater-Than Data High Byte
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
11111111
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
0xC4
Bits7–0: High byte of ADC0 Greater-Than Data Word.
SFR Definition 4.11. ADC0GTL: ADC0 Greater-Than Data Low Byte
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
11111111
0xC3
Bits7–0: Low byte of ADC0 Greater-Than Data Word.
Rev. 1.4
69
C8051F52x/F53x
SFR Definition 4.12. ADC0LTH: ADC0 Less-Than Data High Byte
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
0xC6
Bits7–0: High byte of ADC0 Less-Than Data Word.
SFR Definition 4.13. ADC0LTL: ADC0 Less-Than Data Low Byte
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
00000000
0xC5
Bits7–0: Low byte of ADC0 Less-Than Data Word.
70
Rev. 1.4
C8051F52x/F53x
4.5.1. Window Detector In Single-Ended Mode
Figure 4.7
shows
two
example
window
comparisons
for
right-justified
data
with
ADC0LTH:ADC0LTL = 0x0200 (512d) and ADC0GTH:ADC0GTL = 0x0100 (256d). The input voltage can
range from 0 to VREF x (4095/4096) with respect to GND, and is represented by a 12-bit unsigned integer
value. The repeat count is set to one. In the left example, an AD0WINT interrupt will be generated if the
ADC0 conversion word (ADC0H:ADC0L) is within the range defined by ADC0GTH:ADC0GTL and
ADC0LTH:ADC0LTL (if 0x0100 < ADC0H:ADC0L < 0x0200). In the right example, and AD0WINT interrupt
will be generated if the ADC0 conversion word is outside of the range defined by the ADC0GT and
ADC0LT registers (if ADC0H:ADC0L < 0x0100 or ADC0H:ADC0L > 0x0200). Figure 4.8 shows an example using left-justified data with the same comparison values.
ADC0H:ADC0L
ADC0H:ADC0L
Input Voltage
(Px.x - GND)
VREF x (4095/4096)
Input Voltage
(Px.x - GND)
VREF x (4095/
4096)
0x0FFF
0x0FFF
AD0WINT
not affected
AD0WINT=1
0x0201
VREF x (512/4096)
0x0200
0x01FF
0x0201
ADC0LTH:ADC0LTL
VREF x (512/4096)
0x0200
0x01FF
AD0WINT=1
0x0101
VREF x (256/4096)
0x0100
0x0101
ADC0GTH:ADC0GTL
VREF x (256/4096)
0x00FF
0x0100
AD0WINT
not affected
ADC0LTH:ADC0LTL
0x00FF
AD0WINT=1
AD0WINT
not affected
0
ADC0GTH:ADC0GTL
0x0000
0x0000
0
Figure 4.7. ADC Window Compare Example: Right-Justified Single-Ended Data
ADC0H:ADC0L
ADC0H:ADC0L
Input Voltage
(Px.x - GND)
VREF x (4095/4096)
Input Voltage
(Px.x - GND)
0xFFF0
VREF x (4095/4096)
0xFFF0
AD0WINT
not affected
AD0WINT=1
0x2010
VREF x (512/4096)
0x2000
0x2010
ADC0LTH:ADC0LTL
VREF x (512/4096)
0x1FF0
0x2000
0x1FF0
AD0WINT=1
0x1010
VREF x (256/4096)
0x1000
0x1010
ADC0GTH:ADC0GTL
VREF x (256/4096)
0x0FF0
0x1000
AD0WINT
not affected
ADC0LTH:ADC0LTL
0x0FF0
AD0WINT=1
AD0WINT
not affected
0
ADC0GTH:ADC0GTL
0x0000
0
0x0000
Figure 4.8. ADC Window Compare Example: Left-Justified Single-Ended Data
Rev. 1.4
71
C8051F52x/F53x
5. Voltage Reference
The Voltage reference MUX on C8051F52x/F52xA/F53x/F53xA devices is configurable to use an externally connected voltage reference, the internal reference voltage generator, or the VDD power supply voltage (see Figure 5.1). The REFSL bit in the Reference Control register (REF0CN) selects the reference
source. For an external source or the internal reference applied to the VREF pin, REFSL should be set to 0.
To use VDD as the reference source, REFSL should be set to 1.
The BIASE bit enables the internal voltage bias generator, which is used by the ADC, Temperature Sensor,
and internal oscillators. This bit is forced to logic 1 when any of the aforementioned peripherals are
enabled. The bias generator may be enabled manually by writing a 1 to the BIASE bit in register REF0CN;
see SFR Definition 5.1 for REF0CN register details. The electrical specifications for the voltage reference
circuit are given in Table 2.5 on page 29.
The internal voltage reference circuit consists of a temperature stable bandgap voltage reference generator and a gain-of-two output buffer amplifier. The output voltage is selectable between 1.5 V and 2.2 V. The
internal voltage reference can be driven out on the VREF pin by setting the REFBE bit in register REF0CN
to a 1 (see Figure 5.1). The load seen by the VREF pin must draw less than 200 µA to GND. When using
the internal voltage reference, bypass capacitors of 0.1 µF and 4.7 µF are recommended from the VREF
pin to GND. If the internal reference is not used, the REFBE bit should be cleared to 0. Electrical specifications for the internal voltage reference are given in Table 2.5 on page 29.
REFLV
REFSL
TEMPE
BIASE
REFBE
REF0CN
EN
Bias Generator
To ADC,
Internal Oscillators
IOSCEN
VDD
R1
External
Voltage
Reference
Circuit
EN
VREF
Temp Sensor
To Analog Mux
0
VREF
(to ADC)
GND
VDD
1
REFBE
EN
Internal
Reference
REFLV
Figure 5.1. Voltage Reference Functional Block Diagram
72
Rev. 1.4
C8051F52x/F53x
Important Note About the VREF Pin: Port pin P0.0 is used as the external VREF input and as an output for
the internal VREF. When using either an external voltage reference or the internal reference circuitry, P0.0
should be configured as an analog pin, and skipped by the Digital Crossbar. To configure P0.0 as an analog pin, clear Bit 0 in register P0MDIN to 0. To configure the Crossbar to skip P0.0, set Bit 0 in register
P0SKIP to 1. Refer to Section “13. Port Input/Output” on page 120 for complete Port I/O configuration
details.
The TEMPE bit in register REF0CN enables/disables the temperature sensor. While disabled, the temperature sensor defaults to a high impedance state and any ADC0 measurements performed on the sensor
result in meaningless data.
SFR Definition 5.1. REF0CN: Reference Control
R/W
R/W
Reserved Reserved
Bit7
Bit6
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
ZTCEN
REFLV
REFSL
TEMPE
BIASE
REFBE
00000000
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
0xD1
Bits7–6: RESERVED. Read = 00b. Must write 00b.
Bit5:
ZTCEN: Zero-TempCo Bias Enable Bit*.
0: ZeroTC Bias Generator automatically enabled when needed.
1: ZeroTC Bias Generator forced on.
Bit4:
REFLV: Voltage Reference Output Level Select.
This bit selects the output voltage level for the internal voltage reference.
0: Internal voltage reference set to 1.5 V.
1: Internal voltage reference set to 2.2 V.
Bit3:
REFSL: Voltage Reference Select.
This bit selects the source for the internal voltage reference.
0: VREF pin used as voltage reference.
1: VDD used as voltage reference.
Bit2:
TEMPE: Temperature Sensor Enable Bit.
0: Internal Temperature Sensor off.
1: Internal Temperature Sensor on.
Bit1:
BIASE: Internal Analog Bias Generator Enable Bit.
0: Internal Analog Bias Generator automatically enabled when needed.
1: Internal Analog Bias Generator on.
Bit0:
REFBE: Internal Reference Buffer Enable Bit.
0: Internal Reference Buffer disabled.
1: Internal Reference Buffer enabled. Internal voltage reference driven on the VREF pin.
*Note: See Section “20.7. Internal Oscillator Suspend Mode” on page 212 for a note related to the ZTCEN bit in
older silicon revisions.
Rev. 1.4
73
C8051F52x/F53x
6. Voltage Regulator (REG0)
C8051F52x/F52xA/F53x/F53xAdevices include an on-chip low dropout voltage regulator (REG0). The
input to REG0 at the VREGIN pin can be as high as 5.25 V. The output can be selected by software to 2.1 V
or 2.6 V. When enabled, the output of REG0 appears on the VDD pin, powers the microcontroller core, and
can be used to power external devices. On reset, REG0 is enabled and can be disabled by software.
The input (VREGIN) and output (VDD) of the voltage regulator should both be bypassed with a large capacitor (4.7 µF + 0.1 µF) to ground. These capacitors are required for regulator stability, and will eliminate
power spikes and provide any immediate power required by the microcontroller. The settling time associated with the voltage regulator is shown in Table 2.6 on page 30.
Important Note: The bypass capacitors are required for the stability of the voltage regulator.
The voltage regulator can also generate an interrupt (if enabled by EREG0, EIE1.6) that is triggered whenever the VREGIN input voltage drops below the dropout threshold (see Table 2.6 on page 30). This dropout
interrupt has no pending flag. The recommended procedure to use the interrupt is as follows:
1. Wait enough time to ensure the VREGIN input voltage is stable.
2. Enable the dropout interrupt (EREG0, EIE1.6) and select the proper priority (PREG0, EIP1.6).
3. If triggered, disable the interrupt in the Interrupt Service Routine (clear EREG0, EIE1.6) and execute all
necessary procedures to put the system in “safe mode,” leaving the interrupt disabled.
4. The main application, now running in safe mode, should regularly check the DROPOUT bit
(REG0CN.0). Once it is cleared by the regulator hardware, the application can re-enable the interrupt
(EREG0, EIE1.6) and return to normal mode operation.
VREGIN
REG0
.1 µF
4.7 µF
VDD
VDD
4.7 µF
.1 µF
Figure 6.1. External Capacitors for Voltage Regulator Input/Output
74
Rev. 1.4
C8051F52x/F53x
SFR Definition 6.1. REG0CN: Regulator Control
R/W
R/W
REGDIS Reserved
Bit7
Bit6
R
R/W
R
R
R
—
REG0MD
—
—
—
Bit5
Bit4
Bit3
Bit2
Bit1
R
Reset Value
DROPOUT 01010000
Bit0
SFR Address:
0xC9
Bit7:
REGDIS: Voltage Regulator Disable Bit.
This bit disables/enables the Voltage Regulator.
0: Voltage Regulator Enabled.
1: Voltage Regulator Disabled.
Bit6:
RESERVED. Read = 1b. Must write 1b.
Bit5:
UNUSED. Read = 0b. Write = don’t care.
Bit4:
REG0MD: Voltage Regulator Mode Select Bit.
This bit selects the Voltage Regulator output voltage.
0: Voltage Regulator output is 2.1 V.
1: Voltage Regulator output is 2.6 V (default).
Bits3–1: UNUSED. Read = 000b. Write = don’t care.
Bit0:
DROPOUT: Voltage Regulator Dropout Indicator Bit.
0: Voltage Regulator is not in dropout.
1: Voltage Regulator is in or near dropout.
Rev. 1.4
75
C8051F52x/F53x
7. Comparator
C8051F52x/F52xA/F53x/F53xA devices include one on-chip programmable voltage comparator. The
Comparator is shown in Figure 7.1.
The Comparator offers programmable response time and hysteresis, an analog input multiplexer, and two
outputs that are optionally available at the Port pins: a synchronous “latched” output (CP0), or an asynchronous “raw” output (CP0A). The asynchronous CP0A signal is available even when the system clock is
not active. This allows the Comparator to operate and generate an output with the device in STOP or SUSPEND mode. When assigned to a Port pin, the Comparator output may be configured as open drain or
push-pull (see Section “13.2. Port I/O Initialization” on page 126). The Comparator may also be used as a
reset source (see Section “11.5. Comparator Reset” on page 110).
The Comparator inputs are selected in the CPT0MX register (SFR Definition 7.2). The CMX0P3–CMX0P0
bits select the Comparator0 positive input; the CMX0N3–CMX0N0 bits select the Comparator0 negative
input.
CPT0CN
Important Note About Comparator Inputs: The Port pins selected as Comparator inputs should be configured as analog inputs in their associated Port configuration register and configured to be skipped by the
Crossbar (for details on Port configuration, see Section “13.3. General Purpose Port I/O” on page 128).
CPT0MX
CMX0N3
CMX0N2
CMX0N1
CMX0N0
CMX0P3
CP0EN
CP0OUT
CP0RIF
VDD
CP0FIF
CP0HYP1
CP0HYP0
CP0
Interrupt
CP0HYN1
CP0HYN0
CMX0P2
CMX0P1
CMX0P0
CP0
Rising-edge
P0.0
CP0
Falling-edge
P0.2
P0.1
P0.4
CP0 +
Interrupt
Logic
P0.3
P0.6*
P0.5
CP0
+
P1.0*
P0.7*
D
P1.2*
-
SET
CLR
Q
Q
D
SET
CLR
Q
Q
P1.1*
Crossbar
P1.4*
(SYNCHRONIZER)
P1.3*
GND
P1.6*
P1.5*
CP0 -
CP0A
Reset
Decision
Tree
P1.7*
*Available in
parts
'F53x/'F53xA
CPT0MD
CP0RIE
CP0FIE
CP0MD1
CP0MD0
Figure 7.1. Comparator Functional Block Diagram
The Comparator output can be polled in software, used as an interrupt source, internal oscillator suspend
awakening source and/or routed to a Port pin. When routed to a Port pin, the Comparator output is available asynchronous or synchronous to the system clock; the asynchronous output is available even in
STOP or SUSPEND mode (with no system clock active). When disabled, the Comparator output (if
assigned to a Port I/O pin via the Crossbar) defaults to the logic low state, and its supply current falls to
76
Rev. 1.4
C8051F52x/F53x
less than 100 nA. See Section “13.1. Priority Crossbar Decoder” on page 122 for details on configuring
Comparator outputs via the digital Crossbar. Comparator inputs can be externally driven from –0.25 V to
(VREGIN) + 0.25 V without damage or upset. The complete Comparator electrical specifications are given
in Table 2.7 on page 31.
The Comparator response time may be configured in software via the CPTnMD register (see SFR Definition 7.3). Selecting a longer response time reduces the Comparator supply current. See Table 2.7 on
page 31 for complete timing and current consumption specifications.
VIN+
VIN-
CP0+
CP0-
+
CP0
_
OUT
CIRCUIT CONFIGURATION
Positive Hysteresis Voltage
(Programmed with CP0HYP Bits)
VIN-
INPUTS
Negative Hysteresis Voltage
(Programmed by CP0HYN Bits)
VIN+
VOH
OUTPUT
VOL
Negative Hysteresis
Disabled
Positive Hysteresis
Disabled
Maximum
Negative Hysteresis
Maximum
Positive Hysteresis
Figure 7.2. Comparator Hysteresis Plot
The Comparator hysteresis is software-programmable via its Comparator Control register CPT0CN. The
user can program both the amount of hysteresis voltage (referred to the input voltage) and the positive and
negative-going symmetry of this hysteresis around the threshold voltage.
The Comparator hysteresis is programmed using Bits3–0 in the Comparator Control Register CPT0CN
(shown in SFR Definition 7.1). The amount of negative hysteresis voltage is determined by the settings of
the CP0HYN bits. As shown in Table 2.7 on page 31, settings of 20, 10 or 5 mV of negative hysteresis can
be programmed, or negative hysteresis can be disabled. In a similar way, the amount of positive hysteresis
is determined by the setting the CP0HYP bits.
Comparator interrupts can be generated on both rising-edge and falling-edge output transitions. (For Interrupt enable and priority control, see Section “10. Interrupt Handler” on page 98). The CP0FIF flag is set to
logic 1 upon a Comparator falling-edge detect, and the CP0RIF flag is set to logic 1 upon the Comparator
rising-edge detect. Once set, these bits remain set until cleared by software. The output state of the Comparator can be obtained at any time by reading the CP0OUT bit. The Comparator is enabled by setting the
CP0EN bit to logic 1 and is disabled by clearing this bit to logic 0. When the Comparator is enabled, the
internal oscillator is awakened from SUSPEND mode if the Comparator output is logic 0.
Rev. 1.4
77
C8051F52x/F53x
Note that false rising edges and falling edges can be detected when the comparator is first powered-on or
if changes are made to the hysteresis or response time control bits. Therefore, it is recommended that the
rising-edge and falling-edge flags be explicitly cleared to logic 0 a short time after the comparator is
enabled or its mode bits have been changed. This Power Up Time is specified in Table 2.7 on page 31.
SFR Definition 7.1. CPT0CN: Comparator0 Control
R/W
R
R/W
R/W
CP0EN
CP0OUT
CP0RIF
CP0FIF
Bit7
Bit6
Bit5
Bit4
R/W
R/W
R/W
R/W
Reset Value
CP0HYP1 CP0HYP0 CP0HYN1 CP0HYN0 00000000
Bit3
Bit2
Bit1
Bit0
SFR Address:
0x9B
Bit7:
CP0EN: Comparator0 Enable Bit.
0: Comparator0 Disabled.
1: Comparator0 Enabled.
Bit6:
CP0OUT: Comparator0 Output State Flag.
0: Voltage on CP0+ < CP0–.
1: Voltage on CP0+ > CP0–.
Bit5:
CP0RIF: Comparator0 Rising-Edge Flag.
0: No Comparator0 Rising Edge has occurred since this flag was last cleared.
1: Comparator0 Rising Edge has occurred.
Bit4:
CP0FIF: Comparator0 Falling-Edge Flag.
0: No Comparator0 Falling-Edge has occurred since this flag was last cleared.
1: Comparator0 Falling-Edge has occurred.
Bits3–2: CP0HYP1–0: Comparator0 Positive Hysteresis Control Bits.
00: Positive Hysteresis Disabled.
01: Positive Hysteresis = 5 mV.
10: Positive Hysteresis = 10 mV.
11: Positive Hysteresis = 20 mV.
Bits1–0: CP0HYN1–0: Comparator0 Negative Hysteresis Control Bits.
00: Negative Hysteresis Disabled.
01: Negative Hysteresis = 5 mV.
10: Negative Hysteresis = 10 mV.
11: Negative Hysteresis = 20 mV.
78
Rev. 1.4
C8051F52x/F53x
SFR Definition 7.2. CPT0MX: Comparator0 MUX Selection
R/W
R/W
R/W
R/W
R/W
CMX0N3 CMX0N2 CMX0N1 CMX0N0 CMX0P3
Bit7
Bit6
Bit5
Bit4
Bit3
R/W
R/W
R/W
CMX0P2
CMX0P1
CMX0P0
Reset Value
01110111
Bit2
Bit1
Bit0
SFR Address:
0x9F
Bits7–4: CMX0N3–CMX0N0: Comparator0 Negative Input MUX Select.
These bits select which Port pin is used as the Comparator0 negative input.
CMX0N3 CMX0N2 CMX0N1 CMX0N0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Negative Input
P0.1
P0.3
P0.5
P0.7*
P1.1*
P1.3*
P1.5*
P1.7*
*Note: Available only on the C8051F53x/53xA devices
Bits1–0: CMX0P3–CMX0P0: Comparator0 Positive Input MUX Select.
These bits select which Port pin is used as the Comparator0 positive input.
CMX0P3 CMX0P2 CMX0P1 CMX0P0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Positive Input
P0.0
P0.2
P0.4
P0.6*
P1.0*
P1.2*
P1.4*
P1.6*
*Note: Available only on the C8051F53x/53xA devices.
Rev. 1.4
79
C8051F52x/F53x
SFR Definition 7.3. CPT0MD: Comparator0 Mode Selection
R/W
R/W
R/W
R/W
R/W
R/W
Reserved
—
CP0RIE
CP0FIE
—
—
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
R/W
R/W
Reset Value
CP0MD1 CP0MD0 00000010
Bit1
Bit0
SFR Address:
0x9D
Bit7:
Bit6:
Bit5:
RESERVED. Read = 0b. Must write 0b.
UNUSED. Read = 0b. Write = don’t care.
CP0RIE: Comparator Rising-Edge Interrupt Enable.
0: Comparator rising-edge interrupt disabled.
1: Comparator rising-edge interrupt enabled.
Bit4:
CP0FIE: Comparator Falling-Edge Interrupt Enable.
0: Comparator falling-edge interrupt disabled.
1: Comparator falling-edge interrupt enabled.
Note: It is necessary to enable both CP0xIE and the correspondent ECPx bit located in EIE1
SFR.
Bits3–2: UNUSED. Read = 00b. Write = don’t care.
Bits1–0: CP0MD1–CP0MD0: Comparator0 Mode Select
These bits select the response time for Comparator0.
Mode
CP0MD1
CP0MD0
CP0 Falling Edge Response
Time (TYP)
0
1
2
3
0
0
1
1
0
1
0
1
Fastest Response Time
—
—
Lowest Power Consumption
Note: Rising Edge response times are approximately double the Falling Edge response
times.
80
Rev. 1.4
C8051F52x/F53x
8. CIP-51 Microcontroller
The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the
MCS-51™ instruction set. Standard 803x/805x assemblers and compilers can be used to develop software. The C8051F52x/F52xA/F53x/F53xA family has a superset of all the peripherals included with a standard 8051. See Section “1. System Overview” on page 13 for more information about the available
peripherals. The CIP-51 includes on-chip debug hardware which interfaces directly with the analog and
digital subsystems, providing a complete data acquisition or control-system solution in a single integrated
circuit.
The CIP-51 Microcontroller core implements the standard 8051 organization and peripherals as well as
additional custom peripherals and functions to extend its capability (see Figure 8.1 for a block diagram).
The CIP-51 core includes the following features:


Fully Compatible with MCS-51 Instruction Set
 25 MIPS Peak Throughput
 256 Bytes of Internal RAM
 Extended Interrupt Handler
Reset Input
 Power Management Modes
 Integrated Debug Logic
 Program and Data Memory Security
D8
D8
ACCUMULATOR
STACK POINTER
TMP1
TMP2
SRAM
ADDRESS
REGISTER
PSW
SRAM
(256 X 8)
D8
D8
D8
ALU
D8
DATA BUS
B REGISTER
D8
D8
D8
DATA BUS
DATA BUS
SFR_ADDRESS
BUFFER
D8
DATA POINTER
D8
D8
SFR_CONTROL
SFR
BUS
INTERFACE
SFR_WRITE_DATA
SFR_READ_DATA
DATA BUS
PC INCREMENTER
PROGRAM COUNTER (PC)
PRGM. ADDRESS REG.
MEM_ADDRESS
D8
MEM_CONTROL
A16
MEMORY
INTERFACE
MEM_WRITE_DATA
MEM_READ_DATA
PIPELINE
RESET
D8
CONTROL
LOGIC
SYSTEM_IRQs
CLOCK
D8
STOP
IDLE
POWER CONTROL
REGISTER
INTERRUPT
INTERFACE
EMULATION_IRQ
D8
Figure 8.1. CIP-51 Block Diagram
Rev. 1.4
81
C8051F52x/F53x
Performance
The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the standard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system
clock cycles to execute, and usually have a maximum system clock of 12 MHz. By contrast, the CIP-51
core executes 70% of its instructions in one or two system clock cycles, with no instructions taking more
than eight system clock cycles.
With the CIP-51's system clock running at 25 MHz, it has a peak throughput of 25 MIPS. The CIP-51 has a
total of 109 instructions. The table below shows the total number of instructions that require each execution
time.
Clocks to Execute
1
2
2/3
3
3/4
4
4/5
5
8
Number of Instructions
26
50
5
14
7
3
1
2
1
Programming and Debugging Support
In-system programming of the Flash program memory and communication with on-chip debug support
logic is accomplished via the Silicon Labs 2-Wire (C2) interface. Note that the re-programmable Flash can
also be read and written a single byte at a time by the application software using the MOVC and MOVX
instructions. This feature allows program memory to be used for non-volatile data storage as well as updating program code under software control.
The on-chip debug support logic facilitates full speed in-circuit debugging, allowing the setting of hardware
breakpoints, starting, stopping and single stepping through program execution (including interrupt service
routines), examination of the program's call stack, and reading/writing the contents of registers and memory. This method of on-chip debugging is completely non-intrusive, requiring no RAM, Stack, timers, or
other on-chip resources.
The CIP-51 is supported by development tools from Silicon Laboratories, Inc. and third party vendors. Silicon Laboratories provides an integrated development environment (IDE) including editor, evaluation compiler, assembler, debugger and programmer. The IDE's debugger and programmer interface to the CIP-51
via the on-chip debug logic to provide fast and efficient in-system device programming and debugging.
Third party macro assemblers and C compilers are also available.
8.1. Instruction Set
The instruction set of the CIP-51 System Controller is fully compatible with the standard MCS-51™ instruction set. Standard 8051 development tools can be used to develop software for the CIP-51. All CIP-51
instructions are the binary and functional equivalent of their MCS-51™ counterparts, including opcodes,
addressing modes and effect on PSW flags. However, instruction timing is different than that of the standard 8051.
8.1.1. Instruction and CPU Timing
In many 8051 implementations, a distinction is made between machine cycles and clock cycles, with
machine cycles varying from 2 to 12 clock cycles in length. However, the CIP-51 implementation is based
solely on clock cycle timing. All instruction timings are specified in terms of clock cycles.
Due to the pipelined architecture of the CIP-51, most instructions execute in the same number of clock
cycles as there are program bytes in the instruction. Conditional branch instructions take one less clock
cycle to complete when the branch is not taken as opposed to when the branch is taken. Table 8.1 is the
CIP-51 Instruction Set Summary, which includes the mnemonic, number of bytes, and number of clock
cycles for each instruction.
82
Rev. 1.4
C8051F52x/F53x
8.1.2. MOVX Instruction and Program Memory
The MOVX instruction is typically used to access data stored in XDATA memory space. In the CIP-51, the
MOVX instruction can also be used to write or erase on-chip program memory space implemented as reprogrammable Flash memory. The Flash access feature provides a mechanism for the CIP-51 to update
program code and use the program memory space for non-volatile data storage. Refer to Section
“12. Flash Memory” on page 113 for further details.
Table 8.1. CIP-51 Instruction Set Summary
Mnemonic
Description
Bytes
Clock
Cycles
Arithmetic Operations
ADD A, Rn
ADD A, direct
ADD A, @Ri
ADD A, #data
ADDC A, Rn
ADDC A, direct
ADDC A, @Ri
ADDC A, #data
SUBB A, Rn
SUBB A, direct
SUBB A, @Ri
SUBB A, #data
INC A
INC Rn
INC direct
INC @Ri
DEC A
DEC Rn
DEC direct
DEC @Ri
INC DPTR
MUL AB
DIV AB
DA A
Add register to A
Add direct byte to A
Add indirect RAM to A
Add immediate to A
Add register to A with carry
Add direct byte to A with carry
Add indirect RAM to A with carry
Add immediate to A with carry
Subtract register from A with borrow
Subtract direct byte from A with borrow
Subtract indirect RAM from A with borrow
Subtract immediate from A with borrow
Increment A
Increment register
Increment direct byte
Increment indirect RAM
Decrement A
Decrement register
Decrement direct byte
Decrement indirect RAM
Increment Data Pointer
Multiply A and B
Divide A by B
Decimal adjust A
1
2
1
2
1
2
1
2
1
2
1
2
1
1
2
1
1
1
2
1
1
1
1
1
1
2
2
2
1
2
2
2
1
2
2
2
1
1
2
2
1
1
2
2
1
4
8
1
AND Register to A
AND direct byte to A
AND indirect RAM to A
AND immediate to A
AND A to direct byte
AND immediate to direct byte
OR Register to A
OR direct byte to A
OR indirect RAM to A
OR immediate to A
OR A to direct byte
1
2
1
2
2
3
1
2
1
2
2
1
2
2
2
2
3
1
2
2
2
2
Logical Operations
ANL A, Rn
ANL A, direct
ANL A, @Ri
ANL A, #data
ANL direct, A
ANL direct, #data
ORL A, Rn
ORL A, direct
ORL A, @Ri
ORL A, #data
ORL direct, A
Rev. 1.4
83
C8051F52x/F53x
Table 8.1. CIP-51 Instruction Set Summary (Continued)
Mnemonic
ORL direct, #data
XRL A, Rn
XRL A, direct
XRL A, @Ri
XRL A, #data
XRL direct, A
XRL direct, #data
CLR A
CPL A
RL A
RLC A
RR A
RRC A
SWAP A
Description
Bytes
Clock
Cycles
OR immediate to direct byte
Exclusive-OR Register to A
Exclusive-OR direct byte to A
Exclusive-OR indirect RAM to A
Exclusive-OR immediate to A
Exclusive-OR A to direct byte
Exclusive-OR immediate to direct byte
Clear A
Complement A
Rotate A left
Rotate A left through Carry
Rotate A right
Rotate A right through Carry
Swap nibbles of A
3
1
2
1
2
2
3
1
1
1
1
1
1
1
3
1
2
2
2
2
3
1
2
1
1
1
1
1
Move Register to A
Move direct byte to A
Move indirect RAM to A
Move immediate to A
Move A to Register
Move direct byte to Register
Move immediate to Register
Move A to direct byte
Move Register to direct byte
Move direct byte to direct byte
Move indirect RAM to direct byte
Move immediate to direct byte
Move A to indirect RAM
Move direct byte to indirect RAM
Move immediate to indirect RAM
Load DPTR with 16-bit constant
Move code byte relative DPTR to A
Move code byte relative PC to A
Move external data (8-bit address) to A
Move A to external data (8-bit address)
Move external data (16-bit address) to A
Move A to external data (16-bit address)
Push direct byte onto stack
Pop direct byte from stack
Exchange Register with A
Exchange direct byte with A
Exchange indirect RAM with A
Exchange low nibble of indirect RAM with A
1
2
1
2
1
2
2
2
2
3
2
3
1
2
2
3
1
1
1
1
1
1
2
2
1
2
1
1
1
2
2
2
1
2
2
2
2
3
2
3
2
2
2
3
3
3
3
3
3
3
2
2
1
2
2
2
Data Transfer
MOV A, Rn
MOV A, direct
MOV A, @Ri
MOV A, #data
MOV Rn, A
MOV Rn, direct
MOV Rn, #data
MOV direct, A
MOV direct, Rn
MOV direct, direct
MOV direct, @Ri
MOV direct, #data
MOV @Ri, A
MOV @Ri, direct
MOV @Ri, #data
MOV DPTR, #data16
MOVC A, @A+DPTR
MOVC A, @A+PC
MOVX A, @Ri
MOVX @Ri, A
MOVX A, @DPTR
MOVX @DPTR, A
PUSH direct
POP direct
XCH A, Rn
XCH A, direct
XCH A, @Ri
XCHD A, @Ri
84
Rev. 1.4
C8051F52x/F53x
Table 8.1. CIP-51 Instruction Set Summary (Continued)
Mnemonic
Description
Bytes
Clock
Cycles
Boolean Manipulation
CLR C
CLR bit
SETB C
SETB bit
CPL C
CPL bit
ANL C, bit
ANL C, /bit
ORL C, bit
ORL C, /bit
MOV C, bit
MOV bit, C
JC rel
JNC rel
JB bit, rel
JNB bit, rel
JBC bit, rel
Clear Carry
Clear direct bit
Set Carry
Set direct bit
Complement Carry
Complement direct bit
AND direct bit to Carry
AND complement of direct bit to Carry
OR direct bit to carry
OR complement of direct bit to Carry
Move direct bit to Carry
Move Carry to direct bit
Jump if Carry is set
Jump if Carry is not set
Jump if direct bit is set
Jump if direct bit is not set
Jump if direct bit is set and clear bit
1
2
1
2
1
2
2
2
2
2
2
2
2
2
3
3
3
1
2
1
2
1
2
2
2
2
2
2
2
2/3
2/3
3/4
3/4
3/4
Absolute subroutine call
Long subroutine call
Return from subroutine
Return from interrupt
Absolute jump
Long jump
Short jump (relative address)
Jump indirect relative to DPTR
Jump if A equals zero
Jump if A does not equal zero
Compare direct byte to A and jump if not equal
Compare immediate to A and jump if not equal
Compare immediate to Register and jump if not
equal
Compare immediate to indirect and jump if not
equal
Decrement Register and jump if not zero
Decrement direct byte and jump if not zero
No operation
2
3
1
1
2
3
2
1
2
2
3
3
3
3
4
5
5
3
4
3
3
2/3
2/3
4/5
3/4
3/4
3
4/5
2
3
1
2/3
3/4
1
Program Branching
ACALL addr11
LCALL addr16
RET
RETI
AJMP addr11
LJMP addr16
SJMP rel
JMP @A+DPTR
JZ rel
JNZ rel
CJNE A, direct, rel
CJNE A, #data, rel
CJNE Rn, #data, rel
CJNE @Ri, #data, rel
DJNZ Rn, rel
DJNZ direct, rel
NOP
Rev. 1.4
85
C8051F52x/F53x
Notes on Registers, Operands and Addressing Modes:
Rn - Register R0–R7 of the currently selected register bank.
@Ri - Data RAM location addressed indirectly through R0 or R1.
rel - 8-bit, signed (two’s complement) offset relative to the first byte of the following instruction. Used by
SJMP and all conditional jumps.
direct - 8-bit internal data location’s address. This could be a direct-access Data RAM location (0x00–
0x7F) or an SFR (0x80–0xFF).
#data - 8-bit constant
#data16 - 16-bit constant
bit - Direct-accessed bit in Data RAM or SFR
addr11 - 11-bit destination address used by ACALL and AJMP. The destination must be within the same
2 kB page of program memory as the first byte of the following instruction.
addr16 - 16-bit destination address used by LCALL and LJMP. The destination may be anywhere within
the 7680 bytes of program memory space.
There is one unused opcode (0xA5) that performs the same function as NOP.
All mnemonics copyrighted © Intel Corporation 1980.
8.2. Register Descriptions
Following are descriptions of SFRs related to the operation of the CIP-51 System Controller. Reserved bits
should not be set to logic 1. Future product versions may use these bits to implement new features in
which case the reset value of the bit will be logic 0, selecting the feature's default state. Detailed descriptions of the remaining SFRs are included in the sections of the datasheet associated with their corresponding system function.
86
Rev. 1.4
C8051F52x/F53x
SFR Definition 8.1. SP: Stack Pointer
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
00000111
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address: 0x81
Bits7–0: SP: Stack Pointer.
The Stack Pointer holds the location of the top of the stack. The stack pointer is incremented
before every PUSH operation. The SP register defaults to 0x07 after reset.
SFR Definition 8.2. DPL: Data Pointer Low Byte
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Reset Value
00000000
SFR Address: 0x82
Bits7–0: DPL: Data Pointer Low.
The DPL register is the low byte of the 16-bit DPTR. DPTR is used to access indirectly
addressed XRAM and Flash memory.
SFR Definition 8.3. DPH: Data Pointer High Byte
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address: 0x83
Bits7–0: DPH: Data Pointer High.
The DPH register is the high byte of the 16-bit DPTR. DPTR is used to access indirectly
addressed XRAM and Flash memory.
Rev. 1.4
87
C8051F52x/F53x
SFR Definition 8.4. PSW: Program Status Word
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
Reset Value
CY
AC
F0
RS1
RS0
OV
F1
PARITY
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Bit
Addressable
SFR Address: 0xD0
Bit7:
CY: Carry Flag.
This bit is set when the last arithmetic operation resulted in a carry (addition) or a borrow
(subtraction). It is cleared to 0 by all other arithmetic operations.
Bit6:
AC: Auxiliary Carry Flag
This bit is set when the last arithmetic operation resulted in a carry into (addition) or a borrow
from (subtraction) the high order nibble. It is cleared to 0 by all other arithmetic operations.
Bit5:
F0: User Flag 0.
This is a bit-addressable, general purpose flag for use under software control.
Bits4–3: RS1–RS0: Register Bank Select.
These bits select which register bank is used during register accesses.
RS1
0
0
1
1
Bit2:
Bit1:
Bit0:
88
RS0
0
1
0
1
Register Bank
0
1
2
3
Address
0x00–0x07
0x08–0x0F
0x10–0x17
0x18–0x1F
OV: Overflow Flag.
This bit is set to 1 under the following circumstances:
• An ADD, ADDC, or SUBB instruction causes a sign-change overflow.
• A MUL instruction results in an overflow (result is greater than 255).
• A DIV instruction causes a divide-by-zero condition.
The OV bit is cleared to 0 by the ADD, ADDC, SUBB, MUL, and DIV instructions in all other
cases.
F1: User Flag 1.
This is a bit-addressable, general purpose flag for use under software control.
PARITY: Parity Flag.
This bit is set to 1 if the sum of the eight bits in the accumulator is odd and cleared if the sum
is even.
Rev. 1.4
C8051F52x/F53x
SFR Definition 8.5. ACC: Accumulator
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
ACC.7
ACC.6
ACC.5
ACC.4
ACC.3
ACC.2
ACC.1
ACC.0
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Bit
Addressable
SFR Address: 0xE0
Bits7–0: ACC: Accumulator.
This register is the accumulator for arithmetic operations.
SFR Definition 8.6. B: B Register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
B.7
B.6
B.5
B.4
B.3
B.2
B.1
B.0
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Bit
Addressable
SFR Address: 0xF0
Bits7–0: B: B Register.
This register serves as a second accumulator for certain arithmetic operations.
8.3. Power Management Modes
The CIP-51 core has two software programmable power management modes: Idle and Stop. Idle mode
halts the CPU while leaving the peripherals and internal clocks active. In Stop mode, the CPU is halted, all
interrupts and timers (except the Missing Clock Detector) are inactive, and the internal oscillator is stopped
(analog peripherals remain in their selected states; the external oscillator is not affected). Since clocks are
running in Idle mode, power consumption is dependent upon the system clock frequency and the number
of peripherals left in active mode before entering Idle. Stop mode consumes the least power. SFR Definition 8.7 describes the Power Control Register (PCON) used to control the CIP-51's power management
modes.
Although the CIP-51 has Idle and Stop modes built in (as with any standard 8051 architecture), power
management of the entire MCU is better accomplished by enabling/disabling individual peripherals as
needed. Each analog peripheral can be disabled when not in use and placed in low power mode. Digital
peripherals, such as timers or serial buses, draw little power when they are not in use. Turning off the oscillators lowers power consumption considerably; however a reset is required to restart the MCU.
The C8051F52x/F52xA/F53x/F53xA devices feature a low-power SUSPEND mode, which stops the internal oscillator until a wakening event occurs. See Section “14.1.1. Internal Oscillator Suspend Mode” on
page 136 for more information.
Rev. 1.4
89
C8051F52x/F53x
8.3.1. Idle Mode
Setting the Idle Mode Select bit (PCON.0) causes the CIP-51 to halt the CPU and enter Idle mode as soon
as the instruction that sets the bit completes execution. All internal registers and memory maintain their
original data. All analog and digital peripherals can remain active during Idle mode.
Idle mode is terminated when an enabled interrupt is asserted or a reset occurs. The assertion of an
enabled interrupt will cause the Idle Mode Selection bit (PCON.0) to be cleared and the CPU to resume
operation. The pending interrupt will be serviced and the next instruction to be executed after the return
from interrupt (RETI) will be the instruction immediately following the one that set the Idle Mode Select bit.
If Idle mode is terminated by an internal or external reset, the CIP-51 performs a normal reset sequence
and begins program execution at address 0x0000.
If enabled, the Watchdog Timer (WDT) will eventually cause an internal watchdog reset and thereby terminate the Idle mode. This feature protects the system from an unintended permanent shutdown in the event
of an inadvertent write to the PCON register. If this behavior is not desired, the WDT may be disabled by
software prior to entering the Idle mode if the WDT was initially configured to allow this operation. This provides the opportunity for additional power savings, allowing the system to remain in the Idle mode indefinitely, waiting for an external stimulus to wake up the system.
8.3.2. Stop Mode
Setting the Stop Mode Select bit (PCON.1) causes the CIP-51 to enter Stop mode as soon as the instruction that sets the bit completes execution. In Stop mode the internal oscillator, CPU, and all digital peripherals are stopped; the state of the external oscillator circuit is not affected. Each analog peripheral (including
the external oscillator circuit) may be shut down individually prior to entering Stop Mode. Stop mode can
only be terminated by an internal or external reset. On reset, the CIP-51 performs the normal reset
sequence and begins program execution at address 0x0000.
If enabled, the Missing Clock Detector will cause an internal reset and thereby terminate the Stop mode.
The Missing Clock Detector should be disabled if the CPU is to be put to in STOP mode for longer than the
MCD timeout period of 100 s.
8.3.3. Suspend Mode
The C8051F52x/F52xA/F53x/F53xA devices feature a low-power Suspend mode, which stops the internal
oscillator until a wakening event occurs. See Section Section “14.1.1. Internal Oscillator Suspend Mode”
on page 136 for more information.
Note: When entering Suspend mode, firmware must set the ZTCEN bit in REF0CN (SFR Definition 5.1).
90
Rev. 1.4
C8051F52x/F53x
SFR Definition 8.7. PCON: Power Control
R/W
R/W
R/W
R/W
R/W
R/W
Reserved Reserved Reserved Reserved Reserved Reserved
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
R/W
R/W
Reset Value
STOP
IDLE
00000000
Bit1
Bit0
SFR Address: 0x87
Bits7–2: RESERVED.
Bit1:
STOP: STOP Mode Select.
Writing a 1 to this bit will place the CIP-51 into STOP mode. This bit will always read 0.
1: CIP-51 forced into power-down mode. (Turns off internal oscillator).
Bit0:
IDLE: IDLE Mode Select.
Writing a 1 to this bit will place the CIP-51 into IDLE mode. This bit will always read 0.
1: CIP-51 forced into IDLE mode. (Shuts off clock to CPU, but clock to Timers, Interrupts,
and all peripherals remain active.)
Rev. 1.4
91
C8051F52x/F53x
9. Memory Organization and SFRs
The memory organization of the C8051F52x/F52xA/F53x/F53xA is similar to that of a standard 8051.
There are two separate memory spaces: program memory and data memory. Program and data memory
share the same address space but are accessed via different instruction types. The memory map is shown
in Figure 9.1.
PROGRAM/DATA MEMORY
(Flash)
'F520/0A/1/1A and 'F530/0A/1/1A
0x1E00
0x1DFF
0xFF
RESERVED
8 kB Flash
(In-System
Programmable in 512
Byte Sectors)
0x0000
'F523/3A/4/4A and 'F533/3A/4/4A
0x1000
0x0FFF
DATA MEMORY (RAM)
INTERNAL DATA ADDRESS SPACE
0x80
0x7F
Upper 128 RAM
(Indirect Addressing
Only)
(Direct and Indirect
Addressing)
0x30
0x2F
0x20
0x1F
0x00
Bit Addressable
Special Function
Register's
(Direct Addressing Only)
Lower 128 RAM
(Direct and Indirect
Addressing)
General Purpose
Registers
RESERVED
4 kB Flash
0x0000
(In-System
Programmable in 512
Byte Sectors)
'F526/6A/7/7A and 'F536/6A/7/7A
0x0800
0x07FF
RESERVED
2 kB Flash
(In-System
Programmable in 512
Byte Sectors)
0x0000
Figure 9.1. Memory Map
9.1. Program Memory
The CIP-51 core has a 64 kB program memory space. The C8051F520/0A/1/1A and C8051F530/0A/1/1A
implement 8 kB of this program memory space as in-system, re-programmable Flash memory, organized
in a contiguous block from addresses 0x0000 to 0x1FFF. Addresses above 0x1DFF are reserved on the
8 kB devices. The C8051F523/3A/4/4A and C8051F533/3A/4/4A implement 4 kB of Flash from addresses
0x0000 to 0x0FFF. The C8051F526/6A/7/7A and C8051F536/6A/7/7A implement 2 kB of Flash from
addresses 0x0000 to 0x07FF.
Program memory is normally assumed to be read-only. However, the C8051F52x/F52xA/F53x/F53xA can
write to program memory by setting the Program Store Write Enable bit (PSCTL.0) and using the MOVX
write instruction. This feature provides a mechanism for updates to program code and use of the program
memory space for non-volatile data storage. Refer to Section “12. Flash Memory” on page 113 for further
details.
92
Rev. 1.4
C8051F52x/F53x
9.2. Data Memory
The C8051F52x/F52xA/F53x/F53xAincludes 256 bytes of internal RAM mapped into the data memory
space from 0x00 through 0xFF. The lower 128 bytes of data memory are used for general purpose registers and scratch pad memory. Either direct or indirect addressing may be used to access the lower
128 bytes of data memory. Locations 0x00 through 0x1F are addressable as four banks of general purpose registers, each bank consisting of eight byte-wide registers. The next 16 bytes, locations 0x20
through 0x2F, may either be addressed as bytes or as 128 bit locations accessible with the direct addressing mode.
The upper 128 bytes of data memory are accessible only by indirect addressing. This region occupies the
same address space as the Special Function Registers (SFRs) but is physically separate from the SFR
space. The addressing mode used by an instruction when accessing locations above 0x7F determines
whether the CPU accesses the upper 128 bytes of data memory space or the SFRs. Instructions that use
direct addressing will access the SFR space. Instructions using indirect addressing above 0x7F access the
upper 128 bytes of data memory. Figure 9.1 illustrates the data memory organization of the C8051F52x/
F52xA/F53x/F53xA.
9.3. General Purpose Registers
The lower 32 bytes of data memory (locations 0x00 through 0x1F) may be addressed as four banks of
general-purpose registers. Each bank consists of eight byte-wide registers designated R0 through R7.
Only one of these banks may be enabled at a time. Two bits in the program status word, RS0 (PSW.3) and
RS1 (PSW.4), select the active register bank (see description of the PSW in SFR Definition 8.4. PSW: Program Status Word). This allows fast context switching when entering subroutines and interrupt service routines. Indirect addressing modes use registers R0 and R1 as index registers.
9.4. Bit Addressable Locations
In addition to direct access to data memory organized as bytes, the sixteen data memory locations at 0x20
through 0x2F are also accessible as 128 individually addressable bits. Each bit has a bit address from
0x00 to 0x7F. Bit 0 of the byte at 0x20 has bit address 0x00 while bit 7 of the byte at 0x20 has bit address
0x07. Bit 7 of the byte at 0x2F has bit address 0x7F. A bit access is distinguished from a full byte access by
the type of instruction used (bit source or destination operands as opposed to a byte source or destination).
The MCS-51™ assembly language allows an alternate notation for bit addressing of the form XX.B where
XX is the byte address and B is the bit position within the byte. For example, the instruction:
MOV
C, 22.3h
moves the Boolean value at 0x13 (bit 3 of the byte at location 0x22) into the Carry flag.
9.5. Stack
A programmer's stack can be located anywhere in the 256-byte data memory. The stack area is designated using the Stack Pointer (SP, 0x81) SFR. The SP will point to the last location used. The next value
pushed on the stack is placed at SP+1 and then SP is incremented. A reset initializes the stack pointer to
location 0x07. Therefore, the first value pushed on the stack is placed at location 0x08, which is also the
first register (R0) of register bank 1. Thus, if more than one register bank is to be used, the SP should be
initialized to a location in the data memory not being used for data storage. The stack depth can extend up
to 256 bytes.
9.6. Special Function Registers
The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers
(SFRs). The SFRs provide control and data exchange with the CIP-51's resources and peripherals. The
CIP-51 duplicates the SFRs found in a typical 8051 implementation as well as implementing additional
Rev. 1.4
93
C8051F52x/F53x
SFRs used to configure and access the sub-systems unique to the MCU. This allows the addition of new
functionality while retaining compatibility with the MCS-51™ instruction set. Table 9.1 lists the SFRs implemented in the CIP-51 System Controller.
The SFR registers are accessed anytime the direct addressing mode is used to access memory locations
from 0x80 to 0xFF. SFRs with addresses ending in 0x0 or 0x8 (e.g. P0, TCON, IE, etc.) are bit-addressable
as well as byte-addressable. All other SFRs are byte-addressable only. Unoccupied addresses in the SFR
space are reserved for future use. Accessing these areas will have an indeterminate effect and should be
avoided. Refer to the corresponding pages of the data sheet, as indicated in Table 9.2, for a detailed
description of each register.
Table 9.1. Special Function Register (SFR) Memory Map
F8
F0
E8
E0
D8
D0
C8
C0
B8
B0
A8
A0
98
90
88
80
94
SPI0CN
B
ADC0CN
ACC
PCA0CN
PSW
TMR2CN
IP
OSCIFIN
IE
SCON0
P1
TCON
P0
0(8)
(bit addressable)
PCA0L
PCA0H PCA0CPL0 PCA0CPH0
VDDMON
P0MDIN
P1MDIN
EIP1
PCA0CPL1 PCA0CPH1 PCA0CPL2 PCA0CPH2
RSTSRC
XBR0
XBR1
IT01CF
EIE1
PCA0MD PCA0CPM0 PCA0CPM1 PCA0CPM2
REF0CN
P0SKIP
P1SKIP
P0MAT
REG0CN TMR2RLL TMR2RLH
TMR2L
TMR2H
P1MAT
ADC0GTL ADC0GTH ADC0LTL ADC0LTH P0MASK
ADC0TK
ADC0MX
ADC0CF
ADC0L
ADC0
P1MASK
OSCXCN OSCICN
OSCICL
FLKEY
CLKSEL
SPI0CFG SPI0CKR SPI0DAT P0MDOUT P1MDOUT
SBUF0
CPT0CN
CPT0MD
CPT0MX
LINADDR LINDATA
LINCF
TMOD
TL0
TL1
TH0
TH1
CKCON
PSCTL
SP
DPL
DPH
PCON
1(9)
2(A)
3(B)
4(C)
5(D)
6(E)
7(F)
Rev. 1.4
C8051F52x/F53x
Table 9.2. Special Function Registers
SFRs are listed in alphabetical order. All undefined SFR locations are reserved
Register
Address
Description
Page
ACC
0xE0
Accumulator
89
ADC0CF
0xBC
ADC0 Configuration
65
ADC0CN
0xE8
ADC0 Control
67
ADC0H
0xBE
ADC0
66
ADC0L
0xBD
ADC0
66
ADC0GTH
0xC4
ADC0 Greater-Than Data High Byte
69
ADC0GTL
0xC3
ADC0 Greater-Than Data Low Byte
69
ADC0LTH
0xC6
ADC0 Less-Than Data High Byte
70
ADC0LTL
0xC5
ADC0 Less-Than Data Low Byte
70
ADC0MX
0xBB
ADC0 Channel Select
64
ADC0TK
0xBA
ADC0 Tracking Mode Select
68
B
0xF0
B Register
89
CKCON
0x8E
Clock Control
188
CLKSEL
0xA9
Clock Select
143
CPT0CN
0x9B
Comparator0 Control
78
CPT0MD
0x9D
Comparator0 Mode Selection
80
CPT0MX
0x9F
Comparator0 MUX Selection
79
DPH
0x83
Data Pointer High
87
DPL
0x82
Data Pointer Low
87
EIE1
0xE6
Extended Interrupt Enable 1
102
EIP1
0xF6
Extended Interrupt Priority 1
103
FLKEY
0xB7
Flash Lock and Key
119
IE
0xA8
Interrupt Enable
100
IP
0xB8
Interrupt Priority
101
IT01CF
0xE4
INT0/INT1 Configuration
105
LINADDR
0x92
LIN indirect address pointer
172
LINCF
0x95
LIN master-slave and automatic baud rate selection
173
LINDATA
0x93
LIN indirect data buffer
172
OSCICL
0xB3
Internal Oscillator Calibration
138
Rev. 1.4
95
C8051F52x/F53x
Table 9.2. Special Function Registers (Continued)
SFRs are listed in alphabetical order. All undefined SFR locations are reserved
Register
Address
Description
Page
OSCICN
0xB2
Internal Oscillator Control
137
OSCXCN
0xB1
External Oscillator Control
142
P0
0x80
Port 0 Latch
129
P0MASK
0xC7
Port 0 Mask
131
P0MAT
0xD7
Port 0 Match
131
P0MDIN
0xF1
Port 0 Input Mode Configuration
129
P0MDOUT
0xA4
Port 0 Output Mode Configuration
130
P0SKIP
0xD4
Port 0 Skip
130
P1
0x90
Port 1 Latch
132
P1MASK
0xBF
Port 1 Mask
134
P1MAT
0xCF
Port 1 Match
134
P1MDIN
0xF2
Port 1 Input Mode Configuration
132
P1MDOUT
0xA5
Port 1 Output Mode Configuration
133
P1SKIP
0xD5
Port 1 Skip
133
PCA0CN
0xD8
PCA Control
206
PCA0CPH0
0xFC
PCA Capture 0 High
209
PCA0CPH1
0xEA
PCA Capture 1 High
209
PCA0CPH2
0xEC
PCA Capture 2 High
209
PCA0CPL0
0xFB
PCA Capture 0 Low
209
PCA0CPL1
0xE9
PCA Capture 1 Low
209
PCA0CPL2
0xEB
PCA Capture 2 Low
209
PCA0CPM0 0xDA
PCA Module 0 Mode
208
PCA0CPM1 0xDB
PCA Module 1 Mode
208
PCA0CPM2 0xDC
PCA Module 2 Mode
208
PCA0H
0xFA
PCA Counter High
209
PCA0L
0xF9
PCA Counter Low
209
PCA0MD
0xD9
PCA Mode
207
PCON
0x87
Power Control
91
PSCTL
0x8F
Program Store R/W Control
119
PSW
0xD0
Program Status Word
88
96
Rev. 1.4
C8051F52x/F53x
Table 9.2. Special Function Registers (Continued)
SFRs are listed in alphabetical order. All undefined SFR locations are reserved
Register
Address
Description
Page
REF0CN
0xD1
Voltage Reference Control
73
REG0CN
0xC9
Voltage Regulator Control
75
RSTSRC
0xEF
Reset Source Configuration/Status
112
SBUF0
0x99
UART0 Data Buffer
150
SCON0
0x98
UART0 Control
149
SP
0x81
Stack Pointer
87
SPI0CFG
0xA1
SPI Configuration
157
SPI0CKR
0xA2
SPI Clock Rate Control
159
SPI0CN
0xF8
SPI Control
158
SPI0DAT
0xA3
SPI Data
160
TCON
0x88
Timer/Counter Control
186
TH0
0x8C
Timer/Counter 0 High
189
TH1
0x8D
Timer/Counter 1 High
189
TL0
0x8A
Timer/Counter 0 Low
189
TL1
0x8B
Timer/Counter 1 Low
189
TMOD
0x89
Timer/Counter Mode
187
TMR2CN
0xC8
Timer/Counter 2 Control
193
TMR2H
0xCD
Timer/Counter 2 High
194
TMR2L
0xCC
Timer/Counter 2 Low
194
TMR2RLH
0xCB
Timer/Counter 2 Reload High
194
TMR2RLL
0xCA
Timer/Counter 2 Reload Low
194
VDDMON
0xFF
VDD Monitor Control
109
XBR0
0xE1
Port I/O Crossbar Control 0
127
XBR1
0xE2
Port I/O Crossbar Control 1
128
Rev. 1.4
97
C8051F52x/F53x
10. Interrupt Handler
The C8051F52x/F52xA/F53x/F53xA family includes an extended interrupt system with two selectable priority levels. The allocation of interrupt sources between on-chip peripherals and external input pins varies
according to the specific version of the device. Each interrupt source has one or more associated interruptpending flag(s) located in an SFR. When a peripheral or external source meets a valid interrupt condition,
the associated interrupt-pending flag is set to logic 1.
If interrupts are enabled for the source, an interrupt request is generated when the interrupt-pending flag is
set. As soon as execution of the current instruction is complete, the CPU generates an LCALL to a predetermined address to begin execution of an interrupt service routine (ISR). Each ISR must end with an RETI
instruction, which returns program execution to the next instruction that would have been executed if the
interrupt request had not occurred. If interrupts are not enabled, the interrupt-pending flag is ignored by the
hardware and program execution continues as normal. (The interrupt-pending flag is set to logic 1 regardless of the interrupt's enable/disable state.)
Each interrupt source can be individually enabled or disabled through the use of an associated interrupt
enable bit in the Interrupt Enable and Extended Interrupt Enable SFRs. However, interrupts must first be
globally enabled by setting the EA bit (IE.7) to logic 1 before the individual interrupt enables are recognized. Setting the EA bit to logic 0 disables all interrupt sources regardless of the individual interruptenable settings. Note that interrupts which occur when the EA bit is set to logic 0 will be held in a pending
state, and will not be serviced until the EA bit is set back to logic 1.
Some interrupt-pending flags are automatically cleared by the hardware when the CPU vectors to the ISR.
However, most are not cleared by the hardware and must be cleared by software before returning from the
ISR. If an interrupt-pending flag remains set after the CPU completes the return-from-interrupt (RETI)
instruction, a new interrupt request will be generated immediately and the CPU will re-enter the ISR after
the completion of the next instruction.
10.1. MCU Interrupt Sources and Vectors
The C8051F52x/F52xA/F53x/F53xA MCUs support 15 interrupt sources. Software can simulate an interrupt by setting any interrupt-pending flag to logic 1. If interrupts are enabled for the flag, an interrupt
request will be generated and the CPU will vector to the ISR address associated with the interrupt-pending
flag. MCU interrupt sources, associated vector addresses, priority order, and control bits are summarized
in Table 10.1 on page 99. Refer to the data sheet section associated with a particular on-chip peripheral for
information regarding valid interrupt conditions for the peripheral and the behavior of its interrupt-pending
flag(s).
10.2. Interrupt Priorities
Each interrupt source can be individually programmed to one of two priority levels: low or high. A low priority interrupt service routine can be preempted by a high priority interrupt. A high priority interrupt cannot be
preempted. Each interrupt has an associated interrupt priority bit in an SFR (IP or EIP1) used to configure
its priority level. Low priority is the default. If two interrupts are recognized simultaneously, the interrupt with
the higher priority is serviced first. If both interrupts have the same priority level, a fixed priority order is
used to arbitrate, given in Table 10.1.
10.3. Interrupt Latency
Interrupt response time depends on the state of the CPU when the interrupt occurs. Pending interrupts are
sampled and priority decoded each system clock cycle. Therefore, the fastest possible response time is 5
system clock cycles: 1 clock cycle to detect the interrupt and 4 clock cycles to complete the LCALL to the
ISR. If an interrupt is pending when a RETI is executed, a single instruction is executed before an LCALL
is made to service the pending interrupt. Therefore, the maximum response time for an interrupt (when no
other interrupt is currently being serviced or the new interrupt is of greater priority) occurs when the CPU is
performing an RETI instruction followed by a DIV as the next instruction. In this case, the response time is
98
Rev. 1.4
C8051F52x/F53x
18 system clock cycles: 1 clock cycle to detect the interrupt, 5 clock cycles to execute the RETI, 8 clock
cycles to complete the DIV instruction, and 4 clock cycles to execute the LCALL to the ISR. If the CPU is
executing an ISR for an interrupt with equal or higher priority, the new interrupt will not be serviced until the
current ISR completes, including the RETI and following instruction.
Interrupt Priority
Vector Order
Pending Flag
Cleared by HW?
Interrupt Source
Bit addressable?
Table 10.1. Interrupt Summary
Priority
Control
Always
Enabled
Always
Highest
Reset
0x0000
Top
None
External Interrupt 0(INT0)
0x0003
0
IE0 (TCON.1)
Y
Y
EX0 (IE.0)
PX0 (IP.0)
Timer 0 Overflow
0x000B
1
TF0 (TCON.5)
Y
Y
ET0 (IE.1)
PT0 (IP.1)
External Interrupt 1(INT0)
0x0013
2
IE1 (TCON.3)
Y
Y
EX1 (IE.2)
PX1 (IP.2)
Timer 1 Overflow
0x001B
3
TF1 (TCON.7)
Y
Y
ET1 (IE.3)
PT1 (IP.3)
UART
0x0023
4
RI0 (SCON0.0)
TI0 (SCON0.1)
Y
N
ES0 (IE.4)
PS0 (IP.4)
Timer 2 Overflow
0x002B
5
TF2H (TMR2CN.7)
TF2L (TMR2CN.6)
Y
N
ET2 (IE.5)
PT2 (IP.5)
SPI0
0x0033
6
SPIF (SPI0CN.7)
WCOL (SPI0CN.6)
MODF (SPI0CN.5)
RXOVRN (SPI0CN.4)
Y
N
ESPI0
(IE.6)
PSPI0
(IP.6)
ADC0 Window Comparator
0x003B
7
AD0WINT
(ADC0CN.3)
Y
N
EWADC0
(EIE1.0)
PWADC0
(EIP1.0)
ADC0 End of Conversion
0x0043
8
AD0INT (ADC0CN.5)
Y
N
EADC0
(EIE1.1)
PADC0
(EIP1.1)
Programmable Counter
Array
0x004B
9
CF (PCA0CN.7)
CCFn (PCA0CN.n)
Y
N
EPCA0
(EIE1.2)
PPCA0
(EIP1.2)
Comparator Falling Edge
0x0053
10
CP0FIF (CPT0CN.4)
N
N
ECPF
(EIE1.3)
PCPF
(EIP1.3)
Comparator Rising Edge
0x005B
11
CP0RIF (CPT0CN.5)
N
N
ECPR
(EIE1.4)
PCPR
(EIP1.4)
LIN Interrupt
0x0063
12
LININT (LINST.3)
N
N*
ELIN
(EIE1.5)
PLIN
(EIP1.5)
Voltage Regulator Dropout 0x006B
13
N/A
N/A N/A
EREG0
(EIE1.6)
PREG0
(EIP1.6)
Port Match
14
N/A
N/A N/A
EMAT
(EIE1.7)
PMAT
(EIP1.7)
0x0073
N/A N/A
Enable
Flag
Note: Software must set the RSTINT bit (LINCTRL.3) to clear the LININT flag.
Rev. 1.4
99
C8051F52x/F53x
10.4. Interrupt Register Descriptions
The SFRs used to enable the interrupt sources and set their priority level are described below. Refer to the
data sheet section associated with a particular on-chip peripheral for information regarding valid interrupt
conditions for the peripheral and the behavior of its interrupt-pending flag(s).
SFR Definition 10.1. IE: Interrupt Enable
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
EA
ESPI0
ET2
ES0
ET1
EX1
ET0
EX0
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Bit
Addressable
SFR Address:
0xA8
Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
100
EA: Global Interrupt Enable.
This bit globally enables/disables all interrupts. It overrides the individual interrupt mask settings.
0: Disable all interrupt sources.
1: Enable each interrupt according to its individual mask setting.
ESPI0: Enable Serial Peripheral Interface (SPI0) Interrupt.
This bit sets the masking of the SPI0 interrupts.
0: Disable all SPI0 interrupts.
1: Enable interrupt requests generated by SPI0.
ET2: Enable Timer 2 Interrupt.
This bit sets the masking of the Timer 2 interrupt.
0: Disable Timer 2 interrupt.
1: Enable interrupt requests generated by the TF2L or TF2H flags.
ES0: Enable UART0 Interrupt.
This bit sets the masking of the UART0 interrupt.
0: Disable UART0 interrupt.
1: Enable UART0 interrupt.
ET1: Enable Timer 1 Interrupt.
This bit sets the masking of the Timer 1 interrupt.
0: Disable all Timer 1 interrupt.
1: Enable interrupt requests generated by the TF1 flag.
EX1: Enable External Interrupt 1.
This bit sets the masking of the external interrupt 1.
0: Disable external interrupt 1.
1: Enable extern interrupt 1 requests.
ET0: Enable Timer 0 Interrupt.
This bit sets the masking of the Timer 0 interrupt.
0: Disable all Timer 0 interrupt.
1: Enable interrupt requests generated by the TF0 flag.
EX0: Enable External Interrupt 0.
This bit sets the masking of the external interrupt 0.
0: Disable external interrupt 0.
1: Enable extern interrupt 0 requests.
Rev. 1.4
C8051F52x/F53x
SFR Definition 10.2. IP: Interrupt Priority
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
-
PSPI0
PT2
PS0
PT1
PX1
PT0
PX0
10000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Bit
Addressable
SFR Address:
0xB8
Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
UNUSED. Read = 1b; Write = don't care.
PSPI0: Serial Peripheral Interface (SPI0) Interrupt Priority Control.
This bit sets the priority of the SPI0 interrupt.
0: SPI0 interrupt set to low priority level.
1: SPI0 interrupt set to high priority level.
PT2: Timer 2 Interrupt Priority Control.
This bit sets the priority of the Timer 2 interrupt.
0: Timer 2 interrupt set to low priority level.
1: Timer 2 interrupt set to high priority level.
PS0: UART0 Interrupt Priority Control.
This bit sets the priority of the UART0 interrupt.
0: UART0 interrupt set to low priority level.
1: UART0 interrupt set to high priority level.
PT1: Timer 1 Interrupt Priority Control.
This bit sets the priority of the Timer 1 interrupt.
0: Timer 1 interrupt set to low priority level.
1: Timer 1 interrupt set to high priority level.
PX1: External Interrupt 0 Priority Control.
This bit sets the priority of the external interrupt 1.
0: INT1 interrupt set to low priority level.
1: INT1 interrupt set to high priority level.
PT0: Timer 0 Interrupt Priority Control.
This bit sets the priority of the Timer 0 interrupt.
0: Timer 0 interrupt set to low priority level.
1: Timer 0 interrupt set to high priority level.
PX0: External Interrupt 0 Priority Control.
This bit sets the priority of the external interrupt 0.
0: INT0 interrupt set to low priority level.
1: INT0 interrupt set to high priority level.
Rev. 1.4
101
C8051F52x/F53x
SFR Definition 10.3. EIE1: Extended Interrupt Enable 1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
EMAT
EREG0
ELIN
ECPR
ECPF
EPCA0
EADC0
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
R/W
Bit0
SFR Address:
Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
102
EMAT: Enable Port Match Interrupt.
This bit sets the masking of the Port Match interrupt.
0: Disable the Port Match interrupt.
1: Enable the Port Match interrupt.
EREG0: Enable Voltage Regulator Interrupt.
This bit sets the masking of the Voltage Regulator Dropout interrupt.
0: Disable the Voltage Regulator Dropout interrupt.
1: Enable the Voltage Regulator Dropout interrupt.
ELIN: Enable LIN Interrupt.
This bit sets the masking of the LIN interrupt.
0: Disable LIN interrupts.
1: Enable LIN interrupt requests.
ECPR: Enable Comparator 0 Rising Edge Interrupt
This bit sets the masking of the CP0 Rising Edge interrupt.
0: Disable CP0 Rising Edge Interrupt.
1: Enable CP0 Rising Edge Interrupt.
ECPF: Enable Comparator 0 Falling Edge Interrupt
This bit sets the masking of the CP0 Falling Edge interrupt.
0: Disable CP0 Falling Edge Interrupt.
1: Enable CP0 Falling Edge Interrupt.
EPCA0: Enable Programmable Counter Array (PCA0) Interrupt.
This bit sets the masking of the PCA0 interrupts.
0: Disable all PCA0 interrupts.
1: Enable interrupt requests generated by PCA0.
EADC0: Enable ADC0 Conversion Complete Interrupt.
This bit sets the masking of the ADC0 Conversion Complete interrupt.
0: Disable ADC0 Conversion Complete interrupt.
1: Enable interrupt requests generated by the AD0INT flag.
EWADC0: Enable ADC0 Window Comparison Interrupt.
This bit sets the masking of the ADC0 Window Comparison interrupt.
0: Disable ADC0 Window Comparison interrupt.
1: Enable interrupt requests generated by the AD0WINT flag.
Rev. 1.4
Reset Value
EWADC0 00000000
0xE6
C8051F52x/F53x
SFR Definition 10.4. EIP1: Extended Interrupt Priority 1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PMAT
PREG0
PLIN
PCPR
PCPF
PPAC0
PREG0
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
R/W
Bit0
SFR Address:
Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
Reset Value
PWADC0 00000000
0xF6
PMAT. Port Match Interrupt Priority Control.
This bit sets the priority of the Port Match interrupt.
0: Port Match interrupt set to low priority level.
1: Port Match interrupt set to high priority level.
PREG0: Voltage Regulator Interrupt Priority Control.
This bit sets the priority of the Voltage Regulator interrupt.
0: Voltage Regulator interrupt set to low priority level.
1: Voltage Regulator interrupt set to high priority level.
PLIN: LIN Interrupt Priority Control.
This bit sets the priority of the CP0 interrupt.
0: LIN interrupt set to low priority level.
1: LIN interrupt set to high priority level.
PCPR: Comparator Rising Edge Interrupt Priority Control.
This bit sets the priority of the Rising Edge Comparator interrupt.
0: Comparator interrupt set to low priority level.
1: Comparator interrupt set to high priority level.
PCPF: Comparator falling Edge Interrupt Priority Control.
This bit sets the priority of the Falling Edge Comparator interrupt.
0: Comparator interrupt set to low priority level.
1: Comparator interrupt set to high priority level.
PPAC0: Programmable Counter Array (PCA0) Interrupt Priority Control.
This bit sets the priority of the PCA0 interrupt.
0: PCA0 interrupt set to low priority level.
1: PCA0 interrupt set to high priority level.
PREG0: ADC0 Conversion Complete Interrupt Priority Control.
This bit sets the priority of the ADC0 Conversion Complete interrupt.
0: ADC0 Conversion Complete interrupt set to low priority level.
1: ADC0 Conversion Complete interrupt set to high priority level.
PWADC0: ADC0 Window Comparison Interrupt Priority Control.
This bit sets the priority of the ADC0 Window Comparison interrupt.
0: ADC0 Window Comparison interrupt set to low priority level.
1: ADC0 Window Comparison interrupt set to high priority level.
Rev. 1.4
103
C8051F52x/F53x
10.5. External Interrupts
The INT0 and INT0 external interrupt sources are configurable as active high or low, edge or level sensitive. The IN0PL (INT0 Polarity) and IN1PL (INT0 Polarity) bits in the IT01CF register select active high or
active low; the IT0 and IT1 bits in TCON (Section “18.1. Timer 0 and Timer 1” on page 182) select level or
edge sensitive. The table below lists the possible configurations.
IT0
IN0PL
INT0 Interrupt
IT1
IN1PL
INT1 Interrupt
1
0
Active low, edge sensitive
1
0
Active low, edge sensitive
1
1
Active high, edge sensitive
1
1
Active high, edge sensitive
0
0
Active low, level sensitive
0
0
Active low, level sensitive
0
1
Active high, level sensitive
0
1
Active high, level sensitive
INT0 and INT0 are assigned to Port pins as defined in the IT01CF register (see SFR Definition 10.5). Note
that INT0 and INT0 Port pin assignments are independent of any Crossbar assignments. INT0 and INT0
will monitor their assigned Port pins without disturbing the peripheral that was assigned the Port pin via the
Crossbar. To assign a Port pin only to INT0 and/or INT0, configure the Crossbar to skip the selected pin(s).
This is accomplished by setting the associated bit in register XBR0 (see Section “13.1. Priority Crossbar
Decoder” on page 122 for complete details on configuring the Crossbar).
In the typical configuration, the external interrupt pins should be skipped in the crossbar and configured as
open-drain with the pin latch set to 1. See Section “13. Port Input/Output” on page 120 for more information.
IE0 (TCON.1) and IE1 (TCON.3) serve as the interrupt-pending flags for the INT0 and INT0 external interrupts, respectively. If an INT0 or INT0 external interrupt is configured as edge-sensitive, the corresponding
interrupt-pending flag is automatically cleared by the hardware when the CPU vectors to the ISR. When
configured as level sensitive, the interrupt-pending flag remains logic 1 while the input is active as defined
by the corresponding polarity bit (IN0PL or IN1PL); the flag remains logic 0 while the input is inactive. The
external interrupt source must hold the input active until the interrupt request is recognized. It must then
deactivate the interrupt request before execution of the ISR completes or another interrupt request will be
generated.
104
Rev. 1.4
C8051F52x/F53x
SFR Definition 10.5. IT01CF: INT0/INT1 Configuration
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
IN1PL
IN1SL2
IN1SL1
IN1SL0
IN0PL
IN0SL2
IN0SL1
IN0SL0
00000001
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
0xE4
Note: Refer to SFR Definition 18.1. “TCON: Timer Control” on page 186 for INT0/1 edge- or level-sensitive interrupt selection.
Bit 7:
IN1PL: INT0 Polarity
0: INT0 input is active low.
1: INT0 input is active high.
Bits 6–4: IN1SL2–0: INT0 Port Pin Selection Bits
These bits select which Port pin is assigned to INT0. Note that this pin assignment is independent of the Crossbar; INT0 will monitor the assigned Port pin without disturbing the
peripheral that has been assigned the Port pin via the Crossbar. The Crossbar will not
assign the Port pin to a peripheral if it is configured to skip the selected pin (accomplished by
setting to 1 the corresponding bit in register P0SKIP).
IN1SL2-0
INT1 Port Pin
000
P0.0
001
P0.1
010
P0.2
011
P0.3
100
P0.4
101
P0.5
110
P0.6*
111
P0.7*
Note: Available in the C80151F53x/C8051F53xA parts.
IN0PL: INT0 Polarity
0: INT0 interrupt is active low.
1: INT0 interrupt is active high.
Bits 2–0: INT0SL2–0: INT0 Port Pin Selection Bits
These bits select which Port pin is assigned to INT0. Note that this pin assignment is independent of the Crossbar. INT0 will monitor the assigned Port pin without disturbing the
peripheral that has been assigned the Port pin via the Crossbar. The Crossbar will not
assign the Port pin to a peripheral if it is configured to skip the selected pin (accomplished by
setting to 1 the corresponding bit in register P0SKIP).
Bit 3:
IN0SL2-0
INT0 Port Pin
000
P0.0
001
P0.1
010
P0.2
011
P0.3
100
P0.4
101
P0.5
110
P0.6*
111
P0.7*
Note: Available in the C80151F53x/C8051F53xA parts.
Rev. 1.4
105
C8051F52x/F53x
11. Reset Sources
Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this
reset state, the following occur:

CIP-51 halts program execution
 Special Function Registers (SFRs) are initialized to their defined reset values
 External Port pins are forced to a known state
 Interrupts and timers are disabled.
All SFRs are reset to the predefined values noted in the SFR detailed descriptions. The contents of internal
data memory are unaffected during a reset; any previously stored data is preserved. However, since the
stack pointer SFR is reset, the stack is effectively lost, even though the data on the stack is not altered.
The Port I/O latches are reset to 0xFF (all logic ones) in open-drain mode. Weak pullups are enabled during and after the reset. For VDD Monitor and power-on resets, the RST pin is driven low until the device
exits the reset state.
On exit from the reset state, the program counter (PC) is reset, and the system clock defaults to the internal oscillator. Refer to Section “14. Oscillators” on page 135 for information on selecting and configuring
the system clock source. The Watchdog Timer is enabled with the system clock divided by 12 as its clock
source (Section “19.3. Watchdog Timer Mode” on page 203 details the use of the Watchdog Timer). Program execution begins at location 0x0000.
VDD
Supply Monitor
(VDDMON0)
+
-
Px.x
Comparator 0
+
-
Supply Monitor
(VDDMON1)
C0RSEF
+
-
Missing
Clock
Detector
(oneshot)
EN
Enable
(wired-OR)
Px.x
Power On
Reset
Enable
'0'
(wired-OR)
Reset
Funnel
PCA
WDT
(Software Reset)
SWRSF
System
Clock
Illegal Flash
Operation
WDT
Enable
MCD
Enable
EN
CIP-51
Microcontroller
Core
System Reset
Extended Interrupt
Handler
Figure 11.1. Reset Sources
106
Rev. 1.4
/RST
C8051F52x/F53x
11.1. Power-On Reset
During power-up, the device is held in a reset state and the RST pin is driven low until VDD settles above
VRST. VDD ramp time is defined as how fast VDD ramps from 0 V to VRST. An additional delay (TPORDelay)
occurs before the device is released from reset. The VRST threshold and TPORDelay are specified in
Table 2.8, “Reset Electrical Characteristics,” on page 32. Figure 11.2 plots the power-on and VDD monitor
reset timing.
Note: Please refer to Section “20.4. VDD Monitors and VDD Ramp Time” on page 211 for definition of VRST and VDD
ramp time in older silicon revisions A and B.
On exit from a power-on reset, the PORSF flag (RSTSRC.1) is set by hardware to logic 1. When PORSF is
set, all of the other reset flags in the RSTSRC Register are indeterminate (PORSF is cleared by all other
resets). Since all resets cause program execution to begin at the same location (0x0000), software can
read the PORSF flag to determine if a power-up was the cause of reset. The contents of internal data
memory should be assumed to be undefined after a power-on reset. Both the VDD monitors (VDDMON0
and VDDMON1) are enabled following a power-on reset.
volts
Note: Please refer to Section “11.2.1. VDD Monitor Thresholds and Minimum VDD” on page 108 for
recommendations related to minimum VDD.
VDD
VD
D
V R ST
1.0
t
Logic H IG H
/RST
T P O R D e lay
Logic LO W
VDD
M onitor
R eset
P ow er-O n
R eset
Figure 11.2. Power-On and VDD Monitor Reset Timing
Rev. 1.4
107
C8051F52x/F53x
11.2. Power-Fail Reset / VDD Monitors (VDDMON0 and VDDMON1)
C8051F52x-C/F53x-C devices include two VDD monitors: a standard VDD monitor (VDDMON0) and a
level-sensitive VDD monitor (VDDMON1). VDDMON0 is primarily intended for setting a higher threshold to
allow safe erase or write of Flash memory from firmware. VDDMON1 is used to hold the device in a reset
state during power-up and brownout conditions.
Note: VDDMON1 is not present in older silicon revisions A and B. Please refer to Section “20.4. VDD Monitors and
VDD Ramp Time” on page 211 for more details.
When a power-down transition or power irregularity causes VDD to drop below VRST, the power supply
monitors (VDDMON0 and VDDMON1) will drive the RST pin low and hold the CIP-51 in a reset state (see
Figure 11.2). When VDD returns to a level above VRST, the CIP-51 will be released from the reset state.
Note that even though internal data memory contents are not altered by the power-fail reset, it is impossible to determine if VDD dropped below the level required for data retention. If the PORSF flag reads 1, the
data may no longer be valid.
VDDMON0 is enabled and is selected as a reset source after power-on resets; however its defined state
(enabled/disabled) is not altered by any other reset source. For example, if VDDMON0 is disabled by software, and a software reset is performed, VDDMON0 will still be disabled after that reset.
VDDMON1 is enabled and is selected as a reset source after power-on reset and any other type of reset.
There is no register setting that can disable this level-sensitive VDD monitor as a reset source.
To protect the integrity of Flash contents, the VDD monitor (VDDMON0) must be enabled to the
higher setting (VDMLVL = '1') and selected as a reset source if software contains routines which
erase or write Flash memory. If the VDD monitor is not enabled and set to the higher setting, any
erase or write performed on Flash memory will cause a Flash Error device reset.
Note: Please refer to Section “20.5. VDD Monitor (VDDMON0) High Threshold Setting” on page 212 for important
notes related to the VDD Monitor high threshold setting in older silicon revisions A and B.
The VDD monitor (VDDMON0) must be enabled before it is selected as a reset source. Selecting the
VDDMON0 as a reset source before it is enabled and stabilized may cause a system reset. The procedure
for re-enabling the VDD monitor and configuring the VDD monitor as a reset source is shown below:
1. Enable the VDD monitor (VDMEN bit in VDDMON = 1).
2. Wait for the VDD monitor to stabilize (see Table 2.8 on page 32 for the VDD Monitor turn-on time). Note:
This delay should be omitted if software contains routines which write or erase Flash memory.
3. Select the VDD monitor as a reset source (PORSF bit in RSTSRC = 1).
See Figure 11.2 for VDD monitor timing; note that the reset delay is not incurred after a VDD monitor reset.
See Table 2.8 on page 32 for complete electrical characteristics of the VDD monitor.
Note: Software should take care not to inadvertently disable the VDD Monitor (VDDMON0) as a reset
source when writing to RSTSRC to enable other reset sources or to trigger a software reset. All
writes to RSTSRC should explicitly set PORSF to '1' to keep the VDD Monitor enabled as a reset
source.
11.2.1. VDD Monitor Thresholds and Minimum VDD
The minimum operating digital supply voltage (VDD) is specified as 2.0 V in Table 2.2 on page 26. The voltage at which the MCU is released from reset (VRST) can be as low as 1.65 V based on the VDD Monitor
thresholds that are specified in Table 2.8 on page 32. This could allow code execution during the power-up
108
Rev. 1.4
C8051F52x/F53x
ramp or during a brownout condition even when VDD is below the specified minimum of 2.0 V. There are
two possible ways to handle this transitional period as described below:
If using the on-chip regulator (REG0) at the 2.6 V setting (default), it is recommended that user software
set the VDDMON0 threshold to its high setting (VRST-HIGH) as soon as possible after reset by setting the
VDMLVL bit to 1 in SFR Definition 11.1 (VDDMON). In this typical configuration, no external hardware or
additional software routines are necessary to monitor the VDD level.
Note: Please refer to Section “20.5. VDD Monitor (VDDMON0) High Threshold Setting” on page 212 for important
notes related to the VDD Monitor high threshold setting in older silicon revisions A and B.
If using the on-chip regulator (REG0) at the 2.1 V setting or if directly driving VDD with REG0 disabled, the
user system (software/hardware) should monitor VDD at power-on and also during device operation. The
two key parameters that can be affected when VDD < 2.0 V are: internal oscillator frequency (Table 2.11 on
page 34) and minimum ADC tracking time (Table 2.3 on page 28).
SFR Definition 11.1. VDDMON: VDD Monitor Control
R/W
R
R/W
R
R
R
R
R
Reset Value
VDMEN VDDSTAT VDMLVL VDM1EN Reserved Reserved Reserved Reserved 1v010000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
0xFF
Bit7:
VDMEN: VDD Monitor Enable (VDDMON0).
This bit turns the VDD monitor circuit on/off. The VDD Monitor cannot generate system
resets until it is also selected as a reset source in register RSTSRC (SFR Definition 11.2).
The VDD Monitor can be allowed to stabilize before it is selected as a reset source. Selecting the VDD monitor as a reset source before it has stabilized may generate a system
reset. See Table 2.8 on page 32 for the minimum VDD Monitor turn-on time.
0: VDD Monitor Disabled.
1: VDD Monitor Enabled (default).
Bit6:
VDDSTAT: VDD Status.
This bit indicates the current power supply status (VDD Monitor output).
0: VDD is at or below the VDD Monitor (VDDMON0) Threshold.
1: VDD is above the VDD Monitor (VDDMON0) Threshold.
Bit5:
VDMLVL: VDD Level Select.
0: VDD Monitor (VDDMON0) Threshold is set to VRST-LOW (default).
1: VDD Monitor (VDDMON0) Threshold is set to VRST-HIGH. This setting is required for any
system that includes code that writes to and/or erases Flash.
Bit4:
VDM1EN*: Level-sensitive VDD Monitor Enable (VDDMON1).
This bit turns the VDD monitor circuit on/off. If turned on, it is also selected as a reset
source, and can generate a system reset.
0: Level-sensitive VDD Monitor Disabled.
1: Level-sensitive VDD Monitor Enabled (default).
Bits3–0: RESERVED. Read = Variable. Write = don’t care.
*Note: Available only on the C8051F52x-C/F53x-C devices
Rev. 1.4
109
C8051F52x/F53x
11.3. External Reset
The external RST pin provides a means for external circuitry to force the device into a reset state. Asserting an active-low signal on the RST pin generates a reset; an external pullup and/or decoupling of the RST
pin may be necessary to avoid erroneous noise-induced resets. See Table 2.8 on page 32 for complete
RST pin specifications. The PINRSF flag (RSTSRC.0) is set on exit from an external reset.
Note: Please refer to Section “20.6. Reset Low Time” on page 212 for restrictions on reset low time in older silicon
revisions A and B.
11.4. Missing Clock Detector Reset
The Missing Clock Detector (MCD) is a one-shot circuit that is triggered by the system clock. If the system
clock remains high or low for more than 100 µs, the one-shot will time out and generate a reset. After a
MCD reset, the MCDRSF flag (RSTSRC.2) will read 1, signifying the MCD as the reset source; otherwise,
this bit reads 0. Writing a 1 to the MCDRSF bit enables the Missing Clock Detector; writing a 0 disables it.
The state of the RST pin is unaffected by this reset.
11.5. Comparator Reset
Comparator0 can be configured as a reset source by writing a 1 to the C0RSEF flag (RSTSRC.5).
Comparator0 should be enabled and allowed to settle prior to writing to C0RSEF to prevent any turn-on
chatter on the output from generating an unwanted reset. The Comparator0 reset is active-low: if the noninverting input voltage (on CP0+) is less than the inverting input voltage (on CP0-), the device is put into
the reset state. After a Comparator0 reset, the C0RSEF flag (RSTSRC.5) will read 1 signifying
Comparator0 as the reset source; otherwise, this bit reads 0. The state of the RST pin is unaffected by this
reset.
11.6. PCA Watchdog Timer Reset
The programmable Watchdog Timer (WDT) function of the Programmable Counter Array (PCA) can be
used to prevent software from running out of control during a system malfunction. The PCA WDT function
can be enabled or disabled by software as described in Section “19.3. Watchdog Timer Mode” on
page 203; the WDT is enabled and clocked by SYSCLK / 12 following any reset. If a system malfunction
prevents user software from updating the WDT, a reset is generated and the WDTRSF bit (RSTSRC.5) is
set to 1. The state of the RST pin is unaffected by this reset.
11.7. Flash Error Reset
If a Flash read/write/erase or program read targets an illegal address, a system reset is generated. This
may occur due to any of the following:





A Flash write or erase is attempted above user code space. This occurs when PSWE is set to 1 and a
MOVX write operation targets an address above the Lock Byte address.
A Flash read is attempted above user code space. This occurs when a MOVC operation targets an
address above the Lock Byte address.
A program read is attempted above user code space. This occurs when user code attempts to branch
to an address above the Lock Byte address.
A Flash read, write or erase attempt is restricted due to a Flash security setting (see Section
“12.4. Security Options” on page 117).
A Flash write or erase is attempted while the VDD Monitor (VDDMON0) is disabled or not set to its high
threshold setting.
The FERROR bit (RSTSRC.6) is set following a Flash error reset. The state of the RST pin is unaffected by
this reset.
110
Rev. 1.4
C8051F52x/F53x
11.8. Software Reset
Software may force a reset by writing a 1 to the SWRSF bit (RSTSRC.4). The SWRSF bit will read 1 following a software forced reset. The state of the RST pin is unaffected by this reset.
Rev. 1.4
111
C8051F52x/F53x
SFR Definition 11.2. RSTSRC: Reset Source
R/W
—
Bit7
R
R/W
FERROR C0RSEF
Bit6
Bit5
R/W
SWRSF
Bit4
R
R/W
WDTRSF MCDRSF
Bit3
Bit2
R/W
R
Reset Value
PORSF
PINRSF
Variable
Bit1
Bit0
SFR Address:
0xEF
Note: Software should avoid read modify write instructions when writing values to RSTSRC.
Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
112
UNUSED. Read = 1, Write = don't care.
FERROR: Flash Error Indicator.
0: Source of last reset was not a Flash read/write/erase error.
1: Source of last reset was a Flash read/write/erase error.
C0RSEF: Comparator0 Reset Enable and Flag.
0: Read: Source of last reset was not Comparator0.
Write: Comparator0 is not a reset source.
1: Read: Source of last reset was Comparator0.
Write: Comparator0 is a reset source (active-low).
SWRSF: Software Reset Force and Flag.
0: Read: Source of last reset was not a write to the SWRSF bit.
Write: No Effect.
1: Read: Source of last reset was a write to the SWRSF bit.
Write: Forces a system reset.
WDTRSF: Watchdog Timer Reset Flag.
0: Source of last reset was not a WDT timeout.
1: Source of last reset was a WDT timeout.
MCDRSF: Missing Clock Detector Flag.
0: Read: Source of last reset was not a Missing Clock Detector timeout.
Write: Missing Clock Detector disabled.
1: Read: Source of last reset was a Missing Clock Detector timeout.
Write: Missing Clock Detector enabled; triggers a reset if a missing clock condition is
detected.
PORSF: Power-On Reset Force and Flag.
This bit is set anytime a power-on reset occurs. Writing this bit enables/disables the VDD
monitor (VDDMON0) as a reset source. Note: writing 1 to this bit before the VDD monitor is enabled and stabilized may cause a system reset. See register VDDMON (SFR
Definition 11.1)
0: Read: Last reset was not a power-on or VDD monitor reset.
Write: VDD monitor (VDDMON0) is not a reset source.
1: Read: Last reset was a power-on or VDD monitor reset; all other reset flags indeterminate.
Write: VDD monitor (VDDMON0) is a reset source.
PINRSF: HW Pin Reset Flag.
0: Source of last reset was not RST pin.
1: Source of last reset was RST pin.
Rev. 1.4
C8051F52x/F53x
12. Flash Memory
On-chip, re-programmable Flash memory is included for program code and non-volatile data storage. The
Flash memory can be programmed in-system through the C2 interface or by software using the MOVX
write instruction. Once cleared to logic 0, a Flash bit must be erased to set it back to logic 1. Flash bytes
would typically be erased (set to 0xFF) before being reprogrammed. The write and erase operations are
automatically timed by hardware for proper execution; data polling to determine the end of the write/erase
operations is not required. Code execution is stalled during Flash write/erase operations. Refer to
Table 2.9 on page 33 for complete Flash memory electrical characteristics.
12.1. Programming The Flash Memory
The simplest means of programming the Flash memory is through the C2 interface using programming
tools provided by Silicon Laboratories or a third party vendor. This is the only means for programming a
non-initialized device. For details on the C2 commands to program Flash memory, see Section “21. C2
Interface” on page 214.
To protect the integrity of Flash contents, the VDD monitor must be enabled to the higher setting
(VDMLVL = '1') and selected as a reset source if software contains routines which erase or write Flash
memory. If the VDD monitor is not enabled, any erase or write performed on Flash memory will cause a
Flash Error device reset. See Section “11.2. Power-Fail Reset / VDD Monitors (VDDMON0 and
VDDMON1)” on page 108 for more information regarding the VDD monitor and the high threshold setting.
The VDD monitor must be enabled before it is selected as a reset source. Selecting the VDD monitor
as a reset source before it is enabled and stabilized may cause a system reset. The procedure for reenabling the VDD monitor and configuring the VDD monitor as a reset source is shown below:
1. Enable the VDD monitor (VDMEN bit in VDDMON = 1).
2. Wait for the VDD monitor to stabilize (see Table 2.8 on page 32 for the VDD Monitor turn-on time). Note:
This delay should be omitted if software contains routines which write or erase Flash memory.
3. Select the VDD monitor as a reset source (PORSF bit in RSTSRC = 1).
Note: 8-bit MOVX instructions cannot be used to erase or write to Flash memory at addresses higher than
0x00FF.
Important Note: For –I (industrial Grade) parts, flash should be programmed (erase/write) at a minimum temperature of 0 °C for reliable flash operation across the entire temperature range of –40 to
+125 °C. This minimum programming temperature does not apply to –A (Automotive Grade) parts.
12.1.1. Flash Lock and Key Functions
Flash writes and erases by user software are protected with a lock and key function. The Flash Lock and
Key Register (FLKEY) must be written with the correct key codes, in sequence, before Flash operations
may be performed. The key codes are: 0xA5, 0xF1. The timing does not matter, but the codes must be
written in order. If the key codes are written out of order, or the wrong codes are written, Flash writes and
erases will be disabled until the next system reset. Flash writes and erases will also be disabled if a Flash
write or erase is attempted before the key codes have been written properly. The Flash lock resets after
each write or erase; the key codes must be written again before a following Flash operation can be performed. The FLKEY register is detailed in SFR Definition 12.2.
Rev. 1.4
113
C8051F52x/F53x
12.1.2. Flash Erase Procedure
The Flash memory can be programmed by software using the MOVX write instruction with the address and
data byte to be programmed provided as normal operands. Before writing to Flash memory using MOVX,
Flash write operations must be enabled by: (1) setting the PSWE Program Store Write Enable bit
(PSCTL.0) to logic 1 (this directs the MOVX writes to target Flash memory); and (2) Writing the Flash key
codes in sequence to the Flash Lock register (FLKEY). The PSWE bit remains set until cleared by software.
A write to Flash memory can clear bits to logic 0 but cannot set them; only an erase operation can set bits
to logic 1 in Flash. A byte location to be programmed should be erased before a new value is written.
The Flash memory is organized in 512-byte pages. The erase operation applies to an entire page (setting
all bytes in the page to 0xFF). To erase an entire 512-byte page, perform the following steps:
1. Disable interrupts (recommended).
2. Write the first key code to FLKEY: 0xA5.
3. Write the second key code to FLKEY: 0xF1.
4. Set the PSEE bit (register PSCTL).
5. Set the PSWE bit (register PSCTL).
6. Using the MOVX instruction, write a data byte to any location within the 512-byte page to be erased.
7. Clear the PSWE and PSEE bits.
8. Re-enable interrupts.
12.1.3. Flash Write Procedure
Flash bytes are programmed by software with the following sequence:
1. Disable interrupts.
2. Write the first key code to FLKEY: 0xA5.
3. Write the second key code to FLKEY: 0xF1.
4. Set the PSWE bit (register PSCTL).
5. Clear the PSEE bit (register PSCTL).
6. Using the MOVX instruction, write a single data byte to the desired location within the 512-byte sector.
7. Clear the PSWE bit.
8. Re-enable interrupts.
Steps 2–7 must be repeated for each byte to be written. After Flash writes are complete, PSWE should be
cleared so that MOVX instructions do not target program memory.
114
Rev. 1.4
C8051F52x/F53x
12.2. Flash Write and Erase Guidelines
Any system which contains routines which write or erase Flash memory from software involves some risk
that the write or erase routines will execute unintentionally if the CPU is operating outside its specified
operating range of VDD, system clock frequency, or temperature. This accidental execution of Flash modifying code can result in alteration of Flash memory contents causing a system failure that is only recoverable by re-Flashing the code in the device.
The following guidelines are recommended for any system which contains routines which write or erase
Flash from code.
12.2.1. VDD Maintenance and the VDD monitor
1. If the system power supply is subject to voltage or current "spikes," add sufficient transient protection
devices to the power supply to ensure that the supply voltages listed in the Absolute Maximum Ratings
table are not exceeded.
2. Make certain that the maximum VDD ramp time specification (if applicable) is met. See Section 20.4 on
page 211 for more details on VDD ramp time. If the system cannot meet this ramp time specification,
then add an external VDD brownout circuit to the RST pin of the device that holds the device in reset
until VDD reaches the minimum specified VDD and re-asserts RST if VDD drops belowthat level.
VDD (min) is specified in Table 2.2 on page 26.
3. Enable the on-chip VDD monitor (VDDMON0) and enable it as a reset source as early in code as
possible. This should be the first set of instructions executed after the Reset Vector. For C-based
systems, this will involve modifying the startup code added by the C compiler. See your compiler
documentation for more details. Make certain that there are no delays in software between enabling the
VDD monitor (VDDMON0) and enabling it as a reset source. Code examples showing this can be found
in “AN201: Writing to Flash from Firmware", available from the Silicon Laboratories web site.
4. As an added precaution, explicitly enable the VDD monitor (VDDMON0) and enable the VDD monitor as
a reset source inside the functions that write and erase Flash memory. The VDD monitor enable
instructions should be placed just after the instruction to set PSWE to a 1, but before the Flash write or
erase operation instruction.
5. Make certain that all writes to the RSTSRC (Reset Sources) register use direct assignment operators
and explicitly DO NOT use the bit-wise operators (such as AND or OR). For example, "RSTSRC =
0x02" is correct. "RSTSRC |= 0x02" is incorrect.
6. Make certain that all writes to the RSTSRC register explicitly set the PORSF bit to a 1. Areas to check
are initialization code which enables other reset sources, such as the Missing Clock Detector or
Comparator, for example, and instructions which force a Software Reset. A global search on "RSTSRC"
can quickly verify this.
12.2.2. PSWE Maintenance
1. Reduce the number of places in code where the PSWE bit (PSCTL.0) is set to a 1. There should be
exactly one routine in code that sets PSWE to a 1 to write Flash bytes and one routine in code that sets
PSWE and PSEE both to a 1 to erase Flash pages.
2. Minimize the number of variable accesses while PSWE is set to a 1. Handle pointer address updates
and loop variable maintenance outside the "PSWE = 1;... PSWE = 0;" area. Code examples showing
this can be found in “AN201: Writing to Flash from Firmware," available from the Silicon Laboratories
web site.
3. Disable interrupts prior to setting PSWE to a 1 and leave them disabled until after PSWE has been
reset to '0'. Any interrupts posted during the Flash write or erase operation will be serviced in priority
order after the Flash operation has been completed and interrupts have been re-enabled by software.
4. Make certain that the Flash write and erase pointer variables are not located in XRAM. See your
compiler documentation for instructions regarding how to explicitly locate variables in different memory
areas.
Rev. 1.4
115
C8051F52x/F53x
5. Add address bounds checking to the routines that write or erase Flash memory to ensure that a routine
called with an illegal address does not result in modification of the Flash.
12.2.3. System Clock
1. If operating from an external crystal, be advised that crystal performance is susceptible to electrical
interference and is sensitive to layout and to changes in temperature. If the system is operating in an
electrically noisy environment, use the internal oscillator or use an external CMOS clock.
2. If operating from the external oscillator, switch to the internal oscillator during Flash write or erase
operations. The external oscillator can continue to run, and the CPU can switch back to the external
oscillator after the Flash operation has completed.
Additional Flash recommendations and example code can be found in application note “AN201: Writing to
Flash from Firmware," available from the Silicon Laboratories website.
116
Rev. 1.4
C8051F52x/F53x
12.3. Non-volatile Data Storage
The Flash memory can be used for non-volatile data storage as well as program code. This allows data
such as calibration coefficients to be calculated and stored at run time. Data is written using the MOVX
write instruction and read using the MOVC instruction. Note: MOVX read instructions always target XRAM.
Note: See Section “12.1. Programming The Flash Memory” on page 113 for minimum VDD and temperature requirements for flash erase and write operations.
12.4. Security Options
The CIP-51 provides security options to protect the Flash memory from inadvertent modification by software as well as to prevent the viewing of proprietary program code and constants. The Program Store
Write Enable (bit PSWE in register PSCTL) and the Program Store Erase Enable (bit PSEE in register
PSCTL) bits protect the Flash memory from accidental modification by software. PSWE must be explicitly
set to 1 before software can modify the Flash memory; both PSWE and PSEE must be set to 1 before software can erase Flash memory. Additional security features prevent proprietary program code and data
constants from being read or altered across the C2 interface.
A Security Lock Byte located at the last byte of Flash user space offers protection of the Flash program
memory from access (reads, writes, or erases) by unprotected code or the C2 interface. The Flash security
mechanism allows the user to lock n 512-byte Flash pages, starting at page 0 (addresses 0x0000 to
0x01FF), where n is the 1’s complement number represented by the Security Lock Byte. Note that the
page containing the Flash Security Lock Byte is unlocked when no other Flash pages are locked
(all bits of the Lock Byte are 1) and locked when any other Flash pages are locked (any bit of the
Lock Byte is 0). See example below.
Security Lock Byte:
1’s Complement:
Flash pages locked:
11111101b
00000010b
3 (First two Flash pages + Lock Byte Page)
Addresses locked:
0x0000 to 0x03FF (first two Flash pages)
0x1C00 to 0x1DFF in ’F520/0A/1/1A and ’F530/0A/1/1A
0x0C00 to 0x0FFF in ’F523/3A/4/4A and ’F533/3A/4/4A and 
0x0600 to 0x07FF in ’F526/6A/7/7A and ’F536/6A/7/7A
'F523/3A/4/4A and 'F533/3A/4/4A
'F520/0A/1/1A and 'F530/0A/1/1A
'F526/6A/7/7A and 'F536/6A/7/7A
Reserved
Reserved
Reserved
0x1E00
Locked when
any other Flash
pages are
locked
Access limit
set according
to the Flash
security lock
byte
Lock Byte
0x1DFF
Lock Byte
0x0FFF
Lock Byte
0x07FF
0x1DFE
0x0FFE
0x07FE
0x1C00
0x0E00
0x0600
Flash memory organized
Unlocked
Flash Pages
in 512-byte
pages
Unlocked Flash Pages
Unlocked Flash Pages
0x0000
0x0000
0x0000
Figure 12.1. Flash Program Memory Map
Rev. 1.4
117
C8051F52x/F53x
The level of Flash security depends on the Flash access method. The three Flash access methods that
can be restricted are reads, writes, and erases from the C2 debug interface, user firmware executing on
unlocked pages, and user firmware executing on locked pages. Table 12.1 summarizes the Flash security
features of the ’F52x/’F52xA/’F53x/’F53xA devices.
Table 12.1. Flash Security Summary
Action
C2 Debug
Interface
User Firmware executing from:
an unlocked page
a locked page
Permitted
Permitted
Permitted
Not Permitted
Flash Error Reset
Permitted
Read or Write page containing Lock Byte
(if no pages are locked)
Permitted
Permitted
Permitted
Read or Write page containing Lock Byte
(if any page is locked)
Not Permitted
Flash Error Reset
Permitted
Read contents of Lock Byte
(if no pages are locked)
Permitted
Permitted
Permitted
Read contents of Lock Byte
(if any page is locked)
Not Permitted
Flash Error Reset
Permitted
Read, Write or Erase unlocked pages
(except page with Lock Byte)
Read, Write or Erase locked pages
(except page with Lock Byte)
Erase page containing Lock Byte
(if no pages are locked)
Permitted
Flash Error Reset Flash Error Reset
C2 Device
Erase Only
Flash Error Reset Flash Error Reset
Lock additional pages
(change 1s to 0s in the Lock Byte)
Not Permitted
Flash Error Reset Flash Error Reset
Unlock individual pages
(change 0s to 1s in the Lock Byte)
Not Permitted
Flash Error Reset Flash Error Reset
Read, Write or Erase Reserved Area
Not Permitted
Flash Error Reset Flash Error Reset
Erase page containing Lock Byte—Unlock all
pages (if any page is locked)

C2 Device Erase—Erases all Flash pages including the page containing the Lock Byte.
Flash Error Reset—Not permitted; Causes Flash Error Device Reset (FERROR bit in RSTSRC is 1 after
reset).
- All prohibited operations that are performed via the C2 interface are ignored (do not cause device reset).
- Locking any Flash page also locks the page containing the Lock Byte.
- Once written to, the Lock Byte cannot be modified except by performing a C2 Device Erase.
- If user code writes to the Lock Byte, the Lock does not take effect until the next device reset.
118
Rev. 1.4
C8051F52x/F53x
SFR Definition 12.1. PSCTL: Program Store R/W Control
R
R
R
R
R
R
R/W
R/W
Reset Value
—
—
—
—
—
—
PSEE
PSWE
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
0x8F
Bits7–2: UNUSED: Read = 000000b, Write = don’t care.
Bit1:
PSEE: Program Store Erase Enable
Setting this bit (in combination with PSWE) allows an entire page of Flash program memory
to be erased. If this bit is logic 1 and Flash writes are enabled (PSWE is logic 1), a write to
Flash memory using the MOVX instruction will erase the entire page that contains the location addressed by the MOVX instruction. The value of the data byte written does not matter.
0: Flash program memory erasure disabled.
1: Flash program memory erasure enabled.
Bit0:
PSWE: Program Store Write Enable
Setting this bit allows writing a byte of data to the Flash program memory using the MOVX
write instruction. The Flash location should be erased before writing data.
0: Writes to Flash program memory disabled.
1: Writes to Flash program memory enabled; the MOVX write instruction targets Flash
memory.
Note: See Section “12.1. Programming The Flash Memory” on page 113 for minimum VDD and temperature
requirements for flash erase and write operations.
SFR Definition 12.2. FLKEY: Flash Lock and Key
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
0xB7
Bits7–0: FLKEY: Flash Lock and Key Register
Write:
This register provides a lock and key function for Flash erasures and writes. Flash writes
and erases are enabled by writing 0xA5 followed by 0xF1 to the FLKEY register. Flash
writes and erases are automatically disabled after the next write or erase is complete. If any
writes to FLKEY are performed incorrectly, or if a Flash write or erase operation is attempted
while these operations are disabled, the Flash will be permanently locked from writes or erasures until the next device reset. If an application never writes to Flash, it can intentionally
lock the Flash by writing a non-0xA5 value to FLKEY from software.
Read:
When read, bits 1–0 indicate the current Flash lock state.
00: Flash is write/erase locked.
01: The first key code has been written (0xA5).
10: Flash is unlocked (writes/erases allowed).
11: Flash writes/erases disabled until the next reset.
Rev. 1.4
119
C8051F52x/F53x
13. Port Input/Output
Digital and analog resources are available through up to 16 I/O pins. Port pins are organized as two or one
byte-wide Ports. Each of the Port pins can be defined as general-purpose I/O (GPIO) or analog input/output; Port pins P0.0 - P2.7 can be assigned to one of the internal digital resources as shown in Figure 13.3.
The designer has complete control over which functions are assigned, limited only by the number of physical I/O pins. This resource assignment flexibility is achieved through the use of a Priority Crossbar
Decoder. Note that the state of a Port I/O pin can always be read in the corresponding Port latch, regardless of the Crossbar settings.
The Crossbar assigns the selected internal digital resources to the I/O pins based on the peripheral priority
order of the Priority Decoder (Figure 13.3 and Figure 13.4). The registers XBR0 and XBR1, defined in SFR
Definition 13.1 and SFR Definition 13.2, are used to select internal digital functions.
Port I/O pins are 5.25 V tolerant over the operating range of VREGIN. Figure 13.2 shows the Port cell circuit.
The Port I/O cells are configured as either push-pull or open-drain in the Port Output Mode registers
(PnMDOUT, where n = 0,1). Complete Electrical Specifications for Port I/O are given in Table 2.10 on
page 33.
P0MASK, P0MATCH
P1MASK, P1MATCH
Registers
XBR0, XBR1,
PnSKIP Registers
2
UART
4
(Internal Digital Signals)
SPI
Lowest
Priority
PnMDOUT,
PnMDIN Registers
Priority
Decoder
Highest
Priority
8
2
LIN
Digital
Crossbar
CP0
Outputs
T0, T1
(Port Latches)
8
7
PCA
P1
I/O
Cells
2
P1.0–1.7 and P0.7
available on C8051F53x/
C8051F53xA parts
8
(P0.0-P0.7)
8
P1
(P1.0-P1.7*)
Figure 13.1. Port I/O Functional Block Diagram
120
P0.0
P0.7
2
SYSCLK
P0
P0
I/O
Cells
Rev. 1.4
P1.0
P1.7
C8051F52x/F53x
/WEAK-PULLUP
VREGIN
PUSH-PULL
/PORT-OUTENABLE
VREGIN
(WEAK)
PORT
PAD
PORT-OUTPUT
GND
Analog Select
ANALOG INPUT
PORT-INPUT
Figure 13.2. Port I/O Cell Block Diagram
Rev. 1.4
121
C8051F52x/F53x
13.1. Priority Crossbar Decoder
The Priority Crossbar Decoder (Figure 13.3) assigns a priority to each I/O function, starting at the top with
UART0. When a digital resource is selected, the least-significant unassigned Port pin is assigned to that
resource (excluding UART0, which will be assigned to pins P0.4 and P0.5). If a Port pin is assigned, the
Crossbar skips that pin when assigning the next selected resource. Additionally, the Crossbar will skip Port
pins whose associated bits in the PnSKIP registers are set. The PnSKIP registers allow software to skip
Port pins that are to be used for analog input, dedicated functions, or GPIO.
1
2
3
4
5
6
7
0
TX0
CNVSTR
VREF
TSSOP 20 and QFN 20
0
PIN I/O
XTAL2
P1
XTAL1
P0
SF Signals
1
2
3
4
5
6
7
C8051F53xA/F53x-C devices
RX0
TX0
C8051F53x devices
RX0
SCK
MISO
MOSI
NSS*
LIN-TX
LIN_RX
CP0
CP0A
/SYSCLK
CEX0
CEX1
CEX2
ECI
T0
T1
0
0
0
0
0
0
0
0
0
0
P0SKIP[0:7]
0
0
0
0
0
0
P1SKIP[0:7]
Port pin potentially assignable to peripheral
SF Signals
Special Function Signals are not assigned by the crossbar.
When these signals are enabled, the Crossbar must be manually configured
to skip their corresponding port pins.
Note: 4-Wire SPI Only.
Figure 13.3. Crossbar Priority Decoder with No Pins Skipped
(TSSOP 20 and QFN 20)
Important Note on Crossbar Configuration: If a Port pin is claimed by a peripheral without use of the
Crossbar, its corresponding PnSKIP bit should be set. This applies to P1.0 and/or P0.7 (F53x/F53xA) or
P0.2 and/or P0.3 (F52x/F52xA) for the external oscillator, P0.0 for VREF, P1.2 (F53x/F53xA) or P0.5
122
Rev. 1.4
C8051F52x/F53x
(F52x/F52xA) for the external CNVSTR signal, and any selected ADC or comparator inputs. The Crossbar
skips selected pins as if they were already assigned, and moves to the next unassigned pin. Figure 13.3
shows the Crossbar Decoder priority with no Port pins skipped (P0SKIP, P1SKIP); Figure 13.4 shows the
Crossbar Decoder priority with the XTAL1 (P1.0) and XTAL2 (P1.1) pins skipped (P1SKIP = 0x03).
Important Note on UART Pins: On C8051F52xA/F52x-C/F53xA/F53x-C devices, the UART pins must be
skipped if the UART is enabled in order for peripherals to appear on port pins beyond the UART on the
crossbar. For example, with the SPI and UART enabled on the crossbar with the SPI on P1.0-P1.3, the
UART pins must be skipped using P0SKIP for the SPI pins to appear correctly.
0
PIN I/O
1
2
3
4
5
6
7
0
CNVSTR
TSSOP 20 and QFN 20
VREF
SF Signals
XTAL2
P1
XTAL1
P0
1
TX0
2
3
4
5
6
7
C8051F53xA/F53x-C
devices
RX0
TX0
C8051F53x devices
RX0
SCK
MISO
MOSI
NSS*
LIN-TX
LIN-RX
CP0
CP0A
/SYSCLK
CEX0
CEX1
CEX2
ECI
T0
T1
0
0
0
0
0
0
0
1
1
P0SKIP[0:7] = 0x80
0
0
0
0
0
0
0
P1SKIP[0:7] = 0x01
Port pin potentially assignable to peripheral
SF Signals
Special Function Signals are not assigned by the crossbar.
When these signals are enabled, the Crossbar must be manually configured
to skip their corresponding port pins.
Note: 4-Wire SPI Only.
Figure 13.4. Crossbar Priority Decoder with Crystal Pins Skipped
(TSSOP 20 and QFN 20)
Rev. 1.4
123
0
1
2
3
CNVSTR
XTAL2
PIN I/O
XTAL1
SF Signals DFN10
VREF
C8051F52x/F53x
4
5
TX0
C8051F52xA/F52x-C
devices
RX0
TX0
C8051F52x devices
RX0
SCK
MISO
MOSI
NSS*
LIN-TX
LIN_RX
CP0
CP0A
/SYSCLK
CEX0
CEX1
CEX2
ECI
T0
T1
0
0
0
0
0
0
P0SKIP[0:5]
Port pin potentially assignable to peripheral
SF Signals
Special Function Signals are not assigned by the crossbar.
When these signals are enabled, the Crossbar must be manually configured
to skip their corresponding port pins.
Note: 4-Wire SPI Only.
Figure 13.5. Crossbar Priority Decoder with No Pins Skipped (DFN 10)
124
Rev. 1.4
C8051F52x/F53x
1
2
3
CNVSTR
0
XTAL2
PIN I/O
XTAL1
SF Signals DFN 10
VREF
P0
4
5
TX0
C8051F52xA/F52x-C
devices
RX0
TX0
C8051F52x devices
RX0
SCK
MISO
MOSI
NSS*
LIN-TX
LIN-RX
CP0
CP0A
/SYSCLK
CEX0
CEX1
CEX2
ECI
T0
T1
0
1
1
0
0
0
P0SKIP[0:5] = 0x06
Port pin potentially assignable to peripheral
SF Signals
Special Function Signals are not assigned by the crossbar.
When these signals are enabled, the Crossbar must be manually configured
to skip their corresponding port pins.
Note: 4-Wire SPI Only.
Figure 13.6. Crossbar Priority Decoder with Some Pins Skipped (DFN 10)
Registers XBR0 and XBR1 are used to assign the digital I/O resources to the physical I/O Port pins. Note
that when the SMBus is selected, the Crossbar assigns both pins associated with the SMBus (SDA and
SCL); when the UART is selected, the Crossbar assigns both pins associated with the UART (TX and RX).
UART0 pin assignments are fixed for bootloading purposes: UART TX0 is always assigned to P0.3 or
P0.4*; UART RX0 is always assigned to P0.4 or P0.5*. Standard Port I/Os appear contiguously starting at
P0.0 after prioritized functions and skipped pins are assigned.
Note: Refer to Section “20. Device Specific Behavior” on page 210.
Rev. 1.4
125
C8051F52x/F53x
Important Note: The SPI can be operated in either 3-wire or 4-wire modes, depending on the state of the
NSSMD1–NSSMD0 bits in register SPI0CN. According to the SPI mode, the NSS signal may or may not
be routed to a Port pin.
13.2. Port I/O Initialization
Port I/O initialization consists of the following steps:
1. Select the input mode (analog or digital) for all Port pins, using the Port Input Mode register (PnMDIN).
2. Select the output mode (open-drain or push-pull) for all Port pins, using the Port Output Mode register
(PnMDOUT).
3. Select any pins to be skipped by the I/O Crossbar using the Port Skip registers (PnSKIP).
4. Assign Port pins to desired peripherals using the XBRn registers.
5. Enable the Crossbar (XBARE = 1).
All Port pins must be configured as either analog or digital inputs. Any pins to be used as Comparator or
ADC inputs should be configured as an analog inputs. When a pin is configured as an analog input, its
weak pullup, digital driver, and digital receiver are disabled. This process saves power and reduces noise
on the analog input. Pins configured as digital inputs may still be used by analog peripherals; however, this
practice is not recommended.
Additionally, all analog input pins should be configured to be skipped by the Crossbar (accomplished by
setting the associated bits in PnSKIP). Port input mode is set in the PnMDIN register, where a 1 indicates a
digital input, and a 0 indicates an analog input. All pins default to digital inputs on reset. See SFR Definition
13.4 for the PnMDIN register details.
Important Note: Port 0 and Port 1 pins are 5.25 V tolerant across the operating range of VREGIN.
The output driver characteristics of the I/O pins are defined using the Port Output Mode registers (PnMDOUT). Each Port Output driver can be configured as either open drain or push-pull. This selection is
required even for the digital resources selected in the XBRn registers, and is not automatic. When the
WEAKPUD bit in XBR1 is 0, a weak pullup is enabled for all Port I/O configured as open-drain. WEAKPUD
does not affect the push-pull Port I/O. Furthermore, the weak pullup is turned off on an output that is driving
a 0 and for pins configured for analog input mode to avoid unnecessary power dissipation.
Registers XBR0 and XBR1 must be loaded with the appropriate values to select the digital I/O functions
required by the design. Setting the XBARE bit in XBR1 to 1 enables the Crossbar. Until the Crossbar is
enabled, the external pins remain as standard Port I/O (in input mode), regardless of the XBRn Register
settings. For given XBRn Register settings, one can determine the I/O pin-out using the Priority Decode
Table.
The Crossbar must be enabled to use Port pins as standard Port I/O in output mode. Port output drivers
are disabled while the Crossbar is disabled.
126
Rev. 1.4
C8051F52x/F53x
SFR Definition 13.1. XBR0: Port I/O Crossbar Register 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
-
-
CP0AE
CP0E
SYSCKE
LINE
SPI0E
URT0E
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
Bit7–6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
0xE1
RESERVED. Read = 00b; Must write 00b.
CP0AE: Comparator0 Asynchronous Output Enable
0: Asynchronous CP0 unavailable at Port pin.
1: Asynchronous CP0 routed to Port pin.
CP0E: Comparator0 Output Enable
0: CP0 unavailable at Port pin.
1: CP0 routed to Port pin.
SYSCKE: /SYSCLK Output Enable
0: /SYSCLK unavailable at Port pin.
1: /SYSCLK output routed to Port pin.
LINE. Lin Output Enable
SPI0E: SPI I/O Enable
0: SPI I/O unavailable at Port pins.
1: SPI I/O routed to Port pins. Note that the SPI can be assigned either 3 or 4 GPIO pins.
URT0E: UART I/O Output Enable
0: UART I/O unavailable at Port pin.
1: UART TX0, RX0 routed to Port pins (P0.3 and P0.4) or (P0.4 and P0.5).*
Note: Refer to Section “20. Device Specific Behavior” on page 210.
Rev. 1.4
127
C8051F52x/F53x
SFR Definition 13.2. XBR1: Port I/O Crossbar Register 1
R/W
R/W
WEAKPUD XBARE
Bit7
Bit6
R/W
R/W
R/W
R/W
T1E
T0E
ECIE
Reserved
Bit5
Bit4
Bit3
Bit2
R/W
R/W
PCA0ME
Bit1
Reset Value
00000000
Bit0
SFR Address:
0xE2
Bit7:
WEAKPUD: Port I/O Weak Pullup Disable.
0: Weak Pullups enabled (except for Ports whose I/O are configured as analog input).
1: Weak Pullups disabled.
Bit6:
XBARE: Crossbar Enable.
0: Crossbar disabled.
1: Crossbar enabled.
Bit5:
T1E: T1 Enable
0: T1 unavailable at Port pin.
1: T1 routed to Port pin.
Bit4:
T0E: T0 Enable
0: T0 unavailable at Port pin.
1: T0 routed to Port pin.
Bit3:
ECIE: PCA0 External Counter Input Enable
0: ECI unavailable at Port pin.
1: ECI routed to Port pin.
Bit2:
Reserved. Must Write 0b.
Bits1–0: PCA0ME: PCA Module I/O Enable Bits.
00: All PCA I/O unavailable at Port pins.
01: CEX0 routed to Port pin.
10: CEX0, CEX1 routed to Port pins.
11: CEX0, CEX1, CEX2 routed to Port pins.
13.3. General Purpose Port I/O
Port pins that remain unassigned by the Crossbar and are not used by analog peripherals can be used for
general purpose I/O. Ports P0–P1 are accessed through corresponding special function registers (SFRs)
that are both byte addressable and bit addressable. When writing to a Port, the value written to the SFR is
latched to maintain the output data value at each pin. When reading, the logic levels of the Port's input pins
are returned regardless of the XBRn settings (i.e., even when the pin is assigned to another signal by the
Crossbar, the Port register can always read its corresponding Port I/O pin). The exception to this is the
execution of the read-modify-write instructions that target a Port Latch register as the destination. The
read-modify-write instructions when operating on a Port SFR are the following: ANL, ORL, XRL, JBC, CPL,
INC, DEC, DJNZ and MOV, CLR or SETB, when the destination is an individual bit in a Port SFR. For
these instructions, the value of the latch register (not the pin) is read, modified, and written back to the
SFR.
128
Rev. 1.4
C8051F52x/F53x
In addition to performing general purpose I/O, P0 and P1 can generate a port match event if the logic levels of the Port’s input pins match a software controlled value. A port match event is generated if
(P0 & P0MASK) does not equal (P0MATCH & P0MASK) or if (P1 & P1MASK) does not equal
(P1MATCH & P1MASK). This allows Software to be notified if a certain change or pattern occurs on P0 or
P1 input pins regardless of the XBRn settings. A port match event can cause an interrupt if EMAT (EIE2.1)
is set to 1 or cause the internal oscillator to awaken from SUSPEND mode. See Section “14.1.1. Internal
Oscillator Suspend Mode” on page 136 for more information.
SFR Definition 13.3. P0: Port0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
P0.7
P0.6
P0.5
P0.4
P0.3
P0.2
P0.1
P0.0
11111111
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Bit
Addressable
SFR Address:
0x80
Bits7–0: P0.[7:0]
Write - Output appears on I/O pins per Crossbar Registers.
0: Logic Low Output.
1: Logic High Output (high impedance if corresponding P0MDOUT.n bit = 0).
Read - Always reads 0 if selected as analog input in register P0MDIN. Directly reads Port
pin when configured as digital input.
0: P0.n pin is logic low.
1: P0.n pin is logic high.
SFR Definition 13.4. P0MDIN: Port0 Input Mode
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Reset Value
11111111
SFR Address:
0xF1
Bits7–0: Analog Input Configuration Bits for P0.7–P0.0 (respectively).
Port pins configured as analog inputs have their weak pullup, digital driver, and digital
receiver disabled.
0: Corresponding P0.n pin is configured as an analog input.
1: Corresponding P0.n pin is not configured as an analog input.
Rev. 1.4
129
C8051F52x/F53x
SFR Definition 13.5. P0MDOUT: Port0 Output Mode
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
0xA4
Bits7–0: Output Configuration Bits for P0.7–P0.0 (respectively): ignored if corresponding bit in register P0MDIN is logic 0.
0: Corresponding P0.n Output is open-drain.
1: Corresponding P0.n Output is push-pull.
Note: When SDA and SCL appear on any of the Port I/O, each are open-drain regardless of the value of P0MDOUT.
SFR Definition 13.6. P0SKIP: Port0 Skip
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
0xD4
Bits7–0: P0SKIP[7:0]: Port0 Crossbar Skip Enable Bits.
These bits select Port pins to be skipped by the Crossbar Decoder. Port pins used as analog inputs (for ADC or Comparator) or used as special functions (VREF input, external oscillator circuit, CNVSTR input) should be skipped by the Crossbar.
0: Corresponding P0.n pin is not skipped by the Crossbar.
1: Corresponding P0.n pin is skipped by the Crossbar.
130
Rev. 1.4
C8051F52x/F53x
SFR Definition 13.7. P0MAT: Port0 Match
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Reset Value
11111111
SFR Address:
0xD7
Bits7–0: P0MAT[7:0]: Port0 Match Value.
These bits control the value that unmasked P0 Port pins are compared against. A Port
Match event is generated if (P0 & P0MASK) does not equal (P0MAT & P0MASK).
SFR Definition 13.8. P0MASK: Port0 Mask
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Reset Value
00000000
SFR Address:
0xC7
Bits7–0: P0MASK[7:0]: Port0 Mask Value.
These bits select which Port pins will be compared to the value stored in P0MAT.
0: Corresponding P0.n pin is ignored and cannot cause a Port Match event.
1: Corresponding P0.n pin is compared to the corresponding bit in P0MAT.
Rev. 1.4
131
C8051F52x/F53x
SFR Definition 13.9. P1: Port1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
P1.7
P1.6
P1.5
P1.4
P1.3
P1.2
P1.1
P1.0
11111111
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Bit
Addressable
SFR Address:
0x90
Bits7–0: P1.[7:0]
Write - Output appears on I/O pins per Crossbar Registers.
0: Logic Low Output.
1: Logic High Output (high impedance if corresponding P1MDOUT.n bit = 0).
Read - Always reads 0 if selected as analog input in register P1MDIN. Directly reads Port
pin when configured as digital input.
0: P1.n pin is logic low.
1: P1.n pin is logic high.
SFR Definition 13.10. P1MDIN: Port1 Input Mode
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Reset Value
11111111
SFR Address:
0xF2
Bits7–0: Analog Input Configuration Bits for P1.7–P1.0 (respectively).
Port pins configured as analog inputs have their weak pullup, digital driver, and digital
receiver disabled.
0: Corresponding P1.n pin is configured as an analog input.
1: Corresponding P1.n pin is not configured as an analog input.
132
Rev. 1.4
C8051F52x/F53x
SFR Definition 13.11. P1MDOUT: Port1 Output Mode
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
0xA5
Bits7–0: Output Configuration Bits for P1.7–P1.0 (respectively): ignored if corresponding bit in register P1MDIN is logic 0.
0: Corresponding P1.n Output is open-drain.
1: Corresponding P1.n Output is push-pull.
Note: When SDA and SCL appear on any of the Port I/O, each are open-drain regardless of the value of P0MDOUT.
SFR Definition 13.12. P1SKIP: Port1 Skip
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
0xD5
Bits7–0: P1SKIP[7:0]: Port1 Crossbar Skip Enable Bits.
These bits select Port pins to be skipped by the Crossbar Decoder. Port pins used as analog inputs (for ADC or Comparator) or used as special functions (VREF input, external oscillator circuit, CNVSTR input) should be skipped by the Crossbar.
0: Corresponding P1.n pin is not skipped by the Crossbar.
1: Corresponding P1.n pin is skipped by the Crossbar.
Rev. 1.4
133
C8051F52x/F53x
SFR Definition 13.13. P0SKIP: Port0 Skip
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
0xD4
Bits7–0: P1SKIP[7:0]: Port1 Crossbar Skip Enable Bits.
These bits select Port pins to be skipped by the Crossbar Decoder. Port pins used as analog inputs (for ADC or Comparator) or used as special functions (VREF input, external oscillator circuit, CNVSTR input) should be skipped by the Crossbar.
0: Corresponding P1.n pin is not skipped by the Crossbar.
1: Corresponding P1.n pin is skipped by the Crossbar.
SFR Definition 13.14. P1MAT: Port1 Match
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Reset Value
11111111
SFR Address:
0xCF
Bits7–0: P1MAT[7:0]: Port1 Match Value.
These bits control the value that unmasked P0 Port pins are compared against. A Port
Match event is generated if (P1 & P1MASK) does not equal (P1MAT & P1MASK).
SFR Definition 13.15. P1MASK: Port1 Mask
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Reset Value
00000000
SFR Address:
Bits7–0: P1MASK[7:0]: Port1 Mask Value.
These bits select which Port pins will be compared to the value stored in P1MAT.
0: Corresponding P1.n pin is ignored and cannot cause a Port Match event.
1: Corresponding P1.n pin is compared to the corresponding bit in P1MAT.
134
Rev. 1.4
0xBF
C8051F52x/F53x
14. Oscillators
C8051F52x/F52xA/F53x/F53xA devices include a programmable internal oscillator, an external oscillator
drive circuit. The internal oscillator can be enabled/disabled and calibrated using the OSCICN and
OSCICL registers, as shown in Figure 14.1. The system clock (SYSCLK) can be derived from the internal
oscillator, external oscillator circuit. Oscillator electrical specifications are given in Table 2.11 on page 34.
Option 3
XTAL2
CLKSEL
CLKSL
OSCICN
IFCN2
IFCN1
IFCN0
OSCIFIN
IOSCEN1
IOSCEN0
SUSPEND
IFRDY
OSCICL
Option 2
VDD
XTAL2
EN
IOSC
Programmable
Internal Clock
Generator
Option 1
n
SYSCLK
XTAL1
EXOSC
Input
Circuit
10M
OSC
Option 4
XTLVLD
XTAL2
XFCN2
XFCN1
XFCN0
XTLVLD
XOSCMD2
XOSCMD1
XOSCMD0
XTAL2
OSCXCN
Figure 14.1. Oscillator Diagram
14.1. Programmable Internal Oscillator
All C8051F52x/53x devices include a programmable internal oscillator that defaults as the system clock
after a system reset. The internal oscillator period can be programmed via the OSCICL and OSCIFIN registers, shown in SFR Definition 14.2 and SFR Definition 14.3. On C8051F52x/53x devices, OSCICL and
OSCIFIN are factory calibrated to obtain a 24.5 MHz frequency.
Electrical specifications for the precision internal oscillator are given in Table 2.11 on page 34. Note that
the system clock may be derived from the programmed internal oscillator divided by 1, 2, 4, 8, 16, 32, 64,
or 128 as defined by the IFCN bits in register OSCICN. The divide value defaults to 128 following a reset.
Rev. 1.4
135
C8051F52x/F53x
14.1.1. Internal Oscillator Suspend Mode
When software writes a logic 1 to SUSPEND (OSCICN.5), the internal oscillator is suspended. If the system clock is derived from the internal oscillator, the input clock to the peripheral or CIP-51 will be stopped
until one of the following events occur:

Port 0 Match Event.
Port 1 Match Event.
 Comparator 0 enabled and output is logic 0.

When one of the internal oscillator awakening events occur, the internal oscillator, CIP-51, and affected
peripherals resume normal operation, regardless of whether the event also causes an interrupt. The CPU
resumes execution at the instruction following the write to SUSPEND.
Note: Please refer to Section “20.7. Internal Oscillator Suspend Mode” on page 212 for a note about suspend mode
in older silicon revisions.
136
Rev. 1.4
C8051F52x/F53x
SFR Definition 14.1. OSCICN: Internal Oscillator Control
R/W
R/W
R/W
IOSCEN1 IOSCEN0 SUSPEND
Bit7
Bit6
Bit5
R
R
R/W
R/W
R/W
Reset Value
IFRDY
—
IFCN2
IFCN1
IFCN0
11000000
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
0xB2
Bits7–6: IOSCEN[1:0]: Internal Oscillator Enable Bits.
00: Oscillator Disabled.
01: Reserved.
10: Reserved.
11: Oscillator Enabled in Normal Mode and Disabled in Suspend Mode.
Bit5:
SUSPEND: Internal Oscillator Suspend Enable Bit.
Setting this bit to logic 1 places the internal oscillator in SUSPEND mode. The internal oscillator resumes operation when one of the SUSPEND mode awakening events occur.
Bit4:
IFRDY: Internal Oscillator Frequency Ready Flag.
0: Internal Oscillator is not running at programmed frequency.
1: Internal Oscillator is running at programmed frequency.
Bit3:
UNUSED. Read = 0b, Write = don't care.
Bits2–0: IFCN2–0: Internal Oscillator Frequency Control Bits.
000: SYSCLK derived from Internal Oscillator divided by 128 (default).
001: SYSCLK derived from Internal Oscillator divided by 64.
010: SYSCLK derived from Internal Oscillator divided by 32.
011: SYSCLK derived from Internal Oscillator divided by 16.
100: SYSCLK derived from Internal Oscillator divided by 8.
101: SYSCLK derived from Internal Oscillator divided by 4.
110: SYSCLK derived from Internal Oscillator divided by 2.
111: SYSCLK derived from Internal Oscillator divided by 1.
Rev. 1.4
137
C8051F52x/F53x
SFR Definition 14.2. OSCICL: Internal Oscillator Calibration
R
R/W
R/W
R/W
—
Bit7
R/W
R/W
R/W
R/W
Bit2
Bit1
Bit0
Reset Value
OSCICL
Bit6
Bit5
Bit4
Varies
Bit3
SFR Address:
0xB3
Bit7:
UNUSED. Read = 0b. Write = don’t care.
Bits6–0: OSCICL: Internal Oscillator Calibration Register.
This register determines the internal oscillator period. On C8051F52x/53x devices, the reset
value is factory calibrated to generate an internal oscillator frequency of 24.5 MHz.
SFR Definition 14.3. OSCIFIN: Internal Fine Oscillator Calibration
R/W
R/W
—
—
Bit7
Bit6
R/W
R
R
R/W
R/W
R/W
OSCIFIN
Bit5
Bit4
Bit3
Bit2
Reset Value
undetermined
Bit1
Bit0
Bit Addressable
SFR Address:
0xB0
Bits7–6: UNUSED. Read = 00b, Write = don't care.
Bits5–0: OSCIFIN. Internal oscillator fine adjustment bits.
The valid range is between 0x00 and 0x27.
This register is a fine adjustment for the internal oscillator period. On
C8051F52x/52xA/53x/53xA devices, the reset value is factory calibrated to generate an
internal oscillator frequency of 24.5 MHz.
138
Rev. 1.4
C8051F52x/F53x
14.2. External Oscillator Drive Circuit
The external oscillator circuit may drive an external crystal, ceramic resonator, capacitor, or RC network. A
CMOS clock may also provide a clock input. For a crystal or ceramic resonator configuration, the crystal/resonator must be wired across the XTAL1 and XTAL2 pins as shown in Option 1 of Figure 14.1. A
10 Mresistor also must be wired across the XTAL1 and XTAL2 pins for the crystal/resonator configuration. In RC, capacitor, or CMOS clock configuration, the clock source should be wired to the XTAL2 pin as
shown in Option 2, 3, or 4 of Figure 14.1. The type of external oscillator must be selected in the OSCXCN
register, and the frequency control bits (XFCN) must be selected appropriately (see SFR
Definition 14.4. OSCXCN: External Oscillator Control).
Important Note on External Oscillator Usage: Port pins must be configured when using the external
oscillator circuit. When the external oscillator drive circuit is enabled in crystal/resonator mode, Port pins
P0.7 and P1.0 ('F53x/'F53xA) or P0.2 and P0.3 ('F52x/'F52xA) are used as XTAL1 and XTAL2 respectively. When the external oscillator drive circuit is enabled in capacitor, RC, or CMOS clock mode, Port pin
P1.0 ('F53x/'F53xA) or P0.3 ('F52x/'F52xA) is used as XTAL2. The Port I/O Crossbar should be configured
to skip the Port pins used by the oscillator circuit; see Section “13.1. Priority Crossbar Decoder” on
page 122 for Crossbar configuration. Additionally, when using the external oscillator circuit in crystal/resonator, capacitor, or RC mode, the associated Port pins should be configured as analog inputs. In CMOS
clock mode, the associated pin should be configured as a digital input. See Section “13.2. Port I/O Initialization” on page 126 for details on Port input mode selection.
14.2.1. Clocking Timers Directly Through the External Oscillator
The external oscillator source divided by eight is a clock option for the timers (Section “18. Timers” on
page 182) and the Programmable Counter Array (PCA) (Section “19. Programmable Counter Array
(PCA0)” on page 195). When the external oscillator is used to clock these peripherals, but is not used as
the system clock, the external oscillator frequency must be less than or equal to the system clock frequency. In this configuration, the clock supplied to the peripheral (external oscillator / 8) is synchronized
with the system clock; the jitter associated with this synchronization is limited to ±0.5 system clock cycles.
14.2.2. External Crystal Example
If a crystal or ceramic resonator is used as an external oscillator source for the MCU, the circuit should be
configured as shown in Figure 14.1, Option 1. The External Oscillator Frequency Control value (XFCN)
should be chosen from the Crystal column of the table in SFR Definition 14.4. For example, a 12 MHz crystal requires an XFCN setting of 111b.
When the crystal oscillator is first enabled, the oscillator amplitude detection circuit requires a settling time
to achieve proper bias. Introducing a delay of 1 ms between enabling the oscillator and checking the
XTLVLD bit will prevent a premature switch to the external oscillator as the system clock. Switching to the
external oscillator before the crystal oscillator has stabilized can result in unpredictable behavior. The recommended procedure is:
1. Configure XTAL1 and XTAL2 pins by writing 1 to the port latch.
2. Configure XTAL1 and XTAL2 as analog inputs.
3. Enable the external oscillator.
4. Wait at least 1 ms.
5. Poll for XTLVLD => 1.
6. Switch the system clock to the external oscillator.
Note: Tuning-fork crystals may require additional settling time before XTLVLD returns a valid result.
The capacitors shown in the external crystal configuration provide the load capacitance required by the
crystal for correct oscillation. These capacitors are "in series" as seen by the crystal and "in parallel" with
the stray capacitance of the XTAL1 and XTAL2 pins.
Rev. 1.4
139
C8051F52x/F53x
Note: The load capacitance depends upon the crystal and the manufacturer. Please refer to the crystal
data sheet when completing these calculations.
The equation for determining the load capacitance for two capacitors is:
CA  CB
C L = -------------------- + C S
CA + CB
Where:
CA and CB are the capacitors connected to the crystal leads.
CS is the total stray capacitance of the PCB.
The stray capacitance for a typical layout where the crystal is as close as possible to the pins is 2–5 pF per
pin.
If CA and CB are the same (C), then the equation becomes:
C
C L = ---- + C S
2
For example, a tuning-fork crystal of 32 kHz with a recommended load capacitance of 12.5 pF should use
the configuration shown in Figure 14.1, Option 1. With a stray capacitance of 3 pF per pin (6 pF total), the
13 pF capacitors yield an equivalent capacitance of 12.5 pF across the crystal, as shown in Figure 14.2.
13 pF
XTAL1

10 M
32 kHz
XTAL2
13 pF
Figure 14.2. 32 kHz External Crystal Example
Important Note on External Crystals: Crystal oscillator circuits are quite sensitive to PCB layout. The
crystal should be placed as close as possible to the XTAL pins on the device. The traces should be as
short as possible and shielded with ground plane from any other traces which could introduce noise or
interference.
140
Rev. 1.4
C8051F52x/F53x
14.2.3. External RC Example
If an RC network is used as an external oscillator source for the MCU, the circuit should be configured as
shown in Figure 14.1, Option 2. The capacitor should be no greater than 100 pF; however for very small
capacitors, the total capacitance may be dominated by parasitic capacitance in the PCB layout. To determine the required External Oscillator Frequency Control value (XFCN) in the OSCXCN Register, first
select the RC network value to produce the desired frequency of oscillation. If the frequency desired is
100 kHz, let R = 246 k and C = 50 pF:
f = 1.23( 103 ) / RC = 1.23 ( 103 ) / [ 246 x 50 ] = 0.1 MHz = 100 kHz
Referring to the table in SFR Definition 14.4, the required XFCN setting is 010b. Programming XFCN to a
higher setting in RC mode will improve frequency accuracy at a slightly increased external oscillator supply
current.
14.2.4. External Capacitor Example
If a capacitor is used as an external oscillator for the MCU, the circuit should be configured as shown in
Figure 14.1, Option 3. The capacitor should be no greater than 100 pF; however for very small capacitors,
the total capacitance may be dominated by parasitic capacitance in the PCB layout. To determine the
required External Oscillator Frequency Control value (XFCN) in the OSCXCN Register, select the frequency of oscillation and calculate the capacitance to be used from the equations below. Assume
VDD = 2.1 V and f = 75 kHz:
f = KF / (C x VDD)
0.075 MHz = KF / (C x 2.1)
Since the frequency of roughly 75 kHz is desired, select the K Factor from the table in SFR Definition 14.4
as KF = 7.7:
0.075 MHz = 7.7 / (C x 2.1)
C x 2.1 = 7.7 / 0.075 MHz
C = 102.6 / 2.0 pF = 51.3 pF
Therefore, the XFCN value to use in this example is 010b.
Rev. 1.4
141
C8051F52x/F53x
SFR Definition 14.4. OSCXCN: External Oscillator Control
R
R/W
R/W
R/W
R/W
XTLVLD XOSCMD2 XOSCMD1 XOSCMD0 Reserved
Bit7
Bit6
Bit5
Bit4
Bit3
R/W
R/W
R/W
Reset Value
XFCN2
XFCN1
XFCN0
00000000
Bit2
Bit1
Bit0
SFR Address:
0xB1
Bit7:
XTLVLD: Crystal Oscillator Valid Flag. (Read only when XOSCMD = 11x.)
0: Crystal Oscillator is unused or not yet stable.
1: Crystal Oscillator is running and stable.
Bits6–4: XOSCMD2–0: External Oscillator Mode Bits.
00x: External Oscillator circuit off.
010: External CMOS Clock Mode.
011: External CMOS Clock Mode with divide by 2 stage.
100: RC Oscillator Mode.
101: Capacitor Oscillator Mode.
110: Crystal Oscillator Mode.
111: Crystal Oscillator Mode with divide by 2 stage.
Bit3:
RESERVED. Read = 0b; Must write 0b.
Bits2–0: XFCN2–0: External Oscillator Frequency Control Bits.
000-111: See table below:
XFCN
Crystal (XOSCMD = 11x)
RC (XOSCMD = 10x)
C (XOSCMD = 10x)
000
f  20 kHz
f 25 kHz
K Factor = 0.87
001
20 kHz f 58 kHz
25 kHz f 50 kHz
K Factor = 2.6
010
58 kHz  f 155 kHz
50 kHz f 100 kHz
K Factor = 7.7
011
155 kHz  f 415 kHz
100 kHz f 200 kHz
K Factor = 22
100
415 kHz  f 1.1 MHz
200 kHz f 400 kHz
K Factor = 65
101
1.1 MHz  f 3.1 MHz
400 kHz f 800 kHz
K Factor = 180
110
3.1 MHz  f 8.2 MHz
800 kHz f 1.6 MHz
K Factor = 664
111
8.2 MHz  f 25 MHz
1.6 MHz f 3.2 MHz
K Factor = 1590
Crystal Mode (Circuit from Figure 14.1, Option 1; XOSCMD = 11x)
Choose XFCN value to match crystal or resonator frequency.
RC Mode (Circuit from Figure 14.1, Option 2; XOSCMD = 10x)
Choose XFCN value to match frequency range:
f = 1.23(103) / (R x C), where
f = frequency of clock in MHz
C = capacitor value in pF
R = Pullup resistor value in k
C Mode (Circuit from Figure 14.1, Option 3; XOSCMD = 10x)
Choose K Factor (KF) for the oscillation frequency desired:
f = KF / (C x VDD), where
f = frequency of clock in MHz
C = capacitor value the XTAL2 pin in pF
VDD = Power Supply on MCU in volts
142
Rev. 1.4
C8051F52x/F53x
14.3. System Clock Selection
The internal oscillator requires little start-up time and may be selected as the system clock immediately following the OSCICN write that enables the internal oscillator. External crystals and ceramic resonators typically require a start-up time before they are settled and ready for use. The Crystal Valid Flag (XTLVLD in
register OSCXCN) is set to 1 by hardware when the external oscillator is settled. To avoid reading a false
XTLVLD in crystal mode, the software should delay at least 1 ms between enabling the external
oscillator and checking XTLVLD. RC and C modes typically require no startup time.
The CLKSL bit in register CLKSEL selects which oscillator source is used as the system clock. CLKSL
must be set to 1 for the system clock to run from the external oscillator; however the external oscillator may
still clock certain peripherals (timers, PCA) when another oscillator is selected as the system clock. The
system clock may be switched on-the-fly between the internal oscillator and external oscillator, as long as
the selected clock source is enabled and has settled.
SFR Definition 14.5. CLKSEL: Clock Select
R
R
-
-
Bit7
Bit6
R/W
R/W
Reserved Reserved
Bit5
Bit4
R
Bit3
R/W
R/W
Reserved Reserved
Bit2
Bit1
R/W
Reset Value
CLKSL
00000000
Bit0
SFR Address:
Bits7–6:
Bits5–4:
Bit3:
Bits2–1:
Bit0:
0xA9
Unused. Read = 00b; Write = don’t care.
Reserved. Read = 00b; Must write 00b.
Unused. Read = 0b; Write = don’t care.
Reserved. Read = 00b; Must write 00b.
CLKSL: System Clock Select
0: Internal Oscillator (as determined by the IFCN bits in register OSCICN).
1: External Oscillator.
Rev. 1.4
143
C8051F52x/F53x
15. UART0
UART0 is an asynchronous, full duplex serial port offering modes 1 and 3 of the standard 8051 UART.
Enhanced baud rate support allows a wide range of clock sources to generate standard baud rates (details
in Section “15.1. Enhanced Baud Rate Generation” on page 145). Received data buffering allows UART0
to start reception of a second incoming data byte before software has finished reading the previous data
byte. (Please refer to Section “20. Device Specific Behavior” on page 210 for more information on the pins associated with the UART interface.)
UART0 has two associated SFRs: Serial Control Register 0 (SCON0) and Serial Data Buffer 0 (SBUF0).
The single SBUF0 location provides access to both transmit and receive registers. Writes to SBUF0
always access the Transmit register. Reads of SBUF0 always access the buffered Receive register;
it is not possible to read data from the Transmit register.
With UART0 interrupts enabled, an interrupt is generated each time a transmit is completed (TI0 is set in
SCON0), or a data byte has been received (RI0 is set in SCON0). The UART0 interrupt flags are not
cleared by hardware when the CPU vectors to the interrupt service routine. They must be cleared manually
by software, allowing software to determine the cause of the UART0 interrupt (transmit complete or receive
complete).
SFR Bus
Write to
SBUF
TB8
SBUF
(TX Shift)
SET
D
Q
TX
CLR
Crossbar
Zero Detector
Stop Bit
Shift
Start
Data
Tx Control
Tx Clock
Send
Tx IRQ
SCON
TI
Serial
Port
Interrupt
MCE
REN
TB8
RB8
TI
RI
SMODE
UART Baud
Rate Generator
Port I/O
RI
Rx IRQ
Rx Clock
Rx Control
Start
Shift
0x1FF
RB8
Load
SBUF
Input Shift Register
(9 bits)
Load SBUF
SBUF
(RX Latch)
Read
SBUF
SFR Bus
RX
Figure 15.1. UART0 Block Diagram
144
Rev. 1.4
Crossbar
C8051F52x/F53x
15.1. Enhanced Baud Rate Generation
The UART0 baud rate is generated by Timer 1 in 8-bit auto-reload mode. The TX clock is generated by
TL1; the RX clock is generated by a copy of TL1 (shown as RX Timer in Figure 15.2), which is not useraccessible. Both TX and RX Timer overflows are divided by two to generate the TX and RX baud rates.
The RX Timer runs when Timer 1 is enabled, and uses the same reload value (TH1). However, an
RX Timer reload is forced when a START condition is detected on the RX pin. This allows a receive to
begin any time a START is detected, independent of the TX Timer state.
Timer 1
TL1
UART
Overflow
2
TX Clock
Overflow
2
RX Clock
TH1
Start
Detected
RX Timer
Figure 15.2. UART0 Baud Rate Logic
Timer 1 should be configured for Mode 2, 8-bit auto-reload (see Section “18.1.3. Mode 2: 8-bit Counter/Timer with Auto-Reload” on page 184). The Timer 1 reload value should be set so that overflows will
occur at two times the desired UART baud rate frequency. Note that Timer 1 may be clocked by one of six
sources: SYSCLK, SYSCLK / 4, SYSCLK / 12, SYSCLK / 48, the external oscillator clock / 8, or an external input T1. The UART0 baud rate is determined by Equation 15.1-A and Equation 15.1-B.
A)
B)
1
UartBaudRate = --- x T1_Overflow_Rate
2
T1 CLK
T1_Overflow_Rate = -------------------------256 – TH1
Equation 15.1. UART0 Baud Rate
Where T1CLK is the frequency of the clock supplied to Timer 1, and T1H is the high byte of Timer 1 (8-bit
auto-reload mode reload value). Timer 1 clock frequency is selected as described in Section “18. Timers”
on page 182. A quick reference for typical baud rates and system clock frequencies is given in Table 15.1.
Note that the internal oscillator may still generate the system clock when the external oscillator is driving
Timer 1.
Rev. 1.4
145
C8051F52x/F53x
15.2. Operational Modes
UART0 provides standard asynchronous, full duplex communication. The UART mode (8-bit or 9-bit) is
selected by the S0MODE bit (SCON0.7). Typical UART connection options are shown below.
TX
RS-232
LEVEL
XLTR
RS-232
RX
C8051Fxxx
OR
TX
TX
RX
RX
MCU
C8051Fxxx
Figure 15.3. UART Interconnect Diagram
15.2.1. 8-Bit UART
8-Bit UART mode uses a total of 10 bits per data byte: one start bit, eight data bits (LSB first), and one stop
bit. Data are transmitted LSB first from the TX0 pin and received at the RX0 pin. On receive, the eight data
bits are stored in SBUF0 and the stop bit goes into RB80 (SCON0.2).
Data transmission begins when software writes a data byte to the SBUF0 register. The TI0 Transmit Interrupt Flag (SCON0.1) is set at the end of the transmission (the beginning of the stop-bit time). Data reception can begin any time after the REN0 Receive Enable bit (SCON0.4) is set to logic 1. After the stop bit is
received, the data byte will be loaded into the SBUF0 receive register if the following conditions are met:
RI0 must be logic 0, and if MCE0 is logic 1, the stop bit must be logic 1. In the event of a receive data overrun, the first received 8 bits are latched into the SBUF0 receive register and the following overrun data bits
are lost.
If these conditions are met, the eight bits of data is stored in SBUF0, the stop bit is stored in RB80 and the
RI0 flag is set. If these conditions are not met, SBUF0 and RB80 will not be loaded and the RI0 flag will not
be set. An interrupt will occur if enabled when either TI0 or RI0 is set.
MARK
SPACE
START
BIT
D0
D1
D2
D3
D4
D5
BIT TIMES
BIT SAMPLING
Figure 15.4. 8-Bit UART Timing Diagram
146
Rev. 1.4
D6
D7
STOP
BIT
C8051F52x/F53x
15.2.2. 9-Bit UART
9-bit UART mode uses a total of eleven bits per data byte: a start bit, 8 data bits (LSB first), a programmable ninth data bit, and a stop bit. The state of the ninth transmit data bit is determined by the value in TB80
(SCON0.3), which is assigned by user software. It can be assigned the value of the parity flag (bit P in register PSW) for error detection, or used in multiprocessor communications. On receive, the ninth data bit
goes into RB80 (SCON0.2) and the stop bit is ignored.
Data transmission begins when an instruction writes a data byte to the SBUF0 register. The TI0 Transmit
Interrupt Flag (SCON0.1) is set at the end of the transmission (the beginning of the stop-bit time). Data
reception can begin any time after the REN0 Receive Enable bit (SCON0.4) is set to 1. After the stop bit is
received, the data byte will be loaded into the SBUF0 receive register if the following conditions are met:
(1) RI0 must be logic 0, and (2) if MCE0 is logic 1, the 9th bit must be logic 1 (when MCE0 is logic 0, the
state of the ninth data bit is unimportant). If these conditions are met, the eight bits of data are stored in
SBUF0, the ninth bit is stored in RB80, and the RI0 flag is set to 1. If the above conditions are not met,
SBUF0 and RB80 will not be loaded and the RI0 flag will not be set to 1. A UART0 interrupt will occur if
enabled when either TI0 or RI0 is set to 1.
MARK
SPACE
START
BIT
D0
D1
D2
D3
D4
D5
D6
D7
D8
STOP
BIT
BIT TIMES
BIT SAMPLING
Figure 15.5. 9-Bit UART Timing Diagram
Rev. 1.4
147
C8051F52x/F53x
15.3. Multiprocessor Communications
9-Bit UART mode supports multiprocessor communication between a master processor and one or more
slave processors by special use of the ninth data bit. When a master processor wants to transmit to one or
more slaves, it first sends an address byte to select the target(s). An address byte differs from a data byte
in that its ninth bit is logic 1; in a data byte, the ninth bit is always set to logic 0.
Setting the MCE0 bit (SCON0.5) of a slave processor configures its UART such that when a stop bit is
received, the UART will generate an interrupt only if the ninth bit is logic 1 (RB80 = 1) signifying an address
byte has been received. In the UART interrupt handler, software will compare the received address with
the slave's own assigned 8-bit address. If the addresses match, the slave will clear its MCE0 bit to enable
interrupts on the reception of the following data byte(s). Slaves that weren't addressed leave their MCE0
bits set and do not generate interrupts on the reception of the following data bytes, thereby ignoring the
data. Once the entire message is received, the addressed slave resets its MCE0 bit to ignore all transmissions until it receives the next address byte.
Multiple addresses can be assigned to a single slave and/or a single address can be assigned to multiple
slaves, thereby enabling "broadcast" transmissions to more than one slave simultaneously. The master
processor can be configured to receive all transmissions or a protocol can be implemented such that the
master/slave role is temporarily reversed to enable half-duplex transmission between the original master
and slave(s).
Master
Device
Slave
Device
Slave
Device
Slave
Device
V+
RX
TX
RX
TX
RX
TX
RX
TX
Figure 15.6. UART Multi-Processor Mode Interconnect Diagram
148
Rev. 1.4
C8051F52x/F53x
SFR Definition 15.1. SCON0: Serial Port 0 Control
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
S0MODE
-
MCE0
REN0
TB80
RB80
TI0
RI0
01000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Bit
Addressable
SFR Address:
0x98
Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
S0MODE: Serial Port 0 Operation Mode.
This bit selects the UART0 Operation Mode.
0: 8-bit UART with Variable Baud Rate.
1: 9-bit UART with Variable Baud Rate.
UNUSED. Read = 1b. Write = don’t care.
MCE0: Multiprocessor Communication Enable.
The function of this bit is dependent on the Serial Port 0 Operation Mode.
S0MODE = 0: Checks for valid stop bit.
0: Logic level of stop bit is ignored.
1: RI0 will only be activated if stop bit is logic level 1.
S0MODE = 1: Multiprocessor Communications Enable.
0: Logic level of ninth bit is ignored.
1: RI0 is set and an interrupt is generated only when the ninth bit is logic 1.
REN0: Receive Enable.
This bit enables/disables the UART receiver.
0: UART0 reception disabled.
1: UART0 reception enabled.
TB80: Ninth Transmission Bit.
The logic level of this bit will be assigned to the ninth transmission bit in 9-bit UART Mode. It
is not used in 8-bit UART Mode. Set or cleared by software as required.
RB80: Ninth Receive Bit.
RB80 is assigned the value of the STOP bit in Mode 0; it is assigned the value of the 9th
data bit in Mode 1.
TI0: Transmit Interrupt Flag.
Set by hardware when a byte of data has been transmitted by UART0 (after the 8th bit in 8bit UART Mode, or at the beginning of the STOP bit in 9-bit UART Mode). When the UART0
interrupt is enabled, setting this bit causes the CPU to vector to the UART0 interrupt service
routine. This bit must be cleared manually by software.
RI0: Receive Interrupt Flag.
Set to 1 by hardware when a byte of data has been received by UART0 (set at the STOP bit
sampling time). When the UART0 interrupt is enabled, setting this bit to 1 causes the CPU to
vector to the UART0 interrupt service routine. This bit must be cleared manually by software.
Rev. 1.4
149
C8051F52x/F53x
SFR Definition 15.2. SBUF0: Serial (UART0) Port Data Buffer
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
0x99
Bits7–0: SBUF0[7:0]: Serial Data Buffer Bits 7–0 (MSB–LSB)
This SFR accesses two registers; a transmit shift register and a receive latch register. When
data is written to SBUF0, it goes to the transmit shift register and is held for serial transmission. Writing a byte to SBUF0 initiates the transmission. A read of SBUF0 returns the contents of the receive latch.
Table 15.1. Timer Settings for Standard Baud Rates 
Using the Internal Oscillator
Frequency: 24.5 MHz
SYSCLK from
Internal Osc.
Target
Baud Rate
(bps)
150
230400
115200
57600
28800
14400
9600
2400
1200
Baud Rate
% Error
Timer Clock SCA1–SCA0
Oscillator Source
(pre-scale
Divide
select)*
Factor
T1M*
–0.32%
106
SYSCLK
XX
1
–0.32%
212
SYSCLK
XX
1
0.15%
426
SYSCLK
XX
1
–0.32%
848
SYSCLK / 4
01
0
0.15%
1704
SYSCLK / 12
00
0
–0.32%
2544
SYSCLK / 12
00
0
–0.32%
10176
SYSCLK / 48
10
0
0.15%
20448
SYSCLK / 48
10
0
X = Don’t care
Note: SCA1–SCA0 and T1M bit definitions can be found in Section 18.1.
Rev. 1.4
Timer 1
Reload
Value (hex)
0xCB
0x96
0x2B
0x96
0xB9
0x96
0x96
0x2B
C8051F52x/F53x
16. Enhanced Serial Peripheral Interface (SPI0)
The Serial Peripheral Interface (SPI0) provides access to a flexible, full-duplex synchronous serial bus.
SPI0 can operate as a master or slave device in both 3-wire or 4-wire modes, and supports multiple masters and slaves on a single SPI bus. The slave-select (NSS) signal can be configured as an input to select
SPI0 in slave mode, or to disable Master Mode operation in a multi-master environment, avoiding contention on the SPI bus when more than one master attempts simultaneous data transfers. NSS can also be
configured as a chip-select output in master mode, or disabled for 3-wire operation. Additional general purpose port I/O pins can be used to select multiple slave devices in master mode.
SFR Bus
SYSCLK
SPI0CN
SPIBSY
MSTEN
CKPHA
CKPOL
SLVSEL
NSSIN
SRMT
RXBMT
SPIF
WCOL
MODF
RXOVRN
NSSMD1
NSSMD0
TXBMT
SPIEN
SPI0CFG
SCR7
SCR6
SCR5
SCR4
SCR3
SCR2
SCR1
SCR0
SPI0CKR
Clock Divide
Logic
SPI CONTROL LOGIC
Data Path
Control
SPI IRQ
Pin Interface
Control
MOSI
Tx Data
SPI0DAT
SCK
Transmit Data Buffer
Shift Register
Rx Data
7 6 5 4 3 2 1 0
Receive Data Buffer
Pin
Control
Logic
MISO
C
R
O
S
S
B
A
R
Port I/O
NSS
Read
SPI0DAT
Write
SPI0DAT
SFR Bus
Figure 16.1. SPI Block Diagram
Rev. 1.4
151
C8051F52x/F53x
16.1. Signal Descriptions
The four signals used by SPI0 (MOSI, MISO, SCK, NSS) are described below.
16.1.1. Master Out, Slave In (MOSI)
The master-out, slave-in (MOSI) signal is an output from a master device and an input to slave devices. It
is used to serially transfer data from the master to the slave. This signal is an output when SPI0 is operating as a master and an input when SPI0 is operating as a slave. Data is transferred most-significant bit
first. When configured as a master, MOSI is driven by the MSB of the shift register in both 3- and 4-wire
mode.
16.1.2. Master In, Slave Out (MISO)
The master-in, slave-out (MISO) signal is an output from a slave device and an input to the master device.
It is used to serially transfer data from the slave to the master. This signal is an input when SPI0 is operating as a master and an output when SPI0 is operating as a slave. Data is transferred most-significant bit
first. The MISO pin is placed in a high-impedance state when the SPI module is disabled and when the SPI
operates in 4-wire mode as a slave that is not selected. When acting as a slave in 3-wire mode, MISO is
always driven by the MSB of the shift register.
16.1.3. Serial Clock (SCK)
The serial clock (SCK) signal is an output from the master device and an input to slave devices. It is used
to synchronize the transfer of data between the master and slave on the MOSI and MISO lines. SPI0 generates this signal when operating as a master. The SCK signal is ignored by a SPI slave when the slave is
not selected (NSS = 1) in 4-wire slave mode.
16.1.4. Slave Select (NSS)
The function of the slave-select (NSS) signal is dependent on the setting of the NSSMD1 and NSSMD0
bits in the SPI0CN register. There are three possible modes that can be selected with these bits:
1. NSSMD[1:0] = 00: 3-Wire Master or 3-Wire Slave Mode: SPI0 operates in 3-wire mode, and NSS is
disabled. When operating as a slave device, SPI0 is always selected in 3-wire mode. Since no select
signal is present, SPI0 must be the only slave on the bus in 3-wire mode. This is intended for point-topoint communication between a master and one slave.
2. NSSMD[1:0] = 01: 4-Wire Slave or Multi-Master Mode: SPI0 operates in 4-wire mode, and NSS is
enabled as an input. When operating as a slave, NSS selects the SPI0 device. When operating as a
master, a 1-to-0 transition of the NSS signal disables the master function of SPI0 so that multiple
master devices can be used on the same SPI bus.
3. NSSMD[1:0] = 1x: 4-Wire Master Mode: SPI0 operates in 4-wire mode, and NSS is enabled as an
output. The setting of NSSMD0 determines what logic level the NSS pin will output. This configuration
should only be used when operating SPI0 as a master device.
See Figure 16.2, Figure 16.3, and Figure 16.4 for typical connection diagrams of the various operational
modes. Note that the setting of NSSMD bits affects the pinout of the device. When in 3-wire master or
3-wire slave mode, the NSS pin will not be mapped by the crossbar. In all other modes, the NSS signal will
be mapped to a pin on the device. See Section “13. Port Input/Output” on page 120 for general purpose
port I/O and crossbar information.
152
Rev. 1.4
C8051F52x/F53x
16.2. SPI0 Master Mode Operation
A SPI master device initiates all data transfers on a SPI bus. SPI0 is placed in master mode by setting the
Master Enable flag (MSTEN, SPI0CN.6). Writing a byte of data to the SPI0 data register (SPI0DAT) when
in master mode writes to the transmit buffer. If the SPI shift register is empty, the byte in the transmit buffer
is moved to the shift register, and a data transfer begins. The SPI0 master immediately shifts out the data
serially on the MOSI line while providing the serial clock on SCK. The SPIF (SPI0CN.7) flag is set to logic
1 at the end of the transfer. If interrupts are enabled, an interrupt request is generated when the SPIF flag
is set. While the SPI0 master transfers data to a slave on the MOSI line, the addressed SPI slave device
simultaneously transfers data to the SPI master on the MISO line in a full-duplex operation. Therefore, the
SPIF flag serves as both a transmit-complete and receive-data-ready flag. The data byte received from the
slave is transferred MSB-first into the master's shift register. When a byte is fully shifted into the register, it
is moved to the receive buffer where it can be read by the processor by reading SPI0DAT.
When configured as a master, SPI0 can operate in one of three different modes: multi-master mode, 3-wire
single-master mode, and 4-wire single-master mode. The default, multi-master mode is active when
NSSMD1 (SPI0CN.3) = 0 and NSSMD0 (SPI0CN.2) = 1. In this mode, NSS is an input to the device, and
is used to disable the master SPI0 when another master is accessing the bus. When NSS is pulled low in
this mode, MSTEN (SPI0CN.6) and SPIEN (SPI0CN.0) are set to 0 to disable the SPI master device, and
a Mode Fault is generated (MODF, SPI0CN.5 = 1). Mode Fault will generate an interrupt if enabled. SPI0
must be manually re-enabled in software under these circumstances. In multi-master systems, devices will
typically default to being slave devices while they are not acting as the system master device. In multi-master mode, slave devices can be addressed individually (if needed) using general-purpose I/O pins.
Figure 16.2 shows a connection diagram between two master devices in multiple-master mode.
3-wire single-master mode is active when NSSMD1 (SPI0CN.3) = 0 and NSSMD0 (SPI0CN.2) = 0. In this
mode, NSS is not used and is not mapped to an external port pin through the crossbar. Any slave devices
that must be addressed in this mode should be selected using general-purpose I/O pins. Figure 16.3
shows a connection diagram between a master device in 3-wire master mode and a slave device.
4-wire single-master mode is active when NSSMD1 (SPI0CN.3) = 1. In this mode, NSS is configured as an
output pin and can be used as a slave-select signal for a single SPI device. In this mode, the output value
of NSS is controlled (in software) with the bit NSSMD0 (SPI0CN.2). Additional slave devices can be
addressed using general-purpose I/O pins. Figure 16.4 shows a connection diagram for a master device in
4-wire master mode and two slave devices.
Rev. 1.4
153
C8051F52x/F53x
Master
Device 1
NSS
GPIO
MISO
MISO
MOSI
MOSI
SCK
SCK
GPIO
NSS
Master
Device 2
Figure 16.2. Multiple-Master Mode Connection Diagram
Master
Device
MISO
MISO
MOSI
MOSI
SCK
SCK
Slave
Device
Figure 16.3. 3-Wire Single Master and Slave Mode Connection Diagram
Master
Device
MISO
MISO
MOSI
MOSI
GPIO
SCK
SCK
NSS
NSS
MISO
MOSI
Slave
Device
Slave
Device
SCK
NSS
Figure 16.4. 4-Wire Single Master and Slave Mode Connection Diagram
16.3. SPI0 Slave Mode Operation
When SPI0 is enabled and not configured as a master, it will operate as a SPI slave. As a slave, bytes are
shifted in through the MOSI pin and out through the MISO pin by a master device controlling the SCK signal. A bit counter in the SPI0 logic counts SCK edges. When 8 bits have been shifted into the shift register,
the SPIF flag is set to logic 1, and the byte is copied into the receive buffer. Data is read from the receive
buffer by reading SPI0DAT. A slave device cannot initiate transfers. Data to be transferred to the master
device is pre-loaded into the shift register by writing to SPI0DAT. Writes to SPI0DAT are double-buffered,
and are placed in the transmit buffer first. If the shift register is empty, the contents of the transmit buffer
will immediately be transferred into the shift register. When the shift register already contains data, the SPI
will load the shift register with the transmit buffer’s contents after the last SCK edge of the next (or current)
SPI transfer.
154
Rev. 1.4
C8051F52x/F53x
The shift register contents are locked after the slave detects the first edge of SCK. Writes to SPI0DAT that
occur after the first SCK edge will be held in the TX latch until the end of the current transfer.
When configured as a slave, SPI0 can be configured for 4-wire or 3-wire operation. The default, 4-wire
slave mode, is active when NSSMD1 (SPI0CN.3) = 0 and NSSMD0 (SPI0CN.2) = 1. In 4-wire mode, the
NSS signal is routed to a port pin and configured as a digital input. SPI0 is enabled when NSS is logic 0,
and disabled when NSS is logic 1. The bit counter is reset on a falling edge of NSS. Note that the NSS signal must be driven low at least 2 system clocks before the first active edge of SCK for each byte transfer.
Figure 16.4 shows a connection diagram between two slave devices in 4-wire slave mode and a master
device.
3-wire slave mode is active when NSSMD1 (SPI0CN.3) = 0 and NSSMD0 (SPI0CN.2) = 0. NSS is not
used in this mode, and is not mapped to an external port pin through the crossbar. Since there is not a way
of uniquely addressing the device in 3-wire slave mode, SPI0 must be the only slave device present on the
bus. It is important to note that in 3-wire slave mode there is no external means of resetting the bit counter
that determines when a full byte has been received. The bit counter can only be reset by disabling and reenabling SPI0 with the SPIEN bit. Figure 16.3 shows a connection diagram between a slave device in 3wire slave mode and a master device.
16.4. SPI0 Interrupt Sources
When SPI0 interrupts are enabled, the following four flags will generate an interrupt when they are set to
logic 1:
Note that all of the following interrupt bits must be cleared by software.
1. The SPI Interrupt Flag, SPIF (SPI0CN.7) is set to logic 1 at the end of each byte transfer. This flag can
occur in all SPI0 modes.
2. The Write Collision Flag, WCOL (SPI0CN.6) is set to logic 1 if a write to SPI0DAT is attempted when
the transmit buffer has not been emptied to the SPI shift register. When this occurs, the write to
SPI0DAT will be ignored, and the transmit buffer will not be written.This flag can occur in all SPI0
modes.
3. The Mode Fault Flag MODF (SPI0CN.5) is set to logic 1 when SPI0 is configured as a master in multimaster mode and the NSS pin is pulled low. When a Mode Fault occurs, the MSTEN and SPIEN bits in
SPI0CN are set to logic 0 to disable SPI0 and allow another master device to access the bus.
4. The Receive Overrun Flag RXOVRN (SPI0CN.4) is set to logic 1 when configured as a slave, and a
transfer is completed while the receive buffer still holds an unread byte from a previous transfer. The
new byte is not transferred to the receive buffer, allowing the previously received data byte to be read.
The data byte which caused the overrun is lost.
Rev. 1.4
155
C8051F52x/F53x
16.5. Serial Clock Timing
Four combinations of serial clock phase and polarity can be selected using the clock control bits in the
SPI0 Configuration Register (SPI0CFG). The CKPHA bit (SPI0CFG.5) selects one of two clock phases
(edge used to latch the data). The CKPOL bit (SPI0CFG.4) selects between a rising edge or a falling edge.
Both master and slave devices must be configured to use the same clock phase and polarity. SPI0 should
be disabled (by clearing the SPIEN bit, SPI0CN.0) when changing the clock phase or polarity. The clock
and data line relationships are shown in Figure 16.5.
The SPI0 Clock Rate Register (SPI0CKR) as shown in SFR Definition 16.3 controls the master mode
serial clock frequency. This register is ignored when operating in slave mode. When the SPI is configured
as a master, the maximum data transfer rate (bits/sec) is one-half the system clock frequency or 12.5 MHz,
whichever is slower. When the SPI is configured as a slave, the maximum data transfer rate (bits/sec) for
full-duplex operation is 1/10 the system clock frequency, provided that the master issues SCK, NSS (in 4wire slave mode), and the serial input data synchronously with the slave’s system clock. If the master
issues SCK, NSS, and the serial input data asynchronously, the maximum data transfer rate (bits/sec)
must be less than 1/10 the system clock frequency. In the special case where the master only wants to
transmit data to the slave and does not need to receive data from the slave (i.e. half-duplex operation), the
SPI slave can receive data at a maximum data transfer rate (bits/sec) of 1/4 the system clock frequency.
This is provided that the master issues SCK, NSS, and the serial input data synchronously with the slave’s
system clock.
SCK
(CKPOL=0, CKPHA=0)
SCK
(CKPOL=0, CKPHA=1)
SCK
(CKPOL=1, CKPHA=0)
SCK
(CKPOL=1, CKPHA=1)
MISO/MOSI
MSB
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Figure 16.5. Data/Clock Timing Relationship
16.6. SPI Special Function Registers
SPI0 is accessed and controlled through four special function registers in the system controller: SPI0CN
Control Register, SPI0DAT Data Register, SPI0CFG Configuration Register, and SPI0CKR Clock Rate
Register. The four special function registers related to the operation of the SPI0 Bus are described in the
following figures.
156
Rev. 1.4
C8051F52x/F53x
SFR Definition 16.1. SPI0CFG: SPI0 Configuration
R
R/W
R/W
R/W
R
R
R
R
Reset Value
SPIBSY
MSTEN
CKPHA
CKPOL
SLVSEL
NSSIN
SRMT
RXBMT
00000111
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address: 0xA1
Bit 7:
Bit 6:
Bit 5:
Bit 4:
Bit 3:
Bit 2:
Bit 1:
Bit 0:
SPIBSY: SPI Busy (read only).
This bit is set to logic 1 when a SPI transfer is in progress (Master or Slave Mode).
MSTEN: Master Mode Enable.
0: Disable master mode. Operate in slave mode.
1: Enable master mode. Operate as a master.
CKPHA: SPI0 Clock Phase.
This bit controls the SPI0 clock phase.
0: Data centered on first edge of SCK period.*
1: Data centered on second edge of SCK period.*
CKPOL: SPI0 Clock Polarity.
This bit controls the SPI0 clock polarity.
0: SCK line low in idle state.
1: SCK line high in idle state.
SLVSEL: Slave Selected Flag (read only).
This bit is set to logic 1 whenever the NSS pin is low indicating SPI0 is the selected slave. It
is cleared to logic 0 when NSS is high (slave not selected). This bit does not indicate the
instantaneous value at the NSS pin, but rather a de-glitched version of the pin input.
NSSIN: NSS Instantaneous Pin Input (read only).
This bit mimics the instantaneous value that is present on the NSS port pin at the time that
the register is read. This input is not de-glitched.
SRMT: Shift Register Empty (Valid in Slave Mode, read only).
This bit will be set to logic 1 when all data has been transferred in/out of the shift register,
and there is no new information available to read from the transmit buffer or write to the
receive buffer. It returns to logic 0 when a data byte is transferred to the shift register from
the transmit buffer or by a transition on SCK.
NOTE: SRMT = 1 when in Master Mode.
RXBMT: Receive Buffer Empty (Valid in Slave Mode, read only).
This bit will be set to logic 1 when the receive buffer has been read and contains no new
information. If there is new information available in the receive buffer that has not been read,
this bit will return to logic 0.
NOTE: RXBMT = 1 when in Master Mode.
Note: See Table 16.1 for timing parameters.
Rev. 1.4
157
C8051F52x/F53x
SFR Definition 16.2. SPI0CN: SPI0 Control
R/W
R/W
R/W
SPIF
WCOL
MODF
Bit7
Bit6
Bit5
R/W
R/W
R/W
RXOVRN NSSMD1 NSSMD0
Bit4
Bit3
Bit2
R
R/W
Reset Value
TXBMT
SPIEN
00000110
Bit1
Bit0
Bit
Addressable
SFR Address: 0xF8
Bit7:
SPIF: SPI0 Interrupt Flag.
This bit is set to logic 1 by hardware at the end of a data transfer. If interrupts are enabled,
setting this bit causes the CPU to vector to the SPI0 interrupt service routine. This bit is not
automatically cleared by hardware. It must be cleared by software.
Bit6:
WCOL: Write Collision Flag.
This bit is set to logic 1 by hardware (and generates a SPI0 interrupt) if a write to SPI0DAT is
attempted when the transmit buffer has not been emptied to the SPI shift register. When this
occurs, the write to SPI0DAT will be ignored, and the transmit buffer will not be written. This
bit is not automatically cleared by hardware. It must be cleared by software.
Bit5:
MODF: Mode Fault Flag.
This bit is set to logic 1 by hardware (and generates a SPI0 interrupt) when a master mode
collision is detected (NSS is low, MSTEN = 1, and NSSMD[1:0] = 01). This bit is not automatically cleared by hardware. It must be cleared by software.
Bit4:
RXOVRN: Receive Overrun Flag (Slave Mode only).
This bit is set to logic 1 by hardware (and generates a SPI0 interrupt) when the receive buffer still holds unread data from a previous transfer and the last bit of the current transfer is
shifted into the SPI0 shift register. This bit is not automatically cleared by hardware. It must
be cleared by software.
Bits3–2: NSSMD1–NSSMD0: Slave Select Mode.
Selects between the following NSS operation modes:
(See Section “16.2. SPI0 Master Mode Operation” on page 153 and Section “16.3. SPI0
Slave Mode Operation” on page 154).
00: 3-Wire Slave or 3-wire Master Mode. NSS signal is not routed to a port pin.
01: 4-Wire Slave or Multi-Master Mode (Default). NSS is always an input to the device.
1x: 4-Wire Single-Master Mode. NSS signal is mapped as an output from the device and will
assume the value of NSSMD0.
Bit1:
TXBMT: Transmit Buffer Empty.
This bit will be set to logic 0 when new data has been written to the transmit buffer. When
data in the transmit buffer is transferred to the SPI shift register, this bit will be set to logic 1,
indicating that it is safe to write a new byte to the transmit buffer.
Bit0:
SPIEN: SPI0 Enable.
This bit enables/disables the SPI.
0: SPI disabled.
1: SPI enabled.
158
Rev. 1.4
C8051F52x/F53x
SFR Definition 16.3. SPI0CKR: SPI0 Clock Rate
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
SCR7
SCR6
SCR5
SCR4
SCR3
SCR2
SCR1
SCR0
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address: 0xA2
Bits7–0: SCR7–SCR0: SPI0 Clock Rate.
These bits determine the frequency of the SCK output when the SPI0 module is configured
for master mode operation. The SCK clock frequency is a divided version of the system
clock, and is given in the following equation, where SYSCLK is the system clock frequency
and SPI0CKR is the 8-bit value held in the SPI0CKR register.
SYSCLK
f SCK = ------------------------------------------------2   SPI0CKR + 1 
for 0 <= SPI0CKR <= 255
Example: If SYSCLK = 2 MHz and SPI0CKR = 0x04,
2000000
f SCK = -------------------------2  4 + 1
f SCK = 200kHz
Rev. 1.4
159
C8051F52x/F53x
SFR Definition 16.4. SPI0DAT: SPI0 Data
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address: 0xA3
Bits7–0: SPI0DAT: SPI0 Transmit and Receive Data.
The SPI0DAT register is used to transmit and receive SPI0 data. Writing data to SPI0DAT
places the data into the transmit buffer and initiates a transfer when in Master Mode. A read
of SPI0DAT returns the contents of the receive buffer.
160
Rev. 1.4
C8051F52x/F53x
SCK*
T
MCKH
T
MCKL
T
T
MIS
MIH
MISO
MOSI
* SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1.
Figure 16.6. SPI Master Timing (CKPHA = 0)
SCK*
T
MCKH
T
MIS
T
MCKL
T
MIH
MISO
MOSI
* SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1.
Figure 16.7. SPI Master Timing (CKPHA = 1)
Rev. 1.4
161
C8051F52x/F53x
NSS
T
T
SE
T
CKL
SD
SCK*
T
CKH
T
SIS
T
SIH
MOSI
T
T
SEZ
T
SOH
SDZ
MISO
* SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1.
Figure 16.8. SPI Slave Timing (CKPHA = 0)
NSS
T
T
SE
T
CKL
SD
SCK*
T
CKH
T
SIS
T
SIH
MOSI
T
SEZ
T
T
SOH
SDZ
MISO
* SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1.
Figure 16.9. SPI Slave Timing (CKPHA = 1)
162
Rev. 1.4
C8051F52x/F53x
Table 16.1. SPI Slave Timing Parameters
Parameter
Description
Min
Max
Units
Master Mode Timing* (See Figure 16.6 and Figure 16.7)
TMCKH
SCK High Time
1 x TSYSCLK
—
ns
TMCKL
SCK Low Time
1 x TSYSCLK
—
ns
TMIS
MISO Valid to SCK Sample Edge
20
—
ns
TMIH
SCK Sample Edge to MISO Change
0
—
ns
Slave Mode Timing* (See Figure 16.8 and Figure 16.9)
TSE
NSS Falling to First SCK Edge
2 x TSYSCLK
—
ns
TSD
Last SCK Edge to NSS Rising
2 x TSYSCLK
—
ns
TSEZ
NSS Falling to MISO Valid
—
4 x TSYSCLK
ns
TSDZ
NSS Rising to MISO High-Z
—
4 x TSYSCLK
ns
TCKH
SCK High Time
5 x TSYSCLK
—
ns
TCKL
SCK Low Time
5 x TSYSCLK
—
ns
TSIS
MOSI Valid to SCK Sample Edge
2 x TSYSCLK
—
ns
TSIH
SCK Sample Edge to MOSI Change
2 x TSYSCLK
—
ns
TSOH
SCK Shift Edge to MISO Change
—
4 x TSYSCLK
ns
Note: TSYSCLK is equal to one period of the device system clock (SYSCLK) in ns. 
The maximum possible frequency of the SPI can be calculated as:
Transmission: SYSCLK/2
Reception: SYSCLK/10
Rev. 1.4
163
C8051F52x/F53x
17. LIN (C8051F520/0A/3/3A/6/6A and C8051F530/0A/3/3A/6/6A)
Important Note: This chapter assumes an understanding of the Local Interconnect Network (LIN) protocol. For more information about the LIN protocol, including specifications, please refer to the LIN consortium (http://www.lin-subbus.org/).
LIN is an asynchronous, serial communications interface used primarily in automotive networks. The Silicon Laboratories LIN controller is compliant to the 2.1 Specification, implements a complete hardware LIN
interface, and includes the following features:

Selectable Master and Slave modes.
Automatic baud rate option in slave mode
 The internal oscillator is accurate to within 0.5% of 24.5 MHz across the entire temperature range and
for VDD voltages greater than or equal to the minimum output of the on-chip voltage regulator, so an
external oscillator is not necessary for master mode operation for most systems.

Note: The minimum system clock (SYSCLK) required when using the LIN peripheral is 8 MHz.
C8051F520/0A/3/3A/6/6A and C8051F530/0A/3/3A/6/6A
LIN Controller
LIN Data
Registers
8051 MCU Core
LIN Control
Registers
LINADDR
LINDATA
Indirectly Addressed Registers
TX
Control State Machine
LINCF
RX
Figure 17.1. LIN Block Diagram
The LIN peripheral has four main components:
1.
2.
3.
4.
164
LIN Access Registers—Provide the interface between the MCU core and the LIN peripheral.
LIN Data Registers—Where transmitted and received message data bytes are stored.
LIN Control Registers—Control the functionality of the LIN interface.
Control State Machine and Bit Streaming Logic—Contains the hardware that serializes messages and controls the bus timing of the controller.
Rev. 1.4
C8051F52x/F53x
17.1. Software Interface with the LIN Peripheral
The selection of the mode (Master or Slave) and the automatic baud rate feature are done though the LIN0
Control Mode (LIN0CF) register. The other LIN registers are accessed indirectly through the two SFRs
LIN0 Address (LINADDR) and LIN0 Data (LINDATA). The LINADDR register selects which LIN register is
targeted by reads/writes of the LINDATA register. The full list of indirectly-accessible LIN register is given in
Table 17.4 on page 174.
17.2. LIN Interface Setup and Operation
The hardware based LIN peripheral allows for the implementation of both Master and Slave nodes with
minimal firmware overhead and complete control of the interface status while allowing for interrupt and
polled mode operation.
The first step to use the peripheral is to define the basic characteristics of the node:

Mode—Master or Slave
 Baud Rate—Either defined manually or using the autobaud feature (slave mode only).
 Checksum Type—Select between classic or enhanced checksum, both of which are implemented in
hardware.
17.2.1. Mode Definition
Following the LIN specification, the peripheral implements both the Slave and Master operating modes in
hardware. The mode is configured using the MODE bit (LIN0CF.6).
17.2.2. Baud Rate Options: Manual or Autobaud
The LIN peripheral can be selected to have its baud rate calculated manually or automatically. A master
node must always have its baud rate set manually, but slave nodes can choose between a manual or automatic setup. The configuration is selected using the ABAUD bit (LIN0CF.5).
Both the manual and automatic baud rate configurations require additional setup. The following sections
explain the different options available and their relation with the baud rate, along with the steps necessary
to achieve the required baud rate.
17.2.3. Baud Rate Calculations—Manual Mode
The baud rate used by the peripheral is a function of the System Clock (SYSCLK) and the bit-timing Registers according to the following equation:
SYSCLK
baud_rate = ----------------------------------------------------------------------------------------------------- prescaler + 1 
 divider   multiplier + 1 
2
The prescaler, divider and multiplier factors are part of the LIN0DIV and LIN0MUL registers and can
assume values in the following range:
Rev. 1.4
165
C8051F52x/F53x
Table 17.1. Baud-Rate Calculation Variable Ranges
Factor
Range
prescaler
0…3
multiplier
0…31
divider
200…511
Important: The minimum system clock (SYSCLK) to operate the LIN peripheral is 8 MHz.
Use the following equations to calculate the values for the variables for the baud-rate equation:
20000
multiplier = --------------------------- – 1
baud_rate
1
SYSCLK
prescaler = ln ------------------------------------------------------------------------------------------  -------- – 1
 multiplier + 1   baud_rate  200
ln2
SYSCLK
divider = ------------------------------------------------------------------------------------------------------------------ prescaler + 1 
2
  multiplier + 1   baud_rate 
It is important to note that in all these equations, the results must be rounded down to the nearest integer.
The following example shows the steps for calculating the baud rate values for a Master node running at
24.5 MHz and communicating at 19200 bits/sec. First, calculate the multiplier:
20000
multiplier = --------------- – 1 = 0.0417  0
19200
Next, calculate the prescaler:
1
24500000
prescaler = ln -----------------------------------------------------  -------- – 1 = 1.674  1
 0 + 1   19200  200 ln2
Finally, calculate the divider:
24500000
- = 319.010  319
divider = -----------------------------------------------------------1 + 1
2
  0 + 1   19200
These values lead to the following baud rate:
24500000
-  19200.63
baud_rate = -----------------------------------------------------1 + 1
2
  0 + 1   319
166
Rev. 1.4
C8051F52x/F53x
The following code programs the interface in Master mode, using the Enhanced Checksum and enables
the interface to operate at 19200 bits/sec using a 24 MHz system clock.
LIN0CF
LIN0CF
= 0x80;// Activate the interface
|= 0x40;// Set the node as a Master
LINADDR
= 0x0D;// Point to the LIN0MUL register
// Initialize the register (prescaler, multiplier and bit 8 of divider)
LINDATA
= ( 0x01 << 6 ) + ( 0x00 << 1 ) + ( ( 0x13F & 0x0100 ) >> 8 );
LINADDR
= 0x0C;// Point to the LIN0DIV register
LINDATA
= (unsigned char)_0x13F;// Initialize LIN0DIV
LINADDR
LINDATA
LINADDR
= 0x0B;// Point to the LIN0SIZE register
|= 0x80;// Initialize the checksum as Enhanced
= 0x08;// Point to LIN0CTRL register
LINDATA = 0x0C;// Reset any error and the interrupt
Table 17.2 includes the configuration values required for the typical system clocks and baud rates:
Table 17.2. Manual Baud Rate Parameters Examples
Baud (bits / sec)
20 K
Mult.
Pres.
Div.
Mult.
Pres.
Div.
Mult.
Pres.
Div.
Mult.
Pres.
Div.
1K
Div.
4.8 K
Pres.
9.6 K
Mult.
SYSCLK
(MHz)
19.2 K
25
0
1
312
0
1
325
1
1
325
3
1
325
19
1
312
24.5
0
1
306
0
1
319
1
1
319
3
1
319
19
1
306
24
0
1
300
0
1
312
1
1
312
3
1
312
19
1
300
22.1184
0
1
276
0
1
288
1
1
288
3
1
288
19
1
276
16
0
1
200
0
1
208
1
1
208
3
1
208
19
1
200
12.25
0
0
306
0
0
319
1
0
319
3
0
319
19
0
306
12
0
0
300
0
0
312
1
0
312
3
0
312
19
0
300
11.0592
0
0
276
0
0
288
1
0
288
3
0
288
19
0
276
8
0
0
200
0
0
208
1
0
208
3
0
208
19
0
200
Rev. 1.4
167
C8051F52x/F53x
17.2.4. Baud Rate Calculations—Automatic Mode
If the LIN peripheral is configured for slave mode, only the prescaler and divider need to be calculated:
SYSCLK
1
prescaler = ln ----------------------  -------- – 1
4000000
ln2
SYSCLK
divider = ---------------------------------------------------- prescaler + 1 
2
 20000
The following example calculates the values of these variables for a 24 MHz system clock:
24500000
1
prescaler = ln ------------------------  -------- – 1 = 1.615  1
4000000
ln2
24500000 = 306.25  306
divider = -----------------------------------1 + 1
 20000
2
Table 17.3 presents some typical values of system clock and baud rate along with their factors.
Table 17.3. Autobaud Parameters Examples
168
System Clock (MHz)
Prescaler
Divider
25
1
312
24.5
1
306
24
1
300
22.1184
1
276
16
1
200
12.25
0
306
12
0
300
11.0592
0
276
8
0
200
Rev. 1.4
C8051F52x/F53x
17.3. LIN Master Mode Operation
The master node is responsible for the scheduling of messages and sends the header of each frame, containing the SYNCH BREAK FIELD, SYNCH FIELD and IDENTIFIER FIELD. The steps to schedule a message transmission or reception are listed below.
1. Load the 6-bit Identifier into the LIN0ID register.
2. Load the data length into the LIN0SIZE register. Set the value to the number of data bytes or "1111b" if
the data length should be decoded from the identifier. Also, set the checksum type, classic or
enhanced, in the same LIN0SIZE register.
3. Set the data direction by setting the TXRX bit (LIN0CTRL.5). Set the bit to 1 to perform a master
transmit operation, or set the bit to 0 to perform a master receive operation.
4. If performing a master transmit operation, load the data bytes to transmit into the data buffer (LIN0DT1
to LIN0DT8).
5. Set the STREQ bit (LIN0CTRL.0) to start the message transfer. The LIN peripheral will schedule the
message frame and request an interrupt if the message transfer is successfully completed or if an error
has occurred.
This code segment shows the procedure to schedule a message in a transmission operation:
LINADDR
LINDATA
LINADDR
LINDATA
LINADDR
LINDATA
=
|=
=
=
=
=
0x08;// Point to LIN0CTRL
0x20;// Select to transmit data
0x0E;// Point to LIN0ID
0x11;// Load the ID, in this example 0x11
0x0B;// Point to LIN0SIZE
( LINDATA & 0xF0 ) | 0x08; // Load the size with 8
LINADDR = 0x00;// Point to Data buffer first byte
for (i=0; i<8; i++)
{
LINDATA = i + 0x41;// Load the buffer with ‘A’, ‘B’, ...
LINADDR++;// Increment the address to the next buffer
}
LINADDR
= 0x08;// Point to LIN0CTRL
LINDATA
= 0x01;// Start Request
The application should perform the following steps when an interrupt is requested.
1. Check the DONE bit (LIN0ST.0) and the ERROR bit (LIN0ST.2).
2. If performing a master receive operation and the transfer was successful, read the received data from
the data buffer.
3. If the transfer was not successful, check the error register to determine the kind of error. Further error
handling has to be done by the application.
4. Set the RSTINT (LIN0CTRL.3) and RSTERR bits (LIN0CTRL.2) to reset the interrupt request and the
error flags.
Rev. 1.4
169
C8051F52x/F53x
17.4. LIN Slave Mode Operation
When the device is configured for slave mode operation, it must wait for a command from a master node.
Access from the firmware to data buffer and ID registers of the LIN peripheral is only possible when a data
request is pending (DTREQ bit (LIN0ST.4) is 1) and also when the LIN bus is not active (ACTIVE bit
(LIN0ST.7) is set to 0).
The LIN peripheral in slave mode detects the header of the message frame sent by the LIN master. If slave
synchronization is enabled (autobaud), the slave synchronizes its internal bit time to the master bit time.
The LIN peripheral configured for slave mode will generated an interrupt in one of three situations:
1. After the reception of the IDENTIFIER FIELD.
2. When an error is detected.
3. When the message transfer is completed.
The application should perform the following steps when an interrupt is detected:
1. Check the status of the DTREQ bit (LIN0ST.4). This bit is set when the IDENTIFIER FIELD has been
received.
2. If DTREQ (LIN0ST.4) is set, read the identifier from LIN0ID and process it. If DTREQ (LIN0ST.4) is not
set, continue to step 7.
3. Set the TXRX bit (LIN0CTRL.5) to 1 if the current frame is a transmit operation for the slave and set to
0 if the current frame is a receive operation for the slave.
4. Load the data length into LIN0SIZE.
5. For a slave transmit operation, load the data to transmit into the data buffer.
6. Set the DTACK bit (LIN0CTRL.4). Continue to step 10.
7. If DTREQ (LIN0ST.4) is not set, check the DONE bit (LIN0ST.0). The transmission was successful if the
DONE bit is set.
8. If the transmission was successful and the current frame was a receive operation for the slave, load the
received data bytes from the data buffer.
9. If the transmission was not successful, check LIN0ERR to determine the nature of the error. Further
error handling has to be done by the application.
10.Set the RSTINT (LIN0CTRL.3) and RSTERR bits (LIN0CTRL.2) to reset the interrupt request and the
error flags.
In addition to these steps, the application should be aware of the following:
1. If the current frame is a transmit operation for the slave, steps 1 through 5 must be completed during
the IN-FRAME RESPONSE SPACE. If it is not completed in time, a timeout will be detected by the
master.
2. If the current frame is a receive operation for the slave, steps 1 through 5 have to be finished until the
reception of the first byte after the IDENTIFIER FIELD. Otherwise, the internal receive buffer of the LIN
peripheral will be overwritten and a timeout error will be detected in the LIN peripheral.
3. The LIN module does not directly support LIN Version 1.3 Extended Frames. If the application detects
an unknown identifier (e.g. extended identifier), it has to write a 1 to the STOP bit (LIN0CTRL.7) instead
of setting the DTACK (LIN0CTRL.4) bit. At that time, steps 2 through 5 can then be skipped. In this
situation, the LIN peripheral stops the processing of the LIN communication until the next SYNC
BREAK is received.
4. Changing the configuration of the checksum during a transaction will cause the interface to reset and
the transaction to be lost. To prevent this, the checksum should not be configured while a transaction is
170
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C8051F52x/F53x
in progress. The same applies to changes in the LIN interface mode from slave mode to master mode
and from master mode to slave mode.
17.5. Sleep Mode and Wake-Up
To reduce the system’s power consumption, the LIN Protocol Specification defines a Sleep Mode. The
message used to broadcast a Sleep Mode request must be transmitted by the LIN master application in
the same way as a normal transmit message. The LIN slave application must decode the Sleep Mode
Frame from the Identifier and data bytes. After that, the LIN slave node must be put into the Sleep Mode by
setting the SLEEP bit (LIN0CTRL.6).
If the SLEEP bit (LIN0CTRL.6) of the LIN slave application is not set and there is no bus activity for four
seconds (specified bus idle timeout), the IDLTOUT bit (LIN0ST.6) is set and an interrupt request is generated. After that the application may assume that the LIN bus is in Sleep Mode and set the SLEEP bit
(LIN0CTRL.6).
Sending a Wakeup signal from the master or any slave node terminates the Sleep Mode of the LIN bus. To
send a Wakeup signal, the application has to set the WUPREQ bit (LIN0CTRL.1). After successful transmission of the wakeup signal, the DONE bit (LIN0ST.0) of the master node is set and an interrupt request
is generated. The LIN slave does not generate an interrupt request after successful transmission of the
Wakeup signal but it generates an interrupt request if the master does not respond to the Wakeup signal
within 150 milliseconds. In that case, the ERROR bit (LIN0ST.2) and TOUT bit (LIN0ERR.2) are set. The
application then has to decide whether or not to transmit another Wakeup signal.
All LIN nodes that detect a wakeup signal will set the WAKEUP (LIN0ST.1) and DONE bits (LIN0ST.0) and
generate an interrupt request. After that, the application has to clear the SLEEP bit (LIN0CTRL.6) in the
LIN slave.
17.6. Error Detection and Handling
The LIN peripheral generates an interrupt request and stops the processing of the current frame if it
detects an error. The application has to check the type of error by processing LIN0ERR. After that, it has to
reset the error register and the ERROR bit (LIN0ST.2) by writing a 1 to the RSTERR bit (LIN0CTRL.2).
Starting a new message with the LIN peripheral selected as master or sending a Wakeup signal with the
LIN peripheral selected as a master or slave is possible only if ERROR bit (LIN0ST.2) is set to 0.
Rev. 1.4
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C8051F52x/F53x
17.7. LIN Registers
The following Special Function Registers (SFRs) are available:
17.7.1. LIN Direct Access SFR Registers Definition
SFR Definition 17.1. LINADDR: Indirect Address Register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
Bit7–0:
0x92
LINADDR7-0: LIN Indirect Address Register Bits.
This register hold an 8-bit address used to indirectly access the LIN0 core registers.
Table 17.4 lists the LIN0 core registers and their indirect addresses. Reads and writes to
LINDATA will target the register indicated by the LINADDR bits.
SFR Definition 17.2. LINDATA: LIN Data Register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
Bit7–0:
172
0x93
LINDATA7-0: LIN Indirect Data Register Bits.
When this register is read, it will read the contents of the LIN0 core register pointed to by
LINADDR.
When this register is written, it will write the value to the LIN0 core register pointed to by LINADDR.
Rev. 1.4
C8051F52x/F53x
SFR Definition 17.3. LINCF Control Mode Register
R/W
R/W
R/W
LINEN
MODE
ABAUD
Bit7
Bit6
Bit5
R/W
R/W
R/W
R/W
R/W
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
Bit7:
Bit6:
Bit5:
Reset Value
00000000
0x95
LINEN: LIN Interface Enable bit
0: LIN0 is disabled.
1: LIN0 is enabled.
MODE: LIN Mode Selection
0: LIN0 operates in Slave mode.
1: LIN0 operates in Master mode.
ABAUD: LIN Mode Automatic Baud Rate Selection (slave mode only).
0: Manual baud rate selection is enabled.
1: Automatic baud rate selection is enabled.
Rev. 1.4
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C8051F52x/F53x
17.7.2. LIN Indirect Access SFR Registers Definition
Table 17.4. LIN Registers* (Indirectly Addressable)
Name
Address
Bit7
Bit6
Bit5
LIN0DT1
0x00
DATA1[7:0]
LIN0DT2
0x01
DATA2[7:0]
LIN0DT3
0x02
DATA3[7:0]
LIN0DT4
0x03
DATA4[7:0]
LIN0DT5
0x04
DATA5[7:0]
LIN0DT6
0x05
DATA6[7:0]
LIN0DT7
0x06
DATA7[7:0]
LIN0DT8
0x07
DATA8[7:0]
LIN0CTRL
0x08
STOP(s) SLEEP(s)
LIN0ST
0x09
ACTIVE IDLTOUT ABORT(s) DTREQ(s) LININT ERROR WAKEUP
LIN0ERR
0x0A
LIN0SIZE
0x0B
LIN0DIV
0x0C
LIN0MUL
0x0D
LIN0ID
0x0E
TXRX
Bit4
Bit3
Bit2
Bit1
Bit0
DTACK(s) RSTINT RSTERR WUPREQ STREQ(m)
SYNCH(s) PRTY(s)
TOUT
ENHCHK
CHK
DONE
BITERR
LINSIZE[3:0]
DIVLSB[7:0]
PRESCL[1:0]
LINMUL[4:0]
DIV9
ID[5:0]
*These registers are used in both master and slave mode. The register bits marked with (m) are accessible
only in Master mode while the register bits marked with (s) are accessible only in slave mode. All other registers are accessible in both modes.
SFR Definition 17.4. LIN0DT1: LIN0 Data Byte 1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Address:
Bit7–0:
174
LIN0DT1: LIN Data Byte 1.
Serial Data Byte 1 that is received or transmitted across the LIN interface.
Rev. 1.4
0x00 (indirect)
C8051F52x/F53x
SFR Definition 17.5. LIN0DT2: LIN0 Data Byte 2
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Address: 0x01 (indirect)
Bit7–0:
LIN0DT2: LIN Data Byte 2.
Serial Data Byte 2 that is received or transmitted across the LIN interface.
SFR Definition 17.6. LIN0DT3: LIN0 Data Byte 3
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Address: 0x02 (indirect)
Bit7–0:
LIN0DT3: LIN Data Byte 3.
Serial Data Byte 3 that is received or transmitted across the LIN interface.
SFR Definition 17.7. LIN0DT4: LIN0 Data Byte 4
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Address: 0x03 (indirect)
Bit7–0:
LIN0DT4: LIN Data Byte 4.
Serial Data Byte 4 that is received or transmitted across the LIN interface.
Rev. 1.4
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C8051F52x/F53x
SFR Definition 17.8. LIN0DT5: LIN0 Data Byte 5
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Address: 0x04 (indirect)
Bit7–0:
LIN0DT5: LIN Data Byte 5.
Serial Data Byte 5 that is received or transmitted across the LIN interface.
SFR Definition 17.9. LIN0DT6: LIN0 Data Byte 6
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Reset Value
00000000
Address: 0x05 (indirect)
Bit7–0:
LIN0DT6: LIN Data Byte 6.
Serial Data Byte 6 that is received or transmitted across the LIN interface.
SFR Definition 17.10. LIN0DT7: LIN0 Data Byte 7
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Address: 0x06 (indirect)
Bit7–0:
LIN0DT7: LIN Data Byte 7.
Serial Data Byte 7 that is received or transmitted across the LIN interface.
SFR Definition 17.11. LIN0DT8: LIN0 Data Byte 8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Address: 0x07 (indirect)
Bit7–0:
176
LIN0DT8: LIN Data Byte 8.
Serial Data Byte 8 that is received or transmitted across the LIN interface.
Rev. 1.4
C8051F52x/F53x
SFR Definition 17.12. LIN0CTRL: LIN0 Control Register
W
W
W
R/W
R/W
STOP
SLEEP
TXRX
DTACK
RSTINT
Bit7
Bit6
Bit5
Bit4
Bit3
R/W
R/W
RSTERR WUPREQ
Bit2
Bit1
R/W
Reset Value
STREQ
00000000
Bit0
Address: 0x08 (indirect)
Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
STOP: Stop Communication Processing Bit (slave mode only).
This bit is to be set by the application to block the processing of the LIN Communications
until the next SYNCH BREAK signal. It is used when the application is handling a data
request interrupt and cannot use the frame content with the received identifier (always reads
0).
SLEEP: Sleep Mode Warning.
This bit is to be set by the application to warn the peripheral that a Sleep Mode Frame was
received and that the Bus is in sleep mode or if a Bus Idle timeout interrupt is requested.
The application must reset it when a Wake-Up interrupt is requested.
TXRX: Transmit/Receive Selection Bit.
This bit determines if the current frame is a transmit frame or a receive frame.
0: Current frame is a receive operation.
1: Current frame is a transmit operation.
DTACK: Data acknowledge bit (slave mode only).
Set to 1 after handling a data request interrupt to acknowledge the transfer. The bit will automatically be cleared to 0 by the LIN controller.
RSTINT: Interrupt Reset bit.
This bit always reads as 0.
0: No effect.
1: Reset the LININT bit (LIN0ST.3).
RSTERR: Error Reset Bit.
This bit always reads as 0.
0: No effect.
1: Reset the error bits in LIN0ST and LIN0ERR.
WUPREQ: Wake-Up Request Bit.
Set to 1 to terminate sleep mode by sending a wakeup signal. The bit will automatically be
cleared to 0 by the LIN controller.
STREQ: Start Request Bit (master mode only).
1: Start a LIN transmission. This should be set only after loading the identifier, data length
and data buffer if necessary.
The bit is reset to 0 upon transmission completion or error detection.
Rev. 1.4
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SFR Definition 17.13. LIN0ST: LIN0 STATUS Register
R
R
R
R
R/W
R
R
R
Reset Value
ACTIVE
IDLTOUT
ABORT
DTREQ
LININT
ERROR
WAKEUP
DONE
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Address: 0x09 (indirect)
Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
178
ACTIVE: LIN Bus Activity Bit.
0: No transmission activity detected on the LIN bus.
1: Transmission activity detected on the LIN bus.
IDLTOUT: Bus Idle Timeout Bit (slave mode only).
0: The bus has not been idle for four seconds.
1: No bus activity has been detected for four seconds, but the bus is not yet in Sleep mode.
ABORT: Aborted transmission signal (slave mode only).
0: The current transmission has not been interrupted or stopped. This bit is reset to 0 after
receiving a SYNCH BREAK that does not interrupt a pending transmission.
1: New SYNCH BREAK detected before the end of the last transmission or the STOP bit
(LIN0CTRL.7) has been set.
DTREQ: Data Request bit (slave mode only).
0: Data identifier has not been received.
1: Data identifier has been received.
LININT: Interrupt Request bit.
0: An interrupt is not pending. This bit is cleared by setting RSTINT (LIN0CTRL.3)
1: There is a pending LIN0 interrupt.
ERROR: Communication Error Bit.
0: No error has been detected. This bit is cleared by setting RSTERR (LIN0CTRL.2)
1: An error has been detected.
WAKEUP: Wakeup Bit.
0: A wakeup signal is not being transmitted and has not been received.
1: A wakeup signal is being transmitted or has been received.
DONE: Transmission Complete Bit.
0: A transmission is not in progress or has not been started. This bit is cleared at the start of
a transmission.
1: The current transmission is complete.
Rev. 1.4
C8051F52x/F53x
SFR Definition 17.14. LIN0ERR: LIN0 ERROR Register
R
Bit7
R
Bit6
R
Bit5
R
R
R
R
R
Reset Value
SYNCH
PRTY
TOUT
CHK
BITERR
00000000
Bit4
Bit3
Bit2
Bit1
Bit0
Address: 0x0A (indirect)
Bits7–5: UNUSED. Read = 000b. Write = don’t care.
Bit4:
SYNCH: Synchronization Error Bit (slave mode only).
0: No error with the SYNCH FIELD has been detected.
1: Edges of the SYNCH FIELD are outside of the maximum tolerance.
Bit3:
PRTY: Parity Error Bit (slave mode only).
0: No parity error has been detected.
1: A parity error has been detected.
Bit2:
TOUT: Timeout Error Bit.
0: A timeout error has not been detected.
1: A timeout error has been detected. This error is detected whenever one of the following
conditions is met:
•The master is expecting data from a slave and the slave does not respond.
•The slave is expecting data but no data is transmitted on the bus.
•A frame is not finished within the maximum frame length.
•The application does not set the DTACK bit (LIN0CTRL.4) or STOP bit (LIN0CTRL.7) until the
end of the reception of the first byte after the identifier.
Bit1:
CHK: Checksum Error Bit.
0: Checksum error has not been detected.
1: Checksum error has been detected.
Bit0:
BITERR: Bit Transmission Error Bit.
0: No error in transmission has been detected.
1: The bit value monitored during transmission is different than the bit value sent.
Rev. 1.4
179
C8051F52x/F53x
SFR Definition 17.15. LIN0SIZE: LIN0 Message Size Register
R/W
R/W
R/W
R/W
ENHCHK
-
-
-
Bit7
Bit6
Bit5
Bit4
R/W
R/W
R/W
R/W
LINSIZE[3:0]
Bit3
Bit2
Bit1
Reset Value
00000000
Bit0
Address: 0x0B (indirect)
Bit7:
Bit6–4:
Bit3–0:
ENHCHK: Checksum Selection Bit.
0: Use the classic, specification 1.3 compliant checksum. Checksum covers the data bytes.
1: Use the enhanced, specification 2.1 compliant checksum. Checksum covers data bytes
and protected identifier.
UNUSED. Read = 000b. Write = don’t care.
LINSIZE3–0: Data Field Size.
0000: 0 data bytes
0001: 1 data byte
0010: 2 data bytes
0011: 3 data bytes
0100: 4 data bytes
0101: 5 data bytes
0110: 6 data bytes
0111: 7 data bytes
1000: 8 data bytes
1001-1110: RESERVED
1111: Use the ID[1:0] bits (LIN0ID[5:4]) to determine the data length.
SFR Definition 17.16. LIN0DIV: LIN0 Divider Register
R
R
R
R
R
R
R
R
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Reset Value
00000000
Address: 0x0C (indirect)
Bit7–0:
180
DIVLSB[7:0]: LIN Baud Rate Divider Least Significant Bits.
The 8 least significant bits for the baud rate divider. The 9th and most significant bit is the
DIV9 bit (LIN0MUL.0). The valid range for the divider is 200 to 511.
Rev. 1.4
C8051F52x/F53x
SFR Definition 17.17. LIN0MUL: LIN0 Multiplier Register
R/W
R/W
R/W
R/W
PRESCL[1:0]
Bit7
Bit6
R/W
R/W
R/W
LINMUL[4:0]
Bit5
Bit4
Bit3
Bit2
Bit1
R/W
Reset Value
DIV9
00000000
Bit0
Address: 0x0D (indirect)
Bit7–6:
Bit5–1:
Bit0:
PRESCL1–0: LIN Baud Rate Prescaler Bits.
These bits are the baud rate prescaler bits.
LINMUL4–0: LIN Baud Rate Multiplier Bits.
These bits are the baud rate multiplier bits. These bits are not used in slave mode.
DIV9: LIN Baud Rate Divider Most Significant Bit.
The most significant bit of the baud rate divider. The 8 least significant bits are in LIN0DIV.
The valid range for the divider is 200 to 511.
SFR Definition 17.18. LIN0ID: LIN0 ID Register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ID[5:0]
Bit7
Bit6
Bit5
Bit4
Bit3
Reset Value
00000000
Bit2
Bit1
Bit0
Address: 0x0E (indirect)
Bit7–6:
Bit5–0:
UNUSED. Read = 00b. Write = don’t care.
ID5–0: LIN Identifier Bits.
These bits form the data identifier.
If the LINSIZE bits (LIN0SIZE[3:0]) are 1111b, bits ID[5:4] are used to determine the data
size and are interpreted as follows:
00: 2 bytes
01: 2 bytes
10: 4 bytes
11: 8 bytes
Rev. 1.4
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C8051F52x/F53x
18. Timers
Each MCU includes three counter/timers: two are 16-bit counter/timers compatible with those found in the
standard 8051, and one is a 16-bit auto-reload timer for use with other device peripherals or for general
purpose use. These timers can be used to measure time intervals, count external events and generate
periodic interrupt requests. Timer 0 and Timer 1 are nearly identical and have four primary modes of operation. Timer 2 offer 16-bit and split 8-bit timer functionality with auto-reload.
Timer 0 and Timer 1 Modes
Timer 2 Modes
13-bit counter/timer
16-bit timer with auto-reload
16-bit counter/timer
8-bit counter/timer with auto-reload
Two 8-bit counter/timers
(Timer 0 only)
Two 8-bit timers with auto-reload
Timers 0 and 1 may be clocked by one of five sources, determined by the Timer Mode Select bits (T1M–
T0M) and the Clock Scale bits (SCA1–SCA0). The Clock Scale bits define a pre-scaled clock from which
Timer 0 and/or Timer 1 may be clocked (See SFR Definition 18.3 for pre-scaled clock selection).
Timer 0/1 may then be configured to use this pre-scaled clock signal or the system clock. Timer 2 may be
clocked by the system clock, the system clock divided by 12, or the external oscillator clock source divided
by 8.
Timer 0 and Timer 1 may also be operated as counters. When functioning as a counter, a counter/timer
register is incremented on each high-to-low transition at the selected input pin (T0 or T1). Events with a frequency of up to one-fourth the system clock's frequency can be counted. The input signal need not be periodic, but it must be held at a given level for at least two full system clock cycles to ensure the level is
properly sampled.
18.1. Timer 0 and Timer 1
Each timer is implemented as a 16-bit register accessed as two separate bytes: a low byte (TL0 or TL1)
and a high byte (TH0 or TH1). The Counter/Timer Control register (TCON) is used to enable Timer 0 and
Timer 1 as well as indicate status. Timer 0 interrupts can be enabled by setting the ET0 bit in the IE register
(Section “10.4. Interrupt Register Descriptions” on page 100); Timer 1 interrupts can be enabled by setting
the ET1 bit in the IE register (Section 10.4). Both counter/timers operate in one of four primary modes
selected by setting the Mode Select bits T1M1–T0M0 in the Counter/Timer Mode register (TMOD). Each
timer can be configured independently. Each operating mode is described below.
18.1.1. Mode 0: 13-bit Counter/Timer
Timer 0 and Timer 1 operate as 13-bit counter/timers in Mode 0. The following describes the configuration
and operation of Timer 0. However, both timers operate identically, and Timer 1 is configured in the same
manner as described for Timer 0.
The TH0 register holds the eight MSBs of the 13-bit counter/timer. TL0 holds the five LSBs in bit positions
TL0.4–TL0.0. The three upper bits of TL0 (TL0.7–TL0.5) are indeterminate and should be masked out or
ignored when reading. As the 13-bit timer register increments and overflows from 0x1FFF (all ones) to
0x0000, the timer overflow flag TF0 (TCON.5) is set and an interrupt will occur if Timer 0 interrupts are
enabled.
The C/T0 bit (TMOD.2) selects the counter/timer's clock source. When C/T0 is set to logic 1, high-to-low
transitions at the selected Timer 0 input pin (T0) increment the timer register (Refer to Section
“13.1. Priority Crossbar Decoder” on page 122 for information on selecting and configuring external I/O
pins). Clearing C/T selects the clock defined by the T0M bit (CKCON.3). When T0M is set, Timer 0 is
182
Rev. 1.4
C8051F52x/F53x
clocked by the system clock. When T0M is cleared, Timer 0 is clocked by the source selected by the Clock
Scale bits in CKCON (see SFR Definition 18.3).
Setting the TR0 bit (TCON.4) enables the timer when either GATE0 (TMOD.3) is logic 0 or the input signal
INT0 is active as defined by bit IN0PL in register IT01CF (see SFR Definition 10.5. IT01CF: INT0/INT1
Configuration). Setting GATE0 to 1 allows the timer to be controlled by the external input signal INT0 (see
Section “10.4. Interrupt Register Descriptions” on page 100), facilitating pulse width measurements.
TR0
GATE0
INT0
Counter/Timer
0
X
X
Disabled
1
0
X
Enabled
1
1
0
Disabled
1
1
1
Enabled
X = Don't Care
Setting TR0 does not force the timer to reset. The timer registers should be loaded with the desired initial
value before the timer is enabled.
TL1 and TH1 form the 13-bit register for Timer 1 in the same manner as described above for TL0 and TH0.
Timer 1 is configured and controlled using the relevant TCON and TMOD bits just as with Timer 0. The
input signal INT0 is used with Timer 1; the INT0 polarity is defined by bit IN1PL in register IT01CF (see
SFR Definition 10.5. IT01CF: INT0/INT1 Configuration).
IT01CF
Figure 18.1. T0 Mode 0 Block Diagram
Rev. 1.4
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C8051F52x/F53x
18.1.2. Mode 1: 16-bit Counter/Timer
Mode 1 operation is the same as Mode 0, except that the counter/timer registers use all 16 bits. The counter/timers are enabled and configured in Mode 1 in the same manner as for Mode 0.
18.1.3. Mode 2: 8-bit Counter/Timer with Auto-Reload
Mode 2 configures Timer 0 and Timer 1 to operate as 8-bit counter/timers with automatic reload of the start
value. TL0 holds the count and TH0 holds the reload value. When the counter in TL0 overflows from all
ones to 0x00, the timer overflow flag TF0 (TCON.5) is set and the counter in TL0 is reloaded from TH0. If
Timer 0 interrupts are enabled, an interrupt will occur when the TF0 flag is set. The reload value in TH0 is
not changed. TL0 must be initialized to the desired value before enabling the timer for the first count to be
correct. When in Mode 2, Timer 1 operates identically to Timer 0.
Both counter/timers are enabled and configured in Mode 2 in the same manner as Mode 0. Setting the
TR0 bit (TCON.4) enables the timer when either GATE0 (TMOD.3) is logic 0 or when the input signal INT0
is active as defined by bit IN0PL in register IT01CF (see Section “10.5. External Interrupts” on page 104 for
details on the external input signals INT0 and INT0).
CKCON
TTTTSS
2 2 1 0 CC
MMMM A A
1 0
HL
Pre-scaled Clock
TMOD
G
A
T
E
1
C
/
T
1
T T G
1 1 A
MM T
1 0 E
0
C
/
T
0
INT01CF
T T
0 0
MM
1 0
I
N
1
P
L
I
N
1
S
L
2
I
N
1
S
L
1
I
N
1
S
L
0
I
N
0
P
L
I
N
0
S
L
2
I
N
0
S
L
1
I
N
0
S
L
0
0
0
SYSCLK
1
1
T0
TL0
(8 bits)
TCON
TCLK
TR0
Crossbar
GATE0
TH0
(8 bits)
/INT0
IN0PL
Reload
XOR
Figure 18.2. T0 Mode 2 Block Diagram
184
Rev. 1.4
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
Interrupt
C8051F52x/F53x
18.1.4. Mode 3: Two 8-bit Counter/Timers (Timer 0 Only)
In Mode 3, Timer 0 is configured as two separate 8-bit counter/timers held in TL0 and TH0. The counter/timer in TL0 is controlled using the Timer 0 control/status bits in TCON and TMOD: TR0, C/T0, GATE0
and TF0. TL0 can use either the system clock or an external input signal as its timebase. The TH0 register
is restricted to a timer function sourced by the system clock or prescaled clock. TH0 is enabled using the
Timer 1 run control bit TR1. TH0 sets the Timer 1 overflow flag TF1 on overflow and thus controls the
Timer 1 interrupt.
Timer 1 is inactive in Mode 3. When Timer 0 is operating in Mode 3, Timer 1 can be operated in Modes 0,
1 or 2, but cannot be clocked by external signals nor set the TF1 flag and generate an interrupt. However,
the Timer 1 overflow can be used to generate baud rates for the SMBus and UART. While Timer 0 is operating in Mode 3, Timer 1 run control is handled through its mode settings. To run Timer 1 while Timer 0 is in
Mode 3, set the Timer 1 Mode as 0, 1, or 2. To disable Timer 1, configure it for Mode 3.
CKCON
TMOD
T T T T T TSS
3 3 2 2 1 0 CC
MMMMMM A A
HLHL
1 0
Pre-scaled Clock
G
A
T
E
1
C
/
T
1
T T
1 1
MM
1 0
G
A
T
E
0
C
/
T
0
T T
0 0
MM
1 0
0
TR1
SYSCLK
TH0
(8 bits)
1
TCON
0
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
Interrupt
Interrupt
1
T0
TL0
(8 bits)
TR0
Crossbar
/INT0
GATE0
IN0PL
XOR
Figure 18.3. T0 Mode 3 Block Diagram
Rev. 1.4
185
C8051F52x/F53x
SFR Definition 18.1. TCON: Timer Control
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Bit
Addressable
SFR Address:
0x88
Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
186
TF1: Timer 1 Overflow Flag.
Set by hardware when Timer 1 overflows. This flag can be cleared by software but is automatically cleared when the CPU vectors to the Timer 1 interrupt service routine.
0: No Timer 1 overflow detected.
1: Timer 1 has overflowed.
TR1: Timer 1 Run Control.
0: Timer 1 disabled.
1: Timer 1 enabled.
TF0: Timer 0 Overflow Flag.
Set by hardware when Timer 0 overflows. This flag can be cleared by software but is automatically cleared when the CPU vectors to the Timer 0 interrupt service routine.
0: No Timer 0 overflow detected.
1: Timer 0 has overflowed.
TR0: Timer 0 Run Control.
0: Timer 0 disabled.
1: Timer 0 enabled.
IE1: External Interrupt 1.
This flag is set by hardware when an edge/level of type defined by IT1 is detected. It can be
cleared by software but is automatically cleared when the CPU vectors to the External Interrupt 1 service routine if IT1 = 1. When IT1 = 0, this flag is set to 1 when INT0 is active as
defined by bit IN1PL in register IT01CF (see SFR Definition 10.5. “IT01CF: INT0/INT1 Configuration” on page 105).
IT1: Interrupt 1 Type Select.
This bit selects whether the configured INT0 interrupt will be edge or level sensitive. INT0 is
configured active low or high by the IN1PL bit in the IT01CF register (see SFR
Definition 10.5. “IT01CF: INT0/INT1 Configuration” on page 105).
0: INT0 is level triggered.
1: INT0 is edge triggered.
IE0: External Interrupt 0.
This flag is set by hardware when an edge/level of type defined by IT0 is detected. It can be
cleared by software but is automatically cleared when the CPU vectors to the External Interrupt 0 service routine if IT0 = 1. When IT0 = 0, this flag is set to 1 when INT0 is active as
defined by bit IN0PL in register IT01CF (see SFR Definition 10.5. “IT01CF: INT0/INT1 Configuration” on page 105).
IT0: Interrupt 0 Type Select.
This bit selects whether the configured INT0 interrupt will be edge or level sensitive. INT0 is
configured active low or high by the IN0PL bit in register IT01CF (see SFR Definition 10.5.
“IT01CF: INT0/INT1 Configuration” on page 105).
0: INT0 is level triggered.
1: INT0 is edge triggered.
Rev. 1.4
C8051F52x/F53x
SFR Definition 18.2. TMOD: Timer Mode
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
GATE1
C/T1
T1M1
T1M0
GATE0
C/T0
T0M1
T0M0
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
0x89
Bit7:
GATE1: Timer 1 Gate Control.
0: Timer 1 enabled when TR1 = 1 irrespective of INT0 logic level.
1: Timer 1 enabled only when TR1 = 1 AND INT0 is active as defined by bit IN1PL in register
IT01CF (see SFR Definition 10.5. “IT01CF: INT0/INT1 Configuration” on page 105).
Bit6:
C/T1: Counter/Timer 1 Select.
0: Timer Function: Timer 1 incremented by clock defined by T1M bit (CKCON.4).
1: Counter Function: Timer 1 incremented by high-to-low transitions on external input pin
(T1).
Bits5–4: T1M1–T1M0: Timer 1 Mode Select.
These bits select the Timer 1 operation mode.
T1M1
T1M0
Mode
0
0
Mode 0: 13-bit counter/timer
0
1
Mode 1: 16-bit counter/timer
1
0
Mode 2: 8-bit counter/timer with auto-reload
1
1
Mode 3: Timer 1 inactive
Bit3:
GATE0: Timer 0 Gate Control.
0: Timer 0 enabled when TR0 = 1 irrespective of INT0 logic level.
1: Timer 0 enabled only when TR0 = 1 AND INT0 is active as defined by bit IN0PL in register
IT01CF (see SFR Definition 10.5. “IT01CF: INT0/INT1 Configuration” on page 105).
Bit2:
C/T0: Counter/Timer Select.
0: Timer Function: Timer 0 incremented by clock defined by T0M bit (CKCON.3).
1: Counter Function: Timer 0 incremented by high-to-low transitions on external input pin
(T0).
Bits1–0: T0M1–T0M0: Timer 0 Mode Select.
These bits select the Timer 0 operation mode.
T0M1
T0M0
Mode
0
0
Mode 0: 13-bit counter/timer
0
1
Mode 1: 16-bit counter/timer
1
0
Mode 2: 8-bit counter/timer with auto-reload
1
1
Mode 3: Two 8-bit counter/timers
Rev. 1.4
187
C8051F52x/F53x
SFR Definition 18.3. CKCON: Clock Control
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
—
—
T2MH
T2ML
T1M
T0M
SCA1
SCA0
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
Bit7–6:
Bit5:
0x8E
RESERVED. Read = 0b; Must write 0b.
T2MH: Timer 2 High Byte Clock Select.
This bit selects the clock supplied to the Timer 2 high byte if Timer 2 is configured in split 8bit timer mode. T2MH is ignored if Timer 2 is in any other mode.
0: Timer 2 high byte uses the clock defined by the T2XCLK bit in TMR2CN.
1: Timer 2 high byte uses the system clock.
Bit4:
T2ML: Timer 2 Low Byte Clock Select.
This bit selects the clock supplied to Timer 2. If Timer 2 is configured in split 8-bit timer
mode, this bit selects the clock supplied to the lower 8-bit timer.
0: Timer 2 low byte uses the clock defined by the T2XCLK bit in TMR2CN.
1: Timer 2 low byte uses the system clock.
Bit3:
T1M: Timer 1 Clock Select.
This select the clock source supplied to Timer 1. T1M is ignored when C/T1 is set to logic 1.
0: Timer 1 uses the clock defined by the prescale bits, SCA1–SCA0.
1: Timer 1 uses the system clock.
Bit2:
T0M: Timer 0 Clock Select.
This bit selects the clock source supplied to Timer 0. T0M is ignored when C/T0 is set to
logic 1.
0: Counter/Timer 0 uses the clock defined by the prescale bits, SCA1–SCA0.
1: Counter/Timer 0 uses the system clock.
Bits1–0: SCA1–SCA0: Timer 0/1 Prescale Bits.
These bits control the division of the clock supplied to Timer 0 and Timer 1 if configured to
use prescaled clock inputs.
SCA1
SCA0
Prescaled Clock
0
0
System clock divided by 12
0
1
System clock divided by 4
1
0
System clock divided by 48
1
1
External clock divided by 8
Note: External clock divided by 8 is synchronized with
the system clock.
188
Rev. 1.4
C8051F52x/F53x
SFR Definition 18.4. TL0: Timer 0 Low Byte
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
0x8A
Reset Value
Bits 7–0: TL0: Timer 0 Low Byte.
The TL0 register is the low byte of the 16-bit Timer 0.
SFR Definition 18.5. TL1: Timer 1 Low Byte
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
00000000
SFR Address:
0x8B
Bits 7–0: TL1: Timer 1 Low Byte.
The TL1 register is the low byte of the 16-bit Timer 1.
SFR Definition 18.6. TH0: Timer 0 High Byte
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
0x8C
Bits 7–0: TH0: Timer 0 High Byte.
The TH0 register is the high byte of the 16-bit Timer 0.
SFR Definition 18.7. TH1: Timer 1 High Byte
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
0x8D
Bits 7–0: TH1: Timer 1 High Byte.
The TH1 register is the high byte of the 16-bit Timer 1.
Rev. 1.4
189
C8051F52x/F53x
18.2. Timer 2
Timer 2 is a 16-bit timer formed by two 8-bit SFRs: TMR2L (low byte) and TMR2H (high byte). Timer 2 may
operate in 16-bit auto-reload mode or (split) 8-bit auto-reload mode. The T2SPLIT bit (TMR2CN.3) defines
the Timer 2 operation mode. Timer 2 can also be used in Capture Mode to measure the RTC0 clock frequency or the External Oscillator clock frequency.
Timer 2 may be clocked by the system clock, the system clock divided by 12, or the external oscillator
source divided by 8. The external oscillator source divided by 8 is synchronized with the system clock.
18.2.1. 16-bit Timer with Auto-Reload
When T2SPLIT (TMR2CN.3) is zero, Timer 2 operates as a 16-bit timer with auto-reload. Timer 2 can be
clocked by SYSCLK, SYSCLK divided by 12, or the external oscillator clock source divided by 8. As the
16-bit timer register increments and overflows from 0xFFFF to 0x0000, the 16-bit value in the Timer 2
reload registers (TMR2RLH and TMR2RLL) is loaded into the Timer 2 register as shown in Figure 18.4,
and the Timer 2 High Byte Overflow Flag (TMR2CN.7) is set. If Timer 2 interrupts are enabled (if IE.5 is
set), an interrupt will be generated on each Timer 2 overflow. Additionally, if Timer 2 interrupts are enabled
and the TF2LEN bit is set (TMR2CN.5), an interrupt will be generated each time the lower 8 bits (TMR2L)
overflow from 0xFF to 0x00.
CKCON
TTTTTTSS
3 3 2 2 1 0CC
T2XCLK M M M M M M A A
HLHL
1 0
0
TMR2L
Overflow
0
TR2
External Clock / 8
SYSCLK
1
TCLK
TMR2L
TMR2H
TMR2CN
SYSCLK / 12
1
TF2H
TF2L
TF2LEN
T2SPLIT
TR2
T2XCLK
TMR2RLL TMR2RLH
Reload
Figure 18.4. Timer 2 16-Bit Mode Block Diagram
190
Rev. 1.4
Interrupt
C8051F52x/F53x
18.2.2. 8-bit Timers with Auto-Reload
When T2SPLIT is set, Timer 2 operates as two 8-bit timers (TMR2H and TMR2L). Both 8-bit timers operate in auto-reload mode as shown in Figure 18.5. TMR2RLL holds the reload value for TMR2L; TMR2RLH
holds the reload value for TMR2H. The TR2 bit in TMR2CN handles the run control for TMR2H. TMR2L is
always running when configured for 8-bit Mode.
Each 8-bit timer may be configured to use SYSCLK, SYSCLK divided by 12, or the external oscillator clock
source divided by 8. The Timer 2 Clock Select bits (T2MH and T2ML in CKCON) select either SYSCLK or
the clock defined by the Timer 2 External Clock Select bit (T2XCLK in TMR2CN), as follows:
T2MH
T2XCLK
TMR2H Clock Source
T2ML
T2XCLK
TMR2L Clock Source
0
0
1
0
1
X
SYSCLK / 12
External Clock / 8
SYSCLK
0
0
1
0
1
X
SYSCLK / 12
External Clock / 8
SYSCLK
The TF2H bit is set when TMR2H overflows from 0xFF to 0x00; the TF2L bit is set when TMR2L overflows
from 0xFF to 0x00. When Timer 2 interrupts are enabled (IE.5), an interrupt is generated each time
TMR2H overflows. If Timer 2 interrupts are enabled and TF2LEN (TMR2CN.5) is set, an interrupt is generated each time either TMR2L or TMR2H overflows. When TF2LEN is enabled, software must check the
TF2H and TF2L flags to determine the source of the Timer 2 interrupt. The TF2H and TF2L interrupt flags
are not cleared by hardware and must be manually cleared by software.
CKCON
T T T T T T S
3 3 2 2 1 0 C
MMMMMMA
H L H L
1
T2XCLK
SYSCLK / 12
0
External Clock / 8
1
S
C
A
0
TMR2RLH
Reload
0
TCLK
TR2
TMR2H
TMR2RLL
SYSCLK
Reload
TMR2CN
1
TF2H
TF2L
TF2LEN
Interrupt
T2SPLIT
TR2
T2XCLK
1
TCLK
TMR2L
0
Figure 18.5. Timer 2 8-Bit Mode Block Diagram
Rev. 1.4
191
C8051F52x/F53x
18.2.3. External Capture Mode
Capture Mode allows the external oscillator to be measured against the system clock. Timer 2 can be
clocked from the system clock, or the system clock divided by 12, depending on the T2ML (CKCON.4) and
T2XCLK bits. When a capture event is generated, the contents of Timer 2 (TMR2H:TMR2L) are loaded
into the Timer 2 reload registers (TMR2RLH:TMR2RLL) and the TF2H flag is set. A capture event is generated by the falling edge of the clock source being measured, which is the external oscillator/8. By recording
the difference between two successive timer capture values, the external oscillator frequency can be
determined with respect to the Timer 2 clock. The Timer 2 clock should be much faster than the capture
clock to achieve an accurate reading. Timer 2 should be in 16-bit auto-reload mode when using Capture
Mode.
For example, if T2ML = 1b and TF2CEN = 1b, Timer 2 will clock every SYSCLK and capture every external
clock divided by 8. If the SYSCLK is 24.5 MHz and the difference between two successive captures is
5984, then the external clock frequency is:
24.5 MHz
------------------------ = 0.032754 MHz or 32.754 kHz
 5984  8 
This mode allows software to determine the external oscillator frequency when an RC network or capacitor
is used to generate the clock source.
CKCON
T T T T T T S
3 3 2 2 1 0 C
MMMMMM A
H L H L
1
S
C
A
0
T2XCLK
SYSCLK
1
1
TCLK
TR2
0
SYSCLK / 12
TMR2H
TMR2L
Capture
0
TMR2RLH TMR2RLL
TMR2CN
External Osc. / 8
External Osc. / 8
TF2CEN
Figure 18.6. Timer 2 Capture Mode Block Diagram
192
Rev. 1.4
TF2H
TF2L
TF2LEN
TF2CEN
TR2
TR2CLK
T2XCLK
Interrupt
C8051F52x/F53x
SFR Definition 18.8. TMR2CN: Timer 2 Control
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
TF2H
TF2L
TF2LEN
TF2CEN
T2SPLIT
TR2
—
T2XCLK
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Bit
Addressable
SFR Address:
0xC8
Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
TF2H: Timer 2 High Byte Overflow Flag.
Set by hardware when the Timer 2 high byte overflows from 0xFF to 0x00. In 16 bit mode,
this will occur when Timer 2 overflows from 0xFFFF to 0x0000. When the Timer 2 interrupt is
enabled, setting this bit causes the CPU to vector to the Timer 2 interrupt service routine.
TF2H is not automatically cleared by hardware and must be cleared by software.
TF2L: Timer 2 Low Byte Overflow Flag.
Set by hardware when the Timer 2 low byte overflows from 0xFF to 0x00. When this bit is
set, an interrupt will be generated if TF2LEN is set and Timer 2 interrupts are enabled. TF2L
will set when the low byte overflows regardless of the Timer 2 mode. This bit is not automatically cleared by hardware.
TF2LEN: Timer 2 Low Byte Interrupt Enable.
This bit enables/disables Timer 2 Low Byte interrupts. If TF2LEN is set and Timer 2 interrupts are enabled, an interrupt will be generated when the low byte of Timer 2 overflows.
This bit should be cleared when operating Timer 2 in 16-bit mode.
0: Timer 2 Low Byte interrupts disabled.
1: Timer 2 Low Byte interrupts enabled.
TF2CEN. Timer 2 Capture Enable.
0: Timer 2 capture mode disabled.
1: Timer 2 capture mode enabled.
T2SPLIT: Timer 2 Split Mode Enable.
When this bit is set, Timer 2 operates as two 8-bit timers with auto-reload.
0: Timer 2 operates in 16-bit auto-reload mode.
1: Timer 2 operates as two 8-bit auto-reload timers.
TR2: Timer 2 Run Control.
This bit enables/disables Timer 2. In 8-bit mode, this bit enables/disables TMR2H only;
TMR2L is always enabled in this mode.
0: Timer 2 disabled.
1: Timer 2 enabled.
Unused. Read = 0b. Write = don't care.
T2XCLK: Timer 2 External Clock Select.
This bit selects the external clock source for Timer 2. If Timer 2 is in 8-bit mode, this bit
selects the external oscillator clock source for both timer bytes. However, the Timer 2 Clock
Select bits (T2MH and T2ML in register CKCON) may still be used to select between the
external clock and the system clock for either timer.
0: Timer 2 external clock selection is the system clock divided by 12.
1: Timer 2 external clock selection is the external clock divided by 8.
Rev. 1.4
193
C8051F52x/F53x
SFR Definition 18.9. TMR2RLL: Timer 2 Reload Register Low Byte
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Reset Value
00000000
SFR Address:
0xCA
Bits7–0: TMR2RLL: Timer 2 Reload Register Low Byte.
TMR2RLL holds the low byte of the reload value for Timer 2.
SFR Definition 18.10. TMR2RLH: Timer 2 Reload Register High Byte
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Reset Value
00000000
SFR Address:
0xCB
Reset Value
Bits7–0: TMR2RLH: Timer 2 Reload Register High Byte.
The TMR2RLH holds the high byte of the reload value for Timer 2.
SFR Definition 18.11. TMR2L: Timer 2 Low Byte
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
00000000
SFR Address:
0xCC
Bits7–0: TMR2L: Timer 2 Low Byte.
In 16-bit mode, the TMR2L register contains the low byte of the 16-bit Timer 2. In 8-bit mode,
TMR2L contains the 8-bit low byte timer value.
SFR Definition 18.12. TMR2H Timer 2 High Byte
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
0xCD
Bits7–0: TMR2H: Timer 2 High Byte.
In 16-bit mode, the TMR2H register contains the high byte of the 16-bit Timer 2. In 8-bit
mode, TMR2H contains the 8-bit high byte timer value.
194
Rev. 1.4
C8051F52x/F53x
19. Programmable Counter Array (PCA0)
The Programmable Counter Array (PCA0) provides enhanced timer functionality while requiring less CPU
intervention than the standard 8051 counter/timers. The PCA consists of a dedicated 16-bit counter/timer
and three 16-bit capture/compare modules. Each capture/compare module has its own associated I/O line
(CEXn) which is routed through the Crossbar to Port I/O when enabled (See Section “13.1. Priority Crossbar Decoder” on page 122 for details on configuring the Crossbar). The counter/timer is driven by a programmable timebase that can select between six sources: system clock, system clock divided by four,
system clock divided by twelve, the external oscillator clock source divided by 8, Timer 0 overflow, or an
external clock signal on the ECI input pin. Each capture/compare module may be configured to operate
independently in one of three modes: Edge-Triggered Capture, Software Timer, High-Speed Output, Frequency Output, 8-Bit PWM, or 16-Bit PWM (each mode is described in Section “19.2. Capture/Compare
Modules” on page 197). The PCA is configured and controlled through the system controller's Special
Function Registers. The PCA block diagram is shown in Figure 19.1
Important Note: The PCA Module 2 may be used as a watchdog timer (WDT), and is enabled in this mode
following a system reset. Access to certain PCA registers is restricted while WDT mode is enabled.
See Section “19.3. Watchdog Timer Mode” on page 203 for details.
SYSCLK/12
SYSCLK/4
Timer 0 Overflow
ECI
SYSCLK
PCA
CLOCK
MUX
16-Bit Counter/Timer
External Clock/8
Capture/Compare
Module 0
Capture/Compare
Module 1
Capture/Compare
Module 2
CEX2
CEX1
CEX0
ECI
Crossbar
Port I/O
Figure 19.1. PCA Block Diagram
Rev. 1.4
195
C8051F52x/F53x
19.1. PCA Counter/Timer
The 16-bit PCA counter/timer consists of two 8-bit SFRs: PCA0L and PCA0H. PCA0H is the high byte
(MSB) of the 16-bit counter/timer and PCA0L is the low byte (LSB). Reading PCA0L automatically latches
the value of PCA0H into a “snapshot” register; the following PCA0H read accesses this “snapshot” register.
Reading the PCA0L Register first guarantees an accurate reading of the entire 16-bit PCA0 counter.
Reading PCA0H or PCA0L does not disturb the counter operation. The CPS2-CPS0 bits in the PCA0MD
register select the timebase for the counter/timer as shown in Table 19.1.
When the counter/timer overflows from 0xFFFF to 0x0000, the Counter Overflow Flag (CF) in PCA0MD is
set to logic 1 and an interrupt request is generated if CF interrupts are enabled. Setting the ECF bit in
PCA0MD to logic 1 enables the CF flag to generate an interrupt request. The CF bit is not automatically
cleared by hardware when the CPU vectors to the interrupt service routine, and must be cleared by software (Note: PCA0 interrupts must be globally enabled before CF interrupts are recognized. PCA0 interrupts are globally enabled by setting the EA bit (IE.7) and the EPCA0 bit in EIE1 to logic 1). Clearing the
CIDL bit in the PCA0MD register allows the PCA to continue normal operation while the CPU is in Idle
mode.
Table 19.1. PCA Timebase Input Options
CPS2
CPS1
CPS0
Timebase
0
0
0
System clock divided by 12
0
0
1
System clock divided by 4
0
1
0
Timer 0 overflow
0
1
1
High-to-low transitions on ECI (max rate = system clock divided by 4)
1
0
0
System clock
1
0
1
External oscillator source divided by 8*
Note: External clock divided by 8 is synchronized with the system clock.
IDLE
PCA0MD
C
I
D
L
WW
D D
T L
E C
K
C
P
S
2
C
P
S
1
PCA0CN
CE
PC
S F
0
CC
FR
C
C
F
2
C
C
F
1
C
C
F
0
To SFR Bus
PCA0L
read
Snapshot
Register
SYSCLK/12
SYSCLK/4
Timer 0 Overflow
ECI
000
001
010
011
0
1
PCA0H
PCA0L
Overflow
To PCA Interrupt System
CF
SYSCLK
External Clock/8
100
To PCA Modules
101
Figure 19.2. PCA Counter/Timer Block Diagram
196
Rev. 1.4
C8051F52x/F53x
19.2. Capture/Compare Modules
Each module can be configured to operate independently in one of six operation modes: Edge-triggered
Capture, Software Timer, High Speed Output, Frequency Output, 8-Bit Pulse Width Modulator, or 16-Bit
Pulse Width Modulator. Each module has Special Function Registers (SFRs) associated with it in the CIP51 system controller. These registers are used to exchange data with a module and configure the module's
mode of operation.
Table 19.2 summarizes the bit settings in the PCA0CPMn registers used to select the PCA capture/compare module’s operating modes. Setting the ECCFn bit in a PCA0CPMn register enables the module's
CCFn interrupt. Note that PCA0 interrupts must be globally enabled before individual CCFn interrupts are
recognized. PCA0 interrupts are globally enabled by setting the EA bit and the EPCA0 bit to logic 1. See
Figure 19.3 for details on the PCA interrupt configuration.
Table 19.2. PCA0CPM Register Settings for PCA Capture/Compare Modules
PWM16 ECOM CAPP CAPN
MAT
TOG
PWM ECCF
X
X
1
0
0
0
0
X
X
X
0
1
0
0
0
X
X
X
1
1
0
0
0
X
0
0
0
0
0
0
0
0
0
0
1
1
X
X
X
0
1
1
0
0
0
0
1
1
1
X
X
X
X
X
X
1
X
1
X
1
0
1
1
1
X = Don’t Care
Operation Mode
Capture triggered by positive edge on
CEXn
Capture triggered by negative edge on
CEXn
Capture triggered by transition on
CEXn
Software Timer
High Speed Output
Frequency Output
8-Bit Pulse Width Modulator
16-Bit Pulse Width Modulator
(for n = 0 to 5)
PCA0CPMn
P ECCMT P E
WC A A A OWC
MOPP TGMC
1 MP N n n n F
6 n n n
n
n
PCA0CN
CC
FR
PCA0MD
CCC
CCC
FFF
2 1 0
C
I
D
L
CCCE
PPPC
SSSF
2 1 0
0
PCA Counter/
Timer Overflow
1
EPCA0
(EIE1.4)
ECCF0
PCA Module 0
(CCF0)
EA
(IE.7)
0
0
0
1
1
1
Interrupt
Priority
Decoder
ECCF1
0
PCA Module 1
(CCF1)
1
ECCF2
PCA Module 2
(CCF2)
0
1
Figure 19.3. PCA Interrupt Block Diagram
Rev. 1.4
197
C8051F52x/F53x
19.2.1. Edge-triggered Capture Mode
In this mode, a valid transition on the CEXn pin causes the PCA to capture the value of the PCA counter/timer and load it into the corresponding module's 16-bit capture/compare register (PCA0CPLn and
PCA0CPHn). The CAPPn and CAPNn bits in the PCA0CPMn register are used to select the type of transition that triggers the capture: low-to-high transition (positive edge), high-to-low transition (negative edge),
or either transition (positive or negative edge). When a capture occurs, the Capture/Compare Flag (CCFn)
in PCA0CN is set to logic 1 and an interrupt request is generated if CCF interrupts are enabled. The CCFn
bit is not automatically cleared by hardware when the CPU vectors to the interrupt service routine, and
must be cleared by software. If both CAPPn and CAPNn bits are set to logic 1, then the state of the Port
pin associated with CEXn can be read directly to determine whether a rising-edge or falling-edge caused
the capture.
PCA Interrupt
PCA0CPMn
0
Port I/O
Crossbar
CEXn
PCA0CN
CC
FR
CCC
CCC
FFF
2 1 0
(to CCFn)
P ECCMT P E
WC A A AOWC
MOPP TGMC
1 MP N n n n F
6 n n n
n
n
1
PCA0CPLn
PCA0CPHn
Capture
0
1
PCA
Timebase
PCA0L
PCA0H
Figure 19.4. PCA Capture Mode Diagram
Note: The CEXn input signal must remain high or low for at least 2 system clock cycles to be recognized by the
hardware.
198
Rev. 1.4
C8051F52x/F53x
19.2.2. Software Timer (Compare) Mode
In Software Timer mode, the PCA counter/timer value is compared to the module's 16-bit capture/compare
register (PCA0CPHn and PCA0CPLn). When a match occurs, the Capture/Compare Flag (CCFn) in
PCA0CN is set to logic 1 and an interrupt request is generated if CCF interrupts are enabled. The CCFn bit
is not automatically cleared by hardware when the CPU vectors to the interrupt service routine, and must
be cleared by software. Setting the ECOMn and MATn bits in the PCA0CPMn register enables Software
Timer mode.
Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0 Capture/Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the
ECOMn bit to 0; writing to PCA0CPHn sets ECOMn to 1.
Write to
PCA0CPLn
0
ENB
Reset
Write to
PCA0CPHn
PCA
Interrupt
ENB
1
PCA0CPMn
PCA0CN
P ECCMT P E
WC A A AOWC
MOPP TGMC
1 MP N n n n F
6 n n n
n
n
x
0 0
PCA0CPLn
CC
FR
PCA0CPHn
CCC
CCC
FFF
2 1 0
0 0 x
Enable
16-bit Comparator
PCA
Timebase
PCA0L
Match
0
1
PCA0H
Figure 19.5. PCA Software Timer Mode Diagram
Rev. 1.4
199
C8051F52x/F53x
19.2.3. High Speed Output Mode
In High Speed Output mode, a module’s associated CEXn pin is toggled each time a match occurs
between the PCA Counter and the module's 16-bit capture/compare register (PCA0CPHn and
PCA0CPLn) Setting the TOGn, MATn, and ECOMn bits in the PCA0CPMn register enables the HighSpeed Output mode.
Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0 Capture/Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the
ECOMn bit to 0; writing to PCA0CPHn sets ECOMn to 1.
Write to
PCA0CPLn
0
ENB
Reset
Write to
PCA0CPHn
PCA0CPMn
P ECCMT P E
WC A A AOWC
MOPP TGMC
1 MP N n n n F
6 n n n
n
n
ENB
1
x
0 0
PCA
Interrupt
0 x
PCA0CN
PCA0CPLn
Enable
CC
FR
PCA0CPHn
16-bit Comparator
Match
CCC
CCC
FFF
2 1 0
0
1
TOGn
Toggle
PCA
Timebase
0 CEXn
1
PCA0L
Crossbar
Port I/O
PCA0H
Figure 19.6. PCA High-Speed Output Mode Diagram
Note: The initial state of the Toggle output is logic 1 and is initialized to this state when the module enters High Speed
Output Mode.
200
Rev. 1.4
C8051F52x/F53x
19.2.4. Frequency Output Mode
Frequency Output Mode produces a programmable-frequency square wave on the module’s associated
CEXn pin. The capture/compare module high byte holds the number of PCA clocks to count before the output is toggled. The frequency of the square wave is then defined by Equation 19.1.
F PCA
F CEXn = ----------------------------------------2  PCA0CPHn
Note: A value of 0x00 in the PCA0CPHn register is equal to 256 for this equation.
Equation 19.1. Square Wave Frequency Output
Where FPCA is the frequency of the clock selected by the CPS2-0 bits in the PCA mode register, PCA0MD.
The lower byte of the capture/compare module is compared to the PCA counter low byte; on a match,
CEXn is toggled and the offset held in the high byte is added to the matched value in PCA0CPLn. Frequency Output Mode is enabled by setting the ECOMn, TOGn, and PWMn bits in the PCA0CPMn register.
PCA0CPMn
P ECCMT P E
WC A A AOWC
MOPP TGMC
1 MP N n n n F
6 n n n
n
n
0
0 0 0 1
PCA0CPLn
8-bit Adder
PCA0CPHn
Adder
Enable
TOGn
Toggle
0
Enable
PCA Timebase
8-bit
Comparator
match
0 CEXn
1
Crossbar
Port I/O
PCA0L
Figure 19.7. PCA Frequency Output Mode
Rev. 1.4
201
C8051F52x/F53x
19.2.5. 8-Bit Pulse Width Modulator Mode
Each module can be used independently to generate a pulse width modulated (PWM) output on its associated CEXn pin. The frequency of the output is dependent on the timebase for the PCA counter/timer. The
duty cycle of the PWM output signal is varied using the module's PCA0CPHn capture/compare register.
When the value in the low byte of the PCA counter/timer (PCA0L) is equal to the value in PCA0CPLn, the
output on the CEXn pin will be set. When the count value in PCA0L overflows, the CEXn output will be
reset (see Figure 19.8). Also, when the counter/timer low byte (PCA0L) overflows from 0xFF to 0x00,
PCA0CPLn is reloaded automatically with the value stored in the module’s capture/compare high byte
(PCA0CPHn) without software intervention. Setting the ECOMn and PWMn bits in the PCA0CPMn register
enables 8-Bit Pulse Width Modulator mode. The duty cycle for 8-Bit PWM Mode is given by Equation 19.2.
Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0 Capture/Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the
ECOMn bit to 0; writing to PCA0CPHn sets ECOMn to 1.
 256 – PCA0CPHn 
DutyCycle = --------------------------------------------------256
Equation 19.2. 8-Bit PWM Duty Cycle
Using Equation 19.2, the largest duty cycle is 100% (PCA0CPHn = 0), and the smallest duty cycle is
0.39% (PCA0CPHn = 0xFF). A 0% duty cycle may be generated by clearing the ECOMn bit to 0.
PCA0CPHn
PCA0CPMn
P ECCMT P E
WC A A AOWC
MOPP TGMC
1 MP N n n n F
6 n n n
n
n
0
0 0 0 0
PCA0CPLn
0
Enable
8-bit
Comparator
match
S
R
PCA Timebase
SET
CLR
Q
CEXn
Crossbar
Q
PCA0L
Overflow
Figure 19.8. PCA 8-Bit PWM Mode Diagram
202
Rev. 1.4
Port I/O
C8051F52x/F53x
19.2.6. 16-Bit Pulse Width Modulator Mode
A PCA module may also be operated in 16-Bit PWM mode. In this mode, the 16-bit capture/compare module defines the number of PCA clocks for the low time of the PWM signal. When the PCA counter matches
the module contents, the output on CEXn is asserted high; when the counter overflows, CEXn is asserted
low. To output a varying duty cycle, new value writes should be synchronized with PCA CCFn match interrupts. 16-Bit PWM Mode is enabled by setting the ECOMn, PWMn, and PWM16n bits in the PCA0CPMn
register. For a varying duty cycle, match interrupts should be enabled (ECCFn = 1 AND MATn = 1) to help
synchronize the capture/compare register writes. The duty cycle for 16-Bit PWM Mode is given by
Equation 19.3.
Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0 Capture/Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the
ECOMn bit to 0; writing to PCA0CPHn sets ECOMn to 1.
 65536 – PCA0CPn 
DutyCycle = ----------------------------------------------------65536
Equation 19.3. 16-Bit PWM Duty Cycle
Using Equation 19.3, the largest duty cycle is 100% (PCA0CPn = 0), and the smallest duty cycle is
0.0015% (PCA0CPn = 0xFFFF). A 0% duty cycle may be generated by clearing the ECOMn bit to 0.
PCA0CPMn
P ECCMT P E
WC A A AOWC
MOPP TGMC
1 MP N n n n F
6 n n n
n
n
1
0 0 0 0
PCA0CPHn
PCA0CPLn
0
Enable
match
16-bit Comparator
S
R
PCA Timebase
PCA0H
SET
CLR
Q
CEXn
Crossbar
Port I/O
Q
PCA0L
Overflow
Figure 19.9. PCA 16-Bit PWM Mode
19.3. Watchdog Timer Mode
A programmable watchdog timer (WDT) function is available through the PCA Module 2. The WDT is used
to generate a reset if the time between writes to the WDT update register (PCA0CPH2) exceed a specified
limit. The WDT can be configured and enabled/disabled as needed by software.
With the WDTE bit set in the PCA0MD register, Module 2 operates as a watchdog timer (WDT). The
Module 2 high byte is compared to the PCA counter high byte; the Module 2 low byte holds the offset to be
used when WDT updates are performed. The Watchdog Timer is enabled on reset. Writes to some
PCA registers are restricted while the Watchdog Timer is enabled.
Rev. 1.4
203
C8051F52x/F53x
19.3.1. Watchdog Timer Operation
While the WDT is enabled:






PCA counter is forced on.
Writes to PCA0L and PCA0H are not allowed.
PCA clock source bits (CPS2-CPS0) are frozen.
PCA Idle control bit (CIDL) is frozen.
Module 2 is forced into software timer mode.
Writes to the Module 2 mode register (PCA0CPM2) are disabled.
While the WDT is enabled, writes to the CR bit will not change the PCA counter state; the counter will run
until the WDT is disabled. The PCA counter run control (CR) will read zero if the WDT is enabled but user
software has not enabled the PCA counter. If a match occurs between PCA0CPH2 and PCA0H while the
WDT is enabled, a reset will be generated. To prevent a WDT reset, the WDT may be updated with a write
of any value to PCA0CPH2. Upon a PCA0CPH2 write, PCA0H plus the offset held in PCA0CPL2 is loaded
into PCA0CPH2 (See Figure 19.10).
PCA0MD
CWW
I D D
DT L
L E C
K
CCCE
PPPC
SSSF
2 1 0
PCA0CPH2
Enable
PCA0CPL2
8-bit Adder
Write to
PCA0CPH2
8-bit
Comparator
PCA0H
Match
Reset
PCA0L Overflow
Adder
Enable
Figure 19.10. PCA Module 2 with Watchdog Timer Enabled
Note that the 8-bit offset held in PCA0CPH2 is compared to the upper byte of the 16-bit PCA counter. This
offset value is the number of PCA0L overflows before a reset. Up to 256 PCA clocks may pass before the
first PCA0L overflow occurs, depending on the value of the PCA0L when the update is performed. The
total offset is then given (in PCA clocks) by Equation 19.4, where PCA0L is the value of the PCA0L register
at the time of the update.
Offset =  256  PCA0CPL2  +  256 – PCA0L 
Equation 19.4. Watchdog Timer Offset in PCA Clocks
The WDT reset is generated when PCA0L overflows while there is a match between PCA0CPH2 and
PCA0H. Software may force a WDT reset by writing a 1 to the CCF2 flag (PCA0CN.2) while the WDT is
enabled.
204
Rev. 1.4
C8051F52x/F53x
19.3.2. Watchdog Timer Usage
To configure the WDT, perform the following tasks:

Disable the WDT by writing a 0 to the WDTE bit.
Select the desired PCA clock source (with the CPS2-CPS0 bits).
 Load PCA0CPL2 with the desired WDT update offset value.
 Configure the PCA Idle mode (set CIDL if the WDT should be suspended while the CPU is in Idle
mode).
 Enable the WDT by setting the WDTE bit to 1.

The PCA clock source and Idle mode select cannot be changed while the WDT is enabled. The watchdog
timer is enabled by setting the WDTE or WDLCK bits in the PCA0MD register. When WDLCK is set, the
WDT cannot be disabled until the next system reset. If WDLCK is not set, the WDT is disabled by clearing
the WDTE bit.
The WDT is enabled following any reset. The PCA0 counter clock defaults to the system clock divided by
12, PCA0L defaults to 0x00, and PCA0CPL2 defaults to 0x00. Using Equation 19.4, this results in a WDT
timeout interval of 3072 system clock cycles. Table 19.3 lists some example timeout intervals for typical
system clocks.
Table 19.3. Watchdog Timer Timeout Intervals1
System Clock (Hz)
PCA0CPL2
Timeout Interval (ms)
24,500,000
24,500,000
24,500,000
18,432,000
18,432,000
18,432,000
11,059,200
11,059,200
11,059,200
3,062,500
3,062,500
3,062,500
191,4062
191,4062
191,4062
32,000
32,000
32,000
255
128
32
255
128
32
255
128
32
255
128
32
255
128
32
255
128
32
32.1
16.2
4.1
42.7
21.5
5.5
71.1
35.8
9.2
257
129.5
33.1
4109
2070
530
24576
12384
3168
Notes:
1. Assumes SYSCLK / 12 as the PCA clock source, and a PCA0L
value of 0x00 at the update time.
2. Internal oscillator reset frequency.
Rev. 1.4
205
C8051F52x/F53x
19.4. Register Descriptions for PCA
Following are detailed descriptions of the special function registers related to the operation of the PCA.
SFR Definition 19.1. PCA0CN: PCA Control
R/W
R/W
CF
CR
Bit7
Bit6
R/W
R/W
R/W
Reserved Reserved Reserved
Bit5
Bit4
Bit3
R/W
R/W
R/W
Reset Value
CCF2
CCF1
CCF0
00000000
Bit2
Bit1
Bit0
Bit
Addressable
SFR Address: 0xD8
Bit7:
CF: PCA Counter/Timer Overflow Flag.
Set by hardware when the PCA Counter/Timer overflows from 0xFFFF to 0x0000. When the
Counter/Timer Overflow (CF) interrupt is enabled, setting this bit causes the CPU to vector
to the PCA interrupt service routine. This bit is not automatically cleared by hardware and
must be cleared by software.
Bit6:
CR: PCA Counter/Timer Run Control.
This bit enables/disables the PCA Counter/Timer.
0: PCA Counter/Timer disabled.
1: PCA Counter/Timer enabled.
Bits5–3: Reserved.
Bit2:
CCF2: PCA Module 2 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF2 interrupt is
enabled, setting this bit causes the CPU to vector to the PCA interrupt service routine. This
bit is not automatically cleared by hardware and must be cleared by software.
Bit1:
CCF1: PCA Module 1 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF1 interrupt is
enabled, setting this bit causes the CPU to vector to the PCA interrupt service routine. This
bit is not automatically cleared by hardware and must be cleared by software.
Bit0:
CCF0: PCA Module 0 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF0 interrupt is
enabled, setting this bit causes the CPU to vector to the PCA interrupt service routine. This
bit is not automatically cleared by hardware and must be cleared by software.
206
Rev. 1.4
C8051F52x/F53x
SFR Definition 19.2. PCA0MD: PCA Mode
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
Reset Value
CIDL
WDTE
WDLCK
-
CPS2
CPS1
CPS0
ECF
01000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address: 0xD9
Bit7:
CIDL: PCA Counter/Timer Idle Control.
Specifies PCA behavior when CPU is in Idle Mode.
0: PCA continues to function normally while the system controller is in Idle Mode.
1: PCA operation is suspended while the system controller is in Idle Mode.
Bit6:
WDTE: Watchdog Timer Enable
If this bit is set, PCA Module 2 is used as the watchdog timer.
0: Watchdog Timer disabled.
1: PCA Module 2 enabled as Watchdog Timer.
Bit5:
WDLCK: Watchdog Timer Lock
This bit locks/unlocks the Watchdog Timer Enable. When WDLCK is set, the Watchdog
Timer may not be disabled until the next system reset.
0: Watchdog Timer Enable unlocked.
1: Watchdog Timer Enable locked.
Bit4:
UNUSED. Read = 0b, Write = don't care.
Bits3–1: CPS2–CPS0: PCA Counter/Timer Pulse Select.
These bits select the timebase source for the PCA counter.
CPS2
CPS1
CPS0
Timebase
0
0
0
System clock divided by 12
0
0
1
System clock divided by 4
0
1
0
Timer 0 overflow
0
1
1
High-to-low transitions on ECI (max rate = system clock
divided by 4)
1
0
0
System clock
1
0
1
External clock divided by 8*
1
1
0
Reserved
1
1
1
Reserved
Note: External clock divided by 8 is synchronized with the system clock.
Bit0:
ECF: PCA Counter/Timer Overflow Interrupt Enable.
This bit sets the masking of the PCA Counter/Timer Overflow (CF) interrupt.
0: Disable the CF interrupt.
1: Enable a PCA Counter/Timer Overflow interrupt request when CF (PCA0CN.7) is set.
Note: When the WDTE bit is set to 1, the PCA0MD register cannot be modified. To change the
contents of the PCA0MD register, the Watchdog Timer must first be disabled.
Rev. 1.4
207
C8051F52x/F53x
SFR Definition 19.3. PCA0CPMn: PCA Capture/Compare Mode
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
PWM16n
ECOMn
CAPPn
CAPNn
MATn
TOGn
PWMn
ECCFn
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address: PCA0CPM0: 0xDA, PCA0CPM1: 0xDB, PCA0CPM2: 0xDC
Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
208
PWM16n: 16-bit Pulse Width Modulation Enable.
This bit selects 16-bit mode when Pulse Width Modulation mode is enabled (PWMn = 1).
0: 8-bit PWM selected.
1: 16-bit PWM selected.
ECOMn: Comparator Function Enable.
This bit enables/disables the comparator function for PCA module n.
0: Disabled.
1: Enabled.
CAPPn: Capture Positive Function Enable.
This bit enables/disables the positive edge capture for PCA module n.
0: Disabled.
1: Enabled.
CAPNn: Capture Negative Function Enable.
This bit enables/disables the negative edge capture for PCA module n.
0: Disabled.
1: Enabled.
MATn: Match Function Enable.
This bit enables/disables the match function for PCA module n. When enabled, matches of
the PCA counter with a module's capture/compare register cause the CCFn bit in PCA0MD
register to be set to logic 1.
0: Disabled.
1: Enabled.
TOGn: Toggle Function Enable.
This bit enables/disables the toggle function for PCA module n. When enabled, matches of
the PCA counter with a module's capture/compare register cause the logic level on the
CEXn pin to toggle. If the PWMn bit is also set to logic 1, the module operates in Frequency
Output Mode.
0: Disabled.
1: Enabled.
PWMn: Pulse Width Modulation Mode Enable.
This bit enables/disables the PWM function for PCA module n. When enabled, a pulse width
modulated signal is output on the CEXn pin. 8-bit PWM is used if PWM16n is cleared; 16-bit
mode is used if PWM16n is set to logic 1. If the TOGn bit is also set, the module operates in
Frequency Output Mode.
0: Disabled.
1: Enabled.
ECCFn: Capture/Compare Flag Interrupt Enable.
This bit sets the masking of the Capture/Compare Flag (CCFn) interrupt.
0: Disable CCFn interrupts.
1: Enable a Capture/Compare Flag interrupt request when CCFn is set.
Rev. 1.4
C8051F52x/F53x
SFR Definition 19.4. PCA0L: PCA Counter/Timer Low Byte
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address: 0xF9
Bits7–0: PCA0L: PCA Counter/Timer Low Byte.
The PCA0L register holds the low byte (LSB) of the 16-bit PCA Counter/Timer.
SFR Definition 19.5. PCA0H: PCA Counter/Timer High Byte
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
SFR Address: 0xFA
Bits7–0: PCA0H: PCA Counter/Timer High Byte.
The PCA0H register holds the high byte (MSB) of the 16-bit PCA Counter/Timer.
SFR Definition 19.6. PCA0CPLn: PCA Capture Module Low Byte
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Reset Value
00000000
SFR Address: PCA0CPL0: 0xFB, PCA0CPL1: 0xE9, PCA0CPL2: 0xEB
Bits7–0: PCA0CPLn: PCA Capture Module Low Byte.
The PCA0CPLn register holds the low byte (LSB) of the 16-bit capture module n.
SFR Definition 19.7. PCA0CPHn: PCA Capture Module High Byte
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Reset Value
00000000
SFR Address: PCA0CPH0: 0xFC, PCA0CPH1: 0xE9, PCA0CPH2: 0xEC
Bits7–0: PCA0CPHn: PCA Capture Module High Byte.
The PCA0CPHn register holds the high byte (MSB) of the 16-bit capture module n.
Rev. 1.4
209
C8051F52x/F53x
20. Device Specific Behavior
This chapter contains behavioral differences between the silicon revisions of C8051F52x/52xA/F53x/53xA
devices.
These differences do not affect the functionality or performance of most systems and are described below.
20.1. Device Identification
The Part Number Identifier on the top side of the device package can be used for decoding device
information. The first character of the trace code identifies the silicon revision. On C8051F52x-C/53x-C
devices, the trace code (second line on the TSSOP-20 and DFN-10 packages; third line on the QFN-20
package) will begin with the letter "C". The "A" suffix at the end of the part number such as "C8051F530A"
is only present on Revision B devices. All other revisions do not include this suffix. Figures 20.1, 20.2, and
20.3 show how to find the part number on the top side of the device package.
First character of
the trace code
identifies the
silicon revision
Figure 20.1. Device Package—TSSOP 20
First character of
the trace code
identifies the
silicon revision
Figure 20.2. Device Package—QFN 20
210
Rev. 1.4
C8051F52x/F53x
First character of
the trace code
identifies the
silicon revision
Figure 20.3. Device Package—DFN 10
20.2. Reset Pin Behavior
The reset behavior differs between the silicon revisions of C8051F52x/52xA/F53x/F53xA devices. The differences affect the state of the RST pin during a VDD Monitor reset.
On Revision A devices, a VDD Monitor reset does not affect the state of the RST pin. On Revision B and
Revision C devices, a VDD Monitor reset will pull the RST pin low for the duration of the brownout condition.
20.3. Reset Time Delay
The reset time delay differs between the silicon revisions of C8051F52x/52xA/F53x/F53xA devices.
On Revision A devices, the reset time delay will be as long as 80 ms following a power-on reset, meaning
it can take up to 80 ms to begin code execution. Subsequent resets will not cause the long delay. On Revision B and Revision C devices, the startup time is around 350 µs, specified as TPORDELAY in Table 2.8,
“Reset Electrical Characteristics,” on page 32.
20.4. VDD Monitors and VDD Ramp Time
The number of VDD monitors and definition of “VDD ramp time” differs between the silicon revisions of
C8051F52x/52xA/F53x/F53xA devices.
On Revision A and Revision B devices, the only VDD monitor present is the standard VDD monitor
(VDDMON0). On these devices, the VDD ramp time is defined as how fast VDD ramps from 0 V to VRST.
Here, VRST is the VRST-LOW threshold of VDDMON0 specifed in Table 2.8, “Reset Electrical Characteristics,” on page 32. The maximum VDD ramp time for these devices is 1 ms; slower ramp times may cause
the device to be released from reset before VDD reaches the VRST-LOW level.
Revision C devices include two VDD monitors: a standard VDD monitor (VDDMON0) and a level-sensitive
VDD monitor (VDDMON1). See Section 11.2 on page 108 for more details. On these devices, the VDD
ramp time is defined as how fast VDD ramps from 0 V to VRST1. VRST1 is specified in Table 2.8, “Reset
Electrical Characteristics,” on page 32 as the threshold of the new level-sensitive VDD monitor
(VDDMON1). This new VDD monitor will hold the device in reset until VDD reaches the VRST1 level irrespective of the length of the VDD ramp time.
Note: Please refer to Section “11.2.1. VDD Monitor Thresholds and Minimum VDD” on page 108 for
recommendations related to minimum VDD.
Rev. 1.4
211
C8051F52x/F53x
20.5. VDD Monitor (VDDMON0) High Threshold Setting
The calibration behavior of the internal voltage regulator (REG0) and its impact on VDD monitor
(VDDMON0) high threshold setting differs between the silicon revisions of C8051F52x/52xA/F53x/F53xA
devices.
The following note applies to Revision A and Revision B devices: The output of the internal voltage regulator (REG0) is calibrated by the MCU immediately after any reset event. The output of the un-calibrated
internal regulator could be below the high threshold setting (VRST-HIGH) of the VDD Monitor (VDDMON0). If
this is the case and the VDD Monitor is set to the high threshold setting and if the MCU receives a nonpower on reset, the MCU will remain in reset until a power-on reset (POR) occurs (i.e. VDD Monitor will
keep the device in reset). A POR will force the VDD Monitor to the low threshold setting which is guaranteed to be below the un-calibrated output of the internal regulator. The device will then exit reset and
resume normal operation. It is for this reason Silicon Labs strongly recommends that the VDD Monitor is
always left in the low threshold setting (i.e., default value upon POR).
When programming the Flash in-system, the VDD Monitor (VDDMON0) must be set to the high threshold
setting. For the highest system reliability, the time the VDD Monitor is set to the high threshold setting
should be minimized (e.g., setting the VDD Monitor to the high threshold setting just before the Flash write
operation and then changing it back to the low threshold setting immediately after the Flash write operation).
The following note applies to Revision C devices: The output of the internal voltage regulator (REG0) is
calibrated by the MCU immediately after a power-on reset (POR). This calibrated output setting will stay
calibrated through any type of reset other than POR. Because of this change in behavior of REG0, the “low
threshold” recommendation noted above for Revision A and Revision B devices does not apply to Revision
C devices; the VDD Monitor (VDDMON0) can be set to the high threshold as needed depending on the
application.
20.6. Reset Low Time
The maximum reset low time differs between the silicon revisions of C8051F52x/52xA/F53x/F53xA
devices.
Reset low time is the duration for which the RST pin is driven low by an external circuit while power is
applied to the device. On Revision A and Revision B devices with assembly build date code earlier than
1124 (year 2011, work week 24), the reset low time should be a maximum of 1 second. For longer reset
low times, a percentage of devices within a narrow range of temperatures (a 5 to 10 C window) may
“lock up” and fail to execute code. The condition is cleared only by cycling power.
Revision B devices with assembly date code 1124 or later and Revision C devices do not have any restrictions on reset low time.
20.7. Internal Oscillator Suspend Mode
The required bias setting for the internal oscillator before entering suspend mode differs between the silicon revisions of C8051F52x/52xA/F53x/F53xA devices.
On Revision A and Revision B devices, firmware must set the ZTCEN bit in REF0CN (SFR Definition 5.1)
before entering suspend mode. If ZTCEN is not set to 1, there is a low probability of the device remaining
in suspend even when a wake-up condition is triggered. On Revision C devices, this bit need not be set to
1 before entering suspend mode.
212
Rev. 1.4
C8051F52x/F53x
20.8. UART Pins
The location of the pins used by the serial UART interface differs between the silicon revisions of
C8051F52x/52xA/F53x/F53xA devices.
On Revision A devices, the TX and RX pins used by the UART interface are mapped to the P0.3 (TX) and
P0.4 (RX) pins. Beginning with Revision B devices, the TX and RX pins used by the UART interface are
mapped to the P0.4 (TX) and P0.5 (RX) pins.
Important Note: On Revision B and newer devices, the UART pins must be skipped if the UART is
enabled in order for peripherals to appear on port pins beyond the UART on the crossbar. For example,
with the SPI and UART enabled on the crossbar with the SPI on P1.0-P1.3, the UART pins must be
skipped using P0SKIP for the SPI pins to appear correctly.
20.9. LIN
The LIN peripheral behavior differs between the silicon revisions of C8051F52x/52xA/F53x/F53xA devices.
The differences are:
20.9.1. Stop Bit Check
On Revision A devices, the stop bits of the fields in the LIN frame are not checked and no error is generated if the stop bits could not be sent or received correctly. On Revision B and Revision C devices, the stop
bits are checked, and an error will be generated if the stop bit was not sent or received correctly.
20.9.2. Synch Break and Synch Field Length Check
On Revision A devices, the check of sync field length versus sync break length is incorrect. On Revision B
and Revision C devices, the sync break length must be larger than 10 bit times (of the measured bit time)
to enable the synchronization.
Rev. 1.4
213
C8051F52x/F53x
21. C2 Interface
C8051F52x/F52xA/F53x/F53xA devices include an on-chip Silicon Laboratories 2-Wire (C2) debug interface to allow Flash programming and in-system debugging with the production part installed in the end
application. The C2 interface uses a clock signal (C2CK) and a bi-directional C2 data signal (C2D) to transfer information between the device and a host system. See the C2 Interface Specification for details on the
C2 protocol.
21.1. C2 Interface Registers
The following describes the C2 registers necessary to perform Flash programming functions through the
C2 interface. All C2 registers are accessed through the C2 interface as described in the C2 Interface Specification.
C2 Register Definition 21.1. C2ADD: C2 Address
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Bits7–0: The C2ADD register is accessed via the C2 interface to select the target Data register for
C2 Data Read and Data Write commands.
Address
0x00
0x01
0x02
0xB4
Description
Selects the Device ID register for Data Read instructions (DEVICEID)
Selects the Revision ID register for Data Read instructions (REVID)
Selects the C2 Flash Programming Control register for Data Read/Write instructions
(FPCTL)
Selects the C2 Flash Programming Data register for Data Read/Write instructions
(FPDAT)
C2 Register Definition 21.2. DEVICEID: C2 Device ID
Reset Value
00010001
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
This read-only register returns the 8-bit device ID: 0x11 (C8051F52x/F52xA/F53x/F53xA).
214
Rev. 1.4
C8051F52x/F53x
C2 Register Definition 21.3. REVID: C2 Revision ID
Reset Value
Varies
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
This read-only register returns the 8-bit revision ID.
For example, 0x00 = Revision A.
C2 Register Definition 21.4. FPCTL: C2 Flash Programming Control
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Bits7–0 FPCTL: Flash Programming Control Register.
This register is used to enable Flash programming via the C2 interface. To enable C2 Flash
programming, the following codes must be written in order: 0x02, 0x01. Note that once C2
Flash programming is enabled, a system reset must be issued to resume normal operation.
C2 Register Definition 21.5. FPDAT: C2 Flash Programming Data
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Bits7–0: FPDAT: C2 Flash Programming Data Register.
This register is used to pass Flash commands, addresses, and data during C2 Flash
accesses. Valid commands are listed below.
Code
Command
0x06
0x07
0x08
0x03
Flash Block Read
Flash Block Write
Flash Page Erase
Device Erase
Rev. 1.4
215
C8051F52x/F53x
21.2. C2 Pin Sharing
The C2 protocol allows the C2 pins to be shared with user functions so that in-system debugging and
Flash programming functions may be performed. This is possible because C2 communication is typically
performed when the device is in the halt state, where all on-chip peripherals and user software are stalled.
In this halted state, the C2 interface can safely ‘borrow’ the C2CK (/RST) and C2D (P0.1 or P0.6) pins. In
most applications, external resistors are required to isolate C2 interface traffic from the user application. A
typical isolation configuration is shown in Figure 21.1.
C8051Fxxx
/Reset (a)
C2CK
Input (b)
C2D
Output (c)
C2 Interface Master
Figure 21.1. Typical C2 Pin Sharing
The configuration in Figure 21.1 assumes the following:
1. The user input (b) cannot change state while the target device is halted.
2. The /RST pin on the target device is used as an input only.
Additional resistors may be necessary depending on the specific application.
216
Rev. 1.4
C8051F52x/F53x
DOCUMENT CHANGE LIST
Revision 0.3 to 0.4

Updated all specification tables.
Added 'F52xA and 'F53xA information.
 Updated the Selectable Gain section in the ADC section.
 Updated the External Crystal Example in the Oscillators section.
 Updated the LIN section.

Revision 0.4 to 0.5

Updated all specification tables.
Updated Figures 1.1, 1.2, 1.3, and 1.4.
 Updated Section 4 pinout diagrams and tables.

Revision 0.5 to 1.0







Updated all specification tables and moved them to one section.
Added Figure 3.1 and Figure 3.2.
Updated Section 4 pinout diagrams and tables.
Updated Figure 5.6.
Added Figure 15.3.
Updated equations in Section 17.
Updated Figure 21.3.
Revision 1.0 to 1.1

Updated Table 2.3, “ADC0 Electrical Characteristics,” on page 28 with new Burst Mode Oscillator
specification, new Power Supply Current maximum, and made corrections to Temperature Sensor
Offset and Offset Error conditions.
 Updated Table 2.9, “Flash Electrical Characteristics,” on page 33 with new Flash Write and Erase
timing.
 Made correction in Equivalent Gain table in Section “4.4. Selectable Gain” on page 60.
 Updated Section “11.2. Power-Fail Reset / VDD Monitors (VDDMON0 and VDDMON1)” on page 108
regarding higher VDD monitor threshold.
Revision 1.1 to 1.2





Updated “Ordering Information” on page 14 and Table 1.1, “Product Selection Guide (Recommended
for New Designs),” on page 14 to include -A (Automotive) devices and automotive qualification
information.
Updated Table 2.3, “ADC0 Electrical Characteristics,” on page 28 to include Temperature Sensor
tracking time requirement and update INL maximum specification.
Updated Figure 3.2. ’DFN-10 Package Diagram’ on page 38 with new Pin-1 detail drawing.
Updated Table 8.1, “CIP-51 Instruction Set Summary,” on page 83 with correct CJNE and CPL timing.
Updated “Power-Fail Reset / VDD Monitors (VDDMON0 and VDDMON1)” on page 108 to clarify the
recommendations for the VDD monitor.
Note: All items from the C8051F52xA-F53xA Errata dated August 26, 2009 are incorporated into this data sheet.
Rev. 1.4
217
C8051F52x/F53x
Revision 1.2 to 1.3








Updated “System Overview” on page 13 with a voltage range specification for the internal oscillator.
Updated Table 2.11 on page 34 with new conditions for the internal oscillator accuracy. The internal
oscillator accuracy is dependent on the operating voltage range.
Updated Section 2 to remove the internal oscillator curve across temperature diagram.
Updated Figure “4.5 12-Bit ADC Burst Mode Example with Repeat Count Set to 4” on page 58 with new
timing diagram when using CNVSTR pin.
Updated SFR Definition 5.1 (REF0CN) with oscillator suspend requirement for ZTCEN.
Updated SFR Definition 6.1 (REG0CN) with a new definition for Bit 6. The bit 6 reset value is 1b and
must be written to 1b.
Updated Section “8.3.3. Suspend Mode” on page 90 with note regarding ZTCEN.
Updated Section “17. LIN (C8051F520/0A/3/3A/6/6A and C8051F530/0A/3/3A/6/6A)” on page 164 with
a voltage range specification for the internal oscillator.
Revision 1.3 to 1.4
















Added ‘AEC-Q100’ qualification information on page 1.
Changed page headers throughout the document from ‘C8051F52x/F52xA/F53x/F53xA’ to
‘C8051F52x/53x’.
Updated supply voltage to "2.0 to 5.25 V" on page 1 and in Section 1 on page 13.
Corrected reference to development kit (C8051F530DK) in Section “1.2.4. On-Chip Debug Circuitry” on
page 18.
Updated minimum Supply Input Voltage (VREGIN) for C8051F52x-C/F53x-C devices in Table 2.2 on
page 26 and Table 2.6 on page 30.
Updated digital supply current (IDD and Idle IDD) typical values for condition ‘Clock = 25 MHz’ in
Table 2.2 on page 26.
Updated IDD Frequency Sensitivity and Idle IDD Frequency Sensitivity values in Table 2.2 on page 26;
removed Figure 2.1 and Figure 2.2 that used to provide the same frequency sensitivity slopes. Also
removed IDD Supply Sensitivity and Idle IDD Supply Sensitivity typical values.
Added Digital Supply Current (Stop or Suspend Mode) values at multiple temperatures Table 2.2 on
page 26.
Added a note in Table 2.3, “ADC0 Electrical Characteristics,” on page 28 with reference to Section
“4.4. Selectable Gain” on page 60; also added note to indicate that additional tracking time may be
necessary if VDD is less than the minimum specified VDD.
Split off temperature sensor specifications from Table 2.3 into a separate table Table 2.4; Updated
temperature sensor gain and added supply current values.
Added temperature condition for Bias Current specification in Table 2.6 on page 30.
Updated Comparator Input Offset Voltage values in Table 2.7 on page 31.
Updated VDD Monitor (VDDMON0) Low Threshold (VRST-LOW) minimum value for C8051F52xA/F52xC/F53xA/F53x-C devices in Table 2.8 on page 32.
Updated VDD Monitor (VDDMON0) supply current values in Table 2.8 on page 32.
Added specifications for the new level-sensitive VDD monitor (VDDMON1) to Table 2.8, “Reset
Electrical Characteristics,” on page 32 and also added notes to clarify the applicable VRST theshold
level.
Added note in Table 2.9, “Flash Electrical Characteristics,” on page 33 to describe the minimum flash
programming temperature for –I (Industrial Grade) devices; Also added the same note and references
to it in Section “12.1. Programming The Flash Memory” on page 113, Section “12.3. Non-volatile Data
Storage” on page 117, and in SFR Definition 12.1 (PSCTL).
218
Rev. 1.4
C8051F52x/F53x

Replaced minimum VDD value for Flash write/erase operations in Table 2.9 on page 33 with references
to the VRST-HIGH theshold specified in Table 2.8 on page 32.

Removed Output Low Voltage values for condition ‘VREGIN = 1.8 V’ from Table 2.10, “Port I/O DC
Electrical Characteristics,” on page 33.
Corrected minor typo (“IFCN = 111b”) in Table 2.11, “Internal Oscillator Electrical Characteristics,” on
page 34.
Removed the typical value and added the maximum value for the 'Wake-up Time From Suspend'
specification with the 'ZTCEN = 0' condition in Table 2.11, “Internal Oscillator Electrical Characteristics,”
on page 34.
Added Internal Oscillator Supply current values at specific temperatures for conditions ‘ZTCEN = 1’ and
‘ZTCEN = 0’ in Table 2.11, “Internal Oscillator Electrical Characteristics,” on page 34. Also updated the
table name to clarify that the specifications apply to the internal oscillator.
Updated Section “1.1. Ordering Information” on page 14 and Table 1.1 with new C8051F52x-C/F53x-C
part numbers.
Updated Table 1.2, “Product Selection Guide (Not Recommended for New Designs),” on page 15 to
include C8051F52xA/F53xA part numbers.
Updated Figure 1.1, Figure 1.2, Figure 1.3, and Figure 1.4 titles to clarify applicable silicon revisions.
Added figure references to pinout diagrams (Figure 3.1, Figure 3.4, and Figure 3.7) and updated labels
to clarify applicable part numbers.
Updated Table 3.1, Table 3.4, and Table 3.7 to indicate pinouts applicable to C8051F52x-C/F53x-C
devices.
Added note in Section “6. Voltage Regulator (REG0)” on page 74 to indicate the need for bypass
capacitors for voltage regulator stability.
Updated Figure 11.1 on Page 106 and text in Section “11.1. Power-On Reset” on page 107 and Section
“11.2. Power-Fail Reset / VDD Monitors (VDDMON0 and VDDMON1)” on page 108 to describe the
new level-sensitive VDD monitor (VDDMON1).











Updated SFR Definition 11.1. “VDDMON: VDD Monitor Control” on page 109 to include the VDM1EN
bit (bit 4) that controls the new level-sensitive VDD monitor (VDDMON1).

Added notes in Section 11.1 on page 107, Section 11.2 on page 108, and Section 11.3 on page 110
with references to relevant parts of Section “20. Device Specific Behavior” on page 210.
 Moved some notes related to VDD Monitor (VDDMON0) High Threshold setting (VRST-HIGH) from
Section 11.2 on page 108 to Section 20.5 on page 212 in Section “20. Device Specific Behavior”.
 Added Section “11.2.1. VDD Monitor Thresholds and Minimum VDD” on page 108 to describe the
recommendations for minimum VDD as it relates to the VDD monitor thresholds.

Clarified text in Section “11.7. Flash Error Reset” on page 110.
 Clarified text in items 2, 3 and 4 in Section “12.2.1. VDD Maintenance and the VDD monitor” on page 115
to reference appropriate specification tables and specify “VDDMON0”.
Rev. 1.4
219
C8051F52x/F53x
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