CY14B104LA, CY14B104NA 4-Mbit (512 K × 8/256 K × 16) nvSRAM Features ■ Packages ❐ 44-/54-pin thin small outline package (TSOP II) ❐ 48-ball fine-pitch ball grid array (FBGA) Pb-free and restriction of hazardous substances (RoHS) compliant ■ 20 ns, 25 ns, and 45 ns access times ■ Internally organized as 512 K × 8 (CY14B104LA) or 256 K × 16 (CY14B104NA) ■ ■ Hands off automatic STORE on power-down with only a small capacitor Functional Description ■ STORE to QuantumTrap nonvolatile elements initiated by software, device pin, or AutoStore on power-down ■ RECALL to SRAM initiated by software or power-up ■ Infinite read, write, and recall cycles ■ 1 million STORE cycles to QuantumTrap ■ 20 year data retention ■ Single 3 V +20%, -10% operation ■ Industrial temperature The Cypress CY14B104LA/CY14B104NA is a fast static RAM (SRAM), with a nonvolatile element in each memory cell. The memory is organized as 512 K bytes of 8 bits each or 256 K words of 16 bits each. The embedded nonvolatile elements incorporate QuantumTrap technology, producing the world’s most reliable nonvolatile memory. The SRAM provides infinite read and write cycles, while independent nonvolatile data resides in the highly reliable QuantumTrap cell. Data transfers from the SRAM to the nonvolatile elements (the STORE operation) takes place automatically at power-down. On power-up, data is restored to the SRAM (the RECALL operation) from the nonvolatile memory. Both the STORE and RECALL operations are also available under software control. Logic Block Diagram[1, 2, 3] 4XDWUXP7UDS ; $ $ $ $ $ $ $ $ $ $ $ 5 2 : ' ( & 2 ' ( 5 6725( 9&& 9&$3 32:(5 &21752/ 5(&$// 6725(5(&$// &21752/ 67$7,&5$0 $55$< ; 62)7:$5( '(7(&7 +6% $$ '4 '4 '4 '4 , 1 3 8 7 % 8 ) ) ( 5 6 '4 '4 '4 '4 '4 '4 '4 '4 &2/801,2 2( &2/801'(& :( '4 '4 &( '4 $ $ $ $ $ $ $ $ '4 %/( %+( Notes 1. Address A0 - A18 for ×8 configuration and Address A0 - A17 for ×16 configuration. 2. Data DQ0 - DQ7 for ×8 configuration and Data DQ0 - DQ15 for ×16 configuration. 3. BHE and BLE are applicable for ×16 configuration only. Cypress Semiconductor Corporation Document #: 001-49918 Rev. *H • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised January 18, 2011 [+] Feedback CY14B104LA, CY14B104NA Contents Pinouts .............................................................................. 3 Device Operation .............................................................. 5 SRAM Read ....................................................................... 5 SRAM Write ....................................................................... 5 AutoStore Operation ........................................................ 5 Hardware STORE Operation............................................ 5 Hardware RECALL (Power-Up) ....................................... 6 Software STORE ............................................................... 6 Software RECALL............................................................. 6 Preventing AutoStore....................................................... 7 Data Protection ................................................................. 7 Noise Considerations....................................................... 7 Best Practices................................................................... 8 Maximum Ratings............................................................. 9 Operating Range............................................................... 9 DC Electrical Characteristics .......................................... 9 AC Test Conditions ........................................................ 10 Data Retention and Endurance ..................................... 10 Capacitance .................................................................... 10 Thermal Resistance........................................................ 10 AC Switching Characteristics ....................................... 11 Switching Waveforms .................................................... 11 Document #: 001-49918 Rev. *H AutoStore/Power-Up RECALL....................................... Switching Waveforms .................................................... Software Controlled STORE/RECALL Cycle................ Switching Waveforms .................................................... Hardware STORE Cycle ................................................. Switching Waveforms .................................................... Truth Table For SRAM Operations................................ For ×8 Configuration ................................................. For ×16 Configuration ............................................... Ordering Information...................................................... Package Diagrams.......................................................... Acronyms ........................................................................ Document Conventions ............................................. Units of Measure ....................................................... Document History Page ................................................. Sales, Solutions, and Legal Information ...................... Worldwide Sales and Design Support....................... Products .................................................................... PSoC Solutions ......................................................... 14 14 15 15 16 16 17 17 17 18 20 22 22 22 23 24 24 24 24 Page 2 of 24 [+] Feedback CY14B104LA, CY14B104NA Pinouts Figure 1. Pin Diagram - 48-Ball FBGA 48 - FBGA 48 - FBGA (×8) Top View (not to scale) (×16) Top View (not to scale) 1 2 3 4 5 6 A BLE OE A0 A1 A2 NC A NC B DQ8 BHE A3 A4 CE DQ0 B NC DQ4 C DQ9 DQ10 A5 A6 DQ1 DQ2 C A7 DQ5 VCC D VSS A17 A7 DQ3 VCC D 2 3 4 5 6 NC OE A0 A1 A2 NC NC NC A3 A4 CE DQ0 NC A5 A6 VSS DQ1 A17 1 DQ11 VCC DQ2 VCAP A16 DQ6 VSS E VCC DQ12 VCAP A16 DQ4 VSS E DQ3 NC A14 A15 NC DQ7 F DQ14 DQ13 A14 A15 DQ5 DQ6 F NC HSB A12 A13 WE NC G DQ15 HSB A12 A13 WE DQ7 G A18 A8 A9 A10 A11 H NC A9 A10 A11 NC H 44 43 42 41 40 39 38 37 36 35 34 33 32 31 A17 A16 A15 OE BHE NC [4] [4] A8 Figure 2. Pin Diagram - 44-Pin TSOP II (×16)[6] (×8) NC [5] NC A0 A1 A2 A3 A4 CE DQ0 DQ1 VCC VSS DQ2 DQ3 WE A5 A6 A7 A8 A9 NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 - TSOP II (×8) Top View (not to scale) 44 43 42 41 40 39 38 37 36 35 34 33 32 31 HSB NC [4] NC A18 A17 A16 A15 OE DQ7 DQ6 VSS VCC DQ5 DQ4 30 29 28 27 26 25 24 23 VCAP A14 A13 A12 A11 A10 NC NC A0 A1 A2 A3 A4 CE DQ0 DQ1 DQ2 DQ3 VCC VSS DQ4 DQ5 DQ6 DQ7 WE A5 A6 A7 A8 A9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 - TSOP II (×16) Top View (not to scale) 30 29 28 27 26 25 24 23 BLE DQ15 DQ14 DQ13 DQ12 VSS VCC DQ11 DQ10 DQ9 DQ8 VCAP A14 A13 A12 A11 A10 Notes 4. Address expansion for 8 Mbit. NC pin not connected to die. 5. Address expansion for 16 Mbit. NC pin not connected to die. 6. HSB pin is not available in 44-TSOP II (×16) package. Document #: 001-49918 Rev. *H Page 3 of 24 [+] Feedback CY14B104LA, CY14B104NA Pinouts (continued) Figure 3. Pin Diagram - 54-Pin TSOP II (×16) NC [5] NC A0 A1 A2 A3 A4 CE DQ0 DQ1 DQ2 DQ3 VCC VSS DQ4 DQ5 DQ6 DQ7 WE A5 A6 A7 A8 A9 NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 54 - TSOP II (×16) Top View (not to scale) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 HSB NC [4] A17 A16 A15 OE BHE BLE DQ15 DQ14 DQ13 DQ12 VSS VCC DQ11 DQ10 DQ9 DQ8 VCAP A14 A13 A12 A11 A10 NC NC NC Table 1. Pin Definitions Pin Name A0 – A18 A0 – A17 DQ0 – DQ7 I/O Type Input Input/Output DQ0 – DQ15 WE Input CE OE Input Input BHE BLE VSS VCC HSB[7] Input Input Ground Power supply Input/Output VCAP Power supply NC No connect Description Address inputs. Used to select one of the 524,288 bytes of the nvSRAM for x8 Configuration. Address inputs. Used to Select one of the 262,144 words of the nvSRAM for x16 Configuration. Bidirectional data I/O lines for ×8 configuration. Used as input or output lines depending on operation. Bidirectional data I/O lines for ×16 configuration. Used as input or output lines depending on operation. Write Enable input, Active LOW. When selected LOW, data on the I/O pins is written to the specific address location. Chip Enable input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip. Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read cycles. I/O pins are tristated on deasserting OE HIGH. Byte High Enable, Active LOW. Controls DQ15 - DQ8. Byte Low Enable, Active LOW. Controls DQ7 - DQ0. Ground for the device. Must be connected to the ground of the system. Power supply inputs to the device. Hardware STORE Busy (HSB). When LOW this output indicates that a Hardware STORE is in progress. When pulled LOW external to the chip it initiates a nonvolatile STORE operation. After each Hardware and Software STORE operation, HSB is driven HIGH for a short time (tHHHD) with standard output high current, and then a weak internal pull-up resistor keeps this pin HIGH (external pull-up resistor connection optional). AutoStore Capacitor. Supplies power to the nvSRAM during power loss to store data from SRAM to nonvolatile elements. No Connect. This pin is not connected to the die. Note 7. HSB pin is not available in 44-TSOP II (×16) package. Document #: 001-49918 Rev. *H Page 4 of 24 [+] Feedback CY14B104LA, CY14B104NA The CY14B104LA/CY14B104NA nvSRAM is made up of two functional components paired in the same physical cell. They are a SRAM memory cell and a nonvolatile QuantumTrap cell. The SRAM memory cell operates as a standard fast static RAM. Data in the SRAM is transferred to the nonvolatile cell (the STORE operation), or from the nonvolatile cell to the SRAM (the RECALL operation). Using this unique architecture, all cells are stored and recalled in parallel. During the STORE and RECALL operations, SRAM read and write operations are inhibited. The CY14B104LA/CY14B104NA supports infinite reads and writes similar to a typical SRAM. In addition, it provides infinite RECALL operations from the nonvolatile cells and up to 1 million STORE operations. Refer to the Truth Table For SRAM Operations on page 17 for a complete description of read and write modes. SRAM Read The CY14B104LA/CY14B104NA performs a read cycle when CE and OE are LOW and WE and HSB are HIGH. The address specified on pins A0-18 or A0-17 determines which of the 524,288 data bytes or 262,144 words of 16 bits each are accessed. Byte enables (BHE, BLE) determine which bytes are enabled to the output, in the case of 16-bit words. When the read is initiated by an address transition, the outputs are valid after a delay of tAA (read cycle 1). If the read is initiated by CE or OE, the outputs are valid at tACE or at tDOE, whichever is later (read cycle 2). The data output repeatedly responds to address changes within the tAA access time without the need for transitions on any control input pins. This remains valid until another address change or until CE or OE is brought HIGH, or WE or HSB is brought LOW. SRAM Write A write cycle is performed when CE and WE are LOW and HSB is HIGH. The address inputs must be stable before entering the write cycle and must remain stable until CE or WE goes HIGH at the end of the cycle. The data on the common I/O pins DQ0–15 are written into the memory if the data is valid (tSD time) before the end of a WE controlled write or before the end of an CE controlled write. The Byte Enable inputs (BHE, BLE) determine which bytes are written, in the case of 16-bit words. It is recommended that OE be kept HIGH during the entire write cycle to avoid data bus contention on common I/O lines. If OE is left LOW, internal circuitry turns off the output buffers tHZWE after WE goes LOW. AutoStore Operation The CY14B104LA/CY14B104NA stores data to the nvSRAM using one of the following three storage operations: Hardware STORE activated by the HSB; Software STORE activated by an address sequence; AutoStore on device power-down. The AutoStore operation is a unique feature of QuantumTrap technology and is enabled by default on the CY14B104LA/CY14B104NA. During a normal operation, the device draws current from VCC to charge a capacitor connected to the VCAP pin. This stored charge is used by the chip to perform a single STORE operation. If the voltage on the VCC pin drops below VSWITCH, the part automatically disconnects the VCAP pin from VCC. A STORE operation is initiated with power provided by the VCAP capacitor. Note If the capacitor is not connected to VCAP pin, AutoStore must be disabled using the soft sequence specified in Preventing AutoStore on page 7. In case AutoStore is enabled without a capacitor on VCAP pin, the device attempts an AutoStore operation without sufficient charge to complete the Store. This corrupts the data stored in nvSRAM. Figure 4 shows the proper connection of the storage capacitor (VCAP) for automatic store operation. Refer to DC Electrical Characteristics on page 9 for the size of VCAP. The voltage on the VCAP pin is driven to VCC by a regulator on the chip. A pull-up should be placed on WE to hold it inactive during power-up. This pull-up is effective only if the WE signal is tristate during power-up. Many MPUs tristate their controls on power-up. This should be verified when using the pull-up. When the nvSRAM comes out of power-on-RECALL, the MPU must be active or the WE held inactive until the MPU comes out of reset. To reduce unnecessary nonvolatile stores, AutoStore and hardware STORE operations are ignored unless at least one write operation has taken place since the most recent STORE or RECALL cycle. Software initiated STORE cycles are performed regardless of whether a write operation has taken place. The HSB signal is monitored by the system to detect if an AutoStore cycle is in progress. Figure 4. AutoStore Mode VCC 0.1 uF 10 kOhm Device Operation VCC WE VCAP VSS VCAP Hardware STORE Operation The CY14B104LA/CY14B104NA provides the HSB[8] pin to control and acknowledge the STORE operations. The HSB pin is used to request a hardware STORE cycle. When the HSB pin is driven LOW, the CY14B104LA/CY14B104NA conditionally initiates a STORE operation after tDELAY. An actual STORE cycle only begins if a write to the SRAM has taken place since the last STORE or RECALL cycle. The HSB pin also acts as an open drain driver (internal 100 kΩ weak pull-up resistor) that is internally driven LOW to indicate a busy condition when the STORE (initiated by any means) is in progress. Note After each Hardware and Software STORE operation HSB is driven HIGH for a short time (tHHHD) with standard output high current and then remains HIGH by internal 100 kΩ pull-up resistor. Note 8. HSB pin is not available in 44-TSOP II (x16) package. Document #: 001-49918 Rev. *H Page 5 of 24 [+] Feedback CY14B104LA, CY14B104NA SRAM write operations that are in progress when HSB is driven LOW by any means are given time (tDELAY) to complete before the STORE operation is initiated. However, any SRAM write cycles requested after HSB goes LOW are inhibited until HSB returns HIGH. In case the write latch is not set, HSB is not driven LOW by the CY14B104LA/CY14B104NA. But any SRAM read and write cycles are inhibited until HSB is returned HIGH by MPU or other external source. During any STORE operation, regardless of how it is initiated, the CY14B104LA/CY14B104NA continues to drive the HSB pin LOW, releasing it only when the STORE is complete. Upon completion of the STORE operation, the nvSRAM memory access is inhibited for tLZHSB time after HSB pin returns HIGH. Leave the HSB unconnected if it is not used. 1. Read address 0x4E38 Valid READ 2. Read address 0xB1C7 Valid READ 3. Read address 0x83E0 Valid READ 4. Read address 0x7C1F Valid READ 5. Read address 0x703F Valid READ 6. Read address 0x8FC0 Initiate STORE cycle The software sequence may be clocked with CE controlled reads or OE controlled reads, with WE kept HIGH for all the six READ sequences. After the sixth address in the sequence is entered, the STORE cycle commences and the chip is disabled. HSB is driven LOW. After the tSTORE cycle time is fulfilled, the SRAM is activated again for the read and write operation. Software RECALL Hardware RECALL (Power-Up) During power-up or after any low power condition (VCC< VSWITCH), an internal RECALL request is latched. When VCC again exceeds the VSWITCH on powerup, a RECALL cycle is automatically initiated and takes tHRECALL to complete. During this time, the HSB pin is driven LOW by the HSB driver and all reads and writes to nvSRAM are inhibited. Software STORE Data is transferred from the SRAM to the nonvolatile memory by a software address sequence. The CY14B104LA/CY14B104NA software STORE cycle is initiated by executing sequential CE or OE controlled read cycles from six specific address locations in exact order. During the STORE cycle an erase of the previous nonvolatile data is first performed, followed by a program of the nonvolatile elements. After a STORE cycle is initiated, further input and output are disabled until the cycle is completed. Because a sequence of reads from specific addresses is used for STORE initiation, it is important that no other read or write accesses intervene in the sequence, or the sequence is aborted and no STORE or RECALL takes place. Data is transferred from the nonvolatile memory to the SRAM by a software address sequence. A software RECALL cycle is initiated with a sequence of read operations in a manner similar to the software STORE initiation. To initiate the RECALL cycle, perform the following sequence of CE or OE controlled read operations must be performed. 1. Read address 0x4E38 Valid READ 2. Read address 0xB1C7 Valid READ 3. Read address 0x83E0 Valid READ 4. Read address 0x7C1F Valid READ 5. Read address 0x703F Valid READ 6. Read address 0x4C63 Initiate RECALL cycle Internally, RECALL is a two step procedure. First, the SRAM data is cleared; then, the nonvolatile information is transferred into the SRAM cells. After the tRECALL cycle time, the SRAM is again ready for read and write operations. The RECALL operation does not alter the data in the nonvolatile elements. To initiate the software STORE cycle, the following read sequence must be performed. Table 2. Mode Selection CE WE OE BHE, BLE[9] A15 - A0[10] Mode I/O Power H X X X X Not selected Output high-Z Standby L H L L X Read SRAM Output data Active L L X L X Write SRAM Input data Active L H L X 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x8B45 Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM AutoStore Disable Output data Output data Output data Output data Output data Output data Active[11] Notes 9. BHE and BLE are applicable for x16 configuration only. 10. While there are 19 address lines on the CY14B104LA (18 address lines on the CY14B104NA), only 13 address lines (A14 - A2) are used to control software modes. The remaining address lines are don’t care. 11. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a nonvolatile cycle. Document #: 001-49918 Rev. *H Page 6 of 24 [+] Feedback CY14B104LA, CY14B104NA Table 2. Mode Selection (continued) CE WE OE BHE, BLE[9] A15 - A0[10] Mode I/O Power L H L X 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x4B46 Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM AutoStore Enable Output data Output data Output data Output data Output data Output data Active[11] L H L X 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x8FC0 Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile STORE Output data Output data Output data Output data Output data Output high-Z Active ICC2[11] L H L X 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x4C63 Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile RECALL Output data Output data Output data Output data Output data Output high-Z Active[11] Preventing AutoStore Data Protection The AutoStore function is disabled by initiating an AutoStore disable sequence. A sequence of read operations is performed in a manner similar to the software STORE initiation. To initiate the AutoStore disable sequence, the following sequence of CE or OE controlled read operations must be performed: 1. Read address 0x4E38 Valid READ 2. Read address 0xB1C7 Valid READ 3. Read address 0x83E0 Valid READ 4. Read address 0x7C1F Valid READ 5. Read address 0x703F Valid READ 6. Read address 0x8B45 AutoStore Disable The CY14B104LA/CY14B104NA protects data from corruption during low voltage conditions by inhibiting all externally initiated STORE and write operations. The low voltage condition is detected when VCC < VSWITCH. If the CY14B104LA/CY14B104NA is in a write mode (both CE and WE are LOW) at power-up, after a RECALL or STORE, the write is inhibited until the SRAM is enabled after tLZHSB (HSB to output active). This protects against inadvertent writes during power-up or brown out conditions. Noise Considerations Refer to CY application note AN1064. The AutoStore is re-enabled by initiating an AutoStore enable sequence. A sequence of read operations is performed in a manner similar to the software RECALL initiation. To initiate the AutoStore enable sequence, the following sequence of CE or OE controlled read operations must be performed: 1. Read address 0x4E38 Valid READ 2. Read address 0xB1C7 Valid READ 3. Read address 0x83E0 Valid READ 4. Read address 0x7C1F Valid READ 5. Read address 0x703F Valid READ 6. Read address 0x4B46 AutoStore Enable If the AutoStore function is disabled or re-enabled, a manual STORE operation (hardware or software) must be issued to save the AutoStore state through subsequent power-down cycles. The part comes from the factory with AutoStore enabled. Document #: 001-49918 Rev. *H Page 7 of 24 [+] Feedback CY14B104LA, CY14B104NA Best Practices ■ power-up boot firmware routines should rewrite the nvSRAM into the desired state (for example, AutoStore enabled). While the nvSRAM is shipped in a preset state, best practice is to again rewrite the nvSRAM into the desired state as a safeguard against events that might flip the bit inadvertently such as program bugs and incoming inspection routines. ■ The VCAP value specified in this datasheet includes a minimum and a maximum value size. Best practice is to meet this requirement and not exceed the maximum VCAPvalue because the nvSRAM internal algorithm calculates VCAP charge and discharge time based on this maximum VCAP value. Customers that want to use a larger VCAP value to make sure there is extra store charge and store time should discuss their VCAP size selection with Cypress to understand any impact on the VCAP voltage level at the end of a tRECALL period. nvSRAM products have been used effectively for over 27 years. While ease-of-use is one of the product’s main system values, experience gained working with hundreds of applications has resulted in the following suggestions as best practices: ■ The nonvolatile cells in this nvSRAM product are delivered from Cypress with 0x00 written in all cells. Incoming inspection routines at customer or contract manufacturer’s sites sometimes reprogram these values. Final NV patterns are typically repeating patterns of AA, 55, 00, FF, A5, or 5A. End product’s firmware should not assume an NV array is in a set programmed state. Routines that check memory content values to determine first time system configuration, cold or warm boot status, and so on should always program a unique NV pattern (that is, complex 4-byte pattern of 46 E6 49 53 hex or more random bytes) as part of the final system manufacturing test to ensure these system routines work consistently. Document #: 001-49918 Rev. *H Page 8 of 24 [+] Feedback CY14B104LA, CY14B104NA Maximum Ratings Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Transient voltage (<20 ns) on any pin to ground potential .................. –2.0 V to VCC + 2.0 V Storage temperature ................................ –65 °C to +150 °C Package power dissipation capability (TA = 25 °C) ................................................. .1.0 W Maximum accumulated storage time At 150 °C ambient temperature..........................1000 h At 85 °C ambient temperature.................... .. 20 Years Ambient temperature with power applied ........................................... –55 °C to +150 °C Supply voltage on VCC relative to VSS ............–0.5 V to 4.1 V Voltage applied to outputs in high-Z state...................................... –0.5 V to VCC + 0.5 V Input voltage .........................................–0.5 V to Vcc + 0.5 V Surface mount Pb soldering temperature (3 Seconds).......................................... +260 °C DC output current (1 output at a time, 1s duration) ..... 15 mA Static discharge voltage.......................................... > 2001 V (per MIL-STD-883, Method 3015) Latch up current..................................................... > 200 mA Operating Range Range Industrial Ambient Temperature VCC –40 °C to +85 °C 2.7 V to 3.6 V DC Electrical Characteristics Over the Operating Range (VCC = 2.7 V to 3.6 V) Parameter Description Test Conditions Min VCC Power supply 2.7 ICC1 Average VCC current tRC = 20 ns – tRC = 25 ns tRC = 45 ns Values obtained without output loads (IOUT = 0 mA) ICC2 Average VCC current All inputs don’t care, VCC = Max – during STORE Average current for duration tSTORE ICC3 – Average VCC current All inputs cycling at CMOS levels. at tRC= 200 ns, Values obtained without output loads (IOUT = 0 mA). VCC (Typ), 25 °C All inputs don’t care. Average current for duration tSTORE ICC4 Average VCAP – current during AutoStore cycle VCC standby current CE > (VCC – 0.2 V). VIN < 0.2 V or > (VCC – 0.2 V). – ISB Standby current level after nonvolatile cycle is complete. Inputs are static. f = 0 MHz. Input leakage current VCC = Max, VSS < VIN < VCC –1 IIX[13] (except HSB) Input leakage current VCC = Max, VSS < VIN < VCC –100 (for HSB) IOZ Off-state output VCC = Max, VSS < VOUT < VCC, CE or OE > VIH or BHE/BLE –1 leakage current > VIH or WE < VIL VIH Input HIGH voltage 2.0 VIL Input LOW voltage Vss – 0.5 Output HIGH voltage IOUT = –2 mA 2.4 VOH Output LOW voltage IOUT = 4 mA – VOL VCAP Storage capacitor Between VCAP pin and VSS, 5 V rated 61 Typ[12] 3.0 – Max 3.6 70 70 52 Unit V mA mA mA – 10 mA 35 – mA – 5 mA – 5 mA – +1 μA – +1 μA – +1 μA – – – – 68 VCC + 0.5 0.8 – 0.4 180 V V V V μF Notes 12. Typical values are at 25°C, VCC= VCC (Typ). Not 100% tested. 13. The HSB pin has IOUT = -2 uA for VOH of 2.4 V when both active HIGH and LOW drivers are disabled. When they are enabled standard VOH and VOL are valid. This parameter is characterized but not tested. Document #: 001-49918 Rev. *H Page 9 of 24 [+] Feedback CY14B104LA, CY14B104NA Data Retention and Endurance Parameter Description DATAR Data retention NVC Nonvolatile STORE operations Min Unit 20 Years 1,000 K Capacitance In the following table, the capacitance parameters are listed.[14] Parameter CIN Description Test Conditions Max Unit 7 pF 8 pF Output capacitance (except HSB) 7 pF Output capacitance (for HSB) 8 pF TA = 25 °C, f = 1 MHz, VCC = VCC (Typ) Input capacitance (except BHE, BLE and HSB) Input capacitance (for BHE, BLE and HSB) COUT Thermal Resistance In the following table, the thermal resistance parameters are listed. [14] Parameter Description ΘJA Thermal resistance (Junction to ambient) ΘJC Thermal resistance (Junction to case) Test Conditions 48-FBGA 44-TSOP II 54-TSOP II Unit Test conditions follow standard test methods and procedures for measuring thermal impedance, in accordance with EIA/JESD51. 28.82 31.11 30.73 °C/W 7.84 5.56 6.08 °C/W Figure 5. AC Test Loads 577 Ω 3.0 V 577 Ω 3.0 V R1 for tristate specs R1 OUTPUT OUTPUT 30 pF R2 789 Ω 5 pF R2 789 Ω AC Test Conditions Input pulse levels.................................................... 0 V to 3 V Input rise and fall times (10% - 90%) ........................... <3 ns Input and output timing reference levels ....................... 1.5 V Note 14. These parameters are guaranteed by design but not tested. Document #: 001-49918 Rev. *H Page 10 of 24 [+] Feedback CY14B104LA, CY14B104NA AC Switching Characteristics Parameters Cypress Alt Parameter Parameter SRAM Read Cycle tACE tACS tRC[15] tAA[16] tDOE tOHA[16] tLZCE[17, 18] tHZCE[17, 18] tLZOE[17, 18] tHZOE[17, 18] tRC tAA tOE tOH tLZ tHZ tOLZ tOHZ tPU[17] tPA [17] tPD tPS tDBE [17] tLZBE tHZBE[17] SRAM Write Cycle tWC tWC tPWE tWP tSCE tCW tSD tDW tHD tDH tAW tAW tSA tAS tHA tWR [17, 18,19] tHZWE tWZ tOW tLZWE[17, 18] tBW - Switching Waveforms 20 ns Description 25 ns 45 ns Unit Min Max Min Max Min Max Chip enable access time Read cycle time Address access time Output enable to data valid Output hold after address change Chip enable to output active Chip disable to output inactive Output enable to output active – 20 – – 3 3 – 0 20 – 20 10 – – 8 – – 25 – – 3 3 – 0 25 – 25 12 – – 10 – – 45 – – 3 3 – 0 45 – 45 20 – – 15 – ns ns ns ns ns ns ns ns Output disable to output inactive Chip enable to power active Chip disable to power standby Byte enable to data valid Byte enable to output active Byte disable to output inactive – 0 – – 0 – 8 – 20 10 – 8 – 0 – – 0 – 10 – 25 12 – 10 – 0 – – 0 – 15 – 45 20 – 15 ns ns ns ns ns ns Write cycle time Write pulse width Chip enable to end of write Data setup to end of write Data hold after end of write Address setup to end of write Address setup to start of write Address hold after end of write Write enable to output disable Output active after end of write Byte enable to end of write 20 15 15 8 0 15 0 0 – 3 15 – – – – – – – – 8 – – 25 20 20 10 0 20 0 0 – 3 20 – – – – – – – – 10 – – 45 30 30 15 0 30 0 0 – 3 30 – – – – – – – – 15 – – ns ns ns ns ns ns ns ns ns ns ns Figure 6. SRAM Read Cycle #1: Address Controlled[15, 16, 20] tRC Address Address Valid tAA Data Output Previous Data Valid Output Data Valid tOHA Notes 15. WE must be HIGH during SRAM read cycles. 16. Device is continuously selected with CE, OE and BHE / BLE LOW. 17. These parameters are guaranteed by design but not tested. 18. Measured ±200 mV from steady state output voltage. 19. If WE is LOW when CE goes LOW, the outputs remain in the high impedance state. 20. HSB must remain HIGH during read and write cycles. Document #: 001-49918 Rev. *H Page 11 of 24 [+] Feedback CY14B104LA, CY14B104NA Figure 7. SRAM Read Cycle #2: CE and OE Controlled[21, 22, 23] Address Address Valid tRC tHZCE tACE CE tAA tLZCE tHZOE tDOE OE tHZBE tLZOE tDBE BHE, BLE tLZBE Data Output ICC High Impedance Output Data Valid tPU tPD Active Standby Figure 8. SRAM Write Cycle #1: WE Controlled[21, 23, 24, 25] tWC Address Address Valid tSCE tHA CE tBW BHE, BLE tAW tPWE WE tSA tSD Data Input Input Data Valid tHZWE Data Output tHD Previous Data tLZWE High Impedance Notes 21. BHE and BLE are applicable for ×16 configuration only. 22. WE must be HIGH during SRAM read cycles. 23. HSB must remain HIGH during read and write cycles. 24. If WE is LOW when CE goes LOW, the outputs remain in the high impedance state. 25. CE or WE must be >VIH during address transitions. Document #: 001-49918 Rev. *H Page 12 of 24 [+] Feedback CY14B104LA, CY14B104NA Figure 9. SRAM Write Cycle #2: CE Controlled[26, 27, 28, 29] tWC Address Valid Address tSA tSCE tHA CE tBW BHE, BLE tPWE WE tHD tSD Input Data Valid Data Input High Impedance Data Output Figure 10. SRAM Write Cycle #3: BHE and BLE Controlled[26, 27, 28, 29] tWC Address Address Valid tSCE CE tSA tHA tBW BHE, BLE tAW tPWE WE tSD Data Input tHD Input Data Valid High Impedance Data Output Notes 26. BHE and BLE are applicable for ×16 configuration only. 27. If WE is LOW when CE goes LOW, the outputs remain in the high impedance state. 28. HSB must remain HIGH during read and write cycles. 29. CE or WE must be >VIH during address transitions. Document #: 001-49918 Rev. *H Page 13 of 24 [+] Feedback CY14B104LA, CY14B104NA AutoStore/Power-Up RECALL Parameter tHRECALL [30] tSTORE [31] tDELAY [32] VSWITCH tVCCRISE[14] VHDIS[14] tLZHSB[14] tHHHD[14] 20 ns Description Min – – – – 150 – – – Power-Up RECALL duration STORE cycle duration Time allowed to complete SRAM write cycle Low voltage trigger level VCC rise time HSB output disable voltage HSB to output active time HSB high active time Switching Waveforms 25 ns Max 20 8 20 2.65 – 1.9 5 500 Min – – – – 150 – – – 45 ns Max 20 8 25 2.65 – 1.9 5 500 Min – – – – 150 – – – Max 20 8 25 2.65 – 1.9 5 500 Unit ms ms ns V μs V μs ns Figure 11. AutoStore or Power-Up RECALL[33] VCC VSWITCH VHDIS t VCCRISE tHHHD Note 31 Note31 tSTORE tHHHD 34 Note HSB OUT tSTORE Note 34 tDELAY tLZHSB AutoStore tLZHSB tDELAY POWERUP RECALL Read & Write Inhibited (RWI) tHRECALL POWER-UP RECALL Read & Write tHRECALL BROWN OUT AutoStore POWER-UP RECALL Read & Write POWER DOWN AutoStore Notes 30. tHRECALL starts from the time VCC rises above VSWITCH. 31. If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware STORE takes place. 32. On a Hardware STORE and AutoStore initiation, SRAM write operation continues to be enabled for time tDELAY. 33. Read and write cycles are ignored during STORE, RECALL, and while VCC is below VSWITCH. 34. During power-up and power-down, HSB glitches when HSB pin is pulled up through an external resistor. Document #: 001-49918 Rev. *H Page 14 of 24 [+] Feedback CY14B104LA, CY14B104NA Software Controlled STORE/RECALL Cycle In the following table, the software controlled STORE and RECALL cycle parameters are listed.[35, 36] Parameter tRC tSA tCW tHA tRECALL 20 ns Min Max 20 – 0 – 15 – 0 – – 200 Description STORE/RECALL initiation cycle time Address setup time Clock pulse width Address hold time RECALL duration 25 ns Min Max 25 – 0 – 20 – 0 – – 200 45 ns Min Max 45 – 0 – 30 – 0 – – 200 Unit ns ns ns ns μs Switching Waveforms Figure 12. CE and OE Controlled Software STORE/RECALL Cycle[36] tRC Address tRC Address #1 tSA Address #6 tCW tCW CE tHA tSA tHA tHA tHA OE tHHHD HSB (STORE only) tHZCE tLZCE t DELAY 37 Note tLZHSB High Impedance tSTORE/tRECALL DQ (DATA) RWI Figure 13. AutoStore Enable/Disable Cycle Address tSA CE tRC tRC Address #1 Address #6 tCW tCW tHA tSA tHA tHA tHA OE tLZCE tHZCE tSS 37 Note t DELAY DQ (DATA) Notes 35. The software sequence is clocked with CE controlled or OE controlled reads. 36. The six consecutive addresses must be read in the order listed in Table 2 on page 6. WE must be HIGH during all six consecutive cycles. 37. DQ output data at the sixth read may be invalid since the output is disabled at tDELAY time. Document #: 001-49918 Rev. *H Page 15 of 24 [+] Feedback CY14B104LA, CY14B104NA Hardware STORE Cycle Parameter 20 ns Description 25 ns 45 ns Min Max Min Max Min Max 20 – 25 – 25 Unit tDHSB HSB to output active time when write latch not set – tPHSB Hardware STORE pulse width 15 – 15 – 15 – ns tSS [38, 39] Soft sequence processing time – 100 – 100 – 100 μs Switching Waveforms ns Figure 14. Hardware STORE Cycle[40] Write latch set tPHSB HSB (IN) tSTORE tHHHD tDELAY HSB (OUT) tLZHSB DQ (Data Out) RWI Write latch not set tPHSB HSB pin is driven high to VCC only by Internal 100 kOhm resistor, HSB driver is disabled SRAM is disabled as long as HSB (IN) is driven low. HSB (IN) HSB (OUT) tDELAY tDHSB tDHSB RWI Figure 15. Soft Sequence Processing[38, 39] Soft Sequence Command Address Address #1 tSA Address #6 tCW tSS Soft Sequence Command Address #1 tSS Address #6 tCW CE VCC Notes 38. This is the amount of time it takes to take action on a soft sequence command. Vcc power must remain HIGH to effectively register command. 39. Commands such as STORE and RECALL lock out I/O until operation is complete which further increases this time. See the specific command. 40. If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware STORE takes place. Document #: 001-49918 Rev. *H Page 16 of 24 [+] Feedback CY14B104LA, CY14B104NA Truth Table For SRAM Operations HSB should remain HIGH for SRAM Operations. For x8 Configuration Inputs/Outputs[41] CE WE OE H X X High-Z Deselect/Power-down Mode Standby Power L H L Data out (DQ0–DQ7); Read Active L H H High-Z Output disabled Active L L X Data in (DQ0–DQ7); Write Active For x16 Configuration BHE[42] BLE[42] Inputs/Outputs[41] CE WE OE Mode Power H X X X X High-Z Deselect/Power-down Standby L X X H H High-Z Output disabled Active L H L L L Data out (DQ0–DQ15) Read Active L H L H L Data out (DQ0–DQ7); DQ8–DQ15 in High Z Read Active L H L L H Data out (DQ8–DQ15); DQ0–DQ7 in High Z Read Active L H H L L High-Z Output disabled Active L H H H L High-Z Output disabled Active L H H L H High-Z Output disabled Active L L X L L Data in (DQ0–DQ15) Write Active L L X H L Data in (DQ0–DQ7); DQ8–DQ15 in High Z Write Active L L X L H Data in (DQ8–DQ15); DQ0–DQ7 in High Z Write Active Notes 41. Data DQ0 - DQ7 for ×8 configuration and Data DQ0 - DQ15 for ×16 configuration. 42. BHE and BLE are applicable for ×16 configuration only. Document #: 001-49918 Rev. *H Page 17 of 24 [+] Feedback CY14B104LA, CY14B104NA Ordering Information Speed (ns) 20 25 45 Ordering Code Package Diagram Package Type CY14B104LA-ZS20XIT 51-85087 44-pin TSOP II CY14B104LA-ZS20XI 51-85087 44-pin TSOP II CY14B104NA-ZS20XIT 51-85087 44-pin TSOP II CY14B104NA-ZS20XI 51-85087 44-pin TSOP II CY14B104NA-BA20XIT 51-85128 48-ball FBGA CY14B104NA-BA20XI 51-85128 48-ball FBGA CY14B104LA-ZS25XIT 51-85087 44-pin TSOP II CY14B104LA-ZS25XI 51-85087 44-pin TSOP II CY14B104LA-BA25XIT 51-85128 48-ball FBGA CY14B104LA-BA25XI 51-85128 48-ball FBGA CY14B104NA-ZS25XIT 51-85087 44-pin TSOP II CY14B104NA-ZS25XI 51-85087 44-pin TSOP II CY14B104NA-BA25XIT 51-85128 48-ball FBGA CY14B104NA-BA25XI 51-85128 48-ball FBGA CY14B104NA-BA25I 51-85128 48-ball FBGA CY14B104NA-ZSP25XIT 51-85160 54-pin TSOP II CY14B104NA-ZSP25XI 51-85160 54-pin TSOP II CY14B104LA-ZS45XIT 51-85087 44-pin TSOP II CY14B104LA-ZS45XI 51-85087 44-pin TSOP II CY14B104LA-BA45XIT 51-85128 48-ball FBGA CY14B104LA-BA45XI 51-85128 48-ball FBGA CY14B104NA-ZS45XIT 51-85087 44-pin TSOP II CY14B104NA-ZS45XI 51-85087 44-pin TSOP II CY14B104NA-BA45XIT 51-85128 48-ball FBGA CY14B104NA-BA45XI 51-85128 48-ball FBGA CY14B104NA-ZSP45XIT 51-85160 54-pin TSOP II CY14B104NA-ZSP45XI 51-85160 54-pin TSOP II Document #: 001-49918 Rev. *H Operating Range Industrial Page 18 of 24 [+] Feedback CY14B104LA, CY14B104NA Ordering Code Definition CY 14 B 104 L A -ZS 20 X I T Option: T - Tape & Reel Blank - Std. X - Pb-free Blank - Sn Pb Die Revision: Blank - No Rev A - 1st Rev Voltage: B - 3.0 V Temperature: I - Industrial (–40 to 85 °C) Package: BAP - 48 FBGA ZSP - 44 TSOP II ZSP - 54 TSOP II Data Bus: L - x8 N - x16 Speed: 20 - 20 ns 25 - 25 ns 45 - 45 ns Density: 104 - 4 Mb 14 - nvSRAM Cypress Document #: 001-49918 Rev. *H Page 19 of 24 [+] Feedback CY14B104LA, CY14B104NA Package Diagrams Figure 16. 44-Pin TSOP II (51-85087) 51-85087 *C Document #: 001-49918 Rev. *H Page 20 of 24 [+] Feedback CY14B104LA, CY14B104NA Package Diagrams (continued) Figure 17. 48-Ball FBGA - 6 mm x 10 mm x 1.2 mm 51-85128 *E 51-85128 *E Document #: 001-49918 Rev. *H Page 21 of 24 [+] Feedback CY14B104LA, CY14B104NA Package Diagrams (continued) Figure 18. 54-Pin TSOP II (51-85160) 51-85160 *A Document Conventions Acronyms Description Units of Measure nvSRAM nonvolatile static random access memory Symbol TSOP II thin small outline package °C degrees celsius FBGA fine-pitch ball grid array Hz hertz RoHS restriction of hazardous substances kbit 1024 bits I/O input/output kHz kilohertz CMOS complementary metal oxide semiconductor KΩ kilo ohms EIA electronic industries alliance μA microamperes RWI read and write inhibited mA milliampere μF microfarads MHz megahertz μs microseconds ms millisecond ns nanoseconds pF picofarads V volts Ω ohms W watts Acronym Document #: 001-49918 Rev. *H Unit of Measure Page 22 of 24 [+] Feedback CY14B104LA, CY14B104NA Document History Page Document Title: CY14B104LA, CY14B104NA 4-Mbit (512 K × 8/256 K × 16) nvSRAM Document Number: 001-49918 Rev. ECN No. Orig. of Change Submission Date ** 2606696 GVCH/PYRS 11/13/08 New Datasheet *A 2672700 GVCH/PYRS 03/12/09 Added best practices Added CY14B104NA-BA25I part number Added footnote12 for HZ/LZ parameters *B 2710274 GVCH/AESA 05/22/09 Moved datasheet status from Preliminary to Final Updated AutoStore operation Updated ISB test condition Updated footnote 9 Referenced footnote 12 to VCCRISE, tHHHD and tLZHSB parameters Updated VHDIS parameter description Updated figure 12 *C 2738586 GVCH 07/15/09 Page 4: Updated Hardware STORE Operation description Page 5: Updated Software STORE description Updated tDELAY parameter description Updated footnote 20 Added footnote 25 referenced footnote 25 to figure 12 and figure 13 *D 2758397 GVCH/AESA 09/01/09 Removed commercial temperature related specifications Description of Change *E 2773362 GVCH 10/06/09 Ordering Information: Added 20 ns part in a 48-FBGA package *F 2826364 GVCH/PYRS 12/11/09 Changed STORE cycles to QuantumTrap from 200K to 1 Million *G 2923475 GVCH/AESA 04/27/2010 Table 1: Added more clarity on HSB pin operation Hardware STORE Operation: Added more clarity on HSB pin operation Table 2: Added more clarity on BHE/BLE pin opeartion Updated HSB pin operation in Figure 11 Updated footnote 22 Updated Package Diagrams and Sales, Solutions, and Legal Information. *H 3132368 GVCH 01/10/2011 48-ball FBGA package: 16 Mb address expansion is not supported Updated input capacitance for BHE and BLE pin Updated input and output capacitance for HSB pin Fixed typo in Figure 11 Added Acronyms table and Document Conventions table. Document #: 001-49918 Rev. *H Page 23 of 24 [+] Feedback CY14B104LA, CY14B104NA Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control PSoC Solutions cypress.com/go/automotive psoc.cypress.com/solutions cypress.com/go/clocks PSoC 1 | PSoC 3 | PSoC 5 cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2008-2011. The information contained herein is subject to change without notice. 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Document #: 001-49918 Rev. *H Revised January 18, 2011 Page 24 of 24 All products and company names mentioned in this document are the trademarks of their respective holders. [+] Feedback