[AKD4671-B] AKD4671-B Evaluation board Rev.0 for AK4671 GENERAL DESCRIPTION AKD4671 is an evaluation board for the AK4671, stereo CODEC with built-in Microphone-Amplifier, Receiver-Amplifier and Headphone-Amplifier. The AKD4671 can evaluate A/D converter and D/A converter separately in addition to loopback mode (A/D → D/A). The AKD4671-B also has the digital audio interface and can achieve the interface with digital audio systems via opt-connector. Ordering guide AKD4671 --- Evaluation board for AK4671 (Cable for connecting with printer port of IBM-AT,compatible PC and control software are packed with this. This control software does not support Windows NT.) FUNCTION • DIT/DIR with optical input/output • 10pin Header for Digital Audio I/F, PCM I/F (Baseband, Bluetooth) • BNC connector for an external clock input • 10pin Header for serial control mode REG TVDD3 TVDD2 DVDD PVDD SAVDD AVDD 3.3 V Opt Out TX Opt In RX REG AK4114 DIR DIT MIC Jack Digital Audio I/F 10Pin Header Control I/F 10Pin Header LIN1/RIN1 LIN2/3/4 RIN2/3/4 AK4671 SAIN1/2/3 SAIN3 LOUT1/2/3 Control I/F SAR ADC 10Pin Header Baseband I/F 10Pin Header ROUT1/2/3 VSS2 VSS1 HP Jack VSS4 VSS3 4212 HP Bluetooth I/F 10Pin Header GND AK4212 SPK_L Jack SPK_R Jack Figure 1. AKD4671-B Block Diagram * Circuit diagram and PCB layout are attached at the end of this manual <KM089000> 2007 / 05 -1- [AKD4671-B] Evaluation Board Manual Operation sequence 1) Set up the power supply lines. (1-1) In case of using the regulator. Set up the jumper pins. JP JP18 SVDD SEL JP20 AVDD SEL JP22 SAVDD SEL JP24 PVDD SEL JP26 DVDD SEL JP27 TVDD2 SEL JP29 TVDD3 SEL JP31 VCC SEL JP7 VCC2 SEL State Short Short Short Short Short Short Short Short Short Set up the power supply lines. [REG] (red) [D3V] (orange) [AGND] (black) [DGND] (black) = 5.0V = 2.7 ∼ 3.6V = 0V = 0V : for regulator (3.3V output : AK4671 , Logic) : for AK4114 and logic (typ. 3.3V) : for analog ground : for logic ground (1-2) In case of using the power supply connectors. Set up the jumper pins. JP JP18 SVDD SEL JP20 AVDD SEL JP22 SAVDD SEL JP24 PVDD SEL JP26 DVDD SEL JP27 TVDD2 SEL JP29 TVDD3 SEL JP31 VCC SEL JP7 VCC2 SEL State Open Open Open Open Open Open Open Open Open Set up the power supply lines. [SVDD] (orange) [AVDD] (orange) [SAVDD] (orange) [PVDD] (orange) [DVDD] (orange) [TVDD2] (orange) [TVDD3] (orange) [VCC] (orange) [VCC2] (orange) [D3V] (orange) [AGND] (black) [DGND] (black) = 3.0 ~ 5.5V = 2.2 ~ 3.6V = 2.2 ~ 3.6V = 2.2 ∼ 3.6V = 1.6 ∼ 3.6V = 1.6 ∼ 3.6V = 1.6 ∼ 3.6V = 1.6 ∼ 3.6V = 1.6 ∼ 3.6V = 2.7 ∼ 3.6V = 0V = 0V : for SVDD of AK4212 (typ. 3.6V) : for AVDD of AK4671 (typ. 3.3V) : for SAVDD of AK4671 (typ. 3.3V) : for PVDD of AK4671 (typ. 3.3V) : for DVDD of AK4671 (typ. 3.3V) : for TVDD2 of AK4671 (typ. 3.3V) : for TVDD3 of AK4671 (typ. 3.3V) : for logic (typ. 3.3V : the voltage same as DVDD) : for logic (typ. 3.3V : the voltage same as TVDD2 and TVDD3) : for AK4114 and logic (typ. 3.3V) : for analog ground : for logic ground * Each supply line should be distributed from the power supply unit. 2) Set up the evaluation mode, jumper pins and DIP switches. (See the followings.) 3) Power on. The AK4671 and AK4114 should be reset once bringing SW1 (DIR) and SW2 (PDN) “L” upon power-up. <KM089000> 2007 / 05 -2- [AKD4671-B] Evaluation mode 1. Audio I/F evaluation mode In case of AK4671 evaluation using AK4114, it is necessary to correspond to audio interface format for AK4671 and AK4114. About AK4671’s audio interface format, refer to datasheet of AK4671. About AK4114’s audio interface format, refer to Table 2 on page 19. The AK4114 operates at fs of 32kHz or more. If the fs is slower than 32kHz, please use other mode. In addition, MCLK of AK4114 supports 256fs and 512fs. When evaluate it in a condition except this, please use other modes (1) External Slave Mode (1-1) Evaluation of A/D using DIT of AK4114 (1-2) Evaluation of D/A using DIR of AK4114 (1-3) Evaluation of Loop-back using AK4114 <default> (1-4) Evaluation of Loop-back that master clock is fed externally, BICK and LRCK are divided with a board (1-5) All interface signals including master clock are fed externally (2) External Master Mode (2-1) Evaluation of A/D using DIT of AK4114 (2-2) Evaluation of D/A using DIR of AK4114 (2-3) Evaluation of Loop-back using AK4114 (2-4) All interface signals including master clock are fed externally (3) PLL Slave Mode (3-1) PLL Reference Clock : MCKI pin (3-1-1) Evaluation of A/D using DIT of AK4114 (3-1-2) Evaluation of Loop-back using AK4114 (3-1-3) All interface signals including master clock are fed externally (3-2) PLL Reference Clock : BICK or LRCK pin (3-2-1) Evaluation of A/D using DIT of AK4114 (3-2-2) Evaluation of D/A using DIR of AK4114 (3-2-3) Evaluation of Loop-back using AK4114 (3-2-4) All interface signals including master clock are fed externally (4) PLL Master Mode (4-1) Evaluation of A/D using DIT of AK4114 (4-2) Evaluation of Loop-back (4-3) All interface signals including master clock are fed externally <KM089000> 2007 / 05 -3- [AKD4671-B] (1) External Slave Mode When PMPLL bit is “0”, the AK4671 becomes EXT mode. Master clock is input from MCKI pin, the internal PLL circuit is not operated. This mode is compatible with I/F of the normal audio CODEC. The clocks required to operate are MCKI (256fs, 384fs, 512fs, 768fs or 1024fs), LRCK (fs) and BICK (≥32fs). The master clock (MCKI) should be synchronized with LRCK. The phase between these clocks does not matter. The input frequency of MCKI is selected by FS1-0 bits. AK4671 DSP or μP MCKO MCKI 256fs, 384fs, 512fs, 768fs or 1024fs ≥ 32fs BICK BCLK 1fs LRCK MCLK LRCK SDTO SDTI SDTI SDTO (1-1) Evaluation of A/D using DIT of AK4114 X2 (X’tal) and PORT2 (DIT) are used. Nothing should be connected to PORT1 (DIR) and PORT4 (DSP). The jumper pins should be set as the following. JP36 MCLK JP33 BICK_SEL JP38 LRCK_SEL DIR DIR JP35 PHASE JP46 4114_MCKI JP48 M/S DIR EXT 4040 4040 THR Master INV Slave (1-2) Evaluation of D/A using DIR of AK4114 PORT1 (DIR) is used. Nothing should be connected to PORT2 (DIT) and PORT4 (DSP). The jumper pins should be set as the following. JP36 MCLK JP33 BICK_SEL JP38 LRCK_SEL JP51 SDTI_SEL JP35 PHASE JP48 M/S DIR EXT DIR 4040 DIR 4040 DIR <KM089000> ADC THR INV Master Slave 2007 / 05 -4- [AKD4671-B] (1-3) Evaluation of Loop-back using AK4114 <default> X2 (X’tal) is used. Nothing should be connected to PORT1 (DIR), PORT2 (DIT) and PORT4 (DSP). The jumper pins should be set as the following. JP33 BICK_SEL JP36 MCLK JP38 LRCK_SEL JP51 SDTI_SEL JP48 M/S JP46 4114_MCKI JP35 PHASE DIR EXT DIR 4040 DIR 4040 DIR ADC THR Master INV Slave (1-4) Evaluation of Loop-back where master clock is fed externally, BICK and LRCK are generated by on-board divider. J12 (EXT) is used . MCLK is supplied from J12 (EXT). BICK and LRCK are generated by 74HC4040 on AKD4671-B. Nothing should be connected to PORT1 (DIR), PORT2 (DIT) and PORT4 (DSP). The jumper pins should be set as the following. JP36 MCLK JP39 EXT JP33 BICK_SEL JP38 LRCK_SEL JP51 SDTI_SEL JP48 M/S DIR EXT DIR 4040 DIR 4040 DIR ADC Master Slave When a termination (51Ω) is unnecessary, please set JP39 (EXT) open. JP32 (MKFS), JP34 (BCFS), and JP37 (LRCK) should be set according to the frequency of MCLK, BICK and LRCK. Follows are setting examples in MCLK=256fs , BICK=64fs and LRCK=1fs. When MCLK=384fs or 768fs, JP32, JP34, and JP37 should be set to “384” side. . JP34 BCFS JP32 MKFS 64fs-384 32fs-384 64fs 32fs 256fs 512fs 1024fs 384/768fs JP37 LRCK fs-384 fs MCKO (1-5) All interface signals including master clock are fed externally PORT4 (DSP) is used. Nothing should be connected to PORT1 (DIR) and PORT2 (DIT). The jumper pins should be set as the following. JP36 MCLK JP33 BICK_SEL JP38 LRCK_SEL JP51 SDTI_SEL JP48 M/S DIR EXT DIR 4040 DIR 4040 DIR <KM089000> ADC Maste Slave 2007 / 05 -5- [AKD4671-B] (2) External Master Mode The AK4671 becomes EXT Master Mode by setting PMPLL bit = “0” and M/S bit = “1”. Master clock can be input via MCKI pin, without using on-chip PLL circuit. The clock required to operate is MCKI (256fs, 384fs, 512fs, 768fs or 1024fs). The input frequency of MCKI is selected by FS1-0 bits. AK4671 DSP or μP MCKO MCKI 256fs, 384fs, 512fs, 768fs or 1024fs 32fs or 64fs BICK BCLK 1fs LRCK MCLK LRCK SDTO SDTI SDTI SDTO (2-1) Evaluation of A/D using DIT of AK4114 X2 (X’tal) and PORT2 (DIT) are used. Nothing should be connected to PORT1 (DIR) and PORT4 (DSP). In Master Mode, BICK and LRCK of AK4671 should be input to AK4114. Please refer to Table 2 on page 19. The jumper pins should be set as the following. JP36 MCLK JP33 BICK_SEL JP38 LRCK_SEL DIR DIR JP35 PHASE JP46 4114_MCKI JP48 M/S DIR EXT 4040 4040 THR Master INV Slave (2-2) Evaluation of D/A using DIR of AK4114 PORT1 (DIR) is used. Nothing should be connected to PORT2 (DIT) and PORT4 (DSP). In Master Mode, BICK and LRCK of AK4671 should be input to AK4114. Please refer to Table 2 on page 19. The jumper pins should be set as the following. JP36 MCLK JP33 BICK_SEL JP38 LRCK_SEL JP51 SDTI_SEL JP35 PHASE JP48 M/S DIR EXT DIR 4040 DIR 4040 DIR ADC <KM089000> THR INV Master Slave 2007 / 05 -6- [AKD4671-B] (2-3) Evaluation of Loop-back using AK4114 X’tal (X2) is used. Nothing should be connected to PORT1 (DIR), PORT2 (DIT) and PORT4 (DSP). The jumper pins should be set as the following. JP36 MCLK JP33 BICK_SEL JP38 LRCK_SEL JP51 SDTI_SEL JP35 PHASE DIR EXT DIR 4040 DIR 4040 DIR ADC THR INV (2-4) All interface signals including master clock are fed externally PORT4 (DSP) is used. Nothing should be connected to PORT1 (DIR) and PORT2 (DIT). The jumper pins should be set as the following. JP36 MCLK JP33 BICK_SEL JP38 LRCK_SEL JP51 SDTI_SEL JP48 M/S DIR EXT DIR 4040 DIR 4040 DIR <KM089000> ADC Master Slave 2007 / 05 -7- [AKD4671-B] (3) PLL Slave Mode A reference clock of PLL is selected among the input clocks to MCKI, BICK or LRCK pin. The required clock to the AK4671 is generated by an internal PLL circuit. Input frequency is selected by PLL3-0 bits. BICK and LRCK inputs should be synchronized with MCKO output. The phase between MCKO and LRCK dose not matter. MCKO pin outputs the frequency selected by PS1-0 bits and the output is enabled by MCKO bit. Sampling frequency can be selected by FS3-0 bits. (3-1) PLL Reference Clock : MCKI pin 11.2896MHz, 12MHz, 12.288MHz, 13MHz, 13.5MHz, 19.2MHz, 24MHz, 26MHz, 27MHz AK4671 DSP or μP MCKI MCKO 256fs/128fs/64fs/32fs ≥ 32fs BICK 1fs LRCK MCLK BCLK LRCK SDTO SDTI SDTI SDTO (3-1-1) Evaluation of A/D using DIT of AK4114 J12 (EXT) and PORT2 (DIT) are used. Nothing should be connected to PORT1 (DIR) and PORT4 (DSP). X’tal oscillator should be removed from X2. The jumper pins should be set as the following. JP36 MCLK JP39 EXT JP33 BICK_SEL JP38 LRCK_SEL JP46 4114_MCKI JP35 PHASE JP7 MCKO DIR EXT DIR 4040 DIR 4040 THR INV JP48 M/S Master Slave When a termination (51Ω) is unnecessary, please set JP39 (EXT) to open. <KM089000> 2007 / 05 -8- [AKD4671-B] (3-1-2) Evaluation of Loop-back using AK4114 J12 (EXT) is used. Nothing should be connected to PORT1 (DIR), PORT2 (DIT) and PORT4 (DSP). X’tal oscillator should be removed from X2. The jumper pins should be set as the following. JP36 MCLK JP39 EXT JP33 BICK_SEL JP38 LRCK_SEL JP46 4114_MCKI JP35 PHASE JP51 SDTI_SEL DIR EXT DIR 4040 DIR THR 4040 INV DIR ADC JP48 M/S JP7 MCKO Master Slave When a termination (51Ω) is unnecessary, please set JP39 (EXT) open. (3-1-3) All interface signals including master clock are fed externally PORT4 (DSP) is used. Nothing should be connected to PORT1 (DIR) and PORT2 (DIT). The jumper pins should be set as the following. JP36 MCLK JP39 EXT JP33 BICK_SEL JP38 LRCK_SEL JP46 4114_MCKI JP35 PHASE JP51 SDTI_SEL DIR EXT DIR 4040 DIR 4040 THR INV DIR ADC JP48 M/S Master Slave <KM089000> 2007 / 05 -9- [AKD4671-B] (3-2) PLL Reference Clock : BICK or LRCK pin AK4671 DSP or μP MCKO MCKI 32fs or 64fs BICK 1fs LRCK BCLK LRCK SDTO SDTI SDTI SDTO (PLL Reference Clock: BICK pin) AK4671 DSP or μP MCKO MCKI ≥ 32fs BICK 1fs LRCK BCLK LRCK SDTO SDTI SDTI SDTO (PLL Reference Clock: LRCK pin) (3-2-1) Evaluation of A/D using DIT of AK4114 X2 (X’tal) and PORT2 (DIT) are used. Nothing should be connected to PORT1 (DIR) and PORT4 (DSP). The jumper pins should be set as the following. JP36 MCLK JP39 EXT JP33 BICK_SEL JP38 LRCK_SEL JP46 4114_MCKI JP35 PHASE JP48 M/S DIR EXT DIR 4040 DIR 4040 <KM089000> THR INV Master Slave 2007 / 05 - 10 - [AKD4671-B] (3-2-2) Evaluation of D/A using DIR of AK4114 PORT1 (DIR) is used. Nothing should be connected to PORT2 (DIT) and PORT4 (DSP). The jumper pins should be set as the following. JP36 MCLK JP39 EXT JP33 BICK_SEL JP38 LRCK_SEL JP46 4114_MCKI JP35 PHASE JP51 SDTI_SEL DIR EXT DIR 4040 DIR THR 4040 INV DIR ADC JP48 M/S Master Slave (3-2-3) Evaluation of Loop-back using AK4114 X2 (X’tal) is used. Nothing should be connected to PORT1 (DIR), PORT2 (DIT) and PORT4 (DSP). The jumper pins should be set as the following. JP36 MCLK JP39 EXT JP33 BICK_SEL JP38 LRCK_SEL JP46 4114_MCKI JP35 PHASE JP51 SDTI_SEL DIR EXT DIR 4040 DIR THR 4040 INV DIR ADC JP48 M/S Master Slave (3-2-4) All interface signals including master clock are fed externally PORT4 (DSP) is used. Nothing should be connected to PORT1 (DIR) and PORT2 (DIT). The jumper pins should be set as the following. JP36 MCLK JP39 EXT JP33 BICK_SEL JP38 LRCK_SEL JP46 4114_MCKI JP35 PHASE JP51 SDTI_SEL DIR EXT DIR 4040 DIR 4040 THR INV DIR ADC JP48 M/S Master Slave <KM089000> 2007 / 05 - 11 - [AKD4671-B] (4) PLL Master Mode When an external clock (11.2896MHz, 12MHz, 12.288MHz, 13MHz, 13.5MHz, 19.2MHz, 24MHz, 26MHz or 27MHz) is input to MCKI pin, the MCKO, BICK and LRCK clocks are generated by an internal PLL circuit. The MCKO output frequency is selected by PS1-0 bits and the output is enabled by MCKO bit. The BICK output frequency is selected between 32fs or 64fs, by BCKO bit. 11.2896MHz, 12MHz, 12.288MHz, 13MHz, 13.5MHz, 19.2MHz, 24MHz, 26MHz, 27MHz DSP or μP AK4671 MCKI MCKO 256fs/128fs/64fs/32fs 32fs, 64fs BICK 1fs LRCK MCLK BCLK LRCK SDTO SDTI SDTI SDTO (4-1) Evaluation of A/D using DIT of AK4114 J12 (EXT) and PORT2 (DIT) are used. Nothing should be connected to PORT1 (DIR) and PORT4 (DSP). X’tal oscillator should be removed from X2. In Master Mode, BICK and LRCK of AK4671 should be input to AK4114. Please refer to Table 2 on page 19. The jumper pins should be set as the following. JP36 MCLK JP39 EXT JP33 BICK_SEL JP38 LRCK_SEL JP46 4114_MCKI JP35 PHASE JP7 MCKO DIR EXT DIR 4040 DIR 4040 THR INV JP48 M/S Master Slave When a termination (51Ω) is unnecessary, please set JP39 (EXT) open. <KM089000> 2007 / 05 - 12 - [AKD4671-B] (4-2) Evaluation of Loop-back J12 (EXT) is used. Nothing should be connected to PORT1 (DIR), PORT2 (DIT) and PORT4 (DSP). X’tal oscillator should be removed from X2. The jumper pins should be set as the following. JP36 MCLK JP39 EXT JP33 BICK_SEL JP38 LRCK_SEL JP46 4114_MCKI JP35 PHASE JP51 SDTI_SEL DIR EXT DIR 4040 DIR THR 4040 INV DIR ADC JP48 M/S Master Slave When a termination (51Ω) is unnecessary, please set JP39 (EXT) open. (4-3) All interface signals including master clock are fed externally PORT4 (DSP) is used. Nothing should be connected to PORT1 (DIR) and PORT2 (DIT). The jumper pins should be set as the following. JP36 MCLK JP39 EXT JP33 BICK_SEL JP38 LRCK_SEL JP46 4114_MCKI JP35 PHASE JP51 SDTI_SEL DIR EXT DIR 4040 DIR 4040 THR INV DIR ADC JP48 M/S Master Slave <KM089000> 2007 / 05 - 13 - [AKD4671-B] 2. PCM I/F evaluation mode A reference clock of PLLBT is selected among the input clocks to SYNCA, BICKA, SYNCB or BICKB pin. The required clock to PCM I/F is generated by an internal PLLBT circuit. PLLBT circuit is powered up by PMPCM bit. Input frequency is selected by PLLBT2-0 bits. BCKO2 bit select the output clock frequency of BICKA or BICKB pin. AK4671 does not support master mode for both PCM I/F A and B nor slave mode for both PCM I/F A and B. When PMPCM bit is “0”, SYNCA, BICKA, SYNCB and BICKB pins are Hi-Z. (1) PLLBT reference clock: SYNCA or BICKA pin (1-1) SYNCA and BICKA are fed from on-board clock generator. (1-2) SYNCA and BICKA are fed externally via PORT3 (Baseband Module). (2) PLLBT reference clock: SYNCB or BICKB pin (2-1) SYNCB and BICKB are fed from on-board clock generator. (2-2) SYNCB and BICKB are fed externally via PORT6 (Bluetooth Module). <KM089000> 2007 / 05 - 14 - [AKD4671-B] (1) PLLBT reference clock: SYNCA or BICKA pin The PLLBT circuit generates the required clock for PCM I/F from SYNCA or BICKA. Generated clocks are output via SYNCB and BICKB pins. AK4671 Baseband Module 1fs2 SYNCA SYNC ≥ 16fs2 BICKA BICK SDTOA SDTI SDTIA SDTO Bluetooth Module 1fs2 SYNCB SYNC 16fs2 or 32fs2 BICKB BICK SDTOB SDTI SDTIB SDTO (PLLBT Reference Clock: SYNCA or BICKA pin) (1-1) SYNCA and BICKA are fed from on-board clock generator. X1 (X’tal), PORT3 (Baseband Module) and PORT6 (Bluetooth Module) are used. The jumper pins should be set as the following. Please set JP42 (BCFS2) to the required frequency. Follows are setting in BICKA=32fs. When clocks are supplied from J13 (EXT1) without using X1, JP41 (MCLK2) should be set to “EXT1”. JP42 BCFS2 JP41 MCLK2 JP40 XTE XTL EXT1 JP43 BICK2_SEL JP45 LRCK2_SEL JP49 PLLBT BICKA BICKB LRCKA LRCKB BICKA BICKB 256fs2 128fs2 64fs2 32fs2 16fs2 JP62 BICKA JP63 SYNCA JP64 BICKB JP65 SYNCB JP61 SDTIB <KM089000> JP60 SDTIA 2007 / 05 - 15 - [AKD4671-B] JP47 (BICKA PHASE) is jumper which decides polarity of BICKA, “THR” or “INV” should be selected according to the PCM I/F format. JP54 (BICKB PHASE) should be set to “THR”. JP47 BICKA PHASE JP54 BICKB PHASE THR THR INV INV In case of loop-back “SDTOA → SDTIA” and “SDTOB → SDTIB”, please set JP50 (SDTOA LOOP) and JP55 (SDTOB LOOP) short. JP50 SDTOA LOOP JP55 SDTOB LOOP (1-2) SYNCA and BICKA are fed externally via PORT3 (Baseband Module). PORT3 (Baseband Module) and PORT6 (Bluetooth Module) are used. SYNCA and BICKA should be supplied from PORT3. The jumper pins should be set as the following. JP41 MCLK2 JP40 XTE XTL EXT1 JP43 BICK2_SEL JP45 LRCK2_SEL JP49 PLLBT BICKA BICKB LRCKA LRCKB BICKA BICKB JP47 (BICKA PHASE) is jumper which decides polarity of BICKA, “THR” or “INV” should be selected according to the PCM I/F format. JP54 (BICKB PHASE) should be set to “THR”. JP47 BICKA PHASE JP54 BICKB PHASE THR THR INV INV <KM089000> 2007 / 05 - 16 - [AKD4671-B] (2) PLLBT reference clock: SYNCB or BICKB pin The PLLBT circuit generates the required clock for PCM I/F from SYNCB or BICKB. Generated clocks are output via SYNCA and BICKA pins. AK4671 Baseband Module 1fs2 SYNCA BICKA SYNC 16fs2 or 32fs2 BICK SDTOA SDTI SDTIA SDTO Bluetooth Module 1fs2 SYNCB SYNC ≥ 16fs2 BICKB BICK SDTOB SDTI SDTIB SDTO (PLLBT Reference Clock: SYNCB or BICKB pin) (2-1) SYNCB and BICKB are fed from on-board clock generator. X1 (X’tal), PORT3 (Baseband Module) and PORT6 (Bluetooth Module) are used. The jumper pins should be set as the following. Please set JP42 (BCFS2) to the required frequency. Follows are setting in BICKB=32fs. When clocks are supplied from J13 (EXT1) without using X1, JP41 (MCLK2) should be set to “EXT1”. JP42 BCFS2 JP41 MCLK2 JP40 XTE XTL EXT1 JP43 BICK2_SEL JP45 LRCK2_SEL JP49 PLLBT BICKA BICKB LRCKA LRCKB BICKA BICKB 256fs2 128fs2 64fs2 32fs2 16fs2 JP62 BICKA JP63 SYNCA JP64 BICKB JP65 SYNCB <KM089000> JP61 SDTIB JP60 SDTIA 2007 / 05 - 17 - [AKD4671-B] JP54 (BICKB PHASE) is jumper which decides polarity of BICKB, “THR” or “INV” should be selected according to the PCM I/F format. JP47 (BICKA PHASE) should be set to “THR”. JP47 BICKA PHASE JP54 BICKB PHASE THR THR INV INV In case of loop-back “SDTOA → SDTIA” and “SDTOB → SDTIB”, please set JP50 (SDTOA LOOP) and JP55 (SDTOB LOOP) short. JP50 SDTOA LOOP JP55 SDTOB LOOP (2-2) SYNCB and BICKB are fed externally via PORT6 (Bluetooth Module). PORT3 (Baseband Module) and PORT6 (Bluetooth Module) are used. Please supply SYNCB and BICKB from PORT6. The jumper pins should be set as the following. JP41 MCLK2 JP40 XTE XTL EXT1 JP43 BICK2_SEL JP45 LRCK2_SEL JP49 PLLBT BICKA BICKB LRCKA LRCKB BICKA BICKB JP54 (BICKB PHASE) is jumper which decides polarity of BICKB, “THR” or “INV” should be selected according to the PCM I/F format. JP47 (BICKA PHASE) should be set to “THR”. JP47 BICKA PHASE JP54 BICKB PHASE THR THR INV INV <KM089000> 2007 / 05 - 18 - [AKD4671-B] DIP Switch set up [S1] (SW DIP-6): Mode setting for AK4671 and AK4114. No. 1 2 3 4 5 6 Name DIF2 DIF1 DIF0 OCKS1 CAD0 I2C ON (“H”) OFF (“L”) AK4114 Audio Format Setting See Table 2 AK4114 Master Clock Setting : See Table 3 AK4671 Control Mode Setting See Table 4 Default ON OFF OFF OFF OFF ON Table 1. Mode Setting for AK4671 and AK4114 DIF2 0 0 0 0 1 1 1 1 DIF1 0 0 1 1 0 0 1 1 DIF0 0 1 0 1 0 1 0 1 DAUX 24bit, Left justified 24bit, Left justified 24bit, Left justified 24bit, Left justified 24bit, Left justified 24bit, I2S 24bit, Left justified 24bit, I2S SDTO 16bit, Right justified 18bit, Right justified 20bit, Right justified 24bit, Right justified 24bit, Left justified 24bit, I2S 24bit, Left justified 24bit, I2S LRCK H/L O H/L O H/L O H/L O H/L O L/H O H/L I L/H I BICK 64fs 64fs 64fs 64fs 64fs 64fs 64-128fs 64-128fs O O O O O O I I Default Table 2. Setting for AK4114 Audio Interface Format OCKS1 0 1 MCKO1 256fs 512fs X’tal 256fs 512fs Default Table 3. Setting for AK4114 Master Clock <KM089000> 2007 / 05 - 19 - [AKD4671-B] Other jumper pins set up Sub Board [JP1] (RIN2) : RIN2 input. GND : In case of full-differential input. MPWR : MIC-power is supplied to RIN2. OPEN : MIC-power is not supplied to RIN2. <Default> [JP2] (LIN1) : LIN1 input. SHORT : MIC-power is supplied to LIN1. OPEN : MIC-power is not supplied to LIN1. <Default> [JP3] (LIN2) : LIN2 input. SHORT : MIC-power is supplied to LIN2. OPEN : MIC-power is not supplied to LIN2. <Default> [JP4] (RIN1) : RIN1 input. GND : In case of full-differential input. MPWR : MIC-power is supplied to RIN1. OPEN : MIC-power is not supplied to RIN1. <Default> [JP5] (PVDD) : PVDD of AK4212 power supply. SHORT : PVDD is supplied from “PVDD” jack. <Default> OPEN : PVDD is not supplied from “PVDD” jack [JP6] (PDN) : PDN of AK4212. SHORT : PDN is supplied from SW2 (PDN). <Default> OPEN : PDN is not supplied from SW2 (PDN). [JP7] (MCKO) : MCKO output. SHORT : When AK4671 outputs MCKO. <Default> OPEN : When AK4671 does not output MCKO. [JP8] (SDA) : SDA of AK4212. SHORT : SDA is supplied from PORT5 (CTRL). <Default> OPEN : SDA is not supplied from PORT5 (CTRL). [JP9] (SCL) : SCL of AK4212. SHORT : SCL is supplied from PORT5 (CTRL). <Default> OPEN : SCL is not supplied from PORT5 (CTRL). [JP10] (TVDD) : TVDD of AK4212 power supply. SHORT : TVDD is supplied from “DVDD” jack. <Default> OPEN : TVDD is not supplied from “DVDD” jack [JP11] (AVDD) : AVDD of AK4212 power supply. SHORT : AVDD is supplied from “AVDD” jack. <Default> OPEN : AVDD is not supplied from “AVDD” jack [JP12] (U2 RIN1) : RIN1 of AK4212 input SHORT : RIN1 is supplied from ROUT2. <Default> OPEN : RIN1 is not supplied from ROUT2. [JP13] (U2 LIN1) : LIN1 of AK4212. SHORT : LIN1 is supplied from LOUT2. <Default> OPEN : LIN1 is not supplied from LOUT2. <KM089000> 2007 / 05 - 20 - [AKD4671-B] [JP14] (U2 SPRIN) : SPRIN of AK4212. SHORT : SPRIN is supplied from ROUT3. <Default> OPEN : SPRIN is not supplied from ROUT3. [JP15] (U2 SPLIN) : SPLIN of AK4212. SHORT : SPLIN is supplied from LOUT3. <Default> OPEN : SPLIN is not supplied from LOUT3. Main Board [JP30] (GND) : AGND and DGND. SHORT : Common. <Default> OPEN : Separated. [JP46] (4114_MCKI) : MCKI of AK4114. SHORT : MCKO of AK4671. OPEN : X’tal (X2). <Default> [JP56] (D3V) : Power supply of PORT7 SHORT : It is supplied from “D3V” jack. OPEN : It is not supplied from “D3V” jack. <Default> [JP57] (I2C PIN) : AK4671 I2C input. I2C : It is supplied from S1 (I2C). <Default> MCLK2 : It is supplied from MCLK2. <KM089000> 2007 / 05 - 21 - [AKD4671-B] The function of the toggle SW [SW2] (PDN) : Power down of AK4671. Keep “H” during normal operation. [SW1] (DIR) : Power down of AK4114. Keep “H” during normal operation. Keep “L” when AK4114 is not used. Indication for LED [LED1] (ERF) : Monitor INT0 pin of the AK4114. LED turns on when some error has occurred to AK4114. Serial Control The AK4671 can be controlled via the printer port (parallel port) of IBM-AT compatible PC. Connect PORT5 (CTRL) with PC by 10 wire flat cable packed with the AKD4671.Table 4 shows switch and jumper settings for serial control. I2C Mode should be selected in Table 4. Note) When evaluate it in SAR-ADC of AK4671, 4-WIRE Mode should be selected in Table 4. PORT5 CSN Connect CCLK/SCL CDTI/SDA AKD4671 CDTO/SDA PC 10 wire flat cable 10pin Connector 10pin Header Figure 2. Connect of 10 wire flat cable Mode 4-WIRE CAD0=0 I2C CAD0=1 S1 (DIP SW) JP52 I2C CAD0 CTRL_SEL 4-WIRE OFF OFF ON OFF I2C ON ON Table 4. Serial Control Setting <KM089000> JP53 CTRL_SEL2 4-WIRE I2C Default 2007 / 05 - 22 - [AKD4671-B] Analog Input/Output Circuits (1) Input Circuits (1-1) LIN1/RIN1, LIN2/RIN2, LIN3/RIN3 and LIN4/RIN4 Input Circuit J2 1 LIN1 2 3 RIN1 LIN1/RIN1 LIN2 JP23 C50 1u 1 R39 LIN2 LIN3 LIN4 (short) + 2 3 4 5 J5 LIN LIN3 LIN_SEL LIN4 RIN2 JP25 C53 1u 1 R42 (short) RIN2 RIN3 RIN4 + 2 3 4 5 J7 RIN RIN3 RIN_SEL RIN4 Figure 3. LIN1/RIN1, LIN2/RIN2, LIN3/RIN3 and LIN4/RIN4 Input Circuit LIN2/RIN2, LIN3/RIN3 and LIN4/RIN4 share J5/J7. JP23 (LIN_SEL) and JP25 (RIN_SEL) select each path. (1-2) SAIN1, SAIN2 and SAIN3 Input Circuit SAIN1 JP28 2 3 4 5 J9 SAIN SAIN1 SAIN2 SAIN3 1 SAIN2 SAIN_SEL SAIN3 2 3 4 5 J11 SAIN3 1 Figure 4. SAIN1, SAIN2 and SAIN3 Input Circuit SAIN1, SAIN2 and SAIN3 share J9. JP28 (SAIN_SEL) select each path. <KM089000> 2007 / 05 - 23 - [AKD4671-B] (2) Output Circuits (2-1) LOUT1/ROUT1, LOUT2/ROUT2 and LOUT3/ROUT3 Output Circuit JP16 LOUT3 LOUT2 LOUT2 + R32 LOUT3 LOUT1 C44 1u LOUT_SEL J1 LOUT 1 2 3 4 5 R33 20k + LOUT1 220 JP17 HPL JACK R34 (short) C45 100u R35 16 J3 1 JP58 L_16ohm + 2 3 HP JP19 HPR JACK R37 (short) C47 100u JP59 R_16ohm JP21 ROUT3 ROUT2 ROUT2 + R38 ROUT3 ROUT1 C49 1u ROUT1 R36 16 ROUT_SEL 220 1 J4 ROUT 2 3 4 5 R40 20k Figure 5. LOUT1/ROUT1, LOUT2/ROUT2 and LOUT3/ROUT3 Output Circuit LOUT1/ROUT1, LOUT2/ROUT2 and LOUT3/ROUT3 share J1/J4. JP16 (LOUT_SEL) and JP21 (ROUT_SEL) select each path. (2-2) Headphone of AK4212 Output Circuit JP13 (U2LIN1) and JP12 (U2RIN1) on sub board should be shorted, and LOUT2S and ROUT2S signal should be input to Headphone-Amp block of AK4212. JP13 U2LIN1 JP12 U2RIN1 R43 HPL (short) J10 1 R44 2 3 HPR (short) 4212 HP Figure 6. Headphone of AK4212 Output Circuit <KM089000> 2007 / 05 - 24 - [AKD4671-B] (2-3) Speaker of AK4212 Output Circuit JP15 (U2SPLIN) and JP14 (U2SPRIN) on sub board should be shorted, and LOUT3 and ROUT3 signal should be input to Speaker-Amp block of AK4212. JP15 U2SPLIN JP14 U2SPRIN LOUTP J6 1 2 3 LOUTN SPK_L J8 1 ROUTP 2 3 SPK_R ROUTN Figure 7. Speaker of AK4212 Output Circuit * AKM assumes no responsibility for the trouble when using the above circuit examples. <KM089000> 2007 / 05 - 25 - [AKD4671-B] Control Software Manual Set-up of evaluation board and control software 1. Set up the AKD4671-B according to previous term. 2. Connect IBM-AT compatible PC with AKD4671-B by 10-line type flat cable (packed with AKD4671-B). Take care of the direction of 10pin header. (Please install the driver in the CD-ROM when this control software is used on Windows 2000/XP. Please refer “Installation Manual of Control Software Driver by AKM device control software”. In case of Windows95/98/ME, this installation is not needed. This control software does not operate on Windows NT.) 3. Insert the CD-ROM labeled “AKD4671-B Evaluation Kit” into the CD-ROM drive. 4. Access the CD-ROM drive and double-click the icon of “AKD4671.exe” and “AKD4212 .exe” to set up the control program. In case of evaluation using AK4212, “AKD4212 .exe” is necessary. 5. Then please evaluate according to the follows. Operation flow Keep the following flow. 1. Set up the control program according to explanation above. 2. Click “Port Reset” button. 3. Click “Write default” button Explanation of each buttons [Port Reset] : [Write default] : [All Write] : [Function1] : [Function2] : [Function3] : [Function4] : [Function5]: [SAVE] : [OPEN] : [Write] : [Filter] : [5 Band EQ] : Set up the USB interface board (AKDUSBIF-A) . Initialize the register of AK4671. Write all registers that is currently displayed. Dialog to write data by keyboard operation. Dialog to write data by keyboard operation. The sequence of register setting can be set and executed. The sequence that is created on [Function3] can be assigned to buttons and executed. The register setting that is created by [SAVE] function on main window can be assigned to buttons and executed. Save the current register setting. Write the saved values to all register. Dialog to write data by mouse operation. Set Programmable Filter (FIL1, FIL3, EQ) of AK4671 easily. Set 5Band Equalizer of AK4671 easily. Indication of data Input data is indicated on the register map. Red letter indicates “H” or “1” and blue one indicates “L” or “0”. Blank is the part that is not defined in the datasheet. <KM089000> 2007 / 05 - 26 - [AKD4671-B] Explanation of each dialog 1. [Write Dialog] : Dialog to write data by mouse operation There are dialogs corresponding to each register. Click the [Write] button corresponding to each register to set up the dialog. If you check the check box, data becomes “H” or “1”. If not, “L” or “0”. If you want to write the input data to AK4671, click [OK] button. If not, click [Cancel] button. 2. [Function1 Dialog] : Dialog to write data by keyboard operation Address Box: Data Box: Input registers address in 2 figures of hexadecimal. Input registers data in 2 figures of hexadecimal. If you want to write the input data to AK4671, click [OK] button. If not, click [Cancel] button. 3. [Function2 Dialog] : Dialog to evaluate DATT Address Box: Input registers address in 2 figures of hexadecimal. Start Data Box: Input starts data in 2 figures of hexadecimal. End Data Box: Input end data in 2 figures of hexadecimal. Interval Box: Data is written to AK4671 by this interval. Step Box: Data changes by this step. Mode Select Box: If you check this check box, data reaches end data, and returns to start data. [Example] Start Data = 00, End Data = 09 Data flow: 00 01 02 03 04 05 06 07 08 09 09 08 07 06 05 04 03 02 01 00 If you do not check this check box, data reaches end data, but does not return to start data. [Example] Start Data = 00, End Data = 09 Data flow: 00 01 02 03 04 05 06 07 08 09 If you want to write the input data to AK4671, click [OK] button. If not, click [Cancel] button. <KM089000> 2007 / 05 - 27 - [AKD4671-B] 4. [Save] and [Open] 4-1. [Save] Save the current register setting data. The extension of file name is “akr”. <Operation flow> (1) Click [Save] Button. (2) Set the file name and push [Save] Button. The extension of file name is “akr”. 4-2. [Open] The register setting data saved by [Save] is written to AK4671. The file type is the same as [Save]. <Operation flow> (1) Click [Open] Button. (2) Select the file (*.akr) and Click [Open] Button. <KM089000> 2007 / 05 - 28 - [AKD4671-B] 5. [Function3 Dialog] The sequence of register setting can be set and executed. (1) Click [F3] Button. (2) Set the control sequence. Set the address, Data and Interval time. Set “-1” to the address of the step where the sequence should be paused. (3) Click [Start] button. Then this sequence is executed. The sequence is paused at the step of Interval="-1". Click [START] button, the sequence restarts from the paused step. This sequence can be saved and opened by [Save] and [Open] button on the Function3 window. The extension of file name is “aks”. Figure 8. Window of [F3] <KM089000> 2007 / 05 - 29 - [AKD4671-B] 6. [Function4 Dialog] The sequence that is created on [Function3] can be assigned to buttons and executed. When [F4] button is clicked, the window as shown in Figure 9. opens. Figure 9. [F4] window <KM089000> 2007 / 05 - 30 - [AKD4671-B] 6-1. [OPEN] buttons on left side and [START] buttons (1) Click [OPEN] button and select the sequence file (*.aks). The sequence file name is displayed as shown in Figure 10. Figure 10. [F4] window (2) (2) Click [START] button, then the sequence is executed. 6-2. [SAVE] and [OPEN] buttons on right side [SAVE] : The sequence file names can assign be saved. The file name is *.ak4. [OPEN] : The sequence file names assign that are saved in *.ak4 are loaded. 6-3. Note (1) This function doesn't support the pause function of sequence function. (2) All files need to be in same folder used by [SAVE] and [OPEN] function on right side. (3) When the sequence is changed in [Function3], the file should be loaded again in order to reflect the change. <KM089000> 2007 / 05 - 31 - [AKD4671-B] 7. [Function5 Dialog] The register setting that is created by [SAVE] function on main window can be assigned to buttons and executed. When [F5] button is clicked, the following window as shown in Figure 11.opens. Figure 11. [F5] window 7-1. [OPEN] buttons on left side and [WRITE] button (1) Click [OPEN] button and select the register setting file (*.akr). The register setting file name is displayed as shown in Figure 12. (2) Click [WRITE] button, then the register setting is executed. <KM089000> 2007 / 05 - 32 - [AKD4671-B] Figure 12. [F5] windows(2) 7-2. [SAVE] and [OPEN] buttons on right side [SAVE] : The register setting file names assign can be saved. The file name is *.ak5. [OPEN] : The register setting file names assign that are saved in *.ak5 are loaded. 7-3. Note (1) All files need to be in same folder used by [SAVE] and [OPEN] function on right side. (2) When the register setting is changed by [Save] Button in main window, the file should be loaded again in order to reflect the change. <KM089000> 2007 / 05 - 33 - [AKD4671-B] 8. [Filter Dialog] This dialog can easily set the AK4671’s programmable filter. A calculation of a coefficient of Digital Programmable Filter such as HPF,EQ filter ,a write to a register and check frequency response. Window to show to Figure 13 opens when push a [Filter] button . Figure 13. [Filter] window <KM089000> 2007 / 05 - 34 - [AKD4671-B] 8-1. Setting of a parameter (1) Please set a parameter of each Filter. Item Sampling Rate FIL3 Cut Off Frequency Filter type Gain HPF Cut Off Frequency Contents Sampling frequency (fs) Stereo separation emphasis filter cut off frequency Type of stereo separation emphasis filter Gain of stereo separation emphasis filter Setting range 7350Hz ≤ fs ≤ 48000Hz fs/10000 ≤ Cut Off Frequency ≤ (0.497 * fs) LPF or HPF –10dB ≤ Gain ≤ 0dB High pass filter cut off frequency fs/10000 ≤ Cut Off Frequency ≤ (0.497 * fs) LPF Cut Off Frequency Low pass filter cut off frequency fs/20 ≤ Cut Off Frequency ≤ (0.497 * fs) EQ for Gain Compensation (EQ0) Pole Frequency Pole Frequency Zero-point Frequency Zero-point Frequency Gain 5 Band Equalizer EQ1-5 Center Frequency Gain EQ1-5 Center Frequency EQ1-5 Band Width EQ1-5 Band Width ( Note 1) EQ1-5 Gain EQ1-5 Gain ( Note 2) Note 1. Bandwidth where the gain gap is 3dB compared with center frequency. Note 2. When a gain is smaller than "0", EQ becomes a notch filter. fs/10000 ≤ Pole Frequency ≤ (0.497 * fs) fs/10000 ≤ Zero-point Frequency ≤ (0.497 * fs) 0dB ≤ Gain ≤ +12dB 0Hz ≤ Center Frequency < (0.497 * fs) 1Hz ≤ Band Width < (0.497 * fs) -1≤ Gain < 3 (2) Please set ON/OFF of Filter with check buttons of “FIL3”, “EQ0”, “LPF”, “HPF”, “HPFAD”, “EQ1”, “EQ2”, “EQ3”, “EQ4”, “EQ5”. When the button is checked, Filter becomes ON. When “Notch Filter Auto Correction” is checked, automatic compensation is executed for center frequency of notch filter. (“Cf. 8-4. automatic compensation for center frequency of a notch filter”) Figure14. Filter ON/OFF setting button <KM089000> 2007 / 05 - 35 - [AKD4671-B] 8-2. A calculation of a register A register setting values are displayed when [Register Setting] button is clicked. When any value is set to out of range, error message is displayed, and a calculation of register setting is not executed. Figure15. A register setting calculation result In the following cases, a register set values are updated. (1) When [Register Setting] button was pushed. (2) When [Frequency Response] button was pushed. (3) When [UpDate] button was pushed on a frequency characteristic indication window. (4) When set ON/OFF of a check button “Notch Filter Auto Correction” <KM089000> 2007 / 05 - 36 - [AKD4671-B] 8-3.Indication of a frequency characteristic A frequency characteristic is displayed when [Frequency Response] button is clicked. The register values are updated at the same time. If "Frequency Range" is changed, and [UpDate] button is clicked, indication of a frequency characteristic is updated. Figure16. A frequency characteristic indication result In the following cases, a register set values are updated. (1) When [Register Setting] button was pushed. (2) When [Frequency Response] button was pushed. (3) When [UpDate] button was pushed on a frequency characteristic indication window. (4) When set ON/OFF of a check button “Notch Filter Auto Correction” 8-4. Automatic compensation for center frequency of a notch filter When a gain of 5 band Equalizer is set to "-1", Equalizer becomes a notch filter. When center frequency of several notch filters are near frequency each other, center frequency error occurs (Figure 17). When "Notch Filter Auto Correction" button is checked, automatic compensation is executed for center frequency of a notch filter. Register setting and frequency characteristics are displayed after automatic compensation (Figure18). This automatic compensation is available for EqualizerBand where a gain is set to "-1". (Note) When distance among center frequencies is smaller than band width, there is a possibility that automatic compensation does not operate normally. Please confirm a compensation result by indication of a frequency characteristic. <KM089000> 2007 / 05 - 37 - [AKD4671-B] Setting of center frequency: 4400Hz, 5000Hz, 5400Hz / Band Width : 200Hz(3 band common) Figure17. When there is no compensation of center frequency Setting of center frequency: 4400Hz, 5000Hz, 5400Hz / Band Width : 200Hz(3 band common) Figure18. When there is compensation of center frequency <KM089000> 2007 / 05 - 38 - [AKD4671-B] 9. [5 Band EQ Dialog] This dialog can easily set the AK4671’s 5-Band Equalizer. Figure 19. [5 Band EQ] window When the check box of “5 Band EQ” is checked, 5-Band Equalizer is ON (EQ bit = ”1”). When the slide button is changed, its value is written to the internal register immediately. <KM089000> 2007 / 05 - 39 - [AKD4671-B] Revision History Date (YY/MM/DD) Manual Revision Board Revision 07/05/15 KM089000 0 Reason Contents First Edition IMPORTANT NOTICE • These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. • AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. • Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. • AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: (a) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. • It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification. <KM089000> 2007 / 05 - 40 - A B SAIN1 SAIN2 SAIN3 LIN1 RIN1 LIN2 C RIN2 LIN3 RIN3 LIN4 RIN4 D 4670_TVDD2 4670_PVDD 4670_AVDD E 80pin_4 61 62 63 64 65 66 67 68 69 70 71 TP7 LIN4 TP8 RIN4 1 TP6 RIN3 1 72 TP5 LIN3 1 73 TP4 RIN2 1 74 75 TP3 LIN2 1 76 TP2 RIN1 1 77 1 1 TP1 LIN1 JP1 RIN2 AVDD E E R1 MPWR CN3 R2 2.2k TP18 LOUT3 1 JP4 RIN1 SPLIN JP3LIN2 R3 2.2k TP19 ROUT3 60 LOUT3 59 ROUT3 58 LOUT2 57 ROUT2 56 LOUT1 55 ROUT1 1 MPWR R4 2.2k JP2LIN1 TP16 LOUT2 1 2.2k TP46 AVDD SPRIN TP15 ROUT2 1 1 TP45 VSS1 1 GND 1 1 TP9 TP10 TP11 SAIN1 SAIN2 SAIN3 GND 1 78 79 80 CN4 1 TP40 MPWR 1 TP12 LOUT1 TP13 ROUT1 D 1 TP34 TEST A1 MDT TEST A9 B1 MPWR LOUT2 B9 SAIN3 ROUT2 C9 SAIN2 MUTET C8 1 TP22 MUTET PVDD 10 TP61 BICKB + SDTOB VSS2 F9 SYNCB TVDD2 F8 C20 0.1u TP58 51 SYNCB R12 F1 TP14 PVDD R6 10k R27 10k C4 10u TP17 VSS2 C1 4.7n C40 4.7n 9 CP 11 12 10 CN PVDD RIN3/IN3+ CDTI/SDA 7 LIN3/IN3- CCLK/SCL 6 TVDD 5 AVSS 4 51 R20 19 C21 10u C14 C15 2.2u 0.1u 51 VREF 21 RIN2/IN2+ AK4212 TP28 TVDD2 51 12 BICKB SDTOA G9 TP60 51 SDTIB R14 G1 SDTIB SYNCA H9 22 LIN2/IN2- AVDD 3 23 RIN1/IN1+ SPRIN 2 24 LIN1/IN1- MIXR 1 51 TP42 MCKI 51 41 AVDD TP32 SPRIN AVDD 80pin_3 SPLIN B TP38 SPLIN 1 32 MIXL 31 LOUTN 30 LOUTP SVSS 29 28 ROUTP SVDD 27 ROUTN C27 0.22u 25 GPO2 CDTI/SDA C31 1 H8 J9 DVDD J7 H7 H6 VSS4 CCLK/SCL CSN/CAD0 J6 BICK J5 H5 I2C MCKO H4 J4 MCKI LRCK J8 LOUTP 42 JP11 C24 0.1u TP33 GPO2 + TP49 BICK J3 J2 1 16 SDTIA C26 0.22u TP29 LOUTP 1 4670_LRCK PDN 1 TP48 51 LRCK R23 H3 1 GPO1 SDTO 15 U2 LIN1 J1 CDTO 4670_SDTO B JP13 G8 TP31 GPO1 R26 TP35 51 SDTO R25 H2 TP39 SDTI 1 14 BICKA 26 U2 RIN1 SDTI TVDD 43 + 4670_SDTI C23 10u LOUTN 44 DVDD + 51 H1 13 45 TP25 LOUTN SCL C19 10u + C22 0.1u JP12 R19 220k JP9 1 11 4670_SDTIB G2 SDA SDA SCL C18 0.1u 1 4670_BICKB R11 C JP8 JP10 20 1 4670_SYNCB 46 8 1 1 1 9 F2 PDN E8 1 4670_SDTOB LIN4/IN4- 1 AK4671 TVDD3 18 C5 0.1u TP59 SDTOB R13 47 R16 1 E2 8 VSS3 C16 0.1u 48 PDN 51 R18 1 1 C17 10u 17 TP20 VCOCBT 13 VCOCBT E9 E1 1 TP27 TVDD3 C13 0.1u 1 1 C12 + 10u + TP26 VSS3 PVSS D8 + 7 2.2u PVEE VCOC TP43 VCOC + 4670_TVDD3 2.2u 0.1u PDN JP6 U2 14 SAVDD + HPL D2 5 2.2u C38 HPR D9 0.1u 16 VCOM 15 SAIN1 TP44 VCOM RIN4/IN4+ D1 49 1 C6 1u C35 6 10u C9 C8 C2 4 HPL 50 JP5 PVDD C10 + 1 1 C1 + TP24 SAVDD 3 C 51 TP23 HPL C7 + 4670_SAVDD HPR 52 1 2 53 TP21 HPR AVDD ROUT1/RCN 54 A8 B8 C36 0.1u VSS1 B7 A7 LOUT1/RCP LOUT3/LOP ROUT3/LON A6 B6 A5 RIN4/IN4- B5 LIN4/IN4+ RIN3/IN3- B4 A4 LIN3/IN3+ LIN2/IN2+ RIN2/IN2- B3 A3 B2 RIN1/IN1- A2 1 LIN1/IN1+ NC MDT TP41 C3 U1 CN1 C39 10u + D C3 1u 1 C2 1u 1 R5 open R28 51 4670_MCKO 19 R17 51 R15 51 0.1u R29 51 R30 51 C25 C11 (open) 1 TP36 MCKO 1 18 + 4670_MCKI C33 10u JP7 R31 51 JP15 TP37 DVDD SPLIN 1 17 1 4670_BICK R21 10u C34 0.015u 1k TP30 VSS4 MCKO R24 U2 SPLIN R7 51 R9 51 R10 R8 51 51 C37 0.033u 20 PDN JP14 SCL 80pin_1 SPRIN SDA DVDD TP47 SVDD R22 C28 0.015u 1k A C29 0.033u 1 TP57 ROUTP 1 TP56 ROUTN 1 1 1 1 1 TP62 TP64 TP63 TP65 SDTIA BICKA SYNCA SDTOA 1 TP53 TP54 CCLK CDTI 1 1 TP55 TP52 CDTO CSN 1 1 A TP50 I2C 1 TP51 PDN U2 SPRIN 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 CN2 Title 4670_PDN 4670_I2C A CSN/CAD0 4670_CDTO CDTI/SDA 4670_DVDD CCLK/SCL 4670_SDTIA 4670_SYNCA 4670_BICKA B 4670_SDTOA ROUTN ROUTP Size SVDD A2 Date: C D AKD4671-B Document Number Rev AK4671 Wednesday, April 04, 2007 E 0 Sheet 1 of 5 A B C D E AGND1 E OUT C42 + 0.1u C41 0.1u C43 47u 1 T45_BK J2 1 1 LIN1 2 3 RIN1 LOUT2 LOUT1 LOUT1 C44 1u LOUT_SEL R32 220 J1 LOUT 1 JP17 R34 HPL JACK (short) LIN1/RIN1 SVDD C45 100u R35 16 JP58 L_16ohm 2 1 2 + C51 47u 2 1 2 C52 47u LIN2 JP23 LIN2 LIN3 LIN4 JP19 HPR JACK R37 (short) LIN_SEL LIN4 4670_SAVDD JP59 R_16ohm JP21 ROUT3 ROUT3 ROUT2 ROUT2 ROUT1 ROUT1 C49 1u ROUT_SEL 4670_PVDD J7 RIN C53 1u R42 (short) RIN2 RIN3 RIN4 1 1 2 + C54 47u RIN3 2 J6 1 1 1 + 2 T45_OR C55 47u LOUTN 2 3 ROUTP 1 4670_DVDD SPK_L JP27 TVDD2_SEL L6 1 2 3 4 5 LOUTP (short) C TVDD2 D J4 ROUT 1 RIN_SEL RIN4 1 R38 220 R40 20k RIN2 JP25 1 + 2 3 4 5 JP26 DVDD_SEL L5 T45_OR HP R36 16 JP24 PVDD_SEL 2 (short) R41 10 DVDD1 C47 100u LIN3 (short) 1 + R39 (short) JP22 SAVDD_SEL L4 1 T45_OR C50 1u 1 + 1 J5 LIN 4670_AVDD 2 3 4 5 L3 1 T45_OR PVDD1 C48 47u 2 (short) + 1 + D SAVDD1 JP20 AVDD_SEL L2 1 T45_OR J3 2 3 + C46 47u 1 AVDD1 2 3 4 5 R33 20k 1 + 2 T45_OR 2 JP18 SVDD_SEL LOUT3 LOUT2 1 SVDD1 L1 (short) 1 JP16 LOUT3 + T45_RED + IN 1 1 2 REG1 GND T1 TA48033F E 2 4670_TVDD2 (short) J9 SAIN 2 3 4 5 SAIN1 SAIN2 SAIN3 1 J8 2 3 SAIN1 JP28 C SPK_R SAIN2 ROUTN SAIN_SEL SAIN3 1 + 2 T45_OR C56 47u + 2 T45_OR J11 SAIN3 C57 47u 2 1 2 C96 47u (short) 1 J10 R44 2 3 HPR VCC (short) 4212 HP 1 + HPL (short) JP66 VCC2_SEL L11 1 T45_OR R43 1 JP31 VCC_SEL L8 B VCC2 4670_TVDD3 (short) 1 1 1 2 2 3 4 5 JP30 GND VCC1 JP29 TVDD3_SEL L7 1 1 TVDD3 B 2 VCC2 2 D3V (short) L9 D3V1 1 1 1 + 2 T45_OR DGND1 C58 47u (short) 1 T45_BK A A Title Size A2 Date: A B C D AKD4671-B Document Number Rev Power Supply, I/O Wednesday, April 04, 2007 E Sheet 2 0 of 5 A B C D E E E D3V EXT_MCLK EXT_BICK 4114_BICK JP32 R45 51 EXT 14 C59 0.1u JP39 EXT D 7 10 CLK 11 RST MKFS 16 C60 0.1u Vcc 8 GND JP35 INV PHASE 4040 JP37 LRCK JP38 DIR LRCK_SEL ERF 1 2 3 4 5 6 1A 1Y 2A 2Y 3A 3Y 14 Vcc 7 GND 4Y 4A 5Y 5A 6Y 6A 4114_INT0 4114_PDN C62 0.1u C61 0.1u R47 10k D1 U6 74HC14 8 C63 0.1u 74AC163 L HSU119 H SW1 DIR 2 U5 16 D 8 9 10 11 12 13 MCKO ENT ENP Vcc CLK LOAD CLR GND LED1 R46 1k 4114_LRCK 14 13 12 11 15 QA QB QC QD Carry THR BCFS fs-384 fs 4040 A 10 7 2 9 1 A B C D 64fs-384 32fs-384 64fs 32fs U4 74HC4040 U3 74AC74 3 4 5 6 9 7 6 5 3 2 4 13 12 14 15 1 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 VD Q9 Q10 Q11 DGND Q12 A 1 JP34 256fs 512fs 1024fs 384/768fs MCKO 13 12 11 10 9 8 1CLR 2CLR 1D 2D 1CK 2CK 1PR 2PR 1Q 2Q 1Q 2Q K DIR 1 2 3 4 5 6 1 2 3 4 5 JP36 MCLK 3 J12 EXT EXT_LRCK K 4114_MCKO JP33 DIR BICK_SEL 7 14 14 Vcc 4Y 4A 5Y 5A 6Y 6A 8 9 10 11 12 13 4670_PDN C R48 10k A C64 0.1u 1A 1Y 2A 2Y 3A 3Y K GND Vcc 4Y 4A 5Y 5A 6Y 6A 1A 1Y 2A 2Y 3A 3Y 1 2 3 4 5 6 C 1 2 3 4 5 6 HSU119 GND U8 74HC14 H SW2 PDN 2 C66 0.1u L 3 7 C65 0.1u D2 1 8 9 10 11 12 13 VCC U7 74HCU04 4.096MHz X1 1 2 R49 1M JP40 XTE C67 5p C68 5p B B EXT_MCLK2 D3V J13 EXT1 XTL JP41 MCLK2 JP42 512fs2 EXT1 10 CLK 11 RST R50 51 JP44 EXT1 16 C69 0.1u 8 U9 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 VD Q9 Q10 Q11 DGND Q12 9 7 6 5 3 2 4 13 12 14 15 1 256fs2 128fs2 64fs2 32fs2 16fs2 BICKA EXT_BICKA BICKB EXT_BICKB JP43 BICK2_SEL BCFS2 1fs2 74HC4040 A LRCKA EXT_LRCKA LRCKB EXT_LRCKB A JP45 LRCK2_SEL Title Size A2 Date: A B C D AKD4671-B Document Number Rev CLOCK Wednesday, April 04, 2007 E Sheet 0 3 of 5 A B C D E D3V E PORT1 E L10 (short) VCC 3 GND OUT 2 1 1 2 C70 0.1u TORX141 C71 0.1u R51 470 C72 10u + C73 ------OFF------ 1 IPS0 2 37 INT1 38 AVDD R VCOM AVSS 40 41 42 RX0 43 NC 44 RX1 45 46 47 48 NC TEST1 S1 SW DIP-6 D INT0 36 NC OCKS0 35 3 DIF0 OCKS1 34 4 TEST2 CM1 33 5 DIF1 CM0 32 6 NC PDN 31 4114_INT0 DIF2 DIF1 DIF0 OCKS1 CAD0 I2C 1 2 3 4 5 6 L 1 2 3 4 5 6 RX2 H RX3 12 11 10 9 8 7 U10 R52 18k 39 C74 0.47u VCC D 0.1u CAD0 7 6 5 4 3 2 1 I2C AK4114 RP1 47k C 4114_PDN C75 5p MCKO JP46 4114_MCKI 7 DIF2 XTI 30 8 IPS1 XTO 29 9 P/SN DAUX 28 10 XTL0 MCKO2 27 11 XTL1 BICK 26 4114_BICK 12 VIN SDTO 25 4114_SDTO 1 C 2 X2 11.2896MHz C76 5p DAUX LRCK 24 MCKO1 23 C78 0.1u 22 DVSS DVDD 21 VOUT 20 UOUT 19 COUT 18 BOUT 17 TX1 16 15 14 TVDD 13 C77 0.1u TX0 B DVSS B C80 10u + + 4114_LRCK C79 10u 4114_MCKO PORT2 IN VCC 3 2 GND 1 C81 0.1u A A TOTX141 Title Size A3 Date: A B C D AKD4671-B Document Number Rev DIR/DIT Wednesday, April 04, 2007 Sheet E 0 4 of 5 A B C D THR EXT_BICKA VCC INV D3V E VCC2 JP47 BICKA PHASE U12 U11 4 EXT_BICK 5 E 6 R53 10k 7 6 5 4 3 2 1 PORT4 2 GND 4 GND 6 8 10 SDTO 1 3 5 7 9 8 9 10 B1 A2 A3 21 B2 20 B3 19 B4 18 A5 B5 17 A6 B6 16 A7 B7 15 A8 B8 14 A4 4670_LRCK 4670_BICK EXT_MCLK2 RP3 47k 2 1 Slave C83 0.1u 11 Master 12 JP48 M/S DIR OE VCCA 22 VCCB 24 VCCB 23 GND MCLK2 BICKA LRCKA SDTIA VCC 1 3 5 7 9 2 GND 4 GND 6 8 10 SDTOA R54 10k Baseband JP62 BICKA 3 A1 B1 21 4 A2 B2 20 5 A3 B3 19 6 A4 B4 18 7 A5 B5 17 8 A6 B6 16 9 A7 B7 15 10 A8 B8 14 2 DIR 1 VCCA 4670_BICKA 4670_SYNCA JP63 SYNCA RP5 47k D3V 13 SDTOA1 JP50 SDTOA LOOP SDTIA 74AVC8T245 E 7 6 5 4 3 2 1 RP4 47k C84 0.1u GND GND 7 6 5 4 3 2 1 PORT3 7 6 5 4 3 2 1 RP2 47k DSP EXT_LRCKA C82 0.1u BICKA MCLK BICK LRCK SDTI VCC 7 A1 BICKB 3 EXT_LRCK JP49 PLLBT OE 11 GND 12 GND 22 VCCB 24 VCCB 23 GND 13 C85 0.1u 74AVC8T245 VCC U13 D D DAUX D3V I2C I2C 4670_I2C MCLK2 JP51 ADC SDTI_SEL 4114_SDTO JP57 I2C PIN EXT_MCLK EXT_MCLK2 I2C (CAD0) CAD0 C 4-WIRE R55 10k R56 10k PORT5 10 8 6 4 2 9 7 5 3 1 CSN CCLK/SCI CDTI/SDA CDTO/SDA(ACK) R58 R59 R60 470 470 470 MCKO 3 A1 B1 21 4 A2 B2 20 5 A3 B3 19 6 A4 B4 18 7 A5 B5 17 8 A6 B6 16 CSN/CAD0 CCLK/SCL 9 A7 B7 15 10 A8 B8 14 A1 B1 21 4 A2 B2 20 5 A3 B3 19 6 A4 B4 18 7 A5 B5 17 8 A6 B6 16 9 A7 B7 15 10 A8 B8 14 2 DIR 1 VCCA 4670_SDTO 4670_MCKO 4670_SDTI 4670_MCKI D3V C86 0.1u 11 GND 12 GND OE 22 VCCB 24 VCCB 23 GND 13 D3V C88 0.1u C87 0.1u 2 DIR 1 VCCA 11 GND 12 GND OE 22 VCCB 24 VCCB 23 GND 13 14 7 B 4670_CDTO 1A 2A 3A 4A 5A 6A R61 1k 1Y 2Y 3Y 4Y 5Y 6Y INV EXT_BICKB 2 4 6 8 10 12 JP54 THR BICKB PHASE CDTI/SDA EXT_LRCKB Vcc VCC2 GND U18 PORT7 SDTIA 1A1 1B1 13 5 1A2 1B2 12 2 1DIR 1OE 15 6 2A1 2B1 11 EXT_MCLK2 4670_SDTIB 4670_SDTIA JP60 SDTIA CTRL SAR ADC SDTOB1 SDTOA1 D3V 7 2A2 2B2 10 3 2DIR 2OE 14 1 VCCA VCCB 16 GND GND 9 C95 0.1u A 8 7 6 5 4 3 2 1 PORT6 SDTIB 4 SDTIB D3V C C90 0.1u JP61 JP56 D3V GND U15 74HC14 JP53 CTRL_SEL2 74LVC07 DIN CSN SCLK Vcc 7 8 9 10 11 12 13 VCC2 U16 C91 0.1u 9 7 5 3 1 14 4Y 4A 5Y 5A 6Y 6A 74AVC8T245 1 3 5 9 11 13 8 6 4 VCCIO 2 1A 1Y 2A 2Y 3A 3Y I2C (ACK) CTRL DOUT 10 1 2 3 4 5 6 4-WIRE (CDTO) 74AVC8T245 JP52 CTRL_SEL C89 0.1u R57 10k VCC U14 DIR 3 MCLK2 BICKB LRCKB SDTIB VCC 1 3 5 7 9 2 GND 4 GND 6 8 10 SDTOB R62 10k Bluetooth U17 JP64 BICKB 3 A1 B1 21 4 A2 B2 20 5 A3 B3 19 6 A4 B4 18 7 A5 B5 17 8 A6 B6 16 4670_BICKB 4670_SYNCB JP65 SYNCB B 9 A7 B7 15 10 A8 B8 14 2 DIR 1 VCCA 7 6 5 4 3 2 1 RP6 47k D3V RP7 47k C92 0.1u 4670_SDTOB 4670_SDTOA 11 GND 12 GND OE 22 VCCB 24 VCCB 23 GND 13 C93 0.1u 74AVC8T245 SDTOB1 JP55 SDTOB LOOP SDTIB C94 0.1u A 74AVC4T245 Title Size AKD4671-B Document Number Date: A B C D Rev LOGIC A2 Wednesday, April 04, 2007 E Sheet 0 5 of 5