TI BQ24185 Fully integrated switch-mode one-cell li-ion charger with full usb compliance and accessory power connection Datasheet

bq24185
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SLUSA43 – SEPTEMBER 2010
Fully Integrated Switch-Mode One-Cell Li-Ion Charger with Full USB Compliance and
Accessory Power Connection
Check for Samples: bq24185
FEATURES
•
1
•
2
•
•
•
•
•
•
•
•
Charge Faster than Linear Chargers From
Current Limited Input Sources
High-Accuracy Voltage and Current Regulation
– Input Current Regulation Accuracy: ±5%
(100mA, 500mA)
– Charge Voltage Regulation Accuracy:
±0.5% (25°C), ±1% (0 – 125°C)
– Charge Current Regulation Accuracy: ±5%
300mA, 5V Boost Mode for USB OTG Support
Accessory Power Output (DCOUT)
Input Voltage Based Dynamic Power
Management
Safety Limit Register for Maximum Charge
Voltage and Current Limiting
High-Efficiency Mini-USB/AC Battery Charger
for Single-Cell Li-Ion and Li-Polymer Battery
Packs
20V Absolute Maximum and 16.5V Operation
Input Voltage Rating
Built-in Input Current Sensing and Limiting
•
•
•
•
•
•
•
Integrated Power FETs for Up to 1.5A Charge
Rate
Programmable Charge Parameters through
I2C™ compatible Interface (up to 3.4 Mbps)
Synchronous Fixed-Frequency PWM
Controller Operating at 3 MHz With 0% to
99.5% Duty Cycle
Safety Timer and Software Watchdog
Reverse Leakage Protection Prevents Battery
Drainage
Thermal Regulation and Protection
Status Outputs for Charging and Faults
25-Pin WCSP Package
APPLICATIONS
•
•
•
Mobile Phones and Smart Phones
Portable Media Players
Handheld Devices
DESCRIPTION
The bq24185 is a compact, flexible, high-efficiency, USB-friendly switch-mode charge management device for
single-cell Li-ion and Li-polymer batteries used in a wide range of portable applications. The charge parameters
is programmable using an I2C compatible interface. The bq24185 integrates a synchronous PWM controller,
power MOSFETs, input current sensing and overvoltage protection, high-accuracy current and voltage regulation,
and charge termination, into a small WCSP package.
POWER FOR
ACCESSORY
C8
1 µF
SYSTEM
VBUS
C1
1 µF
RSNS
68 mW
DCOUT
VBUS
SW
C4
10 nF
C3
4.7 µF
C2
10 µF
BOOT
PMID
TEMP
PACK +
PGND
HOST
bq24185
CSIN
PACK -
CSOUT
DRV
C7
1 µF
VBUS
D+
D-
VBUS
C5
0.1 µF
PSEL
TS
USB PHY
GND
C6
1 µF
VAUX
R1
10 kW
R2
10 kW
R4
10 kW
CD
INT
Hardware Disable
STAT
SCL
SDA
R3
4 kW
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
I2C is a trademark of Phillips Electronics.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010, Texas Instruments Incorporated
bq24185
SLUSA43 – SEPTEMBER 2010
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
DESCRIPTION (CONTINUED)
The bq24185 charges the battery in three phases: conditioning, constant current and constant voltage. Charge
current is programmable using the I2C interface. Additionally, the input current can be limited to a host
programmable threshold to maintain maximum charge current from current-limited sources, such as USB ports.
Charge is terminated based on user-selectable minimum current level. A software watchdog provides a safety
backup for I2C interface while a safety timer prevents overcharging the battery. During normal operation,
bq24185 automatically restarts the charge cycle if the battery voltage falls below an internal threshold and
automatically enters sleep mode or high impedance mode when the input supply is removed. The charge status
is reported to the host using the I2C interface. During the charging process, the bq24185 monitors its junction
temperature (TJ) and reduces the charge current if TJ increases to 125°C. To support USB OTG peripherals, the
bq24185 contains boost circuitry that supplies VVBUS at 5.05V at up to 300mA by boosting the battery voltage.
The bq24185 is available in 25-pin WCSP package.
ORDERING INFORMATION
VOVP
I2C ADDRESS
bq24185YFFR
16.5 V
6B
bq24185YFFT
16.5 V
6B
PART NUMBER
(1)
(2)
(1) (2)
The YFF package is available in the following options:
R – taped and reeled in quantities of 3,000 devices per reel.
T – taped and reeled in quantities of 250 devices per reel.
This product is RoHS compatible, including a lead concentration that does not exceed 0.1% of total product weight, and is suitable for
use in specified lead-free soldering processes. In addition, this product uses package materials that do not contain halogens, including
bromine (Br) or antimony (Sb) above 0.1% of total product weight.
ABSOLUTE MAXIMUM RATINGS (1) (2)
over operating free-air temperature range (unless otherwise noted)
LIMITS
UNIT
Supply voltage range (with respect to PGND)
VBUS
–2 to 20
V
Input voltage range (with respect to and PGND)
SCL, SDA, PSEL, CSIN, CSOUT, DRV, DCOUT, INT
–0.3 to 7
V
PMID, STAT
–0.3 to 20
SW, BOOT
–0.7 to 20
Output voltage range (with respect to and PGND)
Voltage difference between CSIN and CSOUT inputs (VCSIN –VCSOUT)
Voltage difference between BOOT and SW inputs (VBOOT –VSW)
Output sink
Output current
Output current (average)
V
±7
V
–0.3 to 7
V
INT
5
STAT
10
DCOUT
1.5
A
DRV
10
mA
SW
2
A
mA
TA
Operating free-air temperature range
–30 to +85
°C
TJ
Junction temperature range
–40 to +125
°C
Tstg
Storage temperature
–45 to +150
°C
(1)
(2)
2
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to GND if not specified. Currents are positive into, negative out of the specified terminal. Consult Packaging
Section of the data book for thermal limitations and considerations of packages.
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DISSIPATION RATINGS
(1)
PACKAGE
RqJA
RqJC
TA < 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
WCSP-25
60°C/W (1)
1.57°C/W
540 mW
5.4 mW/°C
Using JEDEC 2s2p PCB standard.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
Supply voltage, VBUS
Operating junction temperature range, TJ
(1)
NOM
MAX
UNIT
4.0
16 (1)
V
0
125
°C
The inherent switching noise voltage spikes should not exceed the absolute maximum rating on either the BOOT or SW pins. A tight
layout minimizes switching noise.
ELECTRICAL CHARACTERISTICS
Circuit of Figure 3, VVBUS = 5V, HZ_MODE=0, CD=0, TJ = –40°C to 125°C and TJ = 25°C for typical values (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT CURRENTS
VVBUS > VVBUS(min), PWM switching
IVBUS
IVBUS_LEAK
IBAT_DCOUT
IBAT_HIZ
VVBUS supply current for control
10
5
mA
0°C< TJ < 85°C, EN=0 or HZ_MODE=1
650
µA
5
µA
800
µA
0°C< TJ < 85°C, VCSOUT = 4.2 V, No Input connected,
DCOUT disabled SCL,SDA=0V or 1.8V
30
µA
0°C< TJ < 85°C, VCSOUT = 4.2 V, High Impedance
mode, DCOUT disabled, VVBUS = 5V,
SCL,SDA=0V or 1.8V
60
µA
V
Leakage current from battery to VBUS pin
0°C< TJ < 85°C, VCSOUT = 4.2 V, No input connected
Battery Current when using DCOUT
DCOUT = enabled, VBAT = 4.2V, DCOUT_ILIM=1A,
IDCOUT=750mA
Battery discharge current in High Impedance
mode, (CSIN, CSOUT, SW pins)
mA
VVBUS > VVBUS(min), PWM NOT switching
VOLTAGE REGULATION
VOREG
Output charge voltage programmable range
Voltage regulation accuracy
Operating in voltage regulation, programmable
3.5
4.44
–0.5%
0.5%
–1%
1%
550
1550
VICHRG = 37.4 mV to 44.2 mV
–3.5%
3.5%
VICHRG > 44.2 mV
–3.0%
3.0%
TA = 25°C
CURRENT REGULATION - FAST CHARGE
IOCHARGE
Output charge current programmable range
Regulation accuracy for charge current
across RSNS
VIREG = IOCHARGE × RSNS
VPRECHG ≤ VCSOUT < VOREG, VVBUS>VSLP,
RSNS = 68 mΩ, Programmable
mA
PSEL, CD LOGIC LEVEL
VIL
Input low threshold level
PSEL, CD falling
VIH
Input high threshold level
PSEL, CD rising
1.2
0.4
25
V
V
CHARGE TERMINATION DETECTION
ITERM
Termination charge current
VCSOUT > VOREG–VRCH , VVBUS>VSLP,
RSNS = 68 MΩ, Programmable
ITERM_dgl
Deglitch time for charge termination
Both rising and falling, 2-mV over- drive,
tRISE, tFALL = 100 ns
Regulation accuracy for termination current
across RSNS
VIREG_TERM = IOTERM × RSNS
200
30
ms
VTERM = 1.7 mV
–40%
40%
VTERM = 3.4 mV to 6.8 mV
–16%
16%
VTERM = 6.8 mV to 13.6 mV
–11%
11%
VTERM ≥ 13.6 mV
–5.5%
5.5%
Battery Detection sink current before charge
done
mA
–550
µA
INPUT BASED DYNAMIC POWER MANAGEMENT
VIN_DPM
The threshold when input based DPM loop
kicks in
Charge mode, programmable
4.15
4.71
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ELECTRICAL CHARACTERISTICS (continued)
Circuit of Figure 3, VVBUS = 5V, HZ_MODE=0, CD=0, TJ = –40°C to 125°C and TJ = 25°C for typical values (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
DPM loop kick-in threshold tolerance
TYP
–2%
MAX
UNIT
2%
FAULTY ADAPTER PROTECTION
VVBUS (MIN)
Faulty adapter threshold
3.6
Deglitch time for Faulty adapter
4.0
30
Hysteresis for faulty adapter protection
VVBUS Rising
100
Current source for faulty adapter protection
tINT
3.8
20
Detection Interval
30
V
ms
200
mV
40
mA
2
s
INPUT CURRENT LIMITING
IIN_LIMIT
USB charge mode, current
pulled from PMID
Input current limiting threshold
IIN_LIMIT = 100 mA
90
95
100
IIN_LIMIT = 500 mA
450
475
500
IIN_LIMIT = 800 mA
700
755
800
mA
DCOUT
RDCOUT
DCOUT Pass FET on-resistance
IDCOUT = 500 mA
ILIM_DCOUT
DCOUT current limit programmable range
Programmable via I2C
tDGL_DCOUT
Deglitch time from DCOUT current-limit event
to DCOUT latch-off
ILIM_DCOUT
300
mΩ
1400
mA
14.5
Programmable via I2C
DCOUT current limit range
350
ILIM_DCOUT = 350mA
270
ILIM_DCOUT = 750mA
650
750
ILIM_DCOUT = 1050mA
800
1050
ILIM_DCOUT = 1400mA
1050
1400
100
120
ms
350
mA
BATTERY RECHARGE THRESHOLD
VRCH
Recharge threshold voltage
Below VOREG
Deglitch time
VCSOUT decreasing below threshold,
tFALL = 100 ns, 10-mV overdrive
150
130
mV
ms
STAT OUTPUTS
VOL(STAT)
Low-level output saturation voltage, STAT
IO = 10 mA, sink current
High-level leakage current
Voltage on STAT pin is 5V
Low-level output saturation voltage, INT
IO = 1 mA, sink current
0.4
V
High-level leakage current
Voltage on INT pin is 5V
1
µA
Output low threshold level
IO = 10 mA, sink current
0.4
V
Input low threshold level
V(pull-up) = 1.8 V, SDA and SCL
0.4
V
Input high threshold level
V(pull-up) = 1.8 V, SDA and SCL
I(bias)
Input bias current
V(pull-up) = 1.8 V, SDA and SCL
fSCL
SCL clock frequency
VOL(INT)
0.5
V
1
µA
I2C BUS LOGIC LEVELS AND TIMING CHARACTERISTICS
VOL
1.2
V
1
µA
3.4
MHz
SLEEP COMPARATOR
VSLP
Sleep-mode entry threshold,
VBUS-VCSOUT
2.3 V ≤ VCSOUT ≤ VOREG, VVBUS falling
VSLP-EXIT
Sleep-mode exit hysteresis
2.3 V ≤ VCSOUT < VOREG
Deglitch time for VBUS rising above
VSLP+VSLP_EXIT
Rising voltage, 2-mV over drive, tRISE = 100 ns
VUVLO
IC active threshold voltage
VVBUS rising
3.05
3.3
VUVLO_HYS
IC active hysteresis
VVBUS falling from above VUVLO
120
150
Internal top reverse blocking MOSFET
on-resistance
IIN_LIMIT = 500 mA, Measured from VVBUS to PMID
110
210
mΩ
Internal top N-channel Switching MOSFET
on-resistance
Measured from PMID to SW
130
250
mΩ
Internal bottom N-channel MOSFET
on-resistance
Measured from SW to PGND
125
210
mΩ
0
40
100
mV
140
200
260
mV
30
ms
UVLO
3.55
V
mV
PWM
fOSC
4
Oscillator frequency
3.0
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ELECTRICAL CHARACTERISTICS (continued)
Circuit of Figure 3, VVBUS = 5V, HZ_MODE=0, CD=0, TJ = –40°C to 125°C and TJ = 25°C for typical values (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
Frequency accuracy
DMAX
Maximum duty cycle
DMIN
Minimum duty cycle
TYP
–10%
MAX
UNIT
10%
99.5%
0
Synchronous mode to non-synchronous
mode transition current threshold (1)
Low-side MOSFET cycle-by-cycle current sensing
VDRV
Internal bias voltage regulator
IDRV = 10 mA
IDRV
DRV Output Current
External load on DRV
VDO_DRV
DRV Dropout Voltage (VVBUS – VDRV)
100
5
5.2
mA
5.45
10
IVBUS = 1A, VVBUS = 5 V, IDRV = 10 mA
340
VUVLO < VVBUS<VSLP
V
mA
750
mV
BOOST MODE OPERATION FOR VBUS (OPA_MODE=1, HZ_MODE=0)
VBUS_BST
Boost output voltage (to VBUS)
2.5V < VCSOUT < 4.5V
4.90
IBO
Maximum output current for boost
VBUS_BST=5.05V, 3V<VCSOUT<4.5V
300
IBLIMIT
Cycle by cycle current limit for boost
VBUS_B=5.05V, 2.5V<VCSOUT<4.5V
VBUSOVP
Over voltage protection threshold for boost
(VBUS pin)
Threshold over VBUS to turn off converter during boost
VBUSOVP hysteresis
VBUS falling from above VBUSOVP
Inductor current threshold for PWM to PFM
mode transition
During the boost
5.05
5.20
1.0
Lower VBUS voltage threshold where
During PFM boost mode
converter begins switching during PFM mode
5.8
6.0
A
6.2
V
162
mV
75
mA
–1.5
–0.5
During boosting
2.5
Before boost starts
2.9
3.05
4.9
5.05
VBATMIN
Minimum battery voltage for boost
VBATMAX
Maximum battery voltage for boost (CSOUT
pin)
VCSOUT rising edge during boost
VBATMAX hysteresis
VCSOUT falling from above VBATMAX
Input OVP threshold voltage
Threshold over VVBUS to turn off converter during charge
VOVP hysteresis
VVBUS falling from above VOVP
Input High threshold
VVBUS Rising, Threshold where IBAT falls to 50 mA
VIN_HIGH_USB hysteresis
VVBUS falling from above VIN_HIGH
tOVP-dgl
OVP deglitch time
VVBUS rising or falling
ILIMIT
Cycle-by-cycle current limit for charge
Charge mode operation
1.8
2.4
3.0
Precharge to fast charge threshold
VCSOUT rising
1.9
2.0
2.1
VPRECHG hysteresis
VCSOUT falling from above VPRECHG
Precharge charge charging current
VCSOUT ≤ VSHORT and VIN_HIGH < VVBUS < VOVP
4.75
V
mA
200
%VBUS
V
V
mV
PROTECTION
VOVP
VIN_HIGH
VPRECHG
IPRECHG
TSHTDWN
TCF
tWATCHDOG
VHOT
VWARM
VCOLD
ITS
(1)
16
9.5
Timeout for the watchdog timer
Watchdog timer
33.5
50.0
Corresponds to 55°C, VTS Falling
TS Hot Threshold Hysteresis
VTS Rising
TS Warm Threshold
Corresponds to 45°C VTS Falling
TS Warm Threshold Hysteresis
VTS Rising
TS Cold Threshold
Corresponds to 5°C, VTS Rising
TS Cold Threshold Hysteresis
VTS Falling
ms
66.5
°C
°C
120
°C
s
20%
0.160
0.169
0.225
1.10
95
Resistance on TS that translates to open circuit on TS
100
V
mV
0.240
V
mV
1.14
75
TS Bias Current
mA
10
12.5
1.06
V
165
12.5
0.210
A
mV
12
0.153
V
mV
100
–20%
TS Hot Threshold
10.1
32
Safety timer accuracy
TS Open Resistance
9.8
V
mV
150
Thermal hysteresis
Charge current begins to taper down
17
185
Thermal trip
Thermal regulation threshold
16.5
V
mV
105
200
µA
kΩ
Bottom N-channel MOSFET always turns on for ~60 ns and then turns off if current is too low.
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SIMPLIFIED BLOCK DIAGRAM
PMID
DRV
5.2V
Reference
Q1
VBUS
BOOT
Charge
Pump
Q2
Input Current Limit
Amplifier
DC-DC
CONVERTER
PWM LOGIC
AND
COMPENSATION
+
+
VIN-DPM
Amplifier
SW
VDRV
Q3
PGND
9.8V
16.5V
+
+
High-Input
Comparator
Thermal Reg
Amplifier
+
OVP
Comparator
CSIN
125°C
TJ
IIN_LIMITV INDPM
SCL
V ITERM
+
+
+
-
SDA
Gm
amp
IOUTREG
Amplifier
Termination
Comparator
V ICHRG
VBATREG
Amplifier
V OREG
Recharge
Comparator
CD
130mV
+
2
I C and
CHARGE
CONTROLLER
CSOUT
+
-
+
VPRECHG Comparator
Sleep
Comparator
+
Q4
VIN
VDRV
VPRECHG
VBAT
+
PSEL
VHIGH
Comparator
Q5
VIN
TMR
STAT
2X
SAFETY
TIMERS
50mA Precharge
Current Source
DCOUT
TIMER
FAULT
INT
DCOUT _ILIM
400 mA
max charge DISABLE
REF
+
+
+
REF
+
Charge
Pump
TS COLD
TS WARM
TS HOT
TS
100uA
Figure 1. Simplified Block Diagram (Charge Mode, OPA_MODE = 0)
6
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PMID
DRV
5.2V
Reference
Q1
VBUS
BOOT
Output Voltage
Amplifier
Output Current Limit
Amplifier
+
5.05V
400mA
Q2
+
Charge
Pump
Feedback
DC-DC
CONVERTER
PWM LOGIC
AND
COMPENSATION
SW
VDRV
+
6V
+
SCL
+
CbC Current
Limit
OVP
Comparator
1A
75mA
PFM Mode
Comparator
Q3
PGND
Low Battery
SDA
CSIN
VBATMIN
+
CSOUT
Battery OVP
CD
+
I2C and
CHARGE
CONTROLLER
VBATMAX
Sleep
Comparator
VDRV
Q4
V IN
VBAT
+
PSEL
Q5
TMR
STAT
2X
SAFETY
TIMERS
DCOUT
TIMER
FAULT
INT
DCOUT_ILIM
+
TS
Charge
Pump
Figure 2. Simplified Block Diagram (Boost Mode, OPA_MODE = 1)
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DEVICE INFORMATION
PIN CONFIGURATION
TOP VIEW
1
2
3
4
5
A
VBUS
VBUS
BOOT
SCL
SDA
B
PMID
PMID
PMID
INT
CD
C
SW
SW
SW
PSEL
STAT
D
PGND
PGND
PGND
DCOUT
DCOUT
E
CSIN
TS
DRV
CSOUT
CSOUT
2.2 mm x 2.4 mm 25-pin WCSP
PIN FUNCTIONS
NAME
PIN NO.
I/O
DESCRIPTION
VBUS
A1, A2
I/O
Charger Input Voltage. Connect to an input supply up to 16V. Bypass VBUS to PGND with a 1µF ceramic
capacitor. During boost mode, VBUS is regulated to 5V at up to 300mA to power USB OTG peripherals.
BOOT
A3
O
High-Side MOSFET Gate Driver Supply. Connect a 10nF ceramic capacitor (voltage rating above 10V) from
BOOT pin to SW pin to supply the gate drive for the high side MOSFET.
SCL
A4
I
I2C interface clock. Connect SCL to the logic rail through a 10kΩ resistor.
SDA
A5
I/O
I2C interface data. Connect SCL to the logic rail through a 10kΩ resistor.
PMID
B1, B2, B3
O
Connection Point Between Reverse Blocking MOSFET and High-Side Switching MOSFET. Bypass PMID to
PGND with a minimum of 3.3µF ceramic capacitor. Use caution when connecting an external load to PMID.
The PMID output is not current limited. Any short on PMID will result in damage to the IC.
INT
B4
O
Host Interface Status Output. INT is a low voltage open drain output used to signal charge status to the host
processor. INT is pulled low during charging. When charging is complete or when charging is disabled, INT is
high impedance. When a fault occurs, a 128µs pulse is sent out as an interrupt for the host. INT is
enabled/disabled using the EN_STAT bit in the control register. Connect INT to a logic rail through a 10kΩ
resistor to communicate with the host processor.
CD
B5
O
Hardware Disable Input. Connect CD to GND to enable charge. Drive CD high to disable charge and place
the bq24185 into high impedance mode. Toggling CD resets the safety timer when in DEFAULT mode, but
does not reset the timer when in host mode. CD is pulled to PGND through a 100kΩ internal resistor.
SW
C1, C2,
C3
O
Inductor Connection. Connect the switched side of the inductor to SW.
PSEL
C4
I
USB Source Detection Input. Drive PSEL high to indicate a USB source is connected to the input and the PC
mode default values should be used. When PSEL is high, the IC starts up with a 100mA input current limit.
Drive PSEL low to indicate that an AC Adapter is connected to the input. When PSEL is low, the IC starts up
with no input current limit and a 1A charge current. PSEL has an internal 100kΩ pullup resistor.
STAT
C5
O
Status Output. STAT is an open drain output that is pulled low during charging. When charging is complete or
when charging is disabled, STAT is high impedance. When a fault occurs, a 128µs pulse is sent out as an
interrupt for the host. STAT is enabled/disabled using the EN_STAT bit in the control register. Connect STAT
to a logic rail using an LED for visual indication or through a 10kΩ resistor to communicate with the host
processor.
PGND
D1, D2,
D3
Power ground. Connect to the ground plane for the circuit.
DCOUT D4, D5
O
Accessory Power Output. DCOUT is connected to the battery through an internal pass FET. When enabled
through I2C, DCOUT is connected to the battery. When disabled, DCOUT is high-impedance. Bypass DCOUT
to PGND with at least a 1µF ceramic capacitor.
CSIN
I
Charge Current-Sense Input. Battery current is sensed via the voltage drop across an external sense resistor.
Bypass CSIN to PGND with a 0.1µF ceramic capacitor.
8
E1
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PIN FUNCTIONS (continued)
I/O
DESCRIPTION
TS
NAME
E2
PIN NO.
I
Battery Pack NTC Monitor. Connect TS to a 4.7kΩ NTC thermistor. During DEFAULT mode, when VTS >
VCOLD or VTS<VHOT charging is suspended. If VHOT < VTS < VWARM charging current is reduced. The faults are
reported by the I2C interface. During host mode, the TS function is active, but does not affect charging. The
faults are only reported by the I2C interface.
DRV
E3
O
Gate Drive Supply. DRV is the supply for the gate drive of the internal MOSFETs. Bypass DRV to PGND with
a 1µF ceramic capacitor. DRV may be used to drive external loads up to 10mA. DRV is active whenever the
input is connected.
I
Battery voltage and Current Sense Input. Connect to the positive terminal of the battery pack. CSOUT is also
the supply for the DCOUT output and VBUS during boost mode. Bypass CSOUT to PGND with 1µF ceramic
capacitor.
CSOUT E4, E5
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TYPICAL APPLICATION CIRCUITS
VBUS = 5V, IIN_LIMIT = 500mA, ICHARGE = 1A, VBAT = 3.5--4.44V (Adjustable), Safety Timer = 27 minute default w/
12 seconds watchdog
C8
1µF
POWER FOR
ACCESSORY
SYSTEM
VBUS
C1
1 µF
DCOUT
VBUS
RSNS
68 mW
SW
C4
10 nF
C2
10 µF
BOOT
PMID
C3
4.7 µF
PACK+
TEMP
PGND
HOST
bq24185
CSIN
PACK-
CSOUT
DRV
C7
1 µF
VBUS
PSEL
C6
1 µF
TS
VAUX
R1
10 kW
R2
10 kW
R4
10 kW
SCL
Hardware Disable
CD
INT
GND
VBUS
USB PHY
STAT
D+
D-
C5
0.1 µF
SDA
R3
4 kW
Figure 3. I2C Controlled 1-Cell USB Charger Application Circuit
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TYPICAL CHARACTERISTICS
5 V/div
VVBUS
VBAT
VBAT
2 V/div
IOUT
500 mA/div
2 V/div
IOUT
5 V/div
200 mA/div
VINT/ STAT
5 V/div
VINT/ STAT
“No Battery” Fault Interrupt
t -Time - 4 ms/div
Figure 4. Adapter Insertion
t -Time - 2 s/div
Figure 5. Battery Insertion/Removal
5 V/div
VVBUS
VVBUS
1 V/div
VVBUS < 3.8 V
2 V/div
VBAT
IVBUS
20 mA/div
500 mA/div
IOUT
5 V/div
2 V/div
VINT/ STAT
VINT/ STAT
"Faulty Adapter" Fault Interrupt
t -Time - 4 ms/div
t -Time - 4 ms/div
Figure 6. PWM Charging Waveforms
Figure 7. Faulty Adapter Detection
VVBUS = 5 V,
VBAT = 3.6 V
2 V/div
VVBUS
1 V/div
IVBUS
VSW
20 mA/div
2 V/div
IL
500 mA/div
VINT/ STAT
"Faulty Adapter" Fault Interrupt
t -Time - 2 ms/div
t -Time - 1 s/div
Figure 8. Faulty Adapter Detection
(Showing Continuous Detection)
Figure 9. Cycle by Cycle Current Limit
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TYPICAL CHARACTERISTICS (continued)
VSW
VSW
2 V/div
VBAT
2 V/div
1 V/div
VBAT
200 mA/div
IVBUS
1 V/div
200 mA/div
IVBUS
t -Time - 400 ms/div
t -Time - 400 ms/div
Figure 10. Input Current Limit Transition
USB500 to USB100
Figure 11. Input Current Limit Transition
USB100 to USB500
VSW
1 V/div
2 V/div
VBAT
VSCL
1 V/div
200 mA/div
200 mA/div
IOUT
IVBUS
t -Time - 400 ms/div
t -Time - 200 ms/div
Figure 12. Input Current Limit Transition
USB500 to 750mA
Figure 13. Charge Current Transition
550mA to 1.05A Using I2C
2 V/div
VVBUS
1 V/div
VBAT
IVBUS
VPSEL
2 V/div
VBAT
1 V/div
IVBUS
Faulty Adapter
Detection
200 mA/div
50 mA/div
t -Time - 10 ms/div
Figure 14. Startup Into Default Mode
No Battery Connected
12
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t -Time - 1 ms/div
Figure 15. PSEL Transition
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TYPICAL CHARACTERISTICS (continued)
RLOAD = 11 W to 1 W,
VBAT = 4 V
2 V/div
VCD
1 V/div
VDCOUT
200 mA/div
IDCOUT
1 V/div
VBAT
IVBUS
500 mA/div
t -Time - 4 ms/div
t -Time - 10 ms/div
Figure 16. Enable/Disable Using CD
Figure 17. DCOUT OCP Response
VVBUS = 5.5 V to 17 V
VVBUS
10 V/div
1 V/div
VDCOUT
IOUT
500 mA/div
IDCOUT
ISW
5 V/div
t -Time - 2 ms/div
t -Time - 10 ms/div
Figure 18. Hotplug 1000µF Capacitor into DCOUT
Figure 19. OVP Response
400
VVBUS = 5.5 V to 10.5 V
VVBUS
5 V/div
500 mA/div
USB100
Trickle Charge
VSW
5 V/div
t -Time - 10 ms/div
VDO(VBUS-DRV) - V
350
IOUT
500 mA/div
VVBUS = 5 V,
IVBUS = 1 A,
IDRV = 10 mA
300
250
200
150
100
-40
-20
0
20
40
60
80
100
120
140
TA - Free-Air Temperature - °C
Figure 20. VINHIGH Response
Figure 21. DRV Dropout vs TA
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TYPICAL CHARACTERISTICS (continued)
VVBUS = 0 V to 5.5 V to 0 V
VVBUS
IDRV
2 V/div
10 mA/div
VDRV
5.1 V Offset
VDRV
2 V/div
10 mV/div
t -Time - 20 ms/div
t -Time - 2 ms/div
Figure 22. DRV Startup/Shutdown
Figure 23. DRV Load Transient
5.15
100
VVBUS = 5 V
VBUS = 5.5 V
90
80
5.13
VOUT = 3.5 V
Efficiency - %
70
VDRV - V
5.11
5.09
60
VOUT = 4.45 V
50
40
30
20
5.07
10
5.05
0
1
2
3
4
5
6
7
8
9
10
0
0.01
Figure 24. DRV Load Regulation
14
0.1
1
10
Current - A
IDRV - mA
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Figure 25. Charger Efficiency
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DETAILED DESCRIPTION
The bq24185 is a highly integrated synchronous switch-mode charger featuring integrated MOSFETs and small
external components, targeted at extremely space-limited portable applications powered by 1-cell Li-Ion or
Li-polymer battery pack. For current limited power source, such as a USB host or hub, the high efficiency
converter is critical in fully utilizing the input power capacity and quickly charging the battery. Due to the high
efficiency in a wide range of the input voltage and battery voltage, the switching mode charger is a good choice
for high speed charging with less power loss and better thermal management.
The bq24185 has two operation modes: charge mode and high impedance mode. In charge mode, the bq24185
supports a precision Li-ion or Li-polymer charging system for single-cell applications. In high impedance mode,
the bq24185 stops charging and operates in a mode with very low current from IN and battery, to effectively
reduce the power consumption when the portable device in standby mode. Through proper control, bq24185
achieves the smooth transition among different operation modes.
Charge Mode Operation
Adapter Plug IN
Watchdog Timer Expired
and Not Active, no active
host communication
VUVLO < VIN < VOVP?
No
Yes
Good Adapter
connected?
No
Wait 2s
Yes
Begin Safety Timer
Yes
VHIGH<VIN<VOVP
Enable 50mA
precharge current
Timer 2x
STAT = 0
No
No
VBAT > 2V?
Enable 50mA
precharge current
STAT = 0
Yes
Begin DEFAULT
Mode Battery
Charge Cycle
Figure 26. Startup on Adapter Plug-In in DEFAULT Mode
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Adapter Plug IN
Watchdog Active
Active Host
Communication
VUVLO < VIN < VOVP?
No
Yes
Hi-Z bit = 0?
No
Enable Hi-Z Mode
Yes
/CE bit = 0?
No
Yes
Good Adapter
connected?
No
Wait 2s
Yes
Begin Safety Timer
Yes
VHIGH<VIN<VOVP
Enable 50mA
precharge current
Timer 2x
STAT = 0
No
No
VBAT > 2V?
Enable 50mA
precharge current
STAT = 0
Begin HOST
Mode Battery
Charging
Figure 27. Startup on Adapter Plug-In in Host-Controlled Mode
Charge Profile
In charge mode, bq24185 has five control loops to regulate input voltage, input current, charge current, charge
voltage and device junction temperature. During the charging process, all five loops are enabled and the one that
is dominant will take over the control. The bq24185 supports a precision Li-ion or Li-polymer charging system for
single-cell applications. Figure 28 indicates a typical charge profile without input current regulation loop and it is
similar to the traditional CC/CV charge curve, while Figure 28 shows a typical charge profile when input current
limiting loop is dominant during the constant current mode, and in this case the charge current is higher than the
input current so the charge process is faster than the linear chargers. For bq24185, the input current limits, the
charge current, termination current, and charge voltage are all programmable using I2C interface.
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Precharge
Phase
Current Regulation
Phase
Voltage Regulation
Phase
Regulation
voltage
Regulation
Current
Charge Voltage
VSHORT
Charge Current
Termination
ISHORT
Precharge
(Linear Charge)
Fast Charge
(PWM Charge )
(a) Without input current limit (default when PSEL = 1)
Precharge
Phase
Current Regulation
Phase
Voltage Regulation
Phase
Regulation
voltage
Charge Voltage
VSHORT
Charge Current
Termination
I SHORT
Precharge
(Linear Charge)
Fast Charge
(PWM Charge)
(b) With input current limit (default when PSEL = 0)
Figure 28. Typical Charging Profile of bq24185
PWM Controller in Charge Mode
The bq24185 provides an integrated, fixed 3 MHz frequency voltage-mode controller with Feed-Forward function
to regulate charge current or voltage. This type of controller is used to help improve line transient response,
thereby simplifying the compensation network used for both continuous and discontinuous current conduction
operation. The voltage and current loops are internally compensated using a Type-III compensation scheme that
provides enough phase margin for stable operation, allowing the use of small ceramic capacitors with very low
ESR. There is a 0.5V offset on the bottom of the PWM ramp to allow the device to operate between 0% to 99.5%
duty cycles.
The bq24185 has two back to back common-drain N-channel MOSFETs at the high side and one N-channel
MOSFET at low side. An input N-MOSFET (Q1) prevents battery discharge when VBUS is lower than VVBUS (MIN).
The second high-side N-MOSFET (Q2) behaves as the switching control switch (see Figure 1). A charge pump
circuit is used to provide gate drive for Q1, while a boot strap circuit with external boot-strap capacitor is used to
boost up the gate drive voltage for Q2.
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Cycle-by-cycle current limit is sensed through the internal sense MOSFETs for Q2 and Q3. The threshold for Q2
is set to a nominal 2.5-A peak current. The low-side MOSFET (Q3) also has a current limit that decides if the
PWM Controller will operate in synchronous or non-synchronous mode. This threshold is set to 100mA and it
turns off the low-side N-channel MOSFET (Q3) before the current reverses, preventing the battery from
discharging. Synchronous operation is used when the current of the low-side MOSFET is greater than 100mA to
minimize power losses.
Battery Charging Process
At the beginning of precharge, while battery voltage is below the VPRECHARGE threshold, the bq24185 applies the
50mA precharge current, IPRECHARGE, to the battery.
When the battery voltage is above VPRECHARGE and below VOREG, the charge current ramps up to fast charge
current, IOCHARGE, or a charge current that corresponds to the input current of IIN_LIMIT. The slew rate for fast
charge current is controlled to minimize the current and voltage over-shoot during transient. The input current
limit, IIN_LIMIT, and fast charge current, IOCHARGE, are programmable by the host. Once the battery voltage is close
to the regulation voltage, VOREG, the charge current is tapered down as shown in Figure 28. The voltage
regulation feedback occurs by monitoring the battery-pack voltage between the CSOUT and PGND pins. The
bq24185 is a fixed single-cell voltage version, with adjustable regulation voltage (3.5V to 4.44V) programmed
using the I2C interface.
The bq24185 monitors the charging current during the voltage regulation phase. Once the termination threshold,
ITERM, is detected and the battery voltage is above the recharge threshold, the bq24185 terminates charge. The
termination current level is programmable. To disable the charge current termination, the host sets the charge
termination bit (TE) of charge control register to 0, refer to I2C section for details.
A new charge cycle is initiated when one of the following conditions is detected:
1. The battery voltage falls below the VOREG-VRCH threshold.
2. VBUS Power-on reset (POR), if battery voltage is below the VPRECHARGE threshold
3. CE bit toggle or RESET bit is set (Host controlled)
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HOST Mode Battery
Charging
Start 32 second
watchdog timer
Safety Timer expired?
Charging suspended
Enter suspended
mode
Fault indicated in
STAT registers
Yes
Safety timer
fault
No
No
Term Enabled ?
Yes
Yes
Charge Done?
ICHG < ITERM
No
Yes
Yes
CV Mode?
Battery Present?
No
STAT = Hi
Update STAT
bits
Terminate
Safety Timer
No
Indicate
Battery Not
Present Fault
Reset I2C to
default
VBAT <VRCH?
Yes
No
DEFAULT Mode ?
Begin HOST
Mode Battery
Charging
Yes
Begin
DEFAULT
Mode Battery
Charge Cycle
32s timer expired?
Yes
No
No
Indicate Timer Fault
Reset I2C to default
Received SW watchdog
RESET?
Yes
Reset 32 second
watchdog timer
Begin DEFAULT
Mode Battery
Charge Cycle
Figure 29. Host Mode Charging Process
DEFAULT Mode
DEFAULT mode is used when I2C communication is not available. DEFAULT mode is entered in the following
situations:
1. When the charger is enabled and VBAT>3.6V before I2C communication is established
2. When the watchdog timer expires without a reset from the I2C interface and the safety timer has not expired.
3. When the device comes out of any fault condition (sleep mode, OVP, faulty adapter mode, etc.) before I2C
communication is established
In default mode, the I2C registers are reset to the default values. The 27 min safety timer is reset and starts when
DEFAULT mode is entered. The default value for VOREG is 3.6V, and the default value for ICHARGE is 1A. The
input current limit is determined by the PSEL input. If PSEL selects adapter mode, there is no input current limit.
If PSEL selects PC mode, the input current limit is set to 100mA. Default mode is exited by programming the I2C
interface. Startup into DEFAULT mode is shown in Figure 30. Note that if termination is enabled and charging
has terminated, a new charge cycle is NOT initiated when entering DEFAULT mode.
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Begin DEFAULT
Mode Battery
Charge Cycle
Reset safety timer to
27min and start
Safety Timer expired?
Yes
Safety timer
fault
No
Charging suspended
Enter suspended
mode
Fault indicated in
STAT registers
PSEL = Hi?
AC Adapter
Mode
(AAM)
Yes
No
Load default values to
I2C registers.
No Input Current Limit
STAT = 0
PC Mode
Load PC default
values for input
current limit from I2C
registers.
STAT = 0
No
No
Load Optimized Charge
Parameters?
Yes
Begin HOST Mode
Battery Charging
Figure 30. DEFAULT Mode Charging Process
Safety Timer and Watchdog Timer in Charge Mode
At the beginning of charging process, the bq24185 starts the safety timer. This timer is active during the entire
charging process. If charging has not terminated before the safety timer expires, the IC enters suspend mode
where charging is halted. The safety timer time is selectable using the I2C interface. A single 128µs pulse is sent
on the STAT and INT outputs and the STATx bits of the status registers are updated in the I2C. The EN bit or
power must be toggled in order to clear the safety timer fault. The safety timer duration is selectable using the
TMR_X bits in the VIN-DPM Voltage/ Safety Timer Register. Changing the safety timer duration resets the safety
timer.
In addition to the safety timer, the bq24185 contains a watchdog timer that monitors the host through the I2C
interface. Once a read/write is performed on the I2C interface, a 12-second timer (tWATCHDOG) is started. The
12-second timer is reset by the host using the I2C interface. This is done by writing a "1" to the reset bit
(TMR_RST) in the control register. The TMR_RST bit is automatically set to “0” when the 12-second timer is
reset. This process continues until battery is fully charged or the safety timer expires. If the 12-second timer
expires, the IC enters DEFAULT mode where the default charge parameters are loaded, the safety timer restarts
at 27 minutes and charging continues. The I2C may be accessed again to reinitialize the desired values and
restart the watchdog timer as long as the 27 minute safety timer has not expired. Once the safety timer expires,
charging is disabled. This function prevents continuous charging of a defective battery if the host fails to reset the
safety timer. The watchdog timer flow chart is shown in Figure 31.
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Start Safety Timer
Safety timer expired?
Yes
Safety timer
fault
No
Charge Done?
ICHG < ITERM
Yes
STAT = Hi
Update STAT
bits
Yes
STAT = Hi
Update STAT
bits
Charging suspended
Enter suspended
mode
Fault indicated in
STAT registers
No
No
I2C Read/Write
performed?
Yes
Start 12 second
watchdog timer
Charge Done?
ICHG < ITERM
Reset 12 second
watchdog timer
No
Yes
Safety timer
fault
Safety timer expired?
No
Charging suspended
Enter suspended
mode
Fault indicated in
STAT registers
No
Yes
12s timer expired?
Yes
No
Received SW watchdog
RESET?
Reset to default
values in I2C
register
Restart 27min
safety timer
Figure 31. The Watchdog Timer Flow Chart for bq24185
Power Source Selector Input (PSEL)
The bq24185 contains a PSEL input that is used to program the input current limit during DEFAULT mode. Drive
PSEL high to indicate a USB source is connected to the input and the PC mode default values should be used.
When PSEL is high, the IC starts up with a 100mA input current limit and a 1A charge current. Drive PSEL low to
indicate that an AC Adapter is connected to the input. When PSEL is high, the IC starts up with no input current
limit and a 1A charge current. PSEL is internally pulled up to the DRV supply with a 100kΩ resistor.
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Hardware Disable Input (CD)
The bq24185 contains a CD input that is used to disable the charger and place the bq24185 into high-impedance
mode. Drive CD low to enable charge and enter normal operation. Drive CD high to disable charge and place the
bq24185 into high-impedance mode. Driving CD high during DEFAULT mode resets the safety timer. Driving CD
high during HOST mode suspends, but does NOT reset the safety timer. CD is internally pulled down to GND
with a 100kΩ resistor.
LDO Output (DRV)
The bq24185 contains a linear regulator (DRV) that is used to supply the internal MOSFET drivers and other
circuitry. Additionally, DRV supplies up to 10mA external loads to power the STAT LED or the USB transceiver
circuitry. The maximum value of the DRV output is 5.5V so it ideal to protect voltage sensitive USB circuits. The
LDO is on whenever a VBUS supply is connected to the bq24185. The DRV is disabled under the following
conditions:
1. Faulty adapter detected or VBUS < UVLO
2. Thermal Shutdown
AC Adapter Mode, Charge Current Limiting
After power is connected and startup is initiated, the PSEL input is read to determine the default startup values. If
PSEL is 0, AC Adapter mode is selected. In AC Adapter mode, the charge current is regulated to maximize the
charging time. The default parameters in AC Adapter mode are ICHARGE=1A and VOUTREG=3.6V. These values
may be changed at any time using the I2C interface. Additionally, if input current monitoring is required, this may
be used during AC Adapter mode as well, but is disabled in DEFAULT mode.
PC Mode, Input Current Limiting
After power is connected and startup is initiated, the PSEL input is read to determine the default startup values.
In PC mode, the input current is limited to maximize the charge rate of bq24185 without overloading the USB
port. The input current for bq24185 can be limited to 100mA, 500mA or 800mA and is programmed in the control
register. Once the input current reaches the input current limiting threshold, the charge current is reduced to
prevent the input current from exceeding the programmed threshold. The input current sensing resistor and
control loop are integrated into bq24185. The input current limit is disabled using I2C control; refer to the
definition of control register (01H) for detail. The default parameters in USB mode are IINLIM=100mA and
VOUTREG=3.6V. Charge current may be monitored in PC mode as well, but by default it is set to a maximum such
that the input current limit loop is active.
Boost Mode Operation
In HOST mode, when the operation mode bit (OPA_MODE) in the control register is set to 1, bq24185 operates
in boost mode and delivers 5.05V to VBUS. Battery voltages of 2.5V to 4.5V are boosted up to VBUS to supply
USB OTG devices connected to the USB connector. VBUS supplies up to 300mA to these devices.
PWM Controller in Boost Mode
Similar to charge mode operation, in boost mode the IC switches at 3MHz using a voltage-mode control scheme
to regulate the voltage at PMID to 5.05V. The voltage control loop is internally compensated using a Type-III
compensation scheme that provides enough phase margin for stable operation with a wide load and input range.
In boost mode, the input blocking FET (Q1 in the block diagram) is used to prevent an overload condition on
VBUS. The current limit is set to 400mA. Additionally, the cycle-by-cycle current limit is set to 1A to provide
additional protection. Synchronous operation is used to maximize efficiency.
During startup, a soft-start algorithm is used to prevent inductor saturation and limit the inrush current.
PFM at Light Load
In boost mode, the IC operates using frequency modulation (PFM) to improve light load efficiency and reduce
power loss. During boosting, the PWM converter is turned off when the inductor current is less than 75mA and
turns back on when the voltage at PMID drops by 0.5% of the regulation voltage. Additionally circuitry is used to
ensure a smooth transition between PWM and PFM mode.
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Safety/Watchdog Timer in Boost Mode
During boost mode, the watchdog and safety timers are active. The safety timer should be disabled using the I2C
interface. The watchdog timer works the same as in charge mode. Write a “1” to the TMR_RST reset bit in the
control register. If the watchdog timer expires, the IC turns off the boost converter, enunciates the fault pulse on
the STAT and INT pins and sets fault status bits in the status register.
STAT/INT During Boost Mode
During boost mode, the STAT and INT outputs are high impedance (open-drain) outputs. Under fault conditions,
a 128µs pulse is sent out to notify the host of the error condition.
Protection in Boost Mode
Output Over-Voltage Protection
The bq24185 contains integrated over-voltage protection on the VBUS line. During boost mode, if an
over-voltage condition is detected, the IC turns off the PWM converter, resets OPA_MODE bit to 0, sets fault
status bits and sends out a fault pulse on STAT and INT. Once VBUS drops to the normal level, the boost
starts after the OPA_MODE bit is set to a “1”.
Output Over Current Protection
The bq24185 contains over current protection to prevent the device and battery damage when VBUS is
overloaded. When an over-current condition is detected, Q1 operates in linear mode to limit the output
current while VPMID remains in regulation. If the overload condition lasts for longer than 30ms, the overload
fault is detected. When an overload condition is detected, the bq24185 turns off the PWM converter, resets
OPA_MODE bit to 0, sets the fault status bits and sends out the fault pulse on STAT and INT. The boost
starts after the fault is cleared using the I2C.
Battery Voltage Protection
During boost mode, when the battery voltage is greater the battery over voltage threshold, VBATMX, or
below the minimum battery voltage threshold, VBATMIN, the IC turns off the PWM converter, , resets
OPA_MODE bit to 0, sets fault status bits and sends out a fault pulse on STAT and INT. Once the battery
voltage returns to the acceptable level, the boost starts after the OPA_MODE bit is set to a “1”.
DCOUT Functionality
The bq24185 contains a DCOUT function that is used to connect a load to the battery through a switch. DCOUT
is implemented using back to back MOSFETs (Q4 and Q5 in Figure 1) to connect DCOUT to the battery. This
prevents reverse feeding the battery from DCOUT when DCOUT is disabled. DCOUT is a current limited source
and can provide up to 1A to power additional accessories. The current limit is programmable from 370mA to 1.5A
in 4 steps using the I2C interface. Additionally, the DCOUT output is enabled or disabled using the I2C interface.
If the load on DCOUT reaches the current limit, the FET that connects DCOUT to the battery is turned off after
the deglitch time (tdgl_DCOUT), a single 128µs pulse is sent on the STAT and INT outputs and the FAULT_x bits of
the status register are updated in the I2C. The DCOUT may be enabled after the fault using the I2C interface.
External NTC Monitoring (TS)
The bq24185 provides a TS input for monitoring an external NTC thermistor. A current is sourced to the NTC
from the TS input and the voltage is monitored. There are 3 temperature thresholds that are monitored; the cold
battery threshold (TNTC < 5°C), the warm battery threshold (45°C < TNTC < 55°C) and the hot battery threshold
(TNTC > 55°C). These temperatures correspond to the VHOT, VWARM, and VCOLD thresholds when using a 4.7kΩ
NTC thermistor (b=3500). The TS input is monitored at all times, however, it only affects charging during default
mode. During default mode, charging is suspended and timers are suspended when TNTC < 5°C or TNTC > 55°C.
When 45°C < TNTC < 55°C, the charging current is reduced to 400mA (max). In PC mode, the charge current
remains at 100mA in this mode.
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1A
400 mA
T1
(5ºC)
T2
(45ºC)
T3
(55ºC)
Figure 32. Charge Current During TS Conditions in Default Mode
When the bq24185 is not in default mode, the TS input is monitored and faults are displayed in the I2C registers.
If any of the 3 TS fault conditions occur, a single 128µs pulse is sent on the STAT and INT outputs and the
STATx and FAULT_x bits of the status registers are updated in the I2C. The FAULT_x bits signal a general
temperature fault. The TS_FAULTX bits in the NTC Monitor Register show the exact TS fault that has occurred.
INTC
bq24185
TS
+
PACK+
TEMP
VCOLD
+
VHOT
+
VWARM
PACK-
Figure 33. TS Circuit
Thermal Regulation and Protection
During the charging process, to prevent overheat of the chip, bq24185 monitors the junction temperature, TJ, of
the die and begins to taper down the charge current once TJ reaches the thermal regulation threshold, TCF. The
charge current is reduced to zero when the junction temperature increases about 10°C above TCF. At any state, if
TJ exceeds TSHTDWN, bq24185 terminates charging and disables DCOUT in the I2C register. During thermal
shutdown mode, PWM is turned off, all timers are terminated and reset, and a single 128µs pulse is sent on the
STAT and INT outputs and the STATx and FAULT_x bits of the status registers are updated in the I2C. A new
charging cycle begins when TJ falls below TSHTDWN by approximately 10°C. DCOUT must be enabled by the host
after a thermal shutdown fault.
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Input Voltage Protection in Charge Mode
Sleep Mode
The bq24185 enters the low-power sleep mode if the voltage on VVBUS falls below sleep-mode entry
threshold, VCSOUT+VSLP, and VVBUS is higher than the undervoltage lockout threshold, VUVLO. This feature
prevents draining the battery during the absence of VVBUS. During sleep mode, both the reverse blocking
switch Q1 and PWM are turned off. Once the input rises above the sleep threshold, the device returns to
normal operation.
Input Voltage Based DPM
During normal charging process, if the input power source is not able to support the programmed or default
charging current, VBUS voltage will decease. Once the VBUS drops to VVBUS_LOW (default 4.76V), the charge
current is tapered down to prevent the further drop of VBUS. When the IC enters this mode, the charge
current is lower than the set value and the DPM_STATUS bit is set (B4 in Register 05H). This feature
ensures IC compatibility with adapters with different current capabilities.
Faulty Adapter Detection
When an input source is connected to the bq24185, the device enter faulty adapter detection mode. In this
mode, the IC sources 30mA to the battery for tINT. After tINT, the input voltage is monitored. If VVBUS>VIN(MIN),
the device continues the startup sequence. If VVBUS<VIN(MIN), a single 128µs pulse is sent on the STAT and
INT outputs and the STATx and FAULT_x bits of the status registers are updated in the I2C and the process
repeats until a good adapter is detected.
High-Input and Input Over-Voltage Protection
The bq24185 provides two levels over-voltage protection on the input. A high-input comparator disables the
PWM operation and sources the 50mA precharge current to the battery when VHIGH < VVBUS < VOVP. This
allows for unregulated adapters to be used. The 50mA pulls the adapter voltage down to the usable voltage
and then normal operation begins.
The built-in input over-voltage protection to protect the device and other components against damage from
overvoltage on the input supply (Voltage from VVBUS to PGND). When VVBUS > VOVP, the bq24185 latches off
the PWM converter, a single 128µs pulse is sent on the STAT and INT outputs and the STATx and FAULT_x
bits of the status registers are updated in the I2C. Once the OVP fault is removed, the STATx and FAULT_x
bits are cleared and the device returns to normal operation.
Charge Status Outputs (STAT, INT)
The STAT and INT outputs are used to indicate operation conditions for bq24185. STAT and INT are pulled low
during charging when EN_STAT bit in the control register (00H) is set to “1”. When charge is complete or
disabled, INT and STAT are high impedance. When a fault occurs, a 128-µs pulse (interrupt) is sent out to notify
the host. The status of STAT and INT during different operation conditions is summarized in Table 1. STAT
drives an LED for visual indication. INT is available for connecting to the logic rail for host communication.
Table 1. STAT Pin Summary
CHARGE STATE
STAT and INT BEHAVIOR
Charge in progress and EN_STAT=1
Low
Other normal conditions
Open-drain
Charge mode faults: Timer fault, sleep mode,
VBUS over voltage, VBUS UVLO, thermal
shutdown
128-µs pulse, then open-drain
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Control Bits in Charge Mode
CE Bit (Charge Enable)
The bit of CE in control register is used to disable or enable the charge process. A low logic level (0) on this
bit enables the charge and a high logic level (1) disables the charge.
RESET Bit
The bit of RESET in control register is used to reset all the charge parameters. Write ‘1” to RESET bit to
reset all the charge parameters to default values and RESET bit is automatically cleared to zero once the
charge parameters get reset. It is designed for charge parameter reset before charge starts and it is not
recommended to set RESET bit when charging or boosting in progress.
OPA MODE Bit (Operation Mode)
The OPA-MODE bit is the operation mode control bit. When OPA_MODE is “0”, the bq24185 operates as a
charger. When OPA_MODE is “1” the bq24185 operates in boost mode. The HZ_MODE bit overrides the
OPA_MODE bit and will always operate the bq24185 in high impedance mode.
Output Inductor and Capacitor Selection Guidelines
The bq24185 provides internal loop compensation. With this scheme, best stability occurs when LC resonant
frequency, of, is approximately 40 kHz (20 kHz to 80 kHz). Equation 1 can be used to calculate the value of the
output inductor, LOUT, and output capacitor, COUT.
1
¦o =
2p ´ LOUT ´ COUT
(1)
To reduce the output voltage ripple, a ceramic capacitor with the capacitance between 4.7µF and 47µF is
recommended for COUT, refer to the application section for components selection.
Selecting Current Sense Resistor
Both the termination current range and charge current range are depending on the sensing resistor (RSNS). The
termination current step (IOTERM_STEP) can be calculated using Equation 2:
V
IOTERM_STEP = ITERM0
RSNS
(2)
Table 2 shows the termination current settings with two sensing resistors.
Table 2. Termination Current Settings for 68mΩ and 100mΩ Sense Resistors
BIT
VITERM (mV)
ITERM (mA)
RSNS = 68 mΩ
ITERM (mA)
RSNS = 100 mΩ
VITERM2
6.8
100
68
VITERM1
3.4
50
43
VITERM0
1.7
25
17
Offset
1.7
25
17
The charge current step (IOCHARGE_STEP) can be calculated using Equation 3:
V
IOCHARG E_STEP = ICHRG0
R SNS
(3)
Table 3 shows the charge current settings with two sensing resistors.
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Table 3. Charge Current Settings for 68 mΩ and 100 mΩ Sense Resistors
BIT
VIREG (mV)
IOCHARGE (mA)
RSNS = 68 mΩ
IOCHARGE (mA)
RSNS = 100 mΩ
VICHRG3
54.4
800
544
VICHRG2
27.2
400
272
VICHRG1
13.6
200
136
VICHRG0
6.8
100
68
Offset
37.4
550
374
SERIAL INTERFACE DESCRIPTION
I2C is a 2-wire serial interface developed by Philips Semiconductor (see I2C-Bus Specification, Version 2.1,
January 2000). The bus consists of a data line (SDA) and a clock line (SCL) with pull-up structures. When the
bus is idle, both SDA and SCL lines are pulled high. All the I2C compatible devices connect to the I2C bus
through open drain I/O pins, SDA and SCL. A master device, usually a microcontroller or a digital signal
processor, controls the bus. The master is responsible for generating the SCL signal and device addresses. The
master also generates specific conditions that indicate the START and STOP of data transfer. A slave device
receives and/or transmits data on the bus under control of the master device.
The bq24185 device works as a slave and is compatible with the following data transfer modes, as defined in the
I2C Bus™ Specification: standard mode (100 kbps), fast mode (400 kbps), and high-speed mode (up to 3.4 Mbps
in write mode). The interface adds flexibility to the battery charge solution, enabling most functions to be
programmed to new values depending on the instantaneous application requirements. Register contents remain
intact as long as battery voltage remains above 2.5 V (typical). The I2C circuitry is powered from VBUS when a
supply is connected. If the VBUS supply is not connected, the I2C circuitry is powered from the battery through
CSOUT. The battery voltage must stay above 2.5V with no input connected in order to maintain proper operation.
The data transfer protocol for standard and fast modes is exactly the same; therefore, they are referred to as the
F/S-mode in this document. The protocol for high-speed mode is different from the F/S-mode, and it is referred to
as the HS-mode. The bq24150/1 device only supports 7-bit addressing. The device 7-bit address is defined as
‘1101011’ (6BH).
F/S Mode Protocol
The master initiates data transfer by generating a start condition. The start condition is when a high-to-low
transition occurs on the SDA line while SCL is high, as shown in Figure 34. All I2C -compatible devices should
recognize a start condition.
DATA
CLK
START Condition
STOP Condition
Figure 34. START and STOP Condition
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The master then generates the SCL pulses, and transmits the 8-bit address and the read/write direction bit R/W
on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition requires
the SDA line to be stable during the entire high period of the clock pulse (see Figure 35). All devices recognize
the address sent by the master and compare it to their internal fixed addresses. Only the slave device with a
matching address generates an acknowledge (see Figure 35) by pulling the SDA line low during the entire high
period of the ninth SCL cycle. Upon detecting this acknowledge, the master knows that communication link with a
slave has been established.
DATA
CLK
Data Line
Stable;
Data Valid
Charge
of Data
Allowed
Figure 35. Bit Transfer on the Serial Interface
The master generates further SCL cycles to either transmit data to the slave (R/W bit 1) or receive data from the
slave (R/W bit 0). In either case, the receiver needs to acknowledge the data sent by the transmitter. So an
acknowledge signal can either be generated by the master or by the slave, depending on which one is the
receiver. the 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as
necessary. To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line
from low to high while the SCL line is high (see Figure 36). This releases the bus and stops the communication
link with the addressed slave. All I2C compatible devices must recognize the stop condition. Upon the receipt of
a stop condition, all devices know that the bus is released, and wait for a start condition followed by a matching
address. If a transaction is terminated prematurely, the master needs sending a STOP condition to prevent the
slave I2C logic from remaining in a incorrect state. Attempting to read data from register addresses not listed in
this section will result in FFh being read out.
Data Output
by Transmitter
Not Acknowledge
Data Output
by Receiver
Acknowledge
SCL From
Master
Clock Pulse for
Acknowledgement
START
Condition
Figure 36. Acknowledge on the I2C Bus
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Figure 37. Bus Protocol
F/S Mode Protocol
When the bus is idle, both SDA and SCL lines are pulled high by the pull-up devices.
The master generates a start condition followed by a valid serial byte containing HS master code '00001XXX'.
This transmission is made in F/S mode at no more than 400 Kbps. No device is allowed to acknowledge the HS
master code, but all devices must recognize it and switch their internal setting to support 3.4-Mbps operation.
The master then generates a repeated start condition (a repeated start condition has the same timing as the start
condition). After this repeated start condition, the protocol is the same as F/S mode, except that transmission
speeds up to 3.4 Mbps are allowed. A stop condition ends the HS mode and switches all the internal settings of
the slave devices to support the F/S mode. Instead of using a stop condition, repeated start conditions should be
used to secure the bus in HS mode. If a transaction is terminated prematurely, the master needs sending a
STOP condition to prevent the slave I2C logic from remaining in a incorrect state.
Attempting to read data from register addresses not listed in this section results in FFh being read out.
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REGISTER DESCRIPTION
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Status/Control Register (READ/WRITE) – Memory location: 00, Reset state: x1xx 0xxx
BIT
NAME
Read/Write
FUNCTION
B7(MSB)
TMR_RST
Read/Write
Write: TMR_RST function, write "1" to reset the watchdog timer (auto clear)
Read: 0 – PSEL indicates low, 1- PSEL indicates high
B6
EN_STAT
Read/Write
1-Enable STAT function, 0-Disable STAT function (default 1)
B5
STAT2
Read only
B4
STAT1
Read only
B3
BOOST
Read only
B2
FAULT_3
Read only
B1
FAULT_2
Read only
B0(LSB)
FAULT_1
Read only
00-Ready, 01-Charge in progress, 10-Charge done, 11-Fault
0 – Charger Mode, 1 – Boost Mode
Charge mode: 000-Normal, 001-VBUS OVP, 010-Sleep mode, 011- Faulty Adapter or
VBUS<VUVLO, 100-DCOUT Current Limit tripped, 101-Thermal shutdown or TS Fault,
110-Timer fault, 111-No battery
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Control Register (READ/WRITE) – Memory location: 01, Reset state: 0011 0000
BIT
NAME
Read/Write
FUNCTION
B7(MSB)
Iin_Limit_2
Read/Write
B6
Iin_Limit_1
Read/Write
00-USB host with 100-mA current limit, 01-USB host with 500-mA current limit, 10-USB
host/charger with 800-mA current limit, 11-No input current limit (default 00(1))
B5
DCOUT_ILIM1
Read/Write
B4
DCOUT_ILIM2
Read/Write
B3
TE
Read/Write
1-Enable charge current termination, 0-Disable charge current termination (default 0)
B2
CE
Read/Write
1-Charger is disabled, 0-Charger enabled (default 0)
B1
HZ_MODE
Read/Write
1-High impedance mode, 0-Not high impedance mode (default 0)
B0 (LSB)
DCOUT_EN
Read/Write
1-DCOUT Enabled, 0-DCOUT Disabled. (default 0)
00-DCOUT 350mA current limit, 01- DCOUT 750mA current limit, 10- DCOUT 1050mA
current limit, 11- DCOUT 1400mA current limit (default 11)
(1) When in DEFAULT mode, the PSEL input determines the input current limit.
Control/Battery Voltage Register (READ/WRITE) – Memory location: 02, Reset state: 0001 01XX
BIT
NAME
Read/Write
FUNCTION
B7(MSB)
VOREG5
Read/Write
Battery Regulation Voltage: 640mV (default 0)
B6
VOREG4
Read/Write
Battery Regulation Voltage: 320mV (default 0)
B5
VOREG3
Read/Write
Battery Regulation Voltage: 160mV (default 0)
B4
VOREG2
Read/Write
Battery Regulation Voltage: 80mV (default 1)
B3
VOREG1
Read/Write
Battery Regulation Voltage: 40mV (default 0)
B2
VOREG0
Read/Write
Battery Regulation Voltage: 20mV (default 1)
B1
NA
Read/Write
NA
B0(LSB)
NA
Read/Write
NA
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• Charge voltage range is 3.5V–4.44V with the offset of 3.5V and step of 20mV (default 3.6V).
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Vender/Part/Revision Register (READ only) – Memory location: 03, Reset state: 0100 0000
BIT
NAME
Read/Write
FUNCTION
B7(MSB)
Vender2
Read only
Vender Code: bit 2 (default 0)
B6
Vender1
Read only
Vender Code: bit 1 (default 1)
B5
Vender0
Read only
Vender Code: bit 0 (default 0)
B4
PN1
Read only
B3
PN0
Read only
B2
Revision2
Read only
B1
Revision1
Read only
B0(LSB)
Revision0
Read only
For I2C Address 6BH: 00 – bq24185
000: Revision 1.0; 001: Revision 1.1
010-111: Future Revisions
Battery Termination/Fast Charge Current Register (READ/WRITE)
Memory location: 04, Reset state: 1010 1011
BIT
NAME
Read/Write
FUNCTION
B7(MSB)
Reset
Write only
Write: 1-Charger in reset mode, 0-No effect
Read: always get "0"
B6
VICHRG3
Read/Write
Charge current sense voltage: 54.4mV— (default 0)
B5
VICHRG2
Read/Write
Charge current sense voltage: 27.2mV—(default 1)
B4
VICHRG1
Read/Write
Charge current sense voltage: 13.6mV— (default 0)
B3
VICHRG0
Read/Write
Charge current sense voltage: 6.8mV (default 1)
B2
VITERM2
Read/Write
Termination current sense voltage: 6.8mV (default 0)
B1
VITERM1
Read/Write
Termination current sense voltage: 3.4mV (default 1)
B0(LSB)
VITERM0
Read/Write
Termination current sense voltage: 1.7mV (default 1)
blank paragraph for spacer
• Charge current sense voltage offset is 37.4mV and default charge current is 1050mA, if 68mΩ sense resistor
is used.
• Termination threshold voltage offset is 1.7mV and default termination current is 100mA if a 68mΩ sense
resistor is used.
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VIN-DPM Voltage/ Safety Timer Register – Memory location: 05, Reset state: XX0X X111
•
BIT
NAME
Read/Write
FUNCTION
B7(MSB)
NA
Read/Write
NA
B6
NA
Read/Write
NA
B5
LOW_CHG
Read/Write
1 – Low charge current sense voltage of 23.8mV,
0 – Normal charge current sense voltage at 04H (default 0)
B4
DPM_STATUS
Read Only
1 – VIN-DPM mode is active,
0 – VIN-DPM mode is not active
B3
CD_STATUS
Read Only
1 – CD high, Charger disabled,
0 – CD low, Charger enabled
B2
VINDPM2
Read/Write
VIN-DPM voltage: 320 mV (default 1)
B1
VINDPM1
Read/Write
VIN-DPM voltage: 160 mV (default 1)
B0(LSB)
VINDPM0
Read/Write
VIN-DPM voltage: 80 mV (default 1)
VIN-DPM voltage offset is 4.15V and default VIN-DPM threshold is 4.71V.
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Safety Limit Register (READ/WRITE, Write only once after reset!)
Memory location: 06, Reset state: 0101 0000
BIT
NAME
Read/Write
FUNCTION
B7(MSB)
VMCHRG3
Read/Write
Maximum charge current sense voltage: 54.4mV (default 0)
B6
VMCHRG2
Read/Write
Maximum charge current sense voltage: 27.2mV (default 1)
B5
VMCHRG1
Read/Write
Maximum charge current sense voltage: 13.6mV (default 0)
B4
VMCHRG0
Read/Write
Maximum charge current sense voltage: 6.8mV (default 1)
B3
VMREG3
Read/Write
Maximum battery regulation voltage: 160mV (default 0)
B2
VMREG2
Read/Write
Maximum battery regulation voltage: 80mV (default 0)
B1
VMREG1
Read/Write
Maximum battery regulation voltage: 40mV (default 0)
B0(LSB)
VMREG0
Read/Write
Maximum battery regulation voltage: 20mV (default 0)
•
Maximum charge current sense voltage offset is 550mA (default at 950mA) and the maximum charge current
option is 1.55A, if 68-mΩ sensing resistor is used.
Maximum battery regulation voltage offset is 4.2V (default at 4.2V) and maximum battery regulation voltage
option is 4.44V.
Memory location 06 resets only when VBAT voltage drops below VSHORT threshold (typ. 2.0V) goes to logic '0'.
During reset, the maximum values in 06H keep the default value regardless of the write action to this register.
After reset (VBAT>VSHORT), the maximum values for battery regulation voltage and charge current can be
programmed many times until any writing to other register locks the safety limits. Programmed values exclude
higher values from memory locations 02 (battery regulation voltage), and from memory location 04 (Fast
charge current).
If host accesses (write command) to some other register before Safety limit register, the default values hold!
•
•
blank paragraph for spacer
NTC Monitor Register (READ/WRITE) – Memory location: 07, Reset state: 100X 1000
BIT
NAME
Read/Write
FUNCTION
B7(MSB)
2XTMR_EN
Read/Write
1 – Timer slowed by 2x when in thermal regulation or VIN_HIGH protection,
0 – Timer not slowed at any time (default 1)
B6
TMR_1
Read/Write
B5
TMR_2
Read/Write
Safety Timer Time Limit
00 – 27 minute fast charge,
01 – 3 hour fast charge,
10 – 6 hour fast charge,
11 – Disable safety timers (default 00)
B4
NA
Read/Write
NA
B3
TS_EN
Read/Write
1 – TS function enabled
0 – TS function disabled (default 1)
B2
TS_FAULT2
Read only
B1
TS_FAULT1
Read only
B0(LSB)
TS_FAULT0
Read only
TS Fault Mode:
000 – TS temp < 5°C or TS temp > 55°C,
010 – Normal, No TS fault,
011 – 45°C < TS temp < 55°C,
100–111 – TS Open
blank paragraph for spacer
Boost Monitor Register (READ/WRITE) – Memory location: 08, Reset state: XX11 0X10
BIT
NAME
Read/Write
FUNCTION
B7(MSB)
NA
Read/Write
NA
B6
NA
Read/Write
NA
B5
VLOWV1
Read/Write
Weak battery voltage threshold: 200mV (default 1)
B4
VLOWV0
Read/Write
Weak battery voltage threshold: 100mV (default 1)
B3
OPA_MODE
Read/Write
bq24185 Operating mode: 1 – bq24185 in boost mode, 0 – bq24185 in charger mode
(default 0)
B2
NA
Read only
NA
B1
NA
Read only
NA
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Boost Monitor Register (READ/WRITE) – Memory location: 08, Reset state: XX11 0X10 (continued)
•
BIT
NAME
Read/Write
B0(LSB)
NA
Read only
FUNCTION
NA
The weak battery threshold voltage offset is 3.4V and default weak battery threshold is 3.7V.
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POWER TOPOLOGIES
System Load After Sensing Resistor
One of the simple high-efficiency topologies connects the system load directly across the battery pack, as shown
in Figure 38. The input voltage has been converted to a usable system voltage with good efficiency from the
input. When the input power is on, it supplies the system load and charges the battery pack at the same time.
When the input power is off, the battery pack powers the system directly.
SW
VBUS
L1
VIN
+
-
Isys
Isns
Rsns
Ichg
bq24185
C1
PMID
+
PGND
C4
C3
System
Load
BAT
C2
Figure 38. System Load After Sensing Resistor
The advantages:
• When the AC adapter is disconnected, the battery pack powers the system load with minimum power
dissipations. Consequently, the time that the system runs on the battery pack can be maximized.
• It saves the external path selection components and offers a low-cost solution.
• Dynamic power management (DPM) can be achieved. The total of the charge current and the system current
can be limited to a desired value by adjusting charge current. When the system current increases, the charge
current drops by the same amount. As a result, no potential over-current or over-heating issues are caused
by excessive system load demand.
• The total of the input current can be limited to a desired value by setting input current limit value. So USB
specifications can be met easily.
• The supply voltage variation range for the system can be minimized.
• The input current soft-start can be achieved by the generic soft-start feature of the IC.
Design considerations and potential issues:
• If the system always demands a high current (but lower than the regulation current), the charging never
terminates. Thus, the battery is always charged, and the lifetime may be reduced.
• Because the total current regulation threshold is fixed and the system always demands some current, the
battery may not be charged with a full-charge rate and thus may lead to a longer charge time.
• If the system load current is large after the charger has been terminated, the voltage drop across the battery
impedance may cause the battery voltage to drop below the refresh threshold and start a new charge. The
charger would then terminate due to low charge current. Therefore, the charger would cycle between
charging and terminating. If the load is smaller, the battery has to discharge down to the refresh threshold,
resulting in a much slower cycling.
• In a charger system, the charge current is typically limited to about 10mA, if the sensed battery voltage is
below 2V short circuit protection threshold. This results in low power availability at the system bus. If an
external supply is connected and the battery is deeply discharged, below the short circuit protection threshold,
the charge current is clamped to the short circuit current limit. This then is the current available to the system
during the power-up phase. Most systems cannot function with such limited supply current, and the battery
supplements the additional power required by the system. Note that the battery pack is already at the
depleted condition, and it discharges further until the battery protector opens, resulting in a system shutdown.
• If the battery is below the short circuit threshold and the system requires a bias current budget lower than the
short circuit current limit, the end-equipment will be operational, but the charging process can be affected
depending on the current left to charge the battery pack. Under extreme conditions, the system current is
34
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•
SLUSA43 – SEPTEMBER 2010
close to the short circuit current levels and the battery may not reach the fast-charge region in a timely
manner. As a result, the safety timers flag the battery pack as defective, terminating the charging process.
Because the safety timer cannot be disabled, the inserted battery pack must not be depleted to make the
application possible.
For instance, if the battery pack voltage is too low, highly depleted, or totally dead or even shorted, the
system voltage is clamped by the battery and it cannot operate even if the input power is on.
System Load Before Sensing Resistor
The second circuit is very similar to first one; the difference is that the system load is connected before the sense
resistor, as shown in Figure 39.
Isys
SW
VBUS
Isns
L1
VIN
+
-
Rsns
Ichg
bq24185
C1
PMID
+
PGND
C4
C3
System
Load
BAT
C2
Figure 39. System Load Before Sensing Resistor
The advantages of system load before sensing resistor to system load after sensing resistor:
• The charger controller is based only on the current goes through the current-sense resistor. So, the constant
current fast charge and termination functions work well, and are not affected by the system load. This is the
major advantage of it.
• A depleted battery pack can be connected to the charger without the risk of the safety timer expiration caused
by high system load.
• The host charger can disable termination and keep the converter running to keep battery fully charged, or let
the switcher terminate when the battery is full and then run off of the battery via the sense resistor.
Design considerations and potential issues:
• The total current is limited by the IC input current limit, or peak current protection, or the thermal regulation
but not the charge current setting. The charge current does not drop when the system current load increases
until the input current limit is reached. This solution is not applicable if the system requires a high current.
• Efficiency declines when discharging through the sense resistor to the system.
DESIGN EXAMPLE FOR TYPICAL APPLICATION CIRCUITS
Systems Design Specifications:
• VBUS = 5 V
• V(BAT) = 4.2 V (1-Cell)
• I(charge) = 1.25 A
• Inductor ripple current = 30% of fast charge current
1. Determine the inductor value (LOUT) for the specified charge current ripple:
L OUT =
VBAT ´ (VBUS - VBAT)
VBUS ´ f ´ D IL
, the worst case is when battery voltage is as close as to half of the input
voltage.
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35
bq24185
SLUSA43 – SEPTEMBER 2010
LOUT =
www.ti.com
2.5 ´ (5 - 2.5)
5 ´ (3 ´ 106 ) ´ 1.25 ´ 0.3
(4)
LOUT = 1.11 mH
Select the output inductor to standard 1 mH. Calculate the total ripple current with using the 1-mH inductor:
DIL =
VBAT ´ (VBUS - VBAT)
VBUS ´ f ´ LOUT
(5)
2.5 ´ (5 - 2.5)
DIL =
5 ´ (3 ´ 106 ) ´ (1 ´ 10-6 )
(6)
ΔIL = 0.42 A
Calculate the maximum output current:
DIL
ILPK = IOUT +
2
(7)
0.42
ILPK = 1.25 +
2
(8)
ILPK = 1.46 A
Select 2.5mm by 2.0mm 1-mH 1.5-A surface mount multi-layer inductor. The suggested inductor part
numbers are shown as following.
Table 4. Inductor Part Numbers
PART NUMBER
INDUCTANCE
SIZE
MANUFACTURER
LQM2HPN1R0MJ0
1 mH
2.5 x 2.0 mm
muRata
MIPS2520D1R0
1 mH
2.5 x 2.0 mm
FDK
MDT2520-CN1R0M
1 mH
2.5 x 2.0 mm
TOKO
CP1008
1 mH
2.5 x 2.0 mm
Inter-Technical
2. Determine the output capacitor value COUT using 40 kHz as the resonant frequency:
fo =
1
2p ´
COUT =
COUT =
LOUT ´ COUT
(9)
1
4p2 ´ f02 ´ LOUT
1
(10)
4p2 ´ (40 ´ 103 )2 ´ (1 ´ 10-6 )
(11)
COUT = 15.8 mF
Select two 0603 X5R 6.3V 10-mF ceramic capacitors in parallel i.e., muRata GRM188R60J106M.
3. Determine the sense resistor using the following equation:
V(RSNS)
R(SNS) =
I(CHARGE)
(12)
The maximum sense voltage across sense resistor is 85 mV. In order to get a better current regulation
accuracy, V(RSNS) should equal 100mV, and calculate the value for the sense resistor.
85mV
R(SNS) =
1.25A
(13)
R(SNS) = 68 mΩ
36
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SLUSA43 – SEPTEMBER 2010
This is a standard value. If it is not a standard value, then choose the next close value and calculate the real
charge current. Calculate the power dissipation on the sense resistor:
P(RSNS) = I(CHARGE) 2 × R(SNS)
P(RSNS) = 1252 × 0.068
P(RSNS) = 0.106 W
Select 0805 0.25-W 68-mΩ 2% sense resistor, i.e. Sosomu RL122OT-R068-G or RL0816T-R068-F 68-mΩ,
0.125W, 0603, 1%.
PCB LAYOUT CONSIDERATION
It is important to pay special attention to the PCB layout. The following provides some guidelines:
• To obtain optimal performance, the power input capacitors, connected from input to PGND, should be placed
as close as possible to the bq24185. The output inductor should be placed close to the IC and the output
capacitor connected between the inductor and PGND of the IC. The intent is to minimize the current path loop
area from the SW pin through the LC filter and back to the PGND pin. To prevent high frequency oscillation
problems, proper layout to minimize high frequency current path loop is critical (see Figure 40). The sense
resistor should be adjacent to the junction of the inductor and output capacitor. Route the sense leads
connected across the RSNS(R1) back to the IC, close to each other (minimize loop area) or on top of each
other on adjacent layers (do not route the sense leads through a high-current path, see Figure 41).
• Place all decoupling capacitor close to their respective IC pin and as close as to PGND (do not place
components such that routing interrupts power stage currents). All small control signals should be routed
away from the high current paths.
• The PCB should have a ground plane (return) connected directly to the return of all components through vias
(two vias per capacitor for power-stage capacitors, two vias for the IC PGND, one via per capacitor for
small-signal components). A star ground design approach is typically used to keep circuit block currents
isolated (high-power/low-power small-signal) which reduces noise-coupling and ground-bounce issues. A
single ground plane for this design gives good results. With this small layout and a single ground plane, there
is no ground-bounce issue, and having the components segregated minimizes coupling between signals.
• The high-current charge paths into VBUS, PMID and from the SW pins must be sized appropriately for the
maximum charge current in order to avoid voltage drops in these traces. The PGND pins should be
connected to the ground plane to return current through the internal low-side FET.
• Place 4.7mF input capacitor as close to PMID pin and PGND pin as possible to make high frequency current
loop area as small as possible. Place 1mF input capacitor as close to VBUS pin and PGND pin as possible to
make high frequency current loop area as small as possible (see Figure 42).
L1
VBUS
SW
R1
V BAT
High
Frequency
BAT
V IN
PMID
Current
Path
PGND
C3
C2
C1
Figure 40. High Frequency Current Path
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Charge Current Direction
R SNS
To Inductor
To Capacitor and battery
Current Sensing Direction
CSOUT must be as large as
possible to avoid error when
using DCOUT
To CSIN and CSOUT pin
Figure 41. Sensing Resistor PCB Layout
VBUS
Vin+
PMID
SW
1uF
Vin4.7uF
PGND
Figure 42. Input Capacitor Position and PCB Layout Example
PACKAGE SUMMARY
WCSP PACKAGE
(Top View)
CHIP SCALE PACKAGE
(Top Side Symbol For bq24180)
VBUS
VBUS
BOOT
SCL
SDA
PMID
PMID
PMID
INT
CD
SW
SW
SW
PSEL
STAT
PGND
PGND
PGND
DCOUT
DCOUT
CSIN
TS
DRV
CSOUT
CSOUT
D
TI YMLLLLS
bq24185
E
0-Pin A1 Marker, TI-TI Letters, YM- Year Month Date Code, LLLL-Lot Trace Code, S-Assembly Site Code
CHIP SCALE PACKAGING DIMENSIONS
TM
The bq24180 devices are available in a 20-bump chip scale package (YFF, NanoFree ). The package dimensions are:
· D = 2.2 ± 0.05 mm
· E = 2.4 ± 0.05 mm
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PACKAGE OPTION ADDENDUM
www.ti.com
8-Jun-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
BQ24185YFFR
ACTIVE
DSBGA
YFF
25
3000
TBD
Call TI
Call TI
-40 to 85
BQ24185
BQ24185YFFT
ACTIVE
DSBGA
YFF
25
250
TBD
Call TI
Call TI
-40 to 85
BQ24185
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
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