LINER LTC1143LCS-ADJ Dual high efficiency so-16 step-down switching regulator controller Datasheet

LTC1143/LTC1143L
LTC1143L-ADJ
Dual High Efficiency SO-16
Step-Down Switching Regulator
Controllers
DESCRIPTION
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FEATURES
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Dual Outputs
LTC1143, LTC1143L: 3.3V, 5V
LTC1143L-ADJ: Dual Adjustable
Very High Efficiency: Over 95% Possible
Current Mode Operation for Excellent Line and Load
Transient Response
High Efficiency Maintained over Three Decades of
Output Current
Low Standby Current at Light Loads: 160µA/Output
Logic-Controlled Shutdown (LTC1143, LTC1143L)
Wide VIN Range: 3.5V to 16V
(LTC1143L, LTC1143L-ADJ)
Very Low Dropout Operation: 100% Duty Cycle
Available in Narrow 16-Pin SO Package
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APPLICATIONS
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, LTC and LT are registered trademarks of Linear Technology Corporation.
Burst Mode is a trademark of Linear Technology Corporation.
TYPICAL APPLICATION
+
VOUT1
3.3V/2A
RSENSE1
0.05Ω
CIN1
22µF
25V
×2
VIN
4V TO 14V
+
0.22µF
0.22µF
P1A
4
L1
27µH
1
13
VIN1
5
VIN2
P-DRIVE 1
P-DRIVE 2
SENSE + 1
SENSE + 2
1000pF
COUT1
220µF
10V
×2
+
R1
49.9k
1%
R2
82.5k
1%
The operating current level for both regulators is userprogrammable via an external current sense resistor.
Wide input supply range allows operation from 4V to 14V
(16V maximum). The LTC1143L and LTC1143L-ADJ
extend operation to VIN = 3.5V. 100% duty cycle provides
low dropout regulation limited only by the RDS(ON) of the
external MOSFET and resistance of the inductor and
current sense resistor.
The LTC1143 series is ideal for applications requiring dual
output voltages with high conversion efficiencies over a
wide load current range in a small amount of board space.
Personal Digital Assistants
Notebook and Palmtop Computers
Battery-Operated Digital Devices
Portable Instruments
DC Power Distribution Systems
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The LTC1143 series is a dual step-down switching regulator
controller featuring automatic Burst ModeTM operation to
maintain high efficiencies at low output currents. This
device is composed of two separate regulator blocks,
each driving an external power MOSFET at switching
frequencies up to 400kHz using a constant off-time current
mode architecture. Both fixed and adjustable voltages are
available.
2
100pF
L1, L2: SUMIDA CDRH125-270
P1: SILICONIX Si4953DY/FAIRCHILD NDS8947
RSENSE1, RSENSE2: DALE WSL-2010-.05
P1B
12
L2
27µH
SENSE – 2
R4
49.9k
1%
8
D2
MBRS320T3
VFB2
VFB1
3
CT1
300pF
CT1
14
ITH1
15
RC1
1k
CC1
CC2
3300pF 3300pF
VOUT2
2.5V/2A
1000pF
SENSE – 1
GND1
RSENSE2
0.05Ω
9
LTC1143L-ADJ
16
D1
MBRS320T3
CIN2
22µF
25V
×2
ITH2
CT2
GND2
7
6
11
10
100pF
+
R3
49.9k
1%
COUT2
220µF
10V
×2
RC2
1k
CT2
300pF
1143 F01
Figure 1. High Efficiency Dual 3.3V/2.5V Regulator
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LTC1143/LTC1143L
LTC1143L-ADJ
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ABSOLUTE MAXIMUM RATINGS
Input Supply Voltage (Pins 5,13) ............... 16V to –0.3V
Continuous Output Current (Pins 4,12) ................ 50mA
Sense Voltages (Pins 1, 8, 9, 16)
VIN ≥ 12.7V .......................................... 13V to – 0.3V
VIN < 12.7V .............................. (VIN + 0.3V) to – 0.3V
Shutdown Voltage
(LTC1143, LTC1143L, Pins 2, 10)...........7V to – 0.3V
VFB Current (LTC1143L-ADJ, Pins 2, 10) ............... 1mA
Operating Temperature Range
Ambient .................................................. 0°C to 70°C
Extended Commercial (Note 4) ........... –40°C to 85°C
Junction Temperature (Note 1) ............................. 125°C
Storage Temperature Range .................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
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PACKAGE/ORDER INFORMATION
TOP VIEW
SENSE+3
1
16
SENSE–
3
ORDER PART
NUMBER
16 SENSE–1
SHUTDOWN 3 2
15 ITH3
VFB1 2
15 ITH1
GND3 3
14 CT3
GND1 3
14 CT1
P-DRIVE 3 4
VIN5 5
13 VIN3
12 P-DRIVE 5
LTC1143CS
LTC1143LCS
P-DRIVE 1 4
VIN2 5
12 P-DRIVE 2
CT5 6
11 GND5
CT2 6
11 GND2
10 SHUTDOWN 5
ITH2 7
10 VFB2
9
SENSE –2 8
SENSE+5
LTC1143LCS-ADJ
13 VIN1
ITH5 7
SENSE–5 8
ORDER PART
NUMBER
TOP VIEW
SENSE +1 1
9
SENSE +2
S PACKAGE
16-LEAD PLASTIC SO
S PACKAGE
16-LEAD PLASTIC SO
TJMAX = 125°C, θJA = 95°C/W
TJMAX = 125°C, θJA = 95°C/W
Consult factory for Industrial and Military grade parts.
ELECTRICAL CHARACTERISTICS
TA = 25°C, VIN = 10V unless otherwise noted.
SYMBOL PARAMETER
CONDITIONS
V2, V10
Feedback Voltage (LTC1143L-ADJ)
VIN = 9V
I2, I10
Feedback Current (LTC1143L-ADJ)
VOUT
Regulated Output Voltage (LTC1143/LTC1143L)
3.3V Output
5V Output
VIN3, VIN5 = 9V, V2 = V10 = 0V
ILOAD = 700mA
ILOAD = 700mA
Output Voltage Line Regulation
VIN = 7V to 12V, ILOAD = 50mA
Output Voltage Load Regulation
LTC1143/LTC1143L
3.3V Output
5V Output
V2 = V10 = 0V
Output Ripple (Burst Mode)
ILOAD = 0A
50
Input DC Supply Current (Note 2)
LTC1143:
Normal Mode
Sleep Mode
Shutdown
LTC1143L:
Normal Mode
Sleep Mode
Shutdown
LTC1143L-ADJ: Normal Mode
Sleep Mode
V2 = V10 = 0V, 4V < VIN < 12V
V2 = V10 = 0V, 4V < VIN3 < 12V, 6V < VIN5 < 12V
V2 = V10 = 2.1V, 4V < VIN < 12V
V2 = V10 = 0V, 3.5V < VIN < 12V
V2 = V10 = 0V, 3.5V < VIN3 < 12V, 6V < VIN5 < 12V
V2 = V10 = 2.1V, 3.5V < VIN < 12V
3.5V < VIN < 12V
3.5V < VIN < 12V, VOUT ≤ 3.3V
1.6
160
10
1.6
160
10
1.6
160
∆VOUT
I5, I13
2
●
MIN
TYP
MAX
UNITS
1.21
1.25
1.29
V
0.2
1
µA
3.23
4.90
3.33
5.05
3.43
5.20
V
V
–40
0
40
mV
40
60
65
100
mV
mV
●
5mA < ILOAD < 2.0A
5mA < ILOAD < 2.0A
●
●
●
●
mVP-P
2.1
230
20
2.1
230
20
2.1
230
mA
µA
µA
mA
µA
µA
mA
µA
LTC1143/LTC1143L
LTC1143L-ADJ
ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER
V1 to V16,
V8 to V9
Current Sense Threshold Voltage
LTC1143/LTC1143L
LTC1143L-ADJ
TA = 25°C, VIN = 10V unless otherwise noted.
CONDITIONS
MIN
V2 = V10 = 0V
VSENSE – = VOUT + 100mV (Forced)
VSENSE – = VOUT – 100mV (Forced)
VSENSE– = 5V, VFB = VOUT /4 + 25mV (Forced)
VSENSE– = 5V, VFB = VOUT /4 – 25mV (Forced)
TYP
MAX
UNITS
●
130
●
130
25
150
25
150
0.5
0.8
2
V
1.2
5
µA
170
170
mV
mV
mV
mV
V2, V10
Shutdown Pin Threshold
LTC1143/LTC1143L
I2, I10
Shutdown Pin Input Current
LTC1143/LTC1143L
0V < VSHUTDOWN = < 8V, VIN3, VIN5 = 16V
I6, I14
CT Pin Discharge Current
VOUT in Regulation, VSENSE- = VOUT
VOUT = 0V
50
70
2
90
10
µA
µA
tOFF
Off-Time (Note 3)
CT = 390pF, ILOAD = 700mA
4
5
6
µs
tr, tf
Driver Output Transition Times
CL = 3000pF (Pins 4, 12), VIN = 6V
100
200
ns
1.20
1.25
1.30
V
3.17
4.85
3.33
5.05
3.43
5.20
V
V
1.6
160
10
1.6
160
10
1.6
160
2.4
260
22
2.4
260
22
2.4
260
mA
µA
µA
mA
µA
µA
mA
µA
–40°C ≤ TA ≤ 85°C (Note 4), VIN = 10V unless otherwise noted.
V2, V10
Feedback Voltage (LTC1143L-ADJ)
VIN = 9V
VOUT
Regulated Output Voltage
LTC1143/LTC1143L
3.3V Output
5V Output
VIN3, VIN5 = 9V
I5, I13
V1 to V16,
V8 to V9
Input DC Supply Current (Note 2)
LTC1143:
Normal Mode
Sleep Mode
Shutdown
LTC1143L:
Normal Mode
Sleep Mode
Shutdown
LTC1143L-ADJ: Normal Mode
Sleep Mode
Current Sense Threshold Voltage
LTC1143/LTC1143L
LTC1143L-ADJ
V2, V10
ILOAD = 700mA
ILOAD = 700mA
V2 = V10 = 0V, 4V < VIN < 12V
V2 = V10 = 0V, 4V < VIN3 < 12V, 6V < VIN5 < 12V
V2 = V10 = 2.1V, 4V < VIN < 12V
V2 = V10 = 0V, 3.5V < VIN < 12V
V2 = V10 = 0V, 3.5V < VIN3 < 12V, 6V < VIN5 < 12V
V2 = V10 = 2.1V, 3.5V < VIN < 12V
3.5V < VIN < 12V
3.5V < VIN < 12V, VOUT ≤ 3.3V
V2 = V10 = 0V
VSENSE – = VOUT + 100mV (Forced)
VSENSE – = VOUT – 100mV (Forced)
VSENSE– = 5V, VFB = VOUT /4 + 25mV (Forced)
VSENSE– = 5V, VFB = VOUT /4 – 25mV (Forced)
Shutdown Pin Threshold
LTC1143/LTC1143L
The ● denotes specifications which apply over the specified temperature
range.
Note 1: TJ is calculated from the ambient temperature TA and power
dissipation PD according to the following formula:
LTC1143 series: TJ = TA + (PD • 125°C/W)
Note 2: This supply current is for one regulator block. Total supply
current is the sum of Pin 5 and Pin 13 currents. Dynamic supply current
125
25
150
25
150
0.55
0.8
125
185
185
2
mV
mV
mV
mV
V
is higher due to the gate charge being delivered at the switching
frequency. See Applications Information.
Note 3: In applications where RSENSE is placed at ground potential, the
off-time increases approximately 40%.
Note 4: The LTC1143 series is guaranteed to meet specified performance
from 0°C to 70°C and is designed, characterized and expected to meet
these extended temperature limits, but is not tested at –40°C to 85°C.
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LTC1143/LTC1143L
LTC1143L-ADJ
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TYPICAL PERFORMANCE CHARACTERISTICS
5V Output Efficiency
3.3V Output Efficiency
100
5V Efficiency vs Input Voltage
100
100
VIN = 6V
95
96
90
VIN = 10V
85
80
90
EFFICIENCY (%)
EFFICIENCY (%)
VIN = 5V
EFFICIENCY (%)
VOUT = 5V
98
95
VIN = 10V
85
80
75
75
70
70
94
ILOAD = 1A
92
90
88
ILOAD = 100mA
86
84
82
1
10
100
1000
1
10
LOAD CURRENT (mA)
100
0
3.3V Efficiency vs Input Voltage
1143 G03
Line Regulation
Load Regulation
40
VOUT = 3.3V
20
96
RSENSE = 0.05Ω
VOUT = 5V
ILOAD = 1A
30
0
20
90
ILOAD = 1A
88
ILOAD = 100mA
86
0
–10
VIN = 12V
–40
VIN = 6V
–60
–20
84
80
–40
4
0
12
8
INPUT VOLTAGE (V)
4
0
16
12
8
INPUT VOLTAGE (V)
LTC1143 G04
DC Supply Current
–100
16
0
SUPPLY CURRENT (µA)
PER REGULATOR BLOCK
0.9
0.6
VOUT = 5V
PER LTC1143/LTC1143L
REGULATOR BLOCK
PINS 5, 13
VSHUTDOWN = 2V
18
1.2
2.5
1.6
14
1.4
NORMALIZED FREQUENCY
PINS 5, 13
ACTIVE MODE
1.5
2.0
1.0
LOAD CURRENT (A)
Operating Frequency vs VIN – VOUT
Supply Current in Shutdown
16
1.5
0.5
LTC1143 G06
20
NOT INCLUDING
GATE CHARGE CURRENT
VOUT = 5V
VOUT = 3.3V
LTC1143 G05
2.1
1.8
VIN = 12V
–80
–30
82
SUPPLY CURRENT (mA)
VIN = 6V
–20
10
∆VOUT (mV)
∆VOUT (mV)
94
92
16
12
8
INPUT VOLTAGE (V)
LTC1143 G02
100
98
4
LOAD CURRENT (mA)
LTC1143 G01
EFFICIENCY (%)
80
1000
12
10
8
6
0°C
1.2
25°C
1.0
70°C
0.8
0.6
0.4
4
0.3
SLEEP MODE
0
0
0
0
2
4
8 10 12 14
6
INPUT VOLTAGE (V)
16
18
LTC1143 • G07
4
0.2
2
0
2
4
6
8 10 12 14
INPUT VOLTAGE (V)
16
18
0
2
4
6
8
10
12
(VIN – VOUT) VOLTAGE (V)
LTC1143 G08
LTC1143 G09
LTC1143/LTC1143L
LTC1143L-ADJ
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TYPICAL PERFORMANCE CHARACTERISTICS
Off-Time vs VOUT
80
12
70
VSENSE = VOUT
6
4
50
40
30
20
QP = 29nC
2
10
0
0
80
200
260
140
OPERATING FREQUENCY (kHz)
MAXIMUM
THRESHOLD
150
SENSE VOLTAGE (mV)
8
20
Current Sense Threshold Voltage
175
60
QP = 100nC
10
OFF-TIME (µs)
GATE CHARGE CURRENT (mA)
Gate Charge Supply Current
14
VOUT = 5V
1
75
50
MINIMUM
THRESHOLD
0
3
4
2
OUTPUT VOLTAGE (V)
LTC1143 G10
100
25
VOUT = 3.3V
0
125
5
LTC1143 G11
0
20
60
40
TEMPERATURE (°C)
80
100
LTC1143 G12
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PIN FUNCTIONS
LTC1143/LTC1143L
SENSE+3 (Pin 1): The (+) Input to the 3.3V Section Current
Comparator. A built-in offset between Pins 1 and 16 in
conjunction with RSENSE 3 sets the current trip threshold
for the 3.3V section.
SHUTDOWN 3 (Pin 2): When grounded, the 3.3V section
operates normally. Pulling Pin 2 high holds the MOSFET
off and puts the 3.3V section in micropower shutdown
mode. Requires CMOS logic level signal with tr, tf < 1µs.
Do not “float” Pin 2.
GND3 (Pin 3): 3.3V Section Ground. Two independent
ground lines must be routed separately from other grounds
to: 1) the (–) terminal of the 3.3V section output capacitor
and 2) the cathode of the Schottky diode D1 and (–)
terminal of CIN3 (see Figure 9).
P-DRIVE 3 (Pin 4): High Current Drive for Top P-Channel
MOSFET, 3.3V Section. Voltage swing at this pin is from
VIN3 to ground.
VIN5 (Pin 5): Supply Pin, 5V Section. Must be closely
decoupled to 5V power ground Pin 11.
CT5 (Pin 6): External capacitor CT5 from Pin 6 to ground sets
the operating frequency for the 5V section. (The actual
frequency is also dependent upon the input voltage.)
ITH5 (Pin 7): Gain Amplifier Decoupling Point, 5V Section.
The 5V section current comparator threshold increases
with the Pin 7 voltage.
SENSE– 5 (Pin 8): Connects to internal resistive divider
which sets the output voltage for the 5V section. Pin 8 is
also the (–) input for the current comparator on the 5V
section.
SENSE+ 5 (Pin 9): The (+) Input to the 5V Section Current
Comparator. A built-in offset between Pins 9 and 8 in
conjunction with RSENSE 5 sets the current trip threshold
for the 5V section.
SHUTDOWN 5 (Pin 10): When grounded, the 5V section
operates normally. Pulling Pin 10 high holds the 5V section
MOSFET off and puts the 5V section in micropower shutdown mode. Requires CMOS logic level signal with tr, tf < 1µs.
Do not “float” Pin 10.
GND5 (Pin 11): 5V Section Ground. Two independent
ground lines must be routed separately from other grounds
to: 1) the (–) terminal of the 5V section output capacitor
and 2) the cathode of the Schottky diode D2 and (–)
terminal of CIN5 (see Figure 9).
P-DRIVE 5 (Pin 12): High Current Drive for Top P-Channel
MOSFET, 5V Section. Voltage swing at this pin is from
VIN5 to ground.
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LTC1143/LTC1143L
LTC1143L-ADJ
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PIN FUNCTIONS
VIN3 (Pin 13): Supply Pin, 3.3V Section. Must be closely
decoupled to 3.3V power ground Pin 3.
CT3 (Pin 14): External capacitor CT3 from Pin 14 to ground
sets the operating frequency for the 3.3V section. (The
actual frequency is also dependent upon the input voltage.)
ITH3 (Pin 15): Gain Amplifier Decoupling Point, 3.3V
Section. The 3.3V section current comparator threshold
increases with the Pin 15 voltage.
SENSE– 3 (Pin 16): Connects to internal resistive
divider which sets the output voltage for the 3.3V
section. Pin 16 is also the (–) input for the current
comparator on the 3.3V section.
LTC1143L-ADJ
SENSE+ 1 (Pin 1): The (+) Input to the Section 1 Current
Comparator. A built-in offset between Pins 1 and 16 in
conjunction with RSENSE 1 sets the current trip threshold
for section 1.
VFB1 (Pin 2): This pin serves as the feedback pin from an
external resistive divider used to set the output voltage for
section 1.
ITH2 (Pin 7): Gain Amplifier Decoupling Point, Section 2.
The section 2 current comparator threshold increases
with the Pin 7 voltage.
SENSE– 2 (Pin 8): Pin 8 is the (–) input for the current
comparator on section 2.
SENSE+ 2 (Pin 9): The (+) Input to the Section 2 Current
Comparator. A built-in offset between Pins 9 and 8 in
conjunction with RSENSE 2 sets the current trip threshold
for section 2.
VFB2 (Pin 10): This pin serves as the feedback pin from an
external resistive divider used to set the output voltage for
section 2.
GND2 (Pin 11): Section 2 Ground. Two independent
ground lines must be routed separately from other grounds
to: 1) the (–) terminal of section 2 output capacitor and 2)
the cathode of the Schottky diode D2 and (–) terminal of
CIN2 (see Figure 1).
P-DRIVE 2 (Pin 12): High Current Drive for Top P-Channel
MOSFET, Section 2. Voltage swing at this pin is from VIN2
to ground.
VIN1 (Pin 13): Supply Pin, Section 1. Must be closely
decoupled to power ground Pin 3.
GND1 (Pin 3): Section 1 Ground. Two independent ground
lines must be routed separately from other grounds to: 1)
the (–) terminal of the section 1 output capacitor and 2) the
cathode of the Schottky diode D1 and (–) terminal of CIN1
(see Figure 1).
CT1 (Pin 14): External capacitor CT1 from Pin 14 to ground
sets the operating frequency for section 1. (The actual
frequency is also dependent upon the input voltage.)
P-DRIVE 1 (Pin 4): High Current Drive for Top P-Channel
MOSFET, Section 1. Voltage swing at this pin is from VIN1
to ground.
ITH1 (Pin 15): Gain Amplifier Decoupling Point, Section 1.
The section 1 current comparator threshold increases
with the Pin 15 voltage.
VIN2 (Pin 5): Supply Pin, Section 2. Must be closely
decoupled to power ground Pin 11.
SENSE – 1 (Pin 16): Pin 16 is the (–) input for the
current comparator on section 1.
CT2 (Pin 6): External capacitor CT2 from Pin 6 to ground sets
the operating frequency for section 2. (The actual frequency
is also dependent upon the input voltage.)
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LTC1143/LTC1143L
LTC1143L-ADJ
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FUNCTIONAL DIAGRA
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Only one regulator block shown. Connections shown for LT1143/LTC1143L; changes create LTC1143L-ADJ
13(5) VIN
4(12)
P-DRIVE
SENSE +
SENSE –
1(9)
16(8)
3(11) GROUND
–
V
SLEEP
–
R
25mV TO 150mV
C
Q
+
+
S
–
+
5pF
VOS
S
–
+
VTH1
VTH2
+
14(6)
CT
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OPERATION
ITH
–
OFF-TIME
CONTROL
–
13k
15(7)
T
VIN
SENSE –
G
+
X
1.25V
SHUTDOWN
(LTC1143/LTC1143L)
2(10)
VFB
(LTC1143L-ADJ)
X
100k
REFERENCE
1143 FD
Refer to Functional Diagram and Figure 1.
The LTC1143 series consists of two individual regulator
blocks, each using current mode, constant off-time architectures to switch an external power MOSFET. The two
LTC1143/LTC1143L regulators are internally set for 3.3V
and 5V, while the two LTC1143L-ADJ regulators have
externally programmable output voltages. Operating frequency is individually set on each section by external
capacitors at the timing capacitor Pins 6 and 14.
The output voltage is sensed by voltage comparator V and
gain block G, which compare the divided output voltage
with a reference voltage of 1.25V. To optimize efficiency,
the LTC1143 series automatically switches between two
modes of operation, burst and continuous. The voltage
comparator is the primary control element when the
device is in Burst Mode operation, while the gain block
controls the output voltage in continuous mode.
During the switch “ON” cycle in continuous mode, current
comparator C monitors the voltage between Pins 1 (9) and
16 (8) connected across an external shunt in series with
the inductor. When the voltage across the shunt reaches
its threshold value, the P-drive output is switched to VIN,
turning off the P-channel MOSFET. The timing capacitor
connected to Pin 14 (6) is now allowed to discharge at a
rate determined by the off-time controller. The discharge
current is made proportional to the feedback voltage to
model the inductor current, which decays at a rate that is
also proportional to the output voltage.
When the voltage on the timing capacitor has discharged
past VTH1, comparator T trips, setting the flip-flop. This
causes the P-drive output to go low, turning the P-channel
MOSFET back on. The cycle then repeats.
As the load current increases, the output voltage
decreases slightly. This causes the output of the gain
stage [Pin 15 (7)] to increase the current comparator
threshold, thus tracking the load current.
The sequence of events for Burst Mode operation is very
similar to continuous operation with the cycle interrupted
by the voltage comparator. When the output voltage is at
or above the desired regulated value, the P-channel
MOSFET is held off by comparator V and the timing
capacitor continues to discharge below VTH1. When the
timing capacitor discharges past VTH2, voltage comparator S trips, causing the internal sleep line to go low.
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LTC1143/LTC1143L
LTC1143L-ADJ
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OPERATION Refer to Functional Diagram and Figure 1
The circuit now enters sleep mode with the power MOSFET
turned off. In sleep mode a majority of the circuitry is
turned off, dropping the quiescent current from 1.6mA to
160µA (for one regulator block). The load current is now
being supplied from the output capacitor. When the output
voltage has dropped by the amount of hysteresis in
comparator V, the P-channel MOSFET is again turned on
and the process repeats.
To avoid the operation of the current loop interfering with
Burst Mode operation, a built-in offset (VOS) is incorpo-
rated in the gain stage. This prevents the current comparator threshold from increasing until the output voltage has
dropped below a minimum threshold.
Using constant off-time architecture the operating frequency is a function of the input voltage. To minimize the
frequency variation as dropout is approached, the off-time
controller increases the CT discharge current as VIN drops
below VOUT + 1.5V. In dropout the P-channel MOSFET is
turned on continuously (100% duty cycle), providing
extremely low dropout operation.
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The basic LTC1143L-ADJ application circuit is shown in
Figure 1. The LTC1143 and LTC1143L are similar but omit
the external resistive VOUT dividers (see Figures 10 and
13). External component selection is driven by the load
requirement and begins with VOUT and the selection of
RSENSE. Once RSENSE is known, CT and L can be chosen.
Next, the power MOSFET and D1 are selected. Finally, CIN
and COUT are selected and the loop is compensated. Since
the two regulator sections are identical, the process of
component selection is the same for both sections. The
circuit shown in Figure 1 can be configured for operation
up to an input voltage of 16V.
Output Voltage Selection
The LTC1143/LTC1143L output voltages are internally set
to 3.3V and 5V. The LTC1143L-ADJ requires an external
resistive divider from VOUT to VFB on each section as
shown in Figure 1. The regulated LTC1143L-ADJ output
voltages are given by:
 R2 
VOUT1 = 1.25  1 + 
 R1
 R4 
VOUT2 = 1.25  1 + 
 R3 
To prevent stray pickup, a 100pF capacitor is suggested
across R1 and R3 located close to the LTC1143L-ADJ.
8
For Figure 1 applications with VOUT below 2V, or when
RSENSE is moved to ground, the current sense comparator
inputs operate near ground. When the current comparator
is operated at less than 2V common mode, the off-time
increases approximately 40%, requiring the use of a
smaller timing capacitor CT.
RSENSE Selection for Output Current
RSENSE is chosen based on the required output current.
The LTC1143 series current comparators have a threshold
range that extends from a minimum of 25mV/RSENSE to a
maximum of 150mV/RSENSE. The current comparator
threshold sets the peak of the inductor ripple current,
yielding a maximum output current IMAX equal to the peak
value less half the peak-to-peak ripple current. For proper
Burst Mode operation, IRIPPLE(P-P) must be less than or
equal to the minimum current comparator threshold.
Since efficiency generally increases with ripple current,
the maximum allowable ripple current is assumed, i.e.,
IRIPPLE(P-P) = 25mV/RSENSE. (See CT and L Selection for
Operating Frequency). Solving for RSENSE and allowing a
margin for variations in the LTC1143 series and external
component values yields:
RSENSE = 100mV
IMAX
A graph for selecting RSENSE versus maximum output
current is given in Figure 2.
LTC1143/LTC1143L
LTC1143L-ADJ
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0.20
CT =
RSENSE (Ω)
0.15
 VIN − VOUT 


1.3 104  f  VIN + VD 
 
1
0.10
where VD is the drop across the diode.
0.05
A graph for selecting CT versus frequency including the
effects of input voltage is given in Figure 3.
1000
0
0
1
3
4
2
MAXIMUM OUTPUT CURRENT (A)
VSENSE = VOUT = 5V
5
800
CAPACITANCE (pF)
1143 F02
Figure 2. Selecting RSENSE
The load current below which Burst Mode operation
commences, IBURST, and the peak short circuit current,
ISC(PK), both track IMAX. Once RSENSE has been chosen,
IBURST and ISC(PK) can be predicted from the following:
600
VIN = 12V
400
VIN = 7V
200
VIN = 10V
0
0
IBURST ≈ 15mV
RSENSE
ISC(PK) = 150mV
RSENSE
The LTC1143 series automatically extends tOFF during a
short circuit to allow sufficient time for the inductor
current to decay between switch cycles. The resulting
ISC(AVG) to be reduced to approximately IMAX.
L and CT Selection for Operating Frequency
Each regulator section of the LTC1143 series uses a
constant off-time architecture with tOFF determined by an
external timing capacitor CT. Each time the P-channel
MOSFET switch turns on the voltage on CT is reset to
approximately 3.3V. During the off-time, CT is discharged
by a current that is proportional to VOUT. The voltage on CT
is analogous to the current in inductor L, which likewise
decays at a rate proportional to VOUT. Thus the inductor
value must track the timing capacitor value.
The value of CT is calculated from the desired continuous
mode operating frequency:
50
150
200
100
FREQUENCY (kHz)
250
300
LTC1143 F03
Figure 3. Timing Capacitor Value
As the operating frequency is increased the gate charge
losses will be higher, reducing efficiency (see Efficiency
Considerations). The complete expression for operating
frequency of the circuit in Figure 1 is given by:
f≈
1  VOUT 
1−
VIN 
t OFF 
where:
V 
t OFF = 1.3  104  CT  REG 
  V 
OUT
V REG is the desired output voltage (i.e., 5V, 3.3V). V OUT
is the measured output voltage. Thus VREG/VOUT = 1 in
regulation.
Note that as VIN decreases, the frequency decreases.
When the input-to-output voltage differential drops below
1.5V for a particular section, the LTC1143 series reduces
tOFF in that section by increasing the discharge current in
CT. This prevents audible operation prior to dropout.
9
LTC1143/LTC1143L
LTC1143L-ADJ
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Once the frequency has been set by CT, the inductor L must
be chosen to provide no more than 25mV/RSENSE of peakto-peak inductor ripple current. This results in a minimum
required inductor value of:
LMIN = 5.1(105)(RSENSE)(CT)VREG
As the inductor value is increased from the minimum
value, the ESR requirements for the output capacitor are
eased at the expense of efficiency. If too small an inductor
is used, the inductor current will become discontinuous
before the LTC1143 series enters Burst Mode operation. A
consequence of this is that the LTC1143 series will delay
entering Burst Mode operation and efficiency will be
degraded at low currents.
Inductor Core Selection
Once the minimum value for L is known, the type of
inductor must be selected. The highest efficiency will be
obtained using Ferrite, Kool Mµ® or Molypermalloy (MPP)
cores. Lower cost powdered iron cores provide suitable
performance, but cut efficiency by 3% to 7%. Actual core
loss is independent of core size for a fixed inductor value,
but it is very dependent on inductance selected. As
inductance increases, core losses go down. Unfortunately,
increased inductance requires more turns of wire and
therefore copper losses will increase.
Ferrite designs have very low core loss, so design goals
can concentrate on copper loss and preventing saturation.
Ferrite core material saturates “hard,” which means that
inductance collapses abruptly when the peak design current
is exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple that
can cause Burst Mode operation to be falsely triggered. Do
not allow the core to saturate!
Kool Mµ (from Magnetics, Inc.) is a very good, low loss core
material for toroids with a “soft” saturation characteristic.
Molypermalloy is slightly more efficient at high ( > 200 kHz)
switching frequencies but quite a bit more expensive.
Toroids are very space efficient, especially when you can
use several layers of wire, while inductors wound on
bobbins are generally easier to surface mount. New designs
for surface mount are available from Coiltronics, Coilcraft
and Sumida.
10
Power MOSFET Selection
An external power MOSFET must be selected for use with
each section of the LTC1143 series. The main selection
criteria for the power MOSFETs are the threshold voltage
VGS(TH), maximum VGS rating and on resistance RDS(ON).
Surface mount P-channel power MOSFETs are widely
available in both single and dual configurations. Logic
level MOSFETs are specified for operation up to 20V
maximum VGS and guarantee a maximum RDS(ON) with
VGS = 4.5V. Newer ‘sub’ logic level MOSFETs allow only 8V
maximum VGS but guarantee RDS(ON) with VGS = 2.7V. If
VIN will exceed 8V, logic level MOSFETs must be used; if
conservatively specified, they are generally usable down
to the 3.5V minimum VIN rating of the LTC1143L and
LTC1143L-ADJ.
The maximum output current IMAX determines the RDS(ON)
requirement for the two MOSFETs. When the LTC1143
series is operating in continuous mode, the simplifying
assumption can be made that either the MOSFET or
Schottky diode is always conducting the average load
current. The duty cycles for the MOSFET and diode are
given by:
V
P - Ch Duty Cycle ≈ OUT
VIN
Schottky Diode Duty Cycle =
(VIN − VOUT + VD)
VIN
From the duty cycles the required RDS(ON) for each MOSFET
can be derived:
P - Ch RDS(ON) =
( )


VOUT IMAX  (1 + δP)


VIN PP
2
where PP is the allowable power dissipation and δP is the
temperature dependencies of RDS(ON). PP will be determined
by efficiency and/or thermal requirements (see Efficiency
Considerations). (1+ δP) is generally given for a MOSFET in
the form of a normalized RDS(ON) vs temperature curve,
Kool Mµ is a registered trademark of Magnetics, Inc.
LTC1143/LTC1143L
LTC1143L-ADJ
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but δ = 0.005/°C can be used as an approximation for low
voltage MOSFETs.
When selecting the P-channel power MOSFET for each
section, consideration should be given to using a dual MOSFET
with the other half used for the second regulator. Assuming
both sections are operating at similar currents, the required
RDS(ON) will be half the value of a single MOSFET to stay within
the package dissipation limit. Remember that worst-case
MOSFET dissipation occurs at minimum VIN.
Output Diode Selection (D1, D2)
The Schottky diodes D1 and D2 shown in Figure 1 conduct
during the off-time. It is important to adequately specify
the diode peak current and average power dissipation to
not exceed the diode ratings.
The most stressful condition for the output diode is under
short circuit (VOUT = 0V). Under this condition the diode
must safely handle ISC(PK) at close to 100% duty cycle.
Under normal load conditions the average current conducted by the diode is:
(VIN − VOUT + VD) (ILOAD)
IDIODE =
VIN
Remember to keep lead lengths short and observe proper
grounding (see Board Layout Checklist) to avoid ringing
and increased dissipation.
The forward voltage drop allowable in the diode is calculated from the maximum short-circuit current as:
VF ≈
PD
ISC(PK)
where PD is the allowable power dissipation and will be
determined by efficiency and/or thermal requirements
(see Efficiency Considerations).
CIN and COUT Selection
In continuous mode, the source current of the P-channel
MOSFET is a square wave of duty cycle VOUT/ VIN. To
prevent large voltage transients, a low effective series
resistance (ESR) input capacitor sized for the maximum
RMS current must be used. The maximum RMS capacitor
current is given by:
CIN Required IRMS ≈ IMAX
[ (
VOUT VIN − VOUT
)]
1/ 2
VIN
This formula has a maximum at VIN = 2VOUT, where IRMS
= IOUT /2. This simple worst-case condition is commonly
used for design because even significant deviations do not
offer much relief. Note that capacitor manufacturer’s
ripple current ratings are often based on only 2000 hours
of life. This makes it advisable to further derate the
capacitor, or to choose a capacitor rated at a higher
temperature than required. Several capacitors may also be
paralleled to meet size or height requirements in the
design. Always consult the manufacturer if there is any
question. An additional 0.1µF to 1µF ceramic capacitor is
also required on each VIN line (Pins 5, 13) for high
frequency decoupling.
The selection of COUT is driven by the required (ESR). The
ESR of COUT must be less than twice the value of RSENSE
for proper operation of the LTC1143 series:
COUT Required ESR < 2RSENSE
Optimum efficiency is obtained by making the ESR equal
to RSENSE. As the ESR is increased up to 2RSENSE the
efficiency degrades by less than 1%. If the ESR is greater
than 2RSENSE, the voltage ripple on the output capacitor
will prematurely trigger Burst Mode operation, resulting in
disruption of continuous mode and an efficiency hit which
can be several percent.
Manufacturers such as Nichicon and United Chemicon
should be considered for high performance capacitors.
The OS-CON semiconductor dielectric capacitor available
from Sanyo has the lowest ESR size/ratio of any aluminum
electrolytic at a somewhat higher price. Once the ESR
requirement for COUT has been met, the RMS current
rating generally far exceeds the IRIPPLE(P-P) requirement.
In surface mount applications multiple capacitors may
have to be parallel to meet the capacitance, ESR or RMS
current handling requirements of the application.
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LTC1143/LTC1143L
LTC1143L-ADJ
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Aluminum electrolytic and dry tantalum capacitors are
both available in surface mount configurations. In the case
of tantalum it is critical that the capacitors are surge tested
for use in switching power supplies. An excellent choice is
the AVX TPS series of surface mount tantalums, available
in case heights ranging from 2mm to 4mm. For example,
if 200µF/10V is called for in an application requiring 3mm
height, (2) AVX 100µF/10V (P/N TPSD 107M010) could be
used. Consult the manufacturer for other specific
recommendations.
At low supply voltages a minimum capacitance at COUT is
needed to prevent an abnormal low frequency operating
mode (see Figure 4). When COUT is made too small the
output ripple at low frequencies will be large enough to trip
the voltage comparator. This causes Burst Mode operation
to be activated when the LTC1143 series would normally
be in continuous operation. The output remains in
regulation at all times.
1000
L = 50µH
RSENSE = 0.02Ω
COUT (µF)
800
L = 25µH
RSENSE = 0.02Ω
600
A second, more severe transient is caused by switching in
loads with large (>1µF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with COUT causing a rapid drop in VOUT. No regulator can
deliver enough current to prevent this problem if the load
switch resistance is low and it is driven quickly. The only
solution is to limit the rise time of the switch drive so that
the load rise time is limited to approximately 25 • CLOAD.
Thus a 10µF capacitor would require a 250µs rise time,
limiting the charging current to about 200mA.
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can be
expressed as:
%Efficiency = 100% – (L1 + L2 + L3 + ...)
400
where L1, L2, etc. are the individual losses as a percentage
of input power. (For high efficiency circuits only small
errors are incurred by expressing losses as a percentage
of output power.)
L = 50µH
RSENSE = 0.05Ω
200
0
0
1
3
4
2
VIN – VOUT VOLTAGE (V)
5
1143 F04
Figure 4. Minimum Value of COUT
Checking Transient Response
The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in DC (resistive) load
current. When a load step occurs, VOUT shifts by an
amount equal to ∆ILOAD × ESR, where ESR is the effective
series resistance of COUT. ∆ILOAD also begins to charge or
discharge COUT until the regulator loop adapts to the
current change and returns VOUT to its steady-state value.
12
During this recovery time VOUT can be monitored for
overshoot or ringing which would indicate a stability
problem. The Pin 15(7) external components shown in the
Figure 1 circuit will prove adequate compensation for
most applications.
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of the
losses in LTC1143 series circuits:
1)
2)
3)
4)
DC bias current
MOSFET gate charge current
I 2 R losses
Voltage drop of the Schottky diode.
1) The DC supply current is the current that flows into
VIN (Pin 13 and Pin 5) less the gate charge current. For
VIN = 10V the DC supply current for each section is 160µA
for no load and increases proportionally with load up to
a constant 1.6mA after the LTC1143 series has entered
continuous mode. Because the DC bias current is
LTC1143/LTC1143L
LTC1143L-ADJ
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2) MOSFET gate charge current results from switching
the gate capacitance of the power MOSFET. Each time
a MOSFET gate is switched from low to high to low again,
a packet of charge dQ moves from VIN to ground. The
resulting dQ/dt is a current out of VIN that is typically
much larger than the DC supply current. In continuous
mode, IGATECHG = ƒ(QP). The typical gate charge for
a 0.05Ω P-channel power MOSFET is 40nC. This
results in IGATECHG = 4mA in 100kHz continuous operation, for a 2% to 3% typical midcurrent loss with
VIN = 10V.
Note that the gate charge loss increases directly with
both input voltage and operating frequency. This is the
principal reason why the highest efficiency circuits
operate at moderate frequencies. Furthermore, it
argues against using a larger MOSFET than necessary
to control I2R losses, since overkill can cost efficiency
as well as money!
3) I2R losses are easily predicted from the DC resistances
of the MOSFET, inductor and current shunt. In continuous
mode the average output current flows through L and
RSENSE, but is “chopped” between the P-channel
MOSFET and Schottky diode. The MOSFET RDS(ON) multiplied by the P-channel duty cycle can be summed with
the resistances of L and RSENSE to obtain I2R losses.
For example, if the RDS(ON) = 0.1Ω, RL = 0.15Ω, and
RSENSE = 0.05Ω, then the total resistance is 0.3Ω. This
results in losses ranging from 3% to 10% as the output
current increases from 0.5A to 2A. I2R losses cause the
efficiency to roll off at high output currents.
4) The Schottky diode is a major source of power loss at
high currents and gets worse at high input voltages.
The diode loss is calculated by multiplying the forward
voltage drop times the Schottky diode duty cycle
multiplied by the load current. For example, assuming
a duty cycle of 50% with a Schottky diode forward
voltage drop of 0.4V, the loss increases from 0.5% to
8% as the load current increases from 0.5A to 2A. If
Schotky diode losses routinely exceed 5% consider
using the synchronously switched LTC1142 series.
Figure 5 shows how the efficiency losses in one section of
a typical LTC1143 series regulator end up being apportioned. The gate charge loss is responsible for the majority
of the efficiency lost in the midcurrent region. If Burst
Mode operation was not employed at low currents, the
gate charge loss alone would cause efficiency to drop to
unacceptable levels. With Burst Mode operation, the DC
supply current represents the lone (and unavoidable) loss
component, which continues to become a higher percentage as output current is reduced. As expected, the I2R
losses and Schottky diode loss dominate at high load
currents.
Other losses including CIN and COUT ESR dissipative
losses, MOSFET switching losses and inductor core losses,
generally account for less than 2% total additional loss.
100
I2R
GATE CHARGE
95
EFFICIENCY (%)
drawn from VIN, the resulting loss increases with
input voltage. For VIN = 10V the DC bias losses are
generally less than 1% for load currents over 30mA.
However at very low load currents the DC bias current
accounts for nearly all of the loss.
1⁄ LTC1143 I
2
Q
SCHOTTKY
DIODE
90
85
80
0.01
0.03
0.3
1
0.1
OUTPUT CURRENT (A)
3
LTC1143 • F05
Figure 5. Efficiency Loss
Shutdown Considerations
Pins 2 and 10 on the LTC1143 and LTC1143L shut down
their respective sections when pulled high. They require
CMOS logic level signals with tr, tf < 1µs and must never
be floated. The LTC1143L-ADJ gives up the pin-controlled
shutdown function in order to gain feedback pins for
programming the output voltages.
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LTC1143/LTC1143L
LTC1143L-ADJ
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The LTC1143L-ADJ outputs can be turned off in one of two
ways: 1) by placing a power MOSFET switch in the VIN line
to the entire regulator or 2) by pulling the VFB pin over
1.4V, which trips comparator V and forces P-DRIVE high
(see Functional Diagram). VFB can be pulled high with a
small current, but any circuitry used to shut down the
LTC1143L-ADJ in this manner must minimize VFB lead
length to prevent noise coupling during normal operation.
In the Figure 6 circuit, taking SHUTDOWN high turns on
PNP QSD that sources a current into VFB. To shut down
properly, RSD must be chosen to pull VFB above 1.4V with
VOUT at 0V and minimum VIN. Note that this technique
depends on the load resistance to prevent VOUT from
floating up due to the current flowing into VFB.
VOUT
R2
100pF
SHUTDOWN
1143 F06
Figure 6. Local VFB Pull-Up Shuts Down LTC1143L-ADJ
Design Example
As a design example, assume VIN = 12V(nominal), VOUT =
3.3V, IMAX = 2A and ƒ = 200kHz. RSENSE, CT and L can
immediately be calculated:
RSENSE = 100mV/2 = 0.05Ω
tOFF = (1/200kHz)[1 – (3.3/12)] = 3.63µs
CT = 3.63µs/(1.3 × 104) = 280pF (use 300pF)
LMIN = 5.1(105 )(0.05Ω)(300pF) 3.3V = 25µH
Assume a dual P-channel power MOSFET is to be
used and dissipation is to be limited to 1W total at
worst-case lowest VIN = 4V. If TA = 50°C and the
thermal resistance of the MOSFET package is 50°C/W,
then the junction temperature will be 100°C and
14
Allowing for V IN being slightly below the VGS used to
specify RDS(ON), this requirement can be met by half of
a Siliconix Si4953DY, Fairchild NDS8947 or similar
SO-8 dual P-channel MOSFET.
The most stringent requirement for the Schottky diode is
with VOUT = 0V (i.e. short circuit). During a continuous short
circuit, the worst-case Schottky diode dissipation rises to:
With the 0.05Ω sense resistor, ISC(AVG) = 2A will result,
increasing the 0.4V Schottky diode dissipation to 0.8W.
100k
R1
50k

( )  = 0.11Ω
( ) ( )
( )
200k
QSD
VFB

41
1
P - Ch RDS(ON) = 
2
2
3.3 2 1.38

 V 
PD = ISC(AVG) VD  1 − OUT 
VIN 

VIN
RSD
δP = 0.005(100 – 25) = 0.38. The maximum RDS(ON) for
each MOSFET can now be calculated:
CIN will require an RMS current rating of at least 1A at
temperature and COUT will require an ESR of 0.05Ω for
optimum efficiency.
Troubleshooting Hints
Since efficiency is critical to LTC1143 series applications
it is very important to verify that the circuit is functioning
correctly in both continuous and Burst Mode operation.
The waveform to monitor is the voltage on the timing
capacitor Pins 6 and 14.
In continuous mode (ILOAD > IBURST) the voltage on the CT
pin should be a sawtooth with a 0.9VP-P swing. This
voltage should never dip below 2V as shown in Figure 7a.
When load currents are low (ILOAD < IBURST) Burst Mode
operation occurs. The voltage on the CT pin now falls to
ground for periods of time as shown in Figure 7b.
If Pin 6 or Pin 14 is observed falling to ground at high
output currents, it indicates poor decoupling or improper
grounding. Refer to the Board Layout Checklist.
LTC1143/LTC1143L
LTC1143L-ADJ
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3.3V
With the addition of R3 a current is generated though R1,
causing an offset of:
0V
(a) CONTINUOUS MODE OPERATION
3.3V
0V
(b) Burst Mode OPERATION
LTC1143 • F07
Figure 7. CT Waveforms
Auxiliary Windings––Suppressing Burst Mode
Operation
The LTC1143 series operates nonsynchronously with the
normal limitation that the power drawn from the inductor
primary winding must not be less than twice the power
drawn from the auxiliary windings. (With synchronous
switching, using the LTC1142 series, auxiliary outputs
may be loaded without regard to the primary output load,
providing that the loop remains in continuous mode
operation.)
Burst Mode operation can be suppressed at low output
currents with a simple external network that cancels the
25mV minimum current comparator threshold. This technique is also useful for eliminating audible noise from
certain types of inductors in high current (IOUT > 5A)
applications when they are lightly loaded.
An external offset is put in series with the Sense– pin to
subtract from the built-in 25mV offset. An example of this
technique is shown in Figure 8. Two 100Ω resistors are
inserted in series with the sense leads from the sense
resistor.
1000pF
SENSE –
[PIN 1(9)]
R1
100Ω
RSENSE
VOUT
+
R3
If VOFFSET > 25mV, the built-in offset will be cancelled and
Burst Mode operation is prevented from occurring. Since
VOFFSET is constant, the maximum load current is also
decreased by the same offset. Thus, to get back to the
same IMAX, the value of the sense resistor must be lower:
RSENSE ≈
75mV
IMAX
To prevent noise spikes from erroneously tripping the
current comparator, a 1000pF capacitor is needed across
Pins 1 (16) and 9 (8).
Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC1143 series. These items are also illustrated graphically in the layout diagram of Figure 9. In general, each
block should be self-contained with little cross coupling
for best performance. Check the following in your layout:
1) Are the signal and power grounds segregated? The
LTC1143 series GND Pin 3 (11) must return separately
to: a) the power and b) the signal grounds. The
power ground returns to the anode of the Schottky
diode and (–) plate of CIN, which should have as short
lead lengths as possible.The signal ground (b) connects to the (–) plate of COUT.
2) Does the LTC1143 series SENSE – Pin 16 (8) connect
to a point close to RSENSE and the (+) plate of COUT?
R2
100Ω
SENSE +
[PIN 16 (8)]
 R1 
VOFFSET = VOUT 

 R1 + R3 
COUT
1143 F08
Figure 8. Suppression of Burst Mode Operation
3) Are the SENSE– and SENSE + leads routed together
with minimum PC trace spacing? The 1000pF
capacitor between Pins 1 (9) and 16 (8) should be as
close as possible to the LTC1143 series.
4) Does the (+) plate of CIN connect to the source of the
P-channel MOSFET as closely as possible? This
capacitor provides the AC current to the P-channel
MOSFET.
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APPLICATIONS INFORMATION
high impedance and must not be allowed to float. Both
pins can be driven by the same external signal if
needed.
5) Is the VIN decoupling capacitor (1µF, 0.1µF) connected closely between Pin 13 (5) and GND Pin 3
(11)? This capacitor carries the MOSFET driver peak
currents.
7) For the LTC1143L-ADJ, are the VFB Pins 2 and 10
decoupled with 100pF as close to the device as
possible? The VFB line is sensitive to noise pickup and
should be kept away from the P-channel MOSFET.
6) For the LTC1143 and LTC1143L, are the SHUTDOWN Pins 2 and 10 actively pulled to ground
during normal operation? Both SHUTDOWN pins are
L1
P-CH
+
+
VIN5
RSENSE5
+
+
CIN5
COUT5
D1
–
VOUT5
–
SHUTDOWN
(5V OUTPUT)
VIN3
LTC1143
SENSE +5
SHUTDOWN 5
1000pF*
–5
0.22µF*
SENSE
ITH5
P-DRIVES5
GND5
CT5
ITH3
CT3
VIN3
P-DRIVES3
VIN5
0.22µF*
SENSE +3
1000pF*
SHUTDOWN 3
0.0033µF
GND3
CT3
SENSE –3
1k
VIN5
SHUTDOWN
(3.3V OUTPUT)
1k
CT5
RSENSE3
+
L2
P-CH
D2
+
VOUT3
0.0033µF
+
+
CIN3
COUT3
–
VIN3
–
1143 F09
*MUST BE LOCATED CLOSE TO LTC1143
BOLD LINES INDICATE HIGH CURRENT PATHS
Figure 9. LTC1143 Layout Diagram (see Board Layout Checklist)
16
LTC1143/LTC1143L
LTC1143L-ADJ
U
TYPICAL APPLICATIONS
VIN RANGE
VOUT5 ON: 5.2V TO 8V
VOUT5 SHUTDOWN: 3.5V TO 8V
CIN3
22µF
25V
×2
+
+
0.22µF
13
VIN3
P1A
VOUT3
3.3V/1A
4
L1
50µH
RSENSE3
0.10Ω
1
10
COUT3
220µF
10V
5
VIN5
SHUTDOWN 5
P-DRIVE 3
P-DRIVE 5
SENSE + 3
SENSE + 5
LTC1143L
0.01µF
+
0.22µF
2
SHUTDOWN 3
16
SENSE – 5
3
14
CT3
270pF
CIN3, CIN5: AVX TPSD226K025R0200
COUT3, COUT5: AVX TPSE227M010R0080
L2: COILTRONICS CTX50-4
L2: COILTRONICS CTX25-4
P1: FAIRCHILD NDS8934
RSENSE3: IRC LR2512-01-OR100G
RSENSE5: IRC LR2512-01-ORO5OG
ITH5
CT5
GND5
15
7
6
11
RC3
1k
RC5
1k
ITH3
CT3
GND3
CIN5
22µF
25V
×2
P1B
12
L2
25µH
RSENSE5
0.05Ω
VOUT5
5V/2A
9
0.01µF
SENSE – 3
D1
MBRS140T3
+
+
0V = NORMAL
>1.5V = SHUTDOWN
CC3
3300pF
8
+
COUT5
220µF
10V
×2
D2
MBRS140T3
1143 F10
CC5
3300pF
CT5
220pF
Figure 10. All Surface Mount Low Dropout Dual 5V/2A, 3.3V/1A Converter
VIN
4V TO 14V
+
VOUT1
1.8V/3A
RSENSE1
0.025Ω
CIN1
22µF
25V
×3
COUT1
330µF
6.3V
×2
0.22µF
P1
4
L1
15µH
1
100Ω
+
R2
22.1k
1%
R1
49.9k
1%
100Ω
D1
MBRS320T3
CIN2
22µF
25V
×2
+
0.22µF
13
VIN1
5
VIN2
P-DRIVE 1
P-DRIVE 2
SENSE + 1
SENSE + 2
1000pF
5.6k
P2
12
2
100pF
SENSE – 2
VFB2
VFB1
GND1
CT1
3
14
CT1
220pF
CIN1, CIN2: AVX TPSD226K025R0200
COUT1: AVX TPSE337M006R0100
COUT2: AVX TPSE227M010R0100
1000pF
SENSE – 1
ITH1
15
RC1
510Ω
CC1
CC2
3300pF 3300pF
L1: SUMIDA CDRH125-150
L2: SUMIDA CDRH125-270
ITH2
CT2
GND2
7
6
11
RSENSE2
0.04Ω
9
LTC1143L-ADJ
16
L2
27µH
100Ω
100Ω
8.2k
D2
MBRS320T3
R4
49.9k
1%
100pF
100pF
R3
49.9k
1%
8
VOUT2
2.5V/2A
10
+
COUT2
220µF
10V
×2
RC2
1k
CT2
300pF
P1: IR IRF7406
P2: IR IRF7204
RSENSE1: DALE WSL-2010-.025
RSENSE2: DALE WSL-2010-.04
1143 F11
Figure 11. Dual 1.8V/3A and 2.5V/2A with Burst Mode Defeated
17
LTC1143/LTC1143L
LTC1143L-ADJ
U
TYPICAL APPLICATIONS
VIN
3.5V TO 10V
+
RSENSE1
0.05Ω
VOUT1
3.3V/2A
CIN1
22µF
25V
×2
0.22µF
P1
4
L1
27µH
1
13
VIN1
5
P-DRIVE 2
P-DRIVE 1
SENSE + 1
SENSE + 2
+
R2
82.5k
1%
R1
49.9k
1%
16
D1
MBRS130L
2
100pF
L2A
VFB2
GND1
3
CT1
14
ITH1
15
RC1
1k
CC1
3300pF
ITH2
CT2
7
6
RC2
1k
CC2
3300pF
L2B
CIN2
22µF
25V
×2
VOUT2
5V/1A
D2
MBRS130L
9
1000pF
SENSE – 2
VFB1
CT1
300pF
CIN1, CIN2: AVX TPSD226K025R0200
COUT1, COUT2: AVX TPSE227M010R0100
L1: SUMIDA CDRH125-270
L2: PULSE ENGINEERING PE-53718
12
LTC1143L-ADJ
SENSE – 1
220µF
10V
+
VIN2
1000pF
COUT1
220µF
10V
×2
+
P2
0.22µF
RSENSE2
0.082Ω
8
10
GND2
COUT2
220µF
10V
R4
150k
1%
R3
49.9k
1%
100pF
11
CT2
180pF
P1, P2: SILICONIX Si9803DY
RSENSE1: IRC 1206-R050F
RSENSE2: IRC 1206-R082F
Z1: MMBZ5231B
OVERVOLTAGE
PROTECTION
Z1
5.1V
MMBT2222ALT1
1k
1143 F12
Figure 12. Dual 3.3V/5V Buck-Boost Regulator
18
LTC1143/LTC1143L
LTC1143L-ADJ
U
PACKAGE DESCRIPTION
Dimensions in inches (millimeters) unless otherwise noted.
S Package
16-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
0.386 – 0.394*
(9.804 – 10.008)
16
15
14
13
12
11
10
9
0.150 – 0.157**
(3.810 – 3.988)
0.228 – 0.244
(5.791 – 6.197)
1
0.010 – 0.020
× 45°
(0.254 – 0.508)
0.008 – 0.010
(0.203 – 0.254)
2
3
4
5
6
0.053 – 0.069
(1.346 – 1.752)
0.014 – 0.019
(0.355 – 0.483)
8
0.004 – 0.010
(0.101 – 0.254)
0° – 8° TYP
0.016 – 0.050
0.406 – 1.270
7
0.050
(1.270)
TYP
S16 0695
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
19
LTC1143/LTC1143L
LTC1143L-ADJ
U
TYPICAL APPLICATION
VIN
5.2V TO 14V
CIN3
22µF
25V
×3
+
+
13
VIN3
P1
VOUT3
3.3V/3A
RSENSE3
0.033Ω
L1
10µH
4
1
+
+
0V = NORMAL
>1.5V = SHUTDOWN
0.22µF
2
0.22µF
10
SHUTDOWN 3
5
VIN5
SHUTDOWN 5
P-DRIVE 3
P-DRIVE 5
SENSE +
SENSE +
3
LTC1143
5
P2
12
16
OUT3
220µF
10V
×3
D1
MBRD340
RSENSE5
0.05Ω
VOUT5
5V/2A
0.01µF
SENSE – 3
GND3
3
SENSE – 5
CT3
ITH3
ITH5
CT5
GND5
7
6
11
15
14
CT3
200pF
CIN3, CIN5: AVX TPSD226K025R0200
COUT3, COUT5: AVX TPSE227M010R0080
L1: COILTRONICS CTX10-4
L2: COILTRONICS CTX25-4
L2
25µH
9
0.01µF
+C
CIN5
22µF
25V
×2
RC3
510Ω
CC3
3300pF
RC5
1k
CC5
3300pF
8
COUT5
220µF
10V
×2
+
D2
MBRD340
LTC1143.F13
CT5
220pF
P1: SILICONIX Si4431DY
P2: SILICONIX Si9435DY
RSENSE3: KRL SL-1/2-C1-0R033J
RSENSE5: KRL SL-1/2-C1-0R050J
Figure 13. All Surface Mount Dual 5V/2A, 3.3V/3A Converter
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC1142
Dual High Efficiency Synchronous Step-Down Switching Regulator
Synchronous Equivalent to LTC1143, 4V < VIN < 16V
LTC1142L-ADJ
Dual High Efficiency Synchronous Step-Down Switching Regulator
Synchronous Equivalent to LTC1143L-ADJ, 3.5V < VIN < 16V
LTC1142HV-ADJ Dual High Efficiency Synchronous Step-Down Switching Regulator
4V < VIN < 20V
LTC1147L
High Efficiency Step-Down Switching Regulator Controller
(1/2) LTC1143L-ADJ in SO-8
LTC1265
1.2A, High Efficiency Step-Down DC/DC Converter
Single Channel with Internal Switch
LTC1438
Dual Synchronous Controller with Power-On Reset and
an Extra Comparator
Constant Frequency Current Mode, Drives Synchronous
N-Channel MOSFETS
LTC1538-AUX
Dual Synchronous Controller with Auxiliary Linear Regulator
Controller and 5V Standby
Up to Four Output Voltages from G28 Package
LTC1539
Dual Synchronous Controller with Phase-Locked Loop
and Adaptive PowerTM Operation
Full Featured Dual Controller in G36 Package
Adaptive Power is a trademark of Linear Technology Corporation.
20
Linear Technology Corporation
1143fa LT/TP 0598 REV A 2K • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408)432-1900 ● FAX: (408) 434-0507 ● www.linear-tech.com
 LINEAR TECHNOLOGY CORPORATION 1994