N
CLC532
High-Speed 2:1 Analog Multiplexer
General Description
Features
The CLC532 is a high-speed 2:1 multiplexer with active input and
output stages. The CLC532 also employs a closed-loop design which
dramatically improves accuracy. This monolithic device is constructed
using an advanced high-performance bipolar process.
■
■
■
■
■
The CLC532 has been specifically designed to provide settling times
of 17ns to 0.01%. This, coupled with the adjustable noise-bandwidth,
makes the CLC532 an ideal choice for infrared and CCD imaging
systems. Channel-to-channel isolation is better than 80dB @
10MHz. Low distortion (80dBc) and spurious signal levels make the
CLC532 a very suitable choice for both I/Q processors and receivers.
12-bit settling (0.01%) - 17ns
Low noise - 32µVrms
High isolation - 80dB @ 10MHz
Low distortion - 80dBc @ 5MHz
Adjustable bandwidth - 190MHz (max)
Applications
■
■
■
■
■
Infrared system multiplexing
CCD sensor signals
Radar I/Q switching
High definition video HDTV
Test and calibration
CLC532
High-Speed 2:1 Analog Multiplexer
June 1999
The CLC532 is offered over both the industrial and military temperature
ranges. The Industrial versions, CLC532AJP\AJE\AID, are specified
from -40°C to +85°C and are packaged in 14-pin plastic DIP's, 14-pin
SOIC's and 14-pin Side-Brazed packages. The extended temperature
versions, CLC532A8B/A8D/A8L-2, are specified from -55°C to +125°C
and are packaged in a 14-pin hermetic DIP and 20-terminal LCC
packages. (Contact factory for LCC and CERDIP availability.)
Ordering Information ...
-40oC
-40oC
-40oC
-55oC
-55oC
+85oC
+85oC
+85oC
+125oC
+125oC
14-pin plastic DIP
14-pin plastic SOIC
dice
dice, MIL-STD-833
14-pin CERDIP;
MIL-STD-883
20-terminal LCC;
CLC532A8L-2A
-55oC to +125oC
MIL-STD-883
Contact factory for other packages and DESC SMD number.
CCOMP1
2
INA
1
RIN
12
CLC532
CHANNEL B
4
INB
3
10
11
6
DREF
VOUT
8
7
6
5
4
9
SELECT 10
RL
7
CCOMP2
RIN
DREF
GND
CHANNEL A
NC
20-Terminal LCC
INB
Typical Application
NC
to
to
to
to
to
DGND
CLC532AJP
CLC532AJE
CLC532ALC
CLC532AMC
CLC532A8B
NC 11
TOP VIEW
VEE 12
13
VEE
COMP1
NC
OUTPUT
Printed in the U.S.A.
NC
1999 National Semiconductor Corporation
1
14
+VCC
3
INA
INA
2
13
+VCC
2
GND
1
NC
GND
3
12
COMP1
INB
4
11
OUTPUT
DGND
5
10
COMP2
DREF
6
9
VEE
SELECT
7
8
VEE
cc
COMP2
SELECT OUTPUT
1
Channel A
0
Channel B
GND
INDEX CORNER
20 +Vcc
19 +V
14 15 16 17 18
CHANNEL
SELECT
Pinout
DIP & SOIC
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Electrical Characteristics (+V
CC
PARAMETER1
Case Temperature
FREQUENCY DOMAIN PERFORMANCE
-3dB bandwidth
-3dB bandwidth
gain flatness
peaking
rolloff
linear phase deviation
differential gain
differential phase
crosstalk rejection
TIME DOMAIN PERFORMANCE
rise and fall time
settling time
2V step; from 50% VOUT
overshoot
slew rate
SWITCH PERFORMANCE
channel to channel switching time
(2V step at output)
switching transient
Ω ; RL=500Ω
Ω ; CCOMP=10pF; ECL Mode, pin 6 = NC)
=+5.0V; -VEE=-5.2V; RIN=50Ω
MAX/MIN RATINGS2
-40°C
+25°C
+85°C
CONDITIONS
CLC532AJP/AJE/AIB
TYP
+25°C
UNITS
SYMBOL
V OUT <0.1Vpp
V OUT=2Vpp
V OUT <0.1Vpp
0.1MHz to 200MHz
0.1MHz to 100MHz
dc to 100MHz
CCOMP = 5pF; RL=150Ω
CCOMP = 5pF; RL=150Ω
2Vpp, 10MHz
2Vpp, 20MHz
2Vpp, 30MHz
190
45
140
35
140
35
110
30
MHz
MHz
SSBW
LSBW
0.2
1.0
2.0
0.05
0.01
80
74
68
0.7
1.8
0.7
1.8
0.8
2.6
75
69
63
75
69
63
74
68
62
dB
dB
deg
%
deg
dB
dB
dB
GFP
GFR
LPD
DG
DP
CT10
CT20
CT30
0.5V step
2V step
±0.0025%
±0.01%
±0.1%
2.0V step
2.7
10
35
17
13
2
160
3.3
12.5
3.3
12.5
3.8
14.5
24
18
5
130
24
18
5
130
27
21
6
110
ns
ns
ns
ns
ns
%
V/µs
TRS
TRL
TS14
TSP
TSS
OS
SR
50% SELECT to 10%V OUT
50% SELECT to 90%V OUT
5
15
30
7
20
7
20
8
23
ns
ns
mV
SWT10
SWT90
ST
DISTORTION AND NOISE PERFORMANCE
2nd harmonic distortion
2Vpp, 5MHz
3rd harmonic distortion
2Vpp, 5MHz
equivalent input noise
spot noise voltage
>1MHz
integrated noise
1MHz to 100MHz
spot noise current
80
86
67
68
67
68
67
68
dBc
dBc
HD2
HD3
3.1
32
3
42
42
46
nV/√Hz
µVrms
pA/√Hz
SNF
INV
SNC
STATIC AND DC PERFORMANCE
* analog output offset voltage
temperature coefficient
analog output offset voltage matching
* analog input bias current
temperature coefficient
analog input bias current matching
analog input resistance
analog input capacitance
* gain accuracy
gain matching
integral endpoint non-linearity
output voltage
output current
output resistance
1
15
TBD
50
0.3
TBD
200
2
0.998
TBD
0.02
±3.4
45
1.5
6.5
90
3.5
5.5
20
250
2.0
120
120
0.8
90
3.0
0.988
120
2.5
0.988
120
2.5
0.988
0.05
2.4
20
4.0
0.03
2.8
30
2.5
0.03
2.8
30
2.5
mV
µV/°C
mV
µA
µA/°C
µA
kΩ
pF
V/V
V/V
%FS
V
mA
Ω
VOS
DVIO
VOSM
IBN
DIBN
IBNM
RIN
CIN
GA
GAM
ILIN
VO
IO
RO
14
50
-1.1
-1.5
50
270
-1.1
-1.5
30
110
-1.1
-1.5
30
110
V
V
µA
µA
VIH1
VIL1
IIH1
IIL1
14
50
2.0
0.8
50
270
2.0
0.8
30
110
2.0
0.8
30
110
V
V
µA
µA
VIH2
VIL2
IIH2
IIL2
30
31
28
30
25
26
60
64
64
mA
mA
mW
dB
ICC
IEE
PD
PSRR
±2V
±2V
±1V (full scale)
no load
dc
DIGITAL INPUT PERFORMANCE
ECL mode (pin 6 floating)
input voltage logic HIGH
input voltage logic LOW
input current logic HIGH
input current logic LOW
TTL mode (pin 6 = +5V)
input voltage logic HIGH
input voltage logic LOW
input current logic HIGH
input current logic LOW
POWER REQUIREMENTS
* supply current (+VCC = +5.0V)
* supply current (-VEE = -5.2V)
nominal power dissipation
* power supply rejection ratio
no load
no load
no load
23
24
240
73
Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are
determined from tested parameters.
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2
Absolute Maximum Ratings3
Recommended Operating Conditions
positive supply voltage (+VCC)
negative supply voltage (-VEE)
differential voltage between any two GND’s
analog input voltage range
SELECT input voltage range (TTL mode)
SELECT input voltage range (ECL mode)
CCOMP range2
θJC (°C/W)
55
35
35
35
thermal data
14-pin plastic
14-pin Cerdip
14-pin SOIC
20-terminal LCC
Note 1:
*
positive supply voltage (+VCC)
negative supply voltage (-VEE)
differential voltage between any two GND’s
analog input voltage range
digital input voltage range
output short circuit duration (output shorted to GND)
junction temperature
operating temperature range
CLC532AJP/AJE/AIB
storage temperature range
lead solder duration (+300°C)
ESD rating
transistor count
+5V
-5.2V or -5.0V
10mV
±2V
0.0V to +3.0V
-2.0V to 0.0V
0pF to 100pF
θJA (°C/W)
100
85
105
50
-0.5V to +7.0V
+0.5V to -7.0V
200mV
-VEE to +VCC
-VEE to +VCC
Infinite
+150°C
-40°C to +85°C
-65°C to +150°C
10 sec
<500V
74
Note 3: Absolute maximum ratings are limiting values, to be applied individually,
and beyond which the serviceability of the circuit may be impaired. Functional
operability under any of these conditions is not necessarily implied. Exposure to
maximum ratings for extended periods may affect device reliability.
Test levels are as follows:
AJ : 100% tested at +25°C.
Note 2: The CLC532 does not require external C COMP capacitors for proper
operation.
System Timing Diagram
Switching Transient Timing Diagram
SETTLING ERROR
WINDOW
A
A
SELECT
SELECT
B
B
TSx
SWT90
SWT10
TRx
TRx
ST
90%
OUTPUT
10%
~
~ 2ns
OUTPUT
OS
CHANNEL A = +1V
CHANNEL B = -1V
Channel A = 0V
Channel B = 0V
... where TSx is TS14 or TSP or TSS,
and TRx is TRS ro TSL.
3
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CLC532 Electrical Characteristics
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(+25°C unless specified)
4
CLC532 Electrical Characteristics
(+25°C unless specified)
5
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Applications Information
Operation
The CLC532 is a 2:1 analog multiplexer with high-impedance
buffered inputs, and a low-impedance, low-distortion, output
stage. The CLC532 employs a closed-loop design, which
dramatically improves accuracy. The channel SELECT control
(Figure 1) determines which of the two inputs (INA or INB) is
present at the OUTPUT. Beyond the basic multiplexer function,
the CLC532 offers compatibility with either TTL or ECL logic
families, as well as adjustable bandwidth.
CLC532
6
Figure 3: TTL/CMOS Level Channel SELECT Configuration
CHANNEL A
Compensation
The CLC532 incorporates compensation nodes that allow both
its bandwidth and its settling time/slew rate to be adjusted.
Bandwidth and settling time/slew adjustments are linked,
meaning that lowering the bandwidth also lowers slew rate
and lengthens settling time. Proper adjustment (compensation)
is necessary to optimize system performance. Time Domain
applications should generally be optimized for lowest RMS
noise at the CLC532 output, while maintaining settling time and
slew rates at adequate levels to meet system needs. Frequency
Domain applications should generally be optimized for maximally
flat frequency response.
CCOMP1
13
14
12
11
CLC532
4
INB
3
RIN
10
5
7
8
R2
R1
0.1 µ F
CHANNEL B
+5V
A/B
+6.8 µ F
RIN
DREF
7
+5V
R3
CHANNEL
SELECT
+5V
2
INA
1
TTL CMOS
620 Ω 3.6k Ω
200 Ω 510 Ω
510 Ω 680 Ω
R3
R2
R1
9
VOUT
6
RL
DREF
CCOMP2
DGND
Figure 4 below describes the basic relationship between
bandwidth and RS for various values of load capacitance, CL,
where CCOMP = 10pF.
+6.8 µ F
CHANNEL
SELECT
0.1µF
100
100
90
Figure 1: Standard CLC532 Circuit Configuration
Digital Interface and Channel SELECT
The CLC532 functions with ECL, TTL and CMOS logic families.
DREF controls logic compatibility. In normal operation, DREF is left
floating, and the channel SELECT responds to ECL level signals,
Figure 2. For TTL or CMOS level SELECT inputs (Figure 3), DREF
should be tied to +5V (the CLC532 incorporates an internal
2300Ω series isolation resistor for the DREF input). For TTL or
CMOS operation, the channel SELECT requires a resistor input
network to prevent saturation of the channel select circuitry.
Without this input network, channel SELECT logic levels above
3V will cause internal junction saturation and slow switching
speeds.
50Ω
50Ω
To ECL
Gate
R2
Ts
20
30
0.01%
20
10
0.05%
0
1000
100
C L (pF)
OUTPUTNOISERMS = (nV)(√1.57*BW-3dB)
where... nV = input spot noise voltage;
BW-3dB = Bandwidth is from figure 5.
200
180
160
140
120
100
80
60
40
20
0
81Ω
130 Ω
-5.2V
Figure 2: ECL Level Channel SELECT Configuration
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40
30
Figure 5 shows the resulting changes in bandwidth and slew rate
for increasing values of CCOMP . The RMS noise at the CLC532
output can be approximated as:
To
SELECT
-2V
50
40
Figure 4: Settling Time and RS vs. CL
DREF
(NC)
R1
60
50
1
Thevinen Equivalent
Output Termination
A/B
70
Slew Rate
-3dB Bandwidth
1
10
Ccomp (pF)
200
180
160
140
120
100
80
60
40
20
Slew Rate (V/µs)
ECL GATE
80
60
0
6
CHANNEL
SELECT
90
1kΩ
2V Output Step
Rs
70
10
CLC532
7
SELECT
CL
80
Recommended R s (Ω )
S e t t l i n g t i m e , Ts ( n s )
-5.2V
Rs
100
Figure 5: CCOMP for Maximally Flat Frequency Response
6
Use of "small" value input termination resistors will also improve
channel-to-channel isolation. However, extremely low values
(<25Ω) tend to stress the driving source's ability to provide a highquality input signal to the CLC532. Higher values tend to
aggravate any layout dependent crosstalk. 75Ω to 50Ω is a
reasonable target, but the lower the better.
Power Supplies and Grounding
Proper power supply bypassing and grounding is essential to
the CLC532’s operation. A 0.1µF to 0.01mF ceramic chip
capacitor should be located as close as possible to the individual
power supply pins. Larger +6.8µF tantalum capacitors should
be used within a few inches of the CLC532. The ground
connections for these larger by-pass capacitors should be very
symmetrically located relative the CLC532 output load ground
connection. Harmonic distortion can be heavily influenced by
non-symmetric decoupling capacitor grounding. The smaller
chip capacitors located directly at the power supply pins are not
particularly susceptible to this effect.
Combining Two Signals in ADC Applications
The CLC532 is applicable in a wide range of circuits and
applications. A classic example of this flexibility is combining two
or more signals for digitization by an analog-to-digital converter
(ADC). A clear understanding of both the multiplexer and the
ADC's operation is needed to optimize this configuration.
Separation of analog and digital ground planes is not
recommended. In most cases, a single low-impedance ground
plane will provide the best performance. In those special cases
requiring separate ground planes, the following table indicates
the signal and supply ground connections.
Pin
1,3
5
To obtain the best performance from the combination, the output
of the CLC532 must be an accurate representation of the
selected input during the ADC conversion cycle. The time at
which the ADC samples the input varies with the type of ADC that
is being used.
Functions
Ground Return
Shield /Supply Returns Supplies and Inputs
DREF Ground
DREF Currents Only
Subranging ADCs usually have a Track-and-Hold (T/H) at their
input. For a successful combination of the multiplexer and the
ADC, the multiplexer timing and the T/H timing must be compatible.
When the ADC is given a convert command, the T/H transitions
from Track mode to Hold mode. The delay between the convert
command and this transition is usually specified as Aperture
Delay or as Sampling Time Offset.
Input Shielding
The CLC532 has been designed for use in high-speed widedynamic range systems. Guard-ring traces and the use of the
ground pins separating the analog inputs are recommended to
maintain high isolation (Figure 6). Likely sources of noise and
interference that may couple onto the inputs, are the logic signals
and power supplies to the CLC532. Other types of clock and
signal traces should not be overlooked, however.
Channel A
Connector
To maximize the time that the multiplexer output has to settle, and
that the T/H has to acquire the signal, the multiplexer should
begin its transition from one input to the other immediately after
the T/H transition into HOLD mode. Unfortunately it is during the
initial portion of the HOLD period that a subranging ADC performs
analog processing of the sampled signal. High slew rate
transitions on the input during this time may have a detrimental
effect on the conversion accuracy.
Pin 1
Chip Resistors
To minimize the effects of high input slew rates, two strategies
that can employed. Strategy one applies when the sample rate
of the system is below the rated speed of the ADC. Here the
CLC532 SELECT timing is delayed until after the multiplexer
transition takes place, and after the A/D has completed one
conversion cycle and is waiting for the next convert command.
As an example, if a CLC935 (15MSPS) ADC is being used at
10MSPS, the conversion takes place in the first 67ns after the
CONVERT command. The next 33ns are spent waiting for the
next CONVERT command, and would be an ideal place to switch
the multiplexer from one channel to the next.
Channel B
Connector
Figure 6: Alternate Layout Using Guard Ring
The general rule in maintaining isolation has two facets, minimize
the primary return ground current path impedances back to the
respective signal sources, while maximizing the impedance
associated with common or secondary ground current return
paths. Success or failure to optimize input signal isolation can
be measured directly as the isolation between the input channels
with the CLC532 removed from circuit. The channel-to-channel
isolation of the CLC532 can never be better than the isolation
level present at its inputs.
50
45
Ccomp (pF)
40
Special attention must be paid to input termination resistors.
Minimizing the return current path that is common to both of the input
termination resistors is essential. In the event that a ground return
current from one input termination resistor is able to find a secondary
path back to its signal source (which also happens to be common
with either the primary or secondary return path for the second input
termination resistor), a small voltage can appear across the second
input termination resistor. The small voltage seen across the
second input termination resistor will be highly correlated with the
signal generating the initial return currents. This situation will
severely degrade channel-to-channel isolation at the input of the
CLC532, even if the CLC532 were removed from circuit. Poor
isolation at the input will be transmitted directly to the output.
35
30
25
20
15
10
5
10
11
12
13 14 15 16 17
Sample Rate (MSPS)
18
19
20
Figure 7: Recommended CCOMP vs. ADC Sample Rate
The second optimization strategy involves lowering the slew rate
at the input of the ADC so that fewer high frequency components
are available to feed through to the hold capacitor during HOLD
7
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mode. The CLC532 output signal can be slew limited by using
its compensation capacitors. This approach also has the
advantage of limiting the excess noise passed through the
CLC532 and on to the ADC. Figure 7 shows the recommended
CCOMP values as a function of ADC Sample rate. Since the optimal
values will change from one ADC to the next, this graph should
be used as a starting point for CCOMP selection. Both CCOMP
capacitors should be the same value to maintain output symmetry.
+1
INA
RECTIFIER
INPUT
RL
INB
-1
Flash ADCs are similar to subranging ADCs in that the sampling
period is very brief. The primary difference is that the acquisition
time of a flash converter is much shorter than that of a subranging
ADC. With a flash ADC, the transition of the CLC532 output
should be after the sampling instant ("Aperture Delay" after the
CONVERT command). It is only during this period that a flash
converter is susceptible to interference from a rapidly changing
analog input signal.
VOUT
CLC532
10114
+20
50Ω
0.1µF
VBB
50Ω
50Ω
50Ω
-2V
Gain Selection for an ADC
In many applications, such as RADAR, the dynamic range
requirements may exceed the accuracy requirements. Since
wide dynamic range ADCs are also typically highly accurate
ADCs, this often leads the designer into selecting an ADC which
is a technical overkill and a budget buster. By using the CLC532
as a selectable-gain stage, a less expensive ADC can be used.
As an example, if an application calls for 80dB of dynamic Range
and 0.05% accuracy, rather than using a 14-bit converter, a 12bit converter combined with the circuit in figure 8 will meet the
same objective. The CLC532 is used to select between the
analog input signal and a version of the input signal attenuated
by 12dB.
This circuit affords 14-bit dynamic range, 12-bit
accuracy and 12-bit ease of implementation.
Zero Crossing
Treshold
Detector
Figure 9: Low Distortion Full Wave Rectifier
Use of the CLC532 as a Mixer.
A double balanced mixer, such as is shown in figure 10, operates
by multiplying the RF input by the LO input. This is done by using
the LO to select one of two paths through a diode bridge
depending upon the LO sign. The result is an output where IF=RF
when LO>0 and IF=-RF if LO<0. This same result can be
obtained with the circuit shown in figure 11. The CLC532 based
circuit uses a digital LO making system design easier in those
cases where the LO is digitally derived. One advantage of the
CLC532 based approach is excellent isolation between all three
ports. Also see the RF design awards article by Thomas Hack
in the January 1993 issue of RF Design.
+5V
+6.8µ F
LO
INPUT
0.1µ F
To 0Ω
Input
Source
50 Ω
R7
2
INA
1
10pF
13
14
12
200 Ω
R6
66.6 Ω R INB
To 50 Ω
Source
11 48.7 Ω
CLC532
4
IN
3 B
RF
INPUT
10
5
7
8
9
6
To 50 Ω
Load
IF
OUTPUT
R OUT
Figure 10: Typical Double-Balanced Mixer
DREF
10pF
DGND
50 Ω
MINI-CIRCUITS
T4-1T
+6.8 µ F
Gain
SELECT
RF INPUT
0.1µF
INA
IF OUTPUT
200Ω
CLC532
-5.2V
INB
Figure 8: Selectable Gain Stage Improves
ADC Dynamic Range
DIGITAL
LO INPUT
Full Wave Rectifier Circuit
The use of a diode rectifier provides significant distortion for
signals that are small compared to the forward bias voltage.
Accordingly, when low distortion performance is needed, standard
diode based circuits do not work well. The CLC532 can be
configured to provide a very low distortion full wave rectifier. The
circuit in figure 9 is used to select between an analog input signal
and an inverted version of the input signal. The resulting output
exhibits very little distortion for small scale signals up to several
hundred kilohertz.
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RL
Figure 11: High-Isolation Mixer Implementation
Evaluation Board
An evaluation board (part number CLC730028) for the CLC532
is available. This board can be used for fast, trouble-free,
evaluation and characterization of the CLC532. Additionally,
this board serves as a template for layout and fabrication
information. The CLC532 evaluation board data sheet is available.
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CLC532
High-Speed 2:1 Analog Multiplexer
Customer Design Applications Support
National Semiconductor is committed to design excellence. For sales, literature and technical support, call the
National Semiconductor Customer Response Group at 1-800-272-9959 or fax 1-800-737-7018.
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of the president of National Semiconductor Corporation. As used herein:
1. Life support devices or systems are devices or systems which, a) are intended for surgical implant into the body, or b) support or
sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to
cause the failure of the life support device or system, or to affect its safety or effectiveness.
N
National Semiconductor
Corporation
National Semiconductor
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National Semiconductor
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Japan Ltd.
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Tel: 1(800) 272-9959
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