DATASHEET EL7242, EL7252 Dual Input, High Speed, Dual Channel Power MOSFET Driver The EL7242/EL7252 dual input, 2-channel drivers achieve the same excellent switching performance of the EL7212 family while providing added flexibility. The 2-input logic and configuration is applicable to numerous power MOSFET drive circuits. As with other Intersil drivers, the EL7242/EL7252 are excellent for driving large capacitive loads with minimal delay and switching times. “Shoot-thru” protection and latching circuits can be implemented by simply “cross-coupling” the 2-channels. Pinouts EL7242 (8 LD PDIP, SOIC) TOP VIEW A IN 1 8 V+ B IN 2 7 OUT A C IN 3 6 OUT B D IN 4 5 GND FN7285 Rev 5.00 September 3, 2015 Features • Logic AND/NAND input • 3V and 5V Input compatible • Clocking speeds up to 10MHz • 20ns Switching/delay time • 2A Peak drive • Isolated drains • Low output impedance • Low quiescent current • Wide operating voltage — 4.5V to 16V • Pb-free available (RoHS compliant) Applications • Short circuit protected switching • Undervoltage shut-down circuits • Switch-mode power supplies • Motor controls EL7252 (8 LD PDIP, SOIC) TOP VIEW • Power MOSFET switching • Switching capacitive loads A IN 1 8 V+ • Shoot-thru protection B IN 2 7 OUT A • Latching drivers C IN 3 6 OUT B D IN 4 5 GND Manufactured under U.S. Patent Nos. 5,334,883, #5,341,047 FN7285 Rev 5.00 September 3, 2015 Page 1 of 9 EL7242, EL7252 Ordering Information PART NUMBER PART MARKING PACKAGE PKG. DWG. # EL7242CNZ (Note 1) EL7242CN Z 8 Ld PDIP** (Pb-free) E8.3 EL7242CSZ (Note 1) 7242CSZ 8 Ld SOIC (Pb-free) MDP0027 EL7242CSZ-T7* (Note 1) 7242CSZ 8 Ld SOIC (Pb-free) MDP0027 EL7242CSZ-T13* (Note 1) 7242CSZ 8 Ld SOIC (Pb-free) MDP0027 EL7252CSZ (Note 1) 7252CSZ 8 Ld SOIC (Pb-free) MDP0027 EL7252CSZ-T7* (Note 1) 7252CSZ 8 Ld SOIC (Pb-free) MDP0027 EL7252CSZ-T13* (Note 1) 7252CSZ 8 Ld SOIC (Pb-free) MDP0027 EL7252CN (No longer available, recommended replacement: EL7252CSZ) EL7252CN 8 Ld PDIP E8.3 *Please refer to TB347 for details on reel specifications. **Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. NOTES: 1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. FN7285 Rev 5.00 September 3, 2015 Page 2 of 9 EL7242, EL7252 Absolute Maximum Ratings (TA = +25°C) Thermal Information Supply (V+ to GND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.5V Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V above V+ Combined Peak Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . .4A Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C Power Dissipation 8 Ld SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .570mW 8 Ld PDIP* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1050mW Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. Operating Conditions Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +125°C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA DC Electrical Specifications PARAMETER TA = +25°C, V = 15V, unless otherwise specified. DESCRIPTION TEST CONDITIONS MIN TYP MAX UNITS INPUT VIH Logic “1' Input Voltage IIH Logic “1' Input Current VIL Logic “0' Input Voltage IIL Logic “0' Input Current VHVS Input Hysteresis 2.4 @V+ V 0.1 @0V 0.1 10 µA 0.8 V 10 µA 0.3 V OUTPUT ROH Pull-up Resistance IOUT = -100mA 3 6 ROL Pull-down Resistance IOUT = +100mA 4 6 IPK Peak Output Current Source 2 A Sink 2 A IDC Continuous Output Current Source/Sink IS Power Supply Current Inputs High VS Operating Voltage 100 mA POWER SUPPLY AC Electrical Specifications PARAMETER 1 4.5 2.5 mA 16 V TA = +25°C, V = 15V, unless otherwise specified. DESCRIPTION TEST CONDITIONS MIN TYP MAX UNITS CL = 500pF 10 ns CL = 1000pF 20 ns CL = 500pF 10 ns CL = 1000pF 20 ns SWITCHING CHARACTERISTICS tR tF Rise Time (Note 2) Fall Time (Note 2) tD-ON Turn-On Delay Time (Note 2) 20 25 ns tD-OFF Turn-Off Delay Time (Note 2) 20 25 ns NOTE: 2. Limits established by characterization and are not production tested. FN7285 Rev 5.00 September 3, 2015 Page 3 of 9 EL7242, EL7252 Timing Table 5V INPUT 2.5V 0 INVERTED OUTPUT NON-INVERTED OUTPUT 90% 10% 90% 10% tD1 tF tR tD2 tR tF Standard Test Configuration V+ 3 4 4.7µF TAN EL7242 1 2 7 OUTPUT 1000pF LOAD INPUT 5 Simplified Schematic V+ OUTPUT + - INPUT + INPUT BUFFER FN7285 Rev 5.00 September 3, 2015 VREF REFERENCE AND LEVEL SHIFTER INVERTING BUFFER WITH HYSTERESIS LOGIC GATE SUPER INVERTER Page 4 of 9 EL7242, EL7252 Typical Performance Curves 2.0 PDIP8 1.05W JA = 95°C/W 0.8 MAX TJ= 125°C 570mW 0.6 0.4 SO8 0.2 0.0 HIGH LIMIT = 2.4V 1.8 1.6 INPUT VOLTAGE POWER DISSIPATION (W) 1.0 HYSTERESIS 1.4 1.2 1.0 LOW LIMIT = 0.8V JA = 175°C/W 0 25 50 75 100 125 AMBIENT TEMPERATURE (°C) 0.0 150 FIGURE 1. MAX POWER/DERATING CURVES 0 5 10 SUPPLY VOLTAGE 15 FIGURE 2. SWITCH THRESHOLD vs SUPPLY VOLTAGE V - SUPPLY 0 15 10 5 0 10 N-CHANNEL SINK (A) 2/DIV 0 -1 1 P-CHANNEL -2 -10 -5 0 V+ 20 0 5 FIGURE 3. INPUT CURRENT vs VOLTAGE B 6 5 C CASE: A ALL INPUTS GND B 3 INPUTS GND C 2 INPUTS GND 4 3 D 2 1 MEASURED AT 100mA 8 D 1 INPUT GND E ALL INPUTS V+ ON-RESISTANCE () SUPPLY CURRENT (mA) 7 15 FIGURE 4. PEAK DRIVE vs SUPPLY VOLTAGE A 8 10 V - SUPPLY VIN 2.5V/DIV PULL-DOWN 6 4 2 PULL-UP E 0 0 5 10 15 SUPPLY VOLTAGE (V) FIGURE 5. QUIESCENT SUPPLY CURRENT FN7285 Rev 5.00 September 3, 2015 0 5 10 15 SUPPLY VOLTAGE (V) FIGURE 6. ON-RESISTANCE vs SUPPLY VOLTAGE Page 5 of 9 SOURCE (A) IIN (mA) 2 EL7242, EL7252 Typical Performance Curves (Continued) 100 VDD = +15V VDD = +10V 10 VDD = +5V 1 CL = 1000pF 0.1 10k 100k 1000pF 10,000pF 1M SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) 100 10 100pF 1 NO LOAD VDD = 10V (EQUIVALENT INTERNAL CAPACITANCE = 470pF) 0.1 10k 10M 100k FREQUENCY (Hz) FIGURE 7. AVERAGE SUPPLY CURRENT vs VOLTAGE AND FREQUENCY 30 VDD = 10V 80 60 40 tF 20 20 tF 10 tR tR 100 1000 CL = 1000pF 0 10,000 5 7.5 10 12.5 SUPPLY VOLTAGE (V) LOAD CAPACITANCE (pF) FIGURE 9. RISE/FALL TIME vs LOAD 30 tD2 30 RISE/FALL TIME (ns) DELAY TIME (ns) 15 FIGURE 10. RISE/FALL TIME vs SUPPLY VOLTAGE 40 20 tD1 10 0 10M FIGURE 8. AVERAGE SUPPLY CURRENT vs CAPACITIVE LOAD RISE/FALL TIME (ns) RISE/FALL TIME (ns) 100 1M FREQUENCY (Hz) CL = 1000pF 5 7.5 10 12.5 15 SUPPLY VOLTAGE (V) FIGURE 11. PROPAGATION DELAY vs SUPPLY VOLTAGE FN7285 Rev 5.00 September 3, 2015 20 tF 10 VDD = 10V 0 -50 tR CL = 1000pF -25 0 25 50 75 100 125 TEMPERATURE (°C) FIGURE 12. RISE/FALL TIME vs TEMPERATURE Page 6 of 9 EL7242, EL7252 Typical Performance Curves (Continued) 40 tD2 DELAY TIME (ns) 30 20 tD1 10 0 -50 VDD = 10V CL = 1000pF -25 0 25 50 75 100 125 TEMPERATURE (°C) FIGURE 13. DELAY vs TEMPERATURE Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that you have the latest revision. DATE REVISION September 3, 2015 FN7285.5 CHANGE Updated Ordering Information Table on page 2. Added Revision History and About Intersil sections. About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support FN7285 Rev 5.00 September 3, 2015 Page 7 of 9 EL7242, EL7252 Small Outline Package Family (SO) A D h X 45° (N/2)+1 N A PIN #1 I.D. MARK E1 E c SEE DETAIL “X” 1 (N/2) B L1 0.010 M C A B e H C A2 GAUGE PLANE SEATING PLANE A1 0.004 C 0.010 M C A B L b 0.010 4° ±4° DETAIL X MDP0027 SMALL OUTLINE PACKAGE FAMILY (SO) INCHES SYMBOL SO-14 SO16 (0.300”) (SOL-16) SO20 (SOL-20) SO24 (SOL-24) SO28 (SOL-28) TOLERANCE NOTES A 0.068 0.068 0.068 0.104 0.104 0.104 0.104 MAX - A1 0.006 0.006 0.006 0.007 0.007 0.007 0.007 0.003 - A2 0.057 0.057 0.057 0.092 0.092 0.092 0.092 0.002 - b 0.017 0.017 0.017 0.017 0.017 0.017 0.017 0.003 - c 0.009 0.009 0.009 0.011 0.011 0.011 0.011 0.001 - D 0.193 0.341 0.390 0.406 0.504 0.606 0.704 0.004 1, 3 E 0.236 0.236 0.236 0.406 0.406 0.406 0.406 0.008 - E1 0.154 0.154 0.154 0.295 0.295 0.295 0.295 0.004 2, 3 e 0.050 0.050 0.050 0.050 0.050 0.050 0.050 Basic - L 0.025 0.025 0.025 0.030 0.030 0.030 0.030 0.009 - L1 0.041 0.041 0.041 0.056 0.056 0.056 0.056 Basic - h 0.013 0.013 0.013 0.020 0.020 0.020 0.020 Reference - 16 20 24 28 Reference - N SO-8 SO16 (0.150”) 8 14 16 NOTES: Rev. M 2/07 1. Plastic or metal protrusions of 0.006” maximum per side are not included. 2. Plastic interlead protrusions of 0.010” maximum per side are not included. 3. Dimensions “D” and “E1” are measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M-1994 FN7285 Rev 5.00 September 3, 2015 Page 8 of 9 EL7242, EL7252 Dual-In-Line Plastic Packages (PDIP) E8.3 (JEDEC MS-001-BA ISSUE D) N 8 LEAD DUAL-IN-LINE PLASTIC PACKAGE E1 INDEX AREA 1 2 3 INCHES N/2 -B- -AD E BASE PLANE -C- SEATING PLANE A2 A L D1 e B1 D1 A1 eC B 0.010 (0.25) M C A B S MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A - 0.210 - 5.33 4 A1 0.015 - 0.39 - 4 A2 0.115 0.195 2.93 4.95 - B 0.014 0.022 0.356 0.558 - C L B1 0.045 0.070 1.15 1.77 8, 10 eA C 0.008 0.014 0.204 C D 0.355 0.400 9.01 eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 5 D1 0.005 - 0.13 - 5 E 0.300 0.325 7.62 8.25 6 E1 0.240 0.280 6.10 7.11 5 e 0.100 BSC 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. eA 0.300 BSC 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. eB - L 0.115 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 0.355 10.16 N 2.54 BSC 7.62 BSC 0.430 - 0.150 2.93 8 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 8 6 10.92 7 3.81 4 9 Rev. 0 12/93 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). © Copyright Intersil Americas LLC 2003-2015. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN7285 Rev 5.00 September 3, 2015 Page 9 of 9